1 /*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef __MDP5_KMS_H__
19 #define __MDP5_KMS_H__
20
21 #include "msm_drv.h"
22 #include "msm_kms.h"
23 #include "mdp/mdp_kms.h"
24 #include "mdp5_cfg.h" /* must be included before mdp5.xml.h */
25 #include "mdp5.xml.h"
26 #include "mdp5_ctl.h"
27 #include "mdp5_smp.h"
28
29 struct mdp5_kms {
30 struct mdp_kms base;
31
32 struct drm_device *dev;
33
34 struct mdp5_cfg_handler *cfg;
35 uint32_t caps; /* MDP capabilities (MDP_CAP_XXX bits) */
36
37
38 /* mapper-id used to request GEM buffer mapped for scanout: */
39 int id;
40 struct msm_mmu *mmu;
41
42 struct mdp5_smp *smp;
43 struct mdp5_ctl_manager *ctlm;
44
45 /* io/register spaces: */
46 void __iomem *mmio, *vbif;
47
48 struct regulator *vdd;
49
50 struct clk *axi_clk;
51 struct clk *ahb_clk;
52 struct clk *src_clk;
53 struct clk *core_clk;
54 struct clk *lut_clk;
55 struct clk *vsync_clk;
56
57 /*
58 * lock to protect access to global resources: ie., following register:
59 * - REG_MDP5_MDP_DISP_INTF_SEL
60 */
61 spinlock_t resource_lock;
62
63 struct mdp_irq error_handler;
64
65 struct {
66 volatile unsigned long enabled_mask;
67 struct irq_domain *domain;
68 } irqcontroller;
69 };
70 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)
71
72 struct mdp5_plane_state {
73 struct drm_plane_state base;
74
75 /* aligned with property */
76 uint8_t premultiplied;
77 uint8_t zpos;
78 uint8_t alpha;
79
80 /* assigned by crtc blender */
81 enum mdp_mixer_stage_id stage;
82
83 /* some additional transactional status to help us know in the
84 * apply path whether we need to update SMP allocation, and
85 * whether current update is still pending:
86 */
87 bool mode_changed : 1;
88 bool pending : 1;
89 };
90 #define to_mdp5_plane_state(x) \
91 container_of(x, struct mdp5_plane_state, base)
92
93 enum mdp5_intf_mode {
94 MDP5_INTF_MODE_NONE = 0,
95
96 /* Modes used for DSI interface (INTF_DSI type): */
97 MDP5_INTF_DSI_MODE_VIDEO,
98 MDP5_INTF_DSI_MODE_COMMAND,
99
100 /* Modes used for WB interface (INTF_WB type): */
101 MDP5_INTF_WB_MODE_BLOCK,
102 MDP5_INTF_WB_MODE_LINE,
103 };
104
105 struct mdp5_interface {
106 int num; /* display interface number */
107 enum mdp5_intf_type type;
108 enum mdp5_intf_mode mode;
109 };
110
mdp5_write(struct mdp5_kms * mdp5_kms,u32 reg,u32 data)111 static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
112 {
113 msm_writel(data, mdp5_kms->mmio + reg);
114 }
115
mdp5_read(struct mdp5_kms * mdp5_kms,u32 reg)116 static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
117 {
118 return msm_readl(mdp5_kms->mmio + reg);
119 }
120
pipe2name(enum mdp5_pipe pipe)121 static inline const char *pipe2name(enum mdp5_pipe pipe)
122 {
123 static const char *names[] = {
124 #define NAME(n) [SSPP_ ## n] = #n
125 NAME(VIG0), NAME(VIG1), NAME(VIG2),
126 NAME(RGB0), NAME(RGB1), NAME(RGB2),
127 NAME(DMA0), NAME(DMA1),
128 NAME(VIG3), NAME(RGB3),
129 #undef NAME
130 };
131 return names[pipe];
132 }
133
pipe2nclients(enum mdp5_pipe pipe)134 static inline int pipe2nclients(enum mdp5_pipe pipe)
135 {
136 switch (pipe) {
137 case SSPP_RGB0:
138 case SSPP_RGB1:
139 case SSPP_RGB2:
140 case SSPP_RGB3:
141 return 1;
142 default:
143 return 3;
144 }
145 }
146
intf2err(int intf_num)147 static inline uint32_t intf2err(int intf_num)
148 {
149 switch (intf_num) {
150 case 0: return MDP5_IRQ_INTF0_UNDER_RUN;
151 case 1: return MDP5_IRQ_INTF1_UNDER_RUN;
152 case 2: return MDP5_IRQ_INTF2_UNDER_RUN;
153 case 3: return MDP5_IRQ_INTF3_UNDER_RUN;
154 default: return 0;
155 }
156 }
157
158 #define GET_PING_PONG_ID(layer_mixer) ((layer_mixer == 5) ? 3 : layer_mixer)
intf2vblank(int lm,struct mdp5_interface * intf)159 static inline uint32_t intf2vblank(int lm, struct mdp5_interface *intf)
160 {
161 /*
162 * In case of DSI Command Mode, the Ping Pong's read pointer IRQ
163 * acts as a Vblank signal. The Ping Pong buffer used is bound to
164 * layer mixer.
165 */
166
167 if ((intf->type == INTF_DSI) &&
168 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND))
169 return MDP5_IRQ_PING_PONG_0_RD_PTR << GET_PING_PONG_ID(lm);
170
171 if (intf->type == INTF_WB)
172 return MDP5_IRQ_WB_2_DONE;
173
174 switch (intf->num) {
175 case 0: return MDP5_IRQ_INTF0_VSYNC;
176 case 1: return MDP5_IRQ_INTF1_VSYNC;
177 case 2: return MDP5_IRQ_INTF2_VSYNC;
178 case 3: return MDP5_IRQ_INTF3_VSYNC;
179 default: return 0;
180 }
181 }
182
lm2ppdone(int lm)183 static inline uint32_t lm2ppdone(int lm)
184 {
185 return MDP5_IRQ_PING_PONG_0_DONE << GET_PING_PONG_ID(lm);
186 }
187
188 int mdp5_disable(struct mdp5_kms *mdp5_kms);
189 int mdp5_enable(struct mdp5_kms *mdp5_kms);
190
191 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
192 uint32_t old_irqmask);
193 void mdp5_irq_preinstall(struct msm_kms *kms);
194 int mdp5_irq_postinstall(struct msm_kms *kms);
195 void mdp5_irq_uninstall(struct msm_kms *kms);
196 irqreturn_t mdp5_irq(struct msm_kms *kms);
197 int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
198 void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
199 int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms);
200 void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);
201
202 uint32_t mdp5_plane_get_flush(struct drm_plane *plane);
203 void mdp5_plane_complete_flip(struct drm_plane *plane);
204 void mdp5_plane_complete_commit(struct drm_plane *plane,
205 struct drm_plane_state *state);
206 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
207 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
208 enum mdp5_pipe pipe, bool private_plane,
209 uint32_t reg_offset, uint32_t caps);
210
211 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
212
213 int mdp5_crtc_get_lm(struct drm_crtc *crtc);
214 void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
215 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc,
216 struct mdp5_interface *intf, struct mdp5_ctl *ctl);
217 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc);
218 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
219 struct drm_plane *plane, int id);
220
221 struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
222 struct mdp5_interface *intf, struct mdp5_ctl *ctl);
223 int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
224 struct drm_encoder *slave_encoder);
225
226 #ifdef CONFIG_DRM_MSM_DSI
227 struct drm_encoder *mdp5_cmd_encoder_init(struct drm_device *dev,
228 struct mdp5_interface *intf, struct mdp5_ctl *ctl);
229 int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
230 struct drm_encoder *slave_encoder);
231 #else
mdp5_cmd_encoder_init(struct drm_device * dev,struct mdp5_interface * intf,struct mdp5_ctl * ctl)232 static inline struct drm_encoder *mdp5_cmd_encoder_init(struct drm_device *dev,
233 struct mdp5_interface *intf, struct mdp5_ctl *ctl)
234 {
235 return ERR_PTR(-EINVAL);
236 }
mdp5_cmd_encoder_set_split_display(struct drm_encoder * encoder,struct drm_encoder * slave_encoder)237 static inline int mdp5_cmd_encoder_set_split_display(
238 struct drm_encoder *encoder, struct drm_encoder *slave_encoder)
239 {
240 return -EINVAL;
241 }
242 #endif
243
244 #endif /* __MDP5_KMS_H__ */
245