1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
4
5 #include <asm/perf_event.h>
6 #include <asm/insn.h>
7
8 #include "perf_event.h"
9
10 /* The size of a BTS record in bytes: */
11 #define BTS_RECORD_SIZE 24
12
13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14 #define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
15 #define PEBS_FIXUP_SIZE PAGE_SIZE
16
17 /*
18 * pebs_record_32 for p4 and core not supported
19
20 struct pebs_record_32 {
21 u32 flags, ip;
22 u32 ax, bc, cx, dx;
23 u32 si, di, bp, sp;
24 };
25
26 */
27
28 union intel_x86_pebs_dse {
29 u64 val;
30 struct {
31 unsigned int ld_dse:4;
32 unsigned int ld_stlb_miss:1;
33 unsigned int ld_locked:1;
34 unsigned int ld_reserved:26;
35 };
36 struct {
37 unsigned int st_l1d_hit:1;
38 unsigned int st_reserved1:3;
39 unsigned int st_stlb_miss:1;
40 unsigned int st_locked:1;
41 unsigned int st_reserved2:26;
42 };
43 };
44
45
46 /*
47 * Map PEBS Load Latency Data Source encodings to generic
48 * memory data source information
49 */
50 #define P(a, b) PERF_MEM_S(a, b)
51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
53
54 /* Version for Sandy Bridge and later */
55 static u64 pebs_data_source[] = {
56 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
57 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
58 OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
59 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
60 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
61 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
62 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
63 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
65 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
66 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
67 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
68 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
69 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
70 OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */
71 OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
72 };
73
74 /* Patch up minor differences in the bits */
intel_pmu_pebs_data_source_nhm(void)75 void __init intel_pmu_pebs_data_source_nhm(void)
76 {
77 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | P(SNOOP, HIT);
78 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | P(SNOOP, HITM);
79 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | P(SNOOP, HITM);
80 }
81
precise_store_data(u64 status)82 static u64 precise_store_data(u64 status)
83 {
84 union intel_x86_pebs_dse dse;
85 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
86
87 dse.val = status;
88
89 /*
90 * bit 4: TLB access
91 * 1 = stored missed 2nd level TLB
92 *
93 * so it either hit the walker or the OS
94 * otherwise hit 2nd level TLB
95 */
96 if (dse.st_stlb_miss)
97 val |= P(TLB, MISS);
98 else
99 val |= P(TLB, HIT);
100
101 /*
102 * bit 0: hit L1 data cache
103 * if not set, then all we know is that
104 * it missed L1D
105 */
106 if (dse.st_l1d_hit)
107 val |= P(LVL, HIT);
108 else
109 val |= P(LVL, MISS);
110
111 /*
112 * bit 5: Locked prefix
113 */
114 if (dse.st_locked)
115 val |= P(LOCK, LOCKED);
116
117 return val;
118 }
119
precise_datala_hsw(struct perf_event * event,u64 status)120 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
121 {
122 union perf_mem_data_src dse;
123
124 dse.val = PERF_MEM_NA;
125
126 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
127 dse.mem_op = PERF_MEM_OP_STORE;
128 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
129 dse.mem_op = PERF_MEM_OP_LOAD;
130
131 /*
132 * L1 info only valid for following events:
133 *
134 * MEM_UOPS_RETIRED.STLB_MISS_STORES
135 * MEM_UOPS_RETIRED.LOCK_STORES
136 * MEM_UOPS_RETIRED.SPLIT_STORES
137 * MEM_UOPS_RETIRED.ALL_STORES
138 */
139 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
140 if (status & 1)
141 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
142 else
143 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
144 }
145 return dse.val;
146 }
147
load_latency_data(u64 status)148 static u64 load_latency_data(u64 status)
149 {
150 union intel_x86_pebs_dse dse;
151 u64 val;
152 int model = boot_cpu_data.x86_model;
153 int fam = boot_cpu_data.x86;
154
155 dse.val = status;
156
157 /*
158 * use the mapping table for bit 0-3
159 */
160 val = pebs_data_source[dse.ld_dse];
161
162 /*
163 * Nehalem models do not support TLB, Lock infos
164 */
165 if (fam == 0x6 && (model == 26 || model == 30
166 || model == 31 || model == 46)) {
167 val |= P(TLB, NA) | P(LOCK, NA);
168 return val;
169 }
170 /*
171 * bit 4: TLB access
172 * 0 = did not miss 2nd level TLB
173 * 1 = missed 2nd level TLB
174 */
175 if (dse.ld_stlb_miss)
176 val |= P(TLB, MISS) | P(TLB, L2);
177 else
178 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
179
180 /*
181 * bit 5: locked prefix
182 */
183 if (dse.ld_locked)
184 val |= P(LOCK, LOCKED);
185
186 return val;
187 }
188
189 struct pebs_record_core {
190 u64 flags, ip;
191 u64 ax, bx, cx, dx;
192 u64 si, di, bp, sp;
193 u64 r8, r9, r10, r11;
194 u64 r12, r13, r14, r15;
195 };
196
197 struct pebs_record_nhm {
198 u64 flags, ip;
199 u64 ax, bx, cx, dx;
200 u64 si, di, bp, sp;
201 u64 r8, r9, r10, r11;
202 u64 r12, r13, r14, r15;
203 u64 status, dla, dse, lat;
204 };
205
206 /*
207 * Same as pebs_record_nhm, with two additional fields.
208 */
209 struct pebs_record_hsw {
210 u64 flags, ip;
211 u64 ax, bx, cx, dx;
212 u64 si, di, bp, sp;
213 u64 r8, r9, r10, r11;
214 u64 r12, r13, r14, r15;
215 u64 status, dla, dse, lat;
216 u64 real_ip, tsx_tuning;
217 };
218
219 union hsw_tsx_tuning {
220 struct {
221 u32 cycles_last_block : 32,
222 hle_abort : 1,
223 rtm_abort : 1,
224 instruction_abort : 1,
225 non_instruction_abort : 1,
226 retry : 1,
227 data_conflict : 1,
228 capacity_writes : 1,
229 capacity_reads : 1;
230 };
231 u64 value;
232 };
233
234 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
235
236 /* Same as HSW, plus TSC */
237
238 struct pebs_record_skl {
239 u64 flags, ip;
240 u64 ax, bx, cx, dx;
241 u64 si, di, bp, sp;
242 u64 r8, r9, r10, r11;
243 u64 r12, r13, r14, r15;
244 u64 status, dla, dse, lat;
245 u64 real_ip, tsx_tuning;
246 u64 tsc;
247 };
248
init_debug_store_on_cpu(int cpu)249 void init_debug_store_on_cpu(int cpu)
250 {
251 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
252
253 if (!ds)
254 return;
255
256 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
257 (u32)((u64)(unsigned long)ds),
258 (u32)((u64)(unsigned long)ds >> 32));
259 }
260
fini_debug_store_on_cpu(int cpu)261 void fini_debug_store_on_cpu(int cpu)
262 {
263 if (!per_cpu(cpu_hw_events, cpu).ds)
264 return;
265
266 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
267 }
268
269 static DEFINE_PER_CPU(void *, insn_buffer);
270
alloc_pebs_buffer(int cpu)271 static int alloc_pebs_buffer(int cpu)
272 {
273 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
274 int node = cpu_to_node(cpu);
275 int max;
276 void *buffer, *ibuffer;
277
278 if (!x86_pmu.pebs)
279 return 0;
280
281 buffer = kzalloc_node(x86_pmu.pebs_buffer_size, GFP_KERNEL, node);
282 if (unlikely(!buffer))
283 return -ENOMEM;
284
285 /*
286 * HSW+ already provides us the eventing ip; no need to allocate this
287 * buffer then.
288 */
289 if (x86_pmu.intel_cap.pebs_format < 2) {
290 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
291 if (!ibuffer) {
292 kfree(buffer);
293 return -ENOMEM;
294 }
295 per_cpu(insn_buffer, cpu) = ibuffer;
296 }
297
298 max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size;
299
300 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
301 ds->pebs_index = ds->pebs_buffer_base;
302 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
303 max * x86_pmu.pebs_record_size;
304
305 return 0;
306 }
307
release_pebs_buffer(int cpu)308 static void release_pebs_buffer(int cpu)
309 {
310 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
311
312 if (!ds || !x86_pmu.pebs)
313 return;
314
315 kfree(per_cpu(insn_buffer, cpu));
316 per_cpu(insn_buffer, cpu) = NULL;
317
318 kfree((void *)(unsigned long)ds->pebs_buffer_base);
319 ds->pebs_buffer_base = 0;
320 }
321
alloc_bts_buffer(int cpu)322 static int alloc_bts_buffer(int cpu)
323 {
324 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
325 int node = cpu_to_node(cpu);
326 int max, thresh;
327 void *buffer;
328
329 if (!x86_pmu.bts)
330 return 0;
331
332 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
333 if (unlikely(!buffer)) {
334 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
335 return -ENOMEM;
336 }
337
338 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
339 thresh = max / 16;
340
341 ds->bts_buffer_base = (u64)(unsigned long)buffer;
342 ds->bts_index = ds->bts_buffer_base;
343 ds->bts_absolute_maximum = ds->bts_buffer_base +
344 max * BTS_RECORD_SIZE;
345 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
346 thresh * BTS_RECORD_SIZE;
347
348 return 0;
349 }
350
release_bts_buffer(int cpu)351 static void release_bts_buffer(int cpu)
352 {
353 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
354
355 if (!ds || !x86_pmu.bts)
356 return;
357
358 kfree((void *)(unsigned long)ds->bts_buffer_base);
359 ds->bts_buffer_base = 0;
360 }
361
alloc_ds_buffer(int cpu)362 static int alloc_ds_buffer(int cpu)
363 {
364 int node = cpu_to_node(cpu);
365 struct debug_store *ds;
366
367 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
368 if (unlikely(!ds))
369 return -ENOMEM;
370
371 per_cpu(cpu_hw_events, cpu).ds = ds;
372
373 return 0;
374 }
375
release_ds_buffer(int cpu)376 static void release_ds_buffer(int cpu)
377 {
378 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
379
380 if (!ds)
381 return;
382
383 per_cpu(cpu_hw_events, cpu).ds = NULL;
384 kfree(ds);
385 }
386
release_ds_buffers(void)387 void release_ds_buffers(void)
388 {
389 int cpu;
390
391 if (!x86_pmu.bts && !x86_pmu.pebs)
392 return;
393
394 get_online_cpus();
395 for_each_online_cpu(cpu)
396 fini_debug_store_on_cpu(cpu);
397
398 for_each_possible_cpu(cpu) {
399 release_pebs_buffer(cpu);
400 release_bts_buffer(cpu);
401 release_ds_buffer(cpu);
402 }
403 put_online_cpus();
404 }
405
reserve_ds_buffers(void)406 void reserve_ds_buffers(void)
407 {
408 int bts_err = 0, pebs_err = 0;
409 int cpu;
410
411 x86_pmu.bts_active = 0;
412 x86_pmu.pebs_active = 0;
413
414 if (!x86_pmu.bts && !x86_pmu.pebs)
415 return;
416
417 if (!x86_pmu.bts)
418 bts_err = 1;
419
420 if (!x86_pmu.pebs)
421 pebs_err = 1;
422
423 get_online_cpus();
424
425 for_each_possible_cpu(cpu) {
426 if (alloc_ds_buffer(cpu)) {
427 bts_err = 1;
428 pebs_err = 1;
429 }
430
431 if (!bts_err && alloc_bts_buffer(cpu))
432 bts_err = 1;
433
434 if (!pebs_err && alloc_pebs_buffer(cpu))
435 pebs_err = 1;
436
437 if (bts_err && pebs_err)
438 break;
439 }
440
441 if (bts_err) {
442 for_each_possible_cpu(cpu)
443 release_bts_buffer(cpu);
444 }
445
446 if (pebs_err) {
447 for_each_possible_cpu(cpu)
448 release_pebs_buffer(cpu);
449 }
450
451 if (bts_err && pebs_err) {
452 for_each_possible_cpu(cpu)
453 release_ds_buffer(cpu);
454 } else {
455 if (x86_pmu.bts && !bts_err)
456 x86_pmu.bts_active = 1;
457
458 if (x86_pmu.pebs && !pebs_err)
459 x86_pmu.pebs_active = 1;
460
461 for_each_online_cpu(cpu)
462 init_debug_store_on_cpu(cpu);
463 }
464
465 put_online_cpus();
466 }
467
468 /*
469 * BTS
470 */
471
472 struct event_constraint bts_constraint =
473 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
474
intel_pmu_enable_bts(u64 config)475 void intel_pmu_enable_bts(u64 config)
476 {
477 unsigned long debugctlmsr;
478
479 debugctlmsr = get_debugctlmsr();
480
481 debugctlmsr |= DEBUGCTLMSR_TR;
482 debugctlmsr |= DEBUGCTLMSR_BTS;
483 if (config & ARCH_PERFMON_EVENTSEL_INT)
484 debugctlmsr |= DEBUGCTLMSR_BTINT;
485
486 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
487 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
488
489 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
490 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
491
492 update_debugctlmsr(debugctlmsr);
493 }
494
intel_pmu_disable_bts(void)495 void intel_pmu_disable_bts(void)
496 {
497 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
498 unsigned long debugctlmsr;
499
500 if (!cpuc->ds)
501 return;
502
503 debugctlmsr = get_debugctlmsr();
504
505 debugctlmsr &=
506 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
507 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
508
509 update_debugctlmsr(debugctlmsr);
510 }
511
intel_pmu_drain_bts_buffer(void)512 int intel_pmu_drain_bts_buffer(void)
513 {
514 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
515 struct debug_store *ds = cpuc->ds;
516 struct bts_record {
517 u64 from;
518 u64 to;
519 u64 flags;
520 };
521 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
522 struct bts_record *at, *base, *top;
523 struct perf_output_handle handle;
524 struct perf_event_header header;
525 struct perf_sample_data data;
526 unsigned long skip = 0;
527 struct pt_regs regs;
528
529 if (!event)
530 return 0;
531
532 if (!x86_pmu.bts_active)
533 return 0;
534
535 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
536 top = (struct bts_record *)(unsigned long)ds->bts_index;
537
538 if (top <= base)
539 return 0;
540
541 memset(®s, 0, sizeof(regs));
542
543 ds->bts_index = ds->bts_buffer_base;
544
545 perf_sample_data_init(&data, 0, event->hw.last_period);
546
547 /*
548 * BTS leaks kernel addresses in branches across the cpl boundary,
549 * such as traps or system calls, so unless the user is asking for
550 * kernel tracing (and right now it's not possible), we'd need to
551 * filter them out. But first we need to count how many of those we
552 * have in the current batch. This is an extra O(n) pass, however,
553 * it's much faster than the other one especially considering that
554 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
555 * alloc_bts_buffer()).
556 */
557 for (at = base; at < top; at++) {
558 /*
559 * Note that right now *this* BTS code only works if
560 * attr::exclude_kernel is set, but let's keep this extra
561 * check here in case that changes.
562 */
563 if (event->attr.exclude_kernel &&
564 (kernel_ip(at->from) || kernel_ip(at->to)))
565 skip++;
566 }
567
568 /*
569 * Prepare a generic sample, i.e. fill in the invariant fields.
570 * We will overwrite the from and to address before we output
571 * the sample.
572 */
573 perf_prepare_sample(&header, &data, event, ®s);
574
575 if (perf_output_begin(&handle, event, header.size *
576 (top - base - skip)))
577 return 1;
578
579 for (at = base; at < top; at++) {
580 /* Filter out any records that contain kernel addresses. */
581 if (event->attr.exclude_kernel &&
582 (kernel_ip(at->from) || kernel_ip(at->to)))
583 continue;
584
585 data.ip = at->from;
586 data.addr = at->to;
587
588 perf_output_sample(&handle, &header, &data, event);
589 }
590
591 perf_output_end(&handle);
592
593 /* There's new data available. */
594 event->hw.interrupts++;
595 event->pending_kill = POLL_IN;
596 return 1;
597 }
598
intel_pmu_drain_pebs_buffer(void)599 static inline void intel_pmu_drain_pebs_buffer(void)
600 {
601 struct pt_regs regs;
602
603 x86_pmu.drain_pebs(®s);
604 }
605
intel_pmu_pebs_sched_task(struct perf_event_context * ctx,bool sched_in)606 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
607 {
608 if (!sched_in)
609 intel_pmu_drain_pebs_buffer();
610 }
611
612 /*
613 * PEBS
614 */
615 struct event_constraint intel_core2_pebs_event_constraints[] = {
616 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
617 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
618 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
619 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
620 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
621 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
622 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
623 EVENT_CONSTRAINT_END
624 };
625
626 struct event_constraint intel_atom_pebs_event_constraints[] = {
627 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
628 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
629 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
630 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
631 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
632 EVENT_CONSTRAINT_END
633 };
634
635 struct event_constraint intel_slm_pebs_event_constraints[] = {
636 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
637 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
638 /* Allow all events as PEBS with no flags */
639 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
640 EVENT_CONSTRAINT_END
641 };
642
643 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
644 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
645 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
646 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
647 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
648 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
649 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
650 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
651 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
652 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
653 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
654 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
655 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
656 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
657 EVENT_CONSTRAINT_END
658 };
659
660 struct event_constraint intel_westmere_pebs_event_constraints[] = {
661 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
662 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
663 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
664 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
665 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
666 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
667 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
668 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
669 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
670 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
671 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
672 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
673 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
674 EVENT_CONSTRAINT_END
675 };
676
677 struct event_constraint intel_snb_pebs_event_constraints[] = {
678 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
679 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
680 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
681 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
682 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
683 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
684 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
685 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
686 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
687 /* Allow all events as PEBS with no flags */
688 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
689 EVENT_CONSTRAINT_END
690 };
691
692 struct event_constraint intel_ivb_pebs_event_constraints[] = {
693 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
694 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
695 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
696 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
697 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
698 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
699 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
700 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
701 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
702 /* Allow all events as PEBS with no flags */
703 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
704 EVENT_CONSTRAINT_END
705 };
706
707 struct event_constraint intel_hsw_pebs_event_constraints[] = {
708 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
709 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
710 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
711 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
712 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
713 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
714 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
715 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
716 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
717 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
718 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
719 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
720 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
721 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
722 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
723 /* Allow all events as PEBS with no flags */
724 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
725 EVENT_CONSTRAINT_END
726 };
727
728 struct event_constraint intel_skl_pebs_event_constraints[] = {
729 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
730 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
731 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
732 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
733 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
734 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
735 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
736 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
737 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
738 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
739 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
740 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
741 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
742 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
743 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
744 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
745 /* Allow all events as PEBS with no flags */
746 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
747 EVENT_CONSTRAINT_END
748 };
749
intel_pebs_constraints(struct perf_event * event)750 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
751 {
752 struct event_constraint *c;
753
754 if (!event->attr.precise_ip)
755 return NULL;
756
757 if (x86_pmu.pebs_constraints) {
758 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
759 if ((event->hw.config & c->cmask) == c->code) {
760 event->hw.flags |= c->flags;
761 return c;
762 }
763 }
764 }
765
766 return &emptyconstraint;
767 }
768
pebs_is_enabled(struct cpu_hw_events * cpuc)769 static inline bool pebs_is_enabled(struct cpu_hw_events *cpuc)
770 {
771 return (cpuc->pebs_enabled & ((1ULL << MAX_PEBS_EVENTS) - 1));
772 }
773
intel_pmu_pebs_enable(struct perf_event * event)774 void intel_pmu_pebs_enable(struct perf_event *event)
775 {
776 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
777 struct hw_perf_event *hwc = &event->hw;
778 struct debug_store *ds = cpuc->ds;
779 bool first_pebs;
780 u64 threshold;
781
782 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
783
784 first_pebs = !pebs_is_enabled(cpuc);
785 cpuc->pebs_enabled |= 1ULL << hwc->idx;
786
787 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
788 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
789 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
790 cpuc->pebs_enabled |= 1ULL << 63;
791
792 /*
793 * When the event is constrained enough we can use a larger
794 * threshold and run the event with less frequent PMI.
795 */
796 if (hwc->flags & PERF_X86_EVENT_FREERUNNING) {
797 threshold = ds->pebs_absolute_maximum -
798 x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
799
800 if (first_pebs)
801 perf_sched_cb_inc(event->ctx->pmu);
802 } else {
803 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
804
805 /*
806 * If not all events can use larger buffer,
807 * roll back to threshold = 1
808 */
809 if (!first_pebs &&
810 (ds->pebs_interrupt_threshold > threshold))
811 perf_sched_cb_dec(event->ctx->pmu);
812 }
813
814 /* Use auto-reload if possible to save a MSR write in the PMI */
815 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
816 ds->pebs_event_reset[hwc->idx] =
817 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
818 }
819
820 if (first_pebs || ds->pebs_interrupt_threshold > threshold)
821 ds->pebs_interrupt_threshold = threshold;
822 }
823
intel_pmu_pebs_disable(struct perf_event * event)824 void intel_pmu_pebs_disable(struct perf_event *event)
825 {
826 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
827 struct hw_perf_event *hwc = &event->hw;
828 struct debug_store *ds = cpuc->ds;
829 bool large_pebs = ds->pebs_interrupt_threshold >
830 ds->pebs_buffer_base + x86_pmu.pebs_record_size;
831
832 if (large_pebs)
833 intel_pmu_drain_pebs_buffer();
834
835 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
836
837 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
838 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
839 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
840 cpuc->pebs_enabled &= ~(1ULL << 63);
841
842 if (large_pebs && !pebs_is_enabled(cpuc))
843 perf_sched_cb_dec(event->ctx->pmu);
844
845 if (cpuc->enabled)
846 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
847
848 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
849 }
850
intel_pmu_pebs_enable_all(void)851 void intel_pmu_pebs_enable_all(void)
852 {
853 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
854
855 if (cpuc->pebs_enabled)
856 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
857 }
858
intel_pmu_pebs_disable_all(void)859 void intel_pmu_pebs_disable_all(void)
860 {
861 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
862
863 if (cpuc->pebs_enabled)
864 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
865 }
866
intel_pmu_pebs_fixup_ip(struct pt_regs * regs)867 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
868 {
869 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
870 unsigned long from = cpuc->lbr_entries[0].from;
871 unsigned long old_to, to = cpuc->lbr_entries[0].to;
872 unsigned long ip = regs->ip;
873 int is_64bit = 0;
874 void *kaddr;
875 int size;
876
877 /*
878 * We don't need to fixup if the PEBS assist is fault like
879 */
880 if (!x86_pmu.intel_cap.pebs_trap)
881 return 1;
882
883 /*
884 * No LBR entry, no basic block, no rewinding
885 */
886 if (!cpuc->lbr_stack.nr || !from || !to)
887 return 0;
888
889 /*
890 * Basic blocks should never cross user/kernel boundaries
891 */
892 if (kernel_ip(ip) != kernel_ip(to))
893 return 0;
894
895 /*
896 * unsigned math, either ip is before the start (impossible) or
897 * the basic block is larger than 1 page (sanity)
898 */
899 if ((ip - to) > PEBS_FIXUP_SIZE)
900 return 0;
901
902 /*
903 * We sampled a branch insn, rewind using the LBR stack
904 */
905 if (ip == to) {
906 set_linear_ip(regs, from);
907 return 1;
908 }
909
910 size = ip - to;
911 if (!kernel_ip(ip)) {
912 int bytes;
913 u8 *buf = this_cpu_read(insn_buffer);
914
915 /* 'size' must fit our buffer, see above */
916 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
917 if (bytes != 0)
918 return 0;
919
920 kaddr = buf;
921 } else {
922 kaddr = (void *)to;
923 }
924
925 do {
926 struct insn insn;
927
928 old_to = to;
929
930 #ifdef CONFIG_X86_64
931 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
932 #endif
933 insn_init(&insn, kaddr, size, is_64bit);
934 insn_get_length(&insn);
935 /*
936 * Make sure there was not a problem decoding the
937 * instruction and getting the length. This is
938 * doubly important because we have an infinite
939 * loop if insn.length=0.
940 */
941 if (!insn.length)
942 break;
943
944 to += insn.length;
945 kaddr += insn.length;
946 size -= insn.length;
947 } while (to < ip);
948
949 if (to == ip) {
950 set_linear_ip(regs, old_to);
951 return 1;
952 }
953
954 /*
955 * Even though we decoded the basic block, the instruction stream
956 * never matched the given IP, either the TO or the IP got corrupted.
957 */
958 return 0;
959 }
960
intel_hsw_weight(struct pebs_record_skl * pebs)961 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
962 {
963 if (pebs->tsx_tuning) {
964 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
965 return tsx.cycles_last_block;
966 }
967 return 0;
968 }
969
intel_hsw_transaction(struct pebs_record_skl * pebs)970 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
971 {
972 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
973
974 /* For RTM XABORTs also log the abort code from AX */
975 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
976 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
977 return txn;
978 }
979
setup_pebs_sample_data(struct perf_event * event,struct pt_regs * iregs,void * __pebs,struct perf_sample_data * data,struct pt_regs * regs)980 static void setup_pebs_sample_data(struct perf_event *event,
981 struct pt_regs *iregs, void *__pebs,
982 struct perf_sample_data *data,
983 struct pt_regs *regs)
984 {
985 #define PERF_X86_EVENT_PEBS_HSW_PREC \
986 (PERF_X86_EVENT_PEBS_ST_HSW | \
987 PERF_X86_EVENT_PEBS_LD_HSW | \
988 PERF_X86_EVENT_PEBS_NA_HSW)
989 /*
990 * We cast to the biggest pebs_record but are careful not to
991 * unconditionally access the 'extra' entries.
992 */
993 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
994 struct pebs_record_skl *pebs = __pebs;
995 u64 sample_type;
996 int fll, fst, dsrc;
997 int fl = event->hw.flags;
998
999 if (pebs == NULL)
1000 return;
1001
1002 sample_type = event->attr.sample_type;
1003 dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
1004
1005 fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
1006 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1007
1008 perf_sample_data_init(data, 0, event->hw.last_period);
1009
1010 data->period = event->hw.last_period;
1011
1012 /*
1013 * Use latency for weight (only avail with PEBS-LL)
1014 */
1015 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
1016 data->weight = pebs->lat;
1017
1018 /*
1019 * data.data_src encodes the data source
1020 */
1021 if (dsrc) {
1022 u64 val = PERF_MEM_NA;
1023 if (fll)
1024 val = load_latency_data(pebs->dse);
1025 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1026 val = precise_datala_hsw(event, pebs->dse);
1027 else if (fst)
1028 val = precise_store_data(pebs->dse);
1029 data->data_src.val = val;
1030 }
1031
1032 /*
1033 * We use the interrupt regs as a base because the PEBS record
1034 * does not contain a full regs set, specifically it seems to
1035 * lack segment descriptors, which get used by things like
1036 * user_mode().
1037 *
1038 * In the simple case fix up only the IP and BP,SP regs, for
1039 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
1040 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
1041 */
1042 *regs = *iregs;
1043 regs->flags = pebs->flags;
1044 set_linear_ip(regs, pebs->ip);
1045 regs->bp = pebs->bp;
1046 regs->sp = pebs->sp;
1047
1048 if (sample_type & PERF_SAMPLE_REGS_INTR) {
1049 regs->ax = pebs->ax;
1050 regs->bx = pebs->bx;
1051 regs->cx = pebs->cx;
1052 regs->dx = pebs->dx;
1053 regs->si = pebs->si;
1054 regs->di = pebs->di;
1055 regs->bp = pebs->bp;
1056 regs->sp = pebs->sp;
1057
1058 regs->flags = pebs->flags;
1059 #ifndef CONFIG_X86_32
1060 regs->r8 = pebs->r8;
1061 regs->r9 = pebs->r9;
1062 regs->r10 = pebs->r10;
1063 regs->r11 = pebs->r11;
1064 regs->r12 = pebs->r12;
1065 regs->r13 = pebs->r13;
1066 regs->r14 = pebs->r14;
1067 regs->r15 = pebs->r15;
1068 #endif
1069 }
1070
1071 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
1072 regs->ip = pebs->real_ip;
1073 regs->flags |= PERF_EFLAGS_EXACT;
1074 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
1075 regs->flags |= PERF_EFLAGS_EXACT;
1076 else
1077 regs->flags &= ~PERF_EFLAGS_EXACT;
1078
1079 if ((sample_type & PERF_SAMPLE_ADDR) &&
1080 x86_pmu.intel_cap.pebs_format >= 1)
1081 data->addr = pebs->dla;
1082
1083 if (x86_pmu.intel_cap.pebs_format >= 2) {
1084 /* Only set the TSX weight when no memory weight. */
1085 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1086 data->weight = intel_hsw_weight(pebs);
1087
1088 if (sample_type & PERF_SAMPLE_TRANSACTION)
1089 data->txn = intel_hsw_transaction(pebs);
1090 }
1091
1092 /*
1093 * v3 supplies an accurate time stamp, so we use that
1094 * for the time stamp.
1095 *
1096 * We can only do this for the default trace clock.
1097 */
1098 if (x86_pmu.intel_cap.pebs_format >= 3 &&
1099 event->attr.use_clockid == 0)
1100 data->time = native_sched_clock_from_tsc(pebs->tsc);
1101
1102 if (has_branch_stack(event))
1103 data->br_stack = &cpuc->lbr_stack;
1104 }
1105
1106 static inline void *
get_next_pebs_record_by_bit(void * base,void * top,int bit)1107 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1108 {
1109 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1110 void *at;
1111 u64 pebs_status;
1112
1113 if (base == NULL)
1114 return NULL;
1115
1116 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1117 struct pebs_record_nhm *p = at;
1118
1119 if (test_bit(bit, (unsigned long *)&p->status)) {
1120 /* PEBS v3 has accurate status bits */
1121 if (x86_pmu.intel_cap.pebs_format >= 3)
1122 return at;
1123
1124 if (p->status == (1 << bit))
1125 return at;
1126
1127 /* clear non-PEBS bit and re-check */
1128 pebs_status = p->status & cpuc->pebs_enabled;
1129 pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
1130 if (pebs_status == (1 << bit))
1131 return at;
1132 }
1133 }
1134 return NULL;
1135 }
1136
__intel_pmu_pebs_event(struct perf_event * event,struct pt_regs * iregs,void * base,void * top,int bit,int count)1137 static void __intel_pmu_pebs_event(struct perf_event *event,
1138 struct pt_regs *iregs,
1139 void *base, void *top,
1140 int bit, int count)
1141 {
1142 struct perf_sample_data data;
1143 struct pt_regs regs;
1144 void *at = get_next_pebs_record_by_bit(base, top, bit);
1145
1146 if (!intel_pmu_save_and_restart(event) &&
1147 !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1148 return;
1149
1150 while (count > 1) {
1151 setup_pebs_sample_data(event, iregs, at, &data, ®s);
1152 perf_event_output(event, &data, ®s);
1153 at += x86_pmu.pebs_record_size;
1154 at = get_next_pebs_record_by_bit(at, top, bit);
1155 count--;
1156 }
1157
1158 setup_pebs_sample_data(event, iregs, at, &data, ®s);
1159
1160 /*
1161 * All but the last records are processed.
1162 * The last one is left to be able to call the overflow handler.
1163 */
1164 if (perf_event_overflow(event, &data, ®s)) {
1165 x86_pmu_stop(event, 0);
1166 return;
1167 }
1168
1169 }
1170
intel_pmu_drain_pebs_core(struct pt_regs * iregs)1171 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1172 {
1173 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1174 struct debug_store *ds = cpuc->ds;
1175 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1176 struct pebs_record_core *at, *top;
1177 int n;
1178
1179 if (!x86_pmu.pebs_active)
1180 return;
1181
1182 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1183 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1184
1185 /*
1186 * Whatever else happens, drain the thing
1187 */
1188 ds->pebs_index = ds->pebs_buffer_base;
1189
1190 if (!test_bit(0, cpuc->active_mask))
1191 return;
1192
1193 WARN_ON_ONCE(!event);
1194
1195 if (!event->attr.precise_ip)
1196 return;
1197
1198 n = (top - at) / x86_pmu.pebs_record_size;
1199 if (n <= 0)
1200 return;
1201
1202 __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1203 }
1204
intel_pmu_drain_pebs_nhm(struct pt_regs * iregs)1205 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1206 {
1207 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1208 struct debug_store *ds = cpuc->ds;
1209 struct perf_event *event;
1210 void *base, *at, *top;
1211 short counts[MAX_PEBS_EVENTS] = {};
1212 short error[MAX_PEBS_EVENTS] = {};
1213 int bit, i;
1214
1215 if (!x86_pmu.pebs_active)
1216 return;
1217
1218 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1219 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1220
1221 ds->pebs_index = ds->pebs_buffer_base;
1222
1223 if (unlikely(base >= top))
1224 return;
1225
1226 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1227 struct pebs_record_nhm *p = at;
1228 u64 pebs_status;
1229
1230 /* PEBS v3 has accurate status bits */
1231 if (x86_pmu.intel_cap.pebs_format >= 3) {
1232 for_each_set_bit(bit, (unsigned long *)&p->status,
1233 MAX_PEBS_EVENTS)
1234 counts[bit]++;
1235
1236 continue;
1237 }
1238
1239 pebs_status = p->status & cpuc->pebs_enabled;
1240 pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
1241
1242 bit = find_first_bit((unsigned long *)&pebs_status,
1243 x86_pmu.max_pebs_events);
1244 if (WARN(bit >= x86_pmu.max_pebs_events,
1245 "PEBS record without PEBS event! status=%Lx pebs_enabled=%Lx active_mask=%Lx",
1246 (unsigned long long)p->status, (unsigned long long)cpuc->pebs_enabled,
1247 *(unsigned long long *)cpuc->active_mask))
1248 continue;
1249
1250 /*
1251 * The PEBS hardware does not deal well with the situation
1252 * when events happen near to each other and multiple bits
1253 * are set. But it should happen rarely.
1254 *
1255 * If these events include one PEBS and multiple non-PEBS
1256 * events, it doesn't impact PEBS record. The record will
1257 * be handled normally. (slow path)
1258 *
1259 * If these events include two or more PEBS events, the
1260 * records for the events can be collapsed into a single
1261 * one, and it's not possible to reconstruct all events
1262 * that caused the PEBS record. It's called collision.
1263 * If collision happened, the record will be dropped.
1264 */
1265 if (p->status != (1ULL << bit)) {
1266 for_each_set_bit(i, (unsigned long *)&pebs_status,
1267 x86_pmu.max_pebs_events)
1268 error[i]++;
1269 continue;
1270 }
1271
1272 counts[bit]++;
1273 }
1274
1275 for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1276 if ((counts[bit] == 0) && (error[bit] == 0))
1277 continue;
1278
1279 event = cpuc->events[bit];
1280 WARN_ON_ONCE(!event);
1281 WARN_ON_ONCE(!event->attr.precise_ip);
1282
1283 /* log dropped samples number */
1284 if (error[bit])
1285 perf_log_lost_samples(event, error[bit]);
1286
1287 if (counts[bit]) {
1288 __intel_pmu_pebs_event(event, iregs, base,
1289 top, bit, counts[bit]);
1290 }
1291 }
1292 }
1293
1294 /*
1295 * BTS, PEBS probe and setup
1296 */
1297
intel_ds_init(void)1298 void __init intel_ds_init(void)
1299 {
1300 /*
1301 * No support for 32bit formats
1302 */
1303 if (!boot_cpu_has(X86_FEATURE_DTES64))
1304 return;
1305
1306 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1307 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1308 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
1309 if (x86_pmu.pebs) {
1310 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1311 int format = x86_pmu.intel_cap.pebs_format;
1312
1313 switch (format) {
1314 case 0:
1315 printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1316 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1317 /*
1318 * Using >PAGE_SIZE buffers makes the WRMSR to
1319 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
1320 * mysteriously hang on Core2.
1321 *
1322 * As a workaround, we don't do this.
1323 */
1324 x86_pmu.pebs_buffer_size = PAGE_SIZE;
1325 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1326 break;
1327
1328 case 1:
1329 printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1330 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1331 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1332 break;
1333
1334 case 2:
1335 pr_cont("PEBS fmt2%c, ", pebs_type);
1336 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1337 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1338 break;
1339
1340 case 3:
1341 pr_cont("PEBS fmt3%c, ", pebs_type);
1342 x86_pmu.pebs_record_size =
1343 sizeof(struct pebs_record_skl);
1344 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1345 x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
1346 break;
1347
1348 default:
1349 printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1350 x86_pmu.pebs = 0;
1351 }
1352 }
1353 }
1354
perf_restore_debug_store(void)1355 void perf_restore_debug_store(void)
1356 {
1357 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1358
1359 if (!x86_pmu.bts && !x86_pmu.pebs)
1360 return;
1361
1362 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1363 }
1364