1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <drm/drmP.h>
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 /* Here's the desired hotplug mode */
40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
41 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
42 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
43 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
44 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
45 ADPA_CRT_HOTPLUG_ENABLE)
46
47 struct intel_crt {
48 struct intel_encoder base;
49 /* DPMS state is stored in the connector, which we need in the
50 * encoder's enable/disable callbacks */
51 struct intel_connector *connector;
52 bool force_hotplug_required;
53 u32 adpa_reg;
54 };
55
intel_encoder_to_crt(struct intel_encoder * encoder)56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
57 {
58 return container_of(encoder, struct intel_crt, base);
59 }
60
intel_attached_crt(struct drm_connector * connector)61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
62 {
63 return intel_encoder_to_crt(intel_attached_encoder(connector));
64 }
65
intel_crt_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)66 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
67 enum pipe *pipe)
68 {
69 struct drm_device *dev = encoder->base.dev;
70 struct drm_i915_private *dev_priv = dev->dev_private;
71 struct intel_crt *crt = intel_encoder_to_crt(encoder);
72 enum intel_display_power_domain power_domain;
73 u32 tmp;
74
75 power_domain = intel_display_port_power_domain(encoder);
76 if (!intel_display_power_is_enabled(dev_priv, power_domain))
77 return false;
78
79 tmp = I915_READ(crt->adpa_reg);
80
81 if (!(tmp & ADPA_DAC_ENABLE))
82 return false;
83
84 if (HAS_PCH_CPT(dev))
85 *pipe = PORT_TO_PIPE_CPT(tmp);
86 else
87 *pipe = PORT_TO_PIPE(tmp);
88
89 return true;
90 }
91
intel_crt_get_flags(struct intel_encoder * encoder)92 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
93 {
94 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
95 struct intel_crt *crt = intel_encoder_to_crt(encoder);
96 u32 tmp, flags = 0;
97
98 tmp = I915_READ(crt->adpa_reg);
99
100 if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
101 flags |= DRM_MODE_FLAG_PHSYNC;
102 else
103 flags |= DRM_MODE_FLAG_NHSYNC;
104
105 if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
106 flags |= DRM_MODE_FLAG_PVSYNC;
107 else
108 flags |= DRM_MODE_FLAG_NVSYNC;
109
110 return flags;
111 }
112
intel_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)113 static void intel_crt_get_config(struct intel_encoder *encoder,
114 struct intel_crtc_state *pipe_config)
115 {
116 struct drm_device *dev = encoder->base.dev;
117 int dotclock;
118
119 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
120
121 dotclock = pipe_config->port_clock;
122
123 if (HAS_PCH_SPLIT(dev))
124 ironlake_check_encoder_dotclock(pipe_config, dotclock);
125
126 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
127 }
128
hsw_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)129 static void hsw_crt_get_config(struct intel_encoder *encoder,
130 struct intel_crtc_state *pipe_config)
131 {
132 intel_ddi_get_config(encoder, pipe_config);
133
134 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
135 DRM_MODE_FLAG_NHSYNC |
136 DRM_MODE_FLAG_PVSYNC |
137 DRM_MODE_FLAG_NVSYNC);
138 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
139 }
140
141 /* Note: The caller is required to filter out dpms modes not supported by the
142 * platform. */
intel_crt_set_dpms(struct intel_encoder * encoder,int mode)143 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
144 {
145 struct drm_device *dev = encoder->base.dev;
146 struct drm_i915_private *dev_priv = dev->dev_private;
147 struct intel_crt *crt = intel_encoder_to_crt(encoder);
148 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
149 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
150 u32 adpa;
151
152 if (INTEL_INFO(dev)->gen >= 5)
153 adpa = ADPA_HOTPLUG_BITS;
154 else
155 adpa = 0;
156
157 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
158 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
159 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
160 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
161
162 /* For CPT allow 3 pipe config, for others just use A or B */
163 if (HAS_PCH_LPT(dev))
164 ; /* Those bits don't exist here */
165 else if (HAS_PCH_CPT(dev))
166 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
167 else if (crtc->pipe == 0)
168 adpa |= ADPA_PIPE_A_SELECT;
169 else
170 adpa |= ADPA_PIPE_B_SELECT;
171
172 if (!HAS_PCH_SPLIT(dev))
173 I915_WRITE(BCLRPAT(crtc->pipe), 0);
174
175 switch (mode) {
176 case DRM_MODE_DPMS_ON:
177 adpa |= ADPA_DAC_ENABLE;
178 break;
179 case DRM_MODE_DPMS_STANDBY:
180 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
181 break;
182 case DRM_MODE_DPMS_SUSPEND:
183 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
184 break;
185 case DRM_MODE_DPMS_OFF:
186 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
187 break;
188 }
189
190 I915_WRITE(crt->adpa_reg, adpa);
191 }
192
intel_disable_crt(struct intel_encoder * encoder)193 static void intel_disable_crt(struct intel_encoder *encoder)
194 {
195 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
196 }
197
pch_disable_crt(struct intel_encoder * encoder)198 static void pch_disable_crt(struct intel_encoder *encoder)
199 {
200 }
201
pch_post_disable_crt(struct intel_encoder * encoder)202 static void pch_post_disable_crt(struct intel_encoder *encoder)
203 {
204 intel_disable_crt(encoder);
205 }
206
intel_enable_crt(struct intel_encoder * encoder)207 static void intel_enable_crt(struct intel_encoder *encoder)
208 {
209 struct intel_crt *crt = intel_encoder_to_crt(encoder);
210
211 intel_crt_set_dpms(encoder, crt->connector->base.dpms);
212 }
213
214 static enum drm_mode_status
intel_crt_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)215 intel_crt_mode_valid(struct drm_connector *connector,
216 struct drm_display_mode *mode)
217 {
218 struct drm_device *dev = connector->dev;
219
220 int max_clock = 0;
221 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
222 return MODE_NO_DBLESCAN;
223
224 if (mode->clock < 25000)
225 return MODE_CLOCK_LOW;
226
227 if (IS_GEN2(dev))
228 max_clock = 350000;
229 else
230 max_clock = 400000;
231 if (mode->clock > max_clock)
232 return MODE_CLOCK_HIGH;
233
234 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
235 if (HAS_PCH_LPT(dev) &&
236 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
237 return MODE_CLOCK_HIGH;
238
239 return MODE_OK;
240 }
241
intel_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)242 static bool intel_crt_compute_config(struct intel_encoder *encoder,
243 struct intel_crtc_state *pipe_config)
244 {
245 struct drm_device *dev = encoder->base.dev;
246
247 if (HAS_PCH_SPLIT(dev))
248 pipe_config->has_pch_encoder = true;
249
250 /* LPT FDI RX only supports 8bpc. */
251 if (HAS_PCH_LPT(dev)) {
252 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
253 DRM_DEBUG_KMS("LPT only supports 24bpp\n");
254 return false;
255 }
256
257 pipe_config->pipe_bpp = 24;
258 }
259
260 /* FDI must always be 2.7 GHz */
261 if (HAS_DDI(dev)) {
262 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
263 pipe_config->port_clock = 135000 * 2;
264
265 pipe_config->dpll_hw_state.wrpll = 0;
266 pipe_config->dpll_hw_state.spll =
267 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
268 }
269
270 return true;
271 }
272
intel_ironlake_crt_detect_hotplug(struct drm_connector * connector)273 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
274 {
275 struct drm_device *dev = connector->dev;
276 struct intel_crt *crt = intel_attached_crt(connector);
277 struct drm_i915_private *dev_priv = dev->dev_private;
278 u32 adpa;
279 bool ret;
280
281 /* The first time through, trigger an explicit detection cycle */
282 if (crt->force_hotplug_required) {
283 bool turn_off_dac = HAS_PCH_SPLIT(dev);
284 u32 save_adpa;
285
286 crt->force_hotplug_required = 0;
287
288 save_adpa = adpa = I915_READ(crt->adpa_reg);
289 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
290
291 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
292 if (turn_off_dac)
293 adpa &= ~ADPA_DAC_ENABLE;
294
295 I915_WRITE(crt->adpa_reg, adpa);
296
297 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
298 1000))
299 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
300
301 if (turn_off_dac) {
302 I915_WRITE(crt->adpa_reg, save_adpa);
303 POSTING_READ(crt->adpa_reg);
304 }
305 }
306
307 /* Check the status to see if both blue and green are on now */
308 adpa = I915_READ(crt->adpa_reg);
309 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
310 ret = true;
311 else
312 ret = false;
313 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
314
315 return ret;
316 }
317
valleyview_crt_detect_hotplug(struct drm_connector * connector)318 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
319 {
320 struct drm_device *dev = connector->dev;
321 struct intel_crt *crt = intel_attached_crt(connector);
322 struct drm_i915_private *dev_priv = dev->dev_private;
323 u32 adpa;
324 bool ret;
325 u32 save_adpa;
326
327 save_adpa = adpa = I915_READ(crt->adpa_reg);
328 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
329
330 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
331
332 I915_WRITE(crt->adpa_reg, adpa);
333
334 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
335 1000)) {
336 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
337 I915_WRITE(crt->adpa_reg, save_adpa);
338 }
339
340 /* Check the status to see if both blue and green are on now */
341 adpa = I915_READ(crt->adpa_reg);
342 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
343 ret = true;
344 else
345 ret = false;
346
347 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
348
349 return ret;
350 }
351
352 /**
353 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
354 *
355 * Not for i915G/i915GM
356 *
357 * \return true if CRT is connected.
358 * \return false if CRT is disconnected.
359 */
intel_crt_detect_hotplug(struct drm_connector * connector)360 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
361 {
362 struct drm_device *dev = connector->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
364 u32 stat;
365 bool ret = false;
366 int i, tries = 0;
367
368 if (HAS_PCH_SPLIT(dev))
369 return intel_ironlake_crt_detect_hotplug(connector);
370
371 if (IS_VALLEYVIEW(dev))
372 return valleyview_crt_detect_hotplug(connector);
373
374 /*
375 * On 4 series desktop, CRT detect sequence need to be done twice
376 * to get a reliable result.
377 */
378
379 if (IS_G4X(dev) && !IS_GM45(dev))
380 tries = 2;
381 else
382 tries = 1;
383
384 for (i = 0; i < tries ; i++) {
385 /* turn on the FORCE_DETECT */
386 i915_hotplug_interrupt_update(dev_priv,
387 CRT_HOTPLUG_FORCE_DETECT,
388 CRT_HOTPLUG_FORCE_DETECT);
389 /* wait for FORCE_DETECT to go off */
390 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
391 CRT_HOTPLUG_FORCE_DETECT) == 0,
392 1000))
393 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
394 }
395
396 stat = I915_READ(PORT_HOTPLUG_STAT);
397 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
398 ret = true;
399
400 /* clear the interrupt we just generated, if any */
401 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
402
403 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
404
405 return ret;
406 }
407
intel_crt_get_edid(struct drm_connector * connector,struct i2c_adapter * i2c)408 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
409 struct i2c_adapter *i2c)
410 {
411 struct edid *edid;
412
413 edid = drm_get_edid(connector, i2c);
414
415 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
416 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
417 intel_gmbus_force_bit(i2c, true);
418 edid = drm_get_edid(connector, i2c);
419 intel_gmbus_force_bit(i2c, false);
420 }
421
422 return edid;
423 }
424
425 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
intel_crt_ddc_get_modes(struct drm_connector * connector,struct i2c_adapter * adapter)426 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
427 struct i2c_adapter *adapter)
428 {
429 struct edid *edid;
430 int ret;
431
432 edid = intel_crt_get_edid(connector, adapter);
433 if (!edid)
434 return 0;
435
436 ret = intel_connector_update_modes(connector, edid);
437 kfree(edid);
438
439 return ret;
440 }
441
intel_crt_detect_ddc(struct drm_connector * connector)442 static bool intel_crt_detect_ddc(struct drm_connector *connector)
443 {
444 struct intel_crt *crt = intel_attached_crt(connector);
445 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
446 struct edid *edid;
447 struct i2c_adapter *i2c;
448
449 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
450
451 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
452 edid = intel_crt_get_edid(connector, i2c);
453
454 if (edid) {
455 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
456
457 /*
458 * This may be a DVI-I connector with a shared DDC
459 * link between analog and digital outputs, so we
460 * have to check the EDID input spec of the attached device.
461 */
462 if (!is_digital) {
463 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
464 return true;
465 }
466
467 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
468 } else {
469 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
470 }
471
472 kfree(edid);
473
474 return false;
475 }
476
477 static enum drm_connector_status
intel_crt_load_detect(struct intel_crt * crt)478 intel_crt_load_detect(struct intel_crt *crt)
479 {
480 struct drm_device *dev = crt->base.base.dev;
481 struct drm_i915_private *dev_priv = dev->dev_private;
482 uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
483 uint32_t save_bclrpat;
484 uint32_t save_vtotal;
485 uint32_t vtotal, vactive;
486 uint32_t vsample;
487 uint32_t vblank, vblank_start, vblank_end;
488 uint32_t dsl;
489 uint32_t bclrpat_reg;
490 uint32_t vtotal_reg;
491 uint32_t vblank_reg;
492 uint32_t vsync_reg;
493 uint32_t pipeconf_reg;
494 uint32_t pipe_dsl_reg;
495 uint8_t st00;
496 enum drm_connector_status status;
497
498 DRM_DEBUG_KMS("starting load-detect on CRT\n");
499
500 bclrpat_reg = BCLRPAT(pipe);
501 vtotal_reg = VTOTAL(pipe);
502 vblank_reg = VBLANK(pipe);
503 vsync_reg = VSYNC(pipe);
504 pipeconf_reg = PIPECONF(pipe);
505 pipe_dsl_reg = PIPEDSL(pipe);
506
507 save_bclrpat = I915_READ(bclrpat_reg);
508 save_vtotal = I915_READ(vtotal_reg);
509 vblank = I915_READ(vblank_reg);
510
511 vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
512 vactive = (save_vtotal & 0x7ff) + 1;
513
514 vblank_start = (vblank & 0xfff) + 1;
515 vblank_end = ((vblank >> 16) & 0xfff) + 1;
516
517 /* Set the border color to purple. */
518 I915_WRITE(bclrpat_reg, 0x500050);
519
520 if (!IS_GEN2(dev)) {
521 uint32_t pipeconf = I915_READ(pipeconf_reg);
522 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
523 POSTING_READ(pipeconf_reg);
524 /* Wait for next Vblank to substitue
525 * border color for Color info */
526 intel_wait_for_vblank(dev, pipe);
527 st00 = I915_READ8(VGA_MSR_WRITE);
528 status = ((st00 & (1 << 4)) != 0) ?
529 connector_status_connected :
530 connector_status_disconnected;
531
532 I915_WRITE(pipeconf_reg, pipeconf);
533 } else {
534 bool restore_vblank = false;
535 int count, detect;
536
537 /*
538 * If there isn't any border, add some.
539 * Yes, this will flicker
540 */
541 if (vblank_start <= vactive && vblank_end >= vtotal) {
542 uint32_t vsync = I915_READ(vsync_reg);
543 uint32_t vsync_start = (vsync & 0xffff) + 1;
544
545 vblank_start = vsync_start;
546 I915_WRITE(vblank_reg,
547 (vblank_start - 1) |
548 ((vblank_end - 1) << 16));
549 restore_vblank = true;
550 }
551 /* sample in the vertical border, selecting the larger one */
552 if (vblank_start - vactive >= vtotal - vblank_end)
553 vsample = (vblank_start + vactive) >> 1;
554 else
555 vsample = (vtotal + vblank_end) >> 1;
556
557 /*
558 * Wait for the border to be displayed
559 */
560 while (I915_READ(pipe_dsl_reg) >= vactive)
561 ;
562 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
563 ;
564 /*
565 * Watch ST00 for an entire scanline
566 */
567 detect = 0;
568 count = 0;
569 do {
570 count++;
571 /* Read the ST00 VGA status register */
572 st00 = I915_READ8(VGA_MSR_WRITE);
573 if (st00 & (1 << 4))
574 detect++;
575 } while ((I915_READ(pipe_dsl_reg) == dsl));
576
577 /* restore vblank if necessary */
578 if (restore_vblank)
579 I915_WRITE(vblank_reg, vblank);
580 /*
581 * If more than 3/4 of the scanline detected a monitor,
582 * then it is assumed to be present. This works even on i830,
583 * where there isn't any way to force the border color across
584 * the screen
585 */
586 status = detect * 4 > count * 3 ?
587 connector_status_connected :
588 connector_status_disconnected;
589 }
590
591 /* Restore previous settings */
592 I915_WRITE(bclrpat_reg, save_bclrpat);
593
594 return status;
595 }
596
597 static enum drm_connector_status
intel_crt_detect(struct drm_connector * connector,bool force)598 intel_crt_detect(struct drm_connector *connector, bool force)
599 {
600 struct drm_device *dev = connector->dev;
601 struct drm_i915_private *dev_priv = dev->dev_private;
602 struct intel_crt *crt = intel_attached_crt(connector);
603 struct intel_encoder *intel_encoder = &crt->base;
604 enum intel_display_power_domain power_domain;
605 enum drm_connector_status status;
606 struct intel_load_detect_pipe tmp;
607 struct drm_modeset_acquire_ctx ctx;
608
609 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
610 connector->base.id, connector->name,
611 force);
612
613 power_domain = intel_display_port_power_domain(intel_encoder);
614 intel_display_power_get(dev_priv, power_domain);
615
616 if (I915_HAS_HOTPLUG(dev)) {
617 /* We can not rely on the HPD pin always being correctly wired
618 * up, for example many KVM do not pass it through, and so
619 * only trust an assertion that the monitor is connected.
620 */
621 if (intel_crt_detect_hotplug(connector)) {
622 DRM_DEBUG_KMS("CRT detected via hotplug\n");
623 status = connector_status_connected;
624 goto out;
625 } else
626 DRM_DEBUG_KMS("CRT not detected via hotplug\n");
627 }
628
629 if (intel_crt_detect_ddc(connector)) {
630 status = connector_status_connected;
631 goto out;
632 }
633
634 /* Load detection is broken on HPD capable machines. Whoever wants a
635 * broken monitor (without edid) to work behind a broken kvm (that fails
636 * to have the right resistors for HP detection) needs to fix this up.
637 * For now just bail out. */
638 if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
639 status = connector_status_disconnected;
640 goto out;
641 }
642
643 if (!force) {
644 status = connector->status;
645 goto out;
646 }
647
648 drm_modeset_acquire_init(&ctx, 0);
649
650 /* for pre-945g platforms use load detect */
651 if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
652 if (intel_crt_detect_ddc(connector))
653 status = connector_status_connected;
654 else if (INTEL_INFO(dev)->gen < 4)
655 status = intel_crt_load_detect(crt);
656 else
657 status = connector_status_unknown;
658 intel_release_load_detect_pipe(connector, &tmp, &ctx);
659 } else
660 status = connector_status_unknown;
661
662 drm_modeset_drop_locks(&ctx);
663 drm_modeset_acquire_fini(&ctx);
664
665 out:
666 intel_display_power_put(dev_priv, power_domain);
667 return status;
668 }
669
intel_crt_destroy(struct drm_connector * connector)670 static void intel_crt_destroy(struct drm_connector *connector)
671 {
672 drm_connector_cleanup(connector);
673 kfree(connector);
674 }
675
intel_crt_get_modes(struct drm_connector * connector)676 static int intel_crt_get_modes(struct drm_connector *connector)
677 {
678 struct drm_device *dev = connector->dev;
679 struct drm_i915_private *dev_priv = dev->dev_private;
680 struct intel_crt *crt = intel_attached_crt(connector);
681 struct intel_encoder *intel_encoder = &crt->base;
682 enum intel_display_power_domain power_domain;
683 int ret;
684 struct i2c_adapter *i2c;
685
686 power_domain = intel_display_port_power_domain(intel_encoder);
687 intel_display_power_get(dev_priv, power_domain);
688
689 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
690 ret = intel_crt_ddc_get_modes(connector, i2c);
691 if (ret || !IS_G4X(dev))
692 goto out;
693
694 /* Try to probe digital port for output in DVI-I -> VGA mode. */
695 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
696 ret = intel_crt_ddc_get_modes(connector, i2c);
697
698 out:
699 intel_display_power_put(dev_priv, power_domain);
700
701 return ret;
702 }
703
intel_crt_set_property(struct drm_connector * connector,struct drm_property * property,uint64_t value)704 static int intel_crt_set_property(struct drm_connector *connector,
705 struct drm_property *property,
706 uint64_t value)
707 {
708 return 0;
709 }
710
intel_crt_reset(struct drm_connector * connector)711 static void intel_crt_reset(struct drm_connector *connector)
712 {
713 struct drm_device *dev = connector->dev;
714 struct drm_i915_private *dev_priv = dev->dev_private;
715 struct intel_crt *crt = intel_attached_crt(connector);
716
717 if (INTEL_INFO(dev)->gen >= 5) {
718 u32 adpa;
719
720 adpa = I915_READ(crt->adpa_reg);
721 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
722 adpa |= ADPA_HOTPLUG_BITS;
723 I915_WRITE(crt->adpa_reg, adpa);
724 POSTING_READ(crt->adpa_reg);
725
726 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
727 crt->force_hotplug_required = 1;
728 }
729
730 }
731
732 /*
733 * Routines for controlling stuff on the analog port
734 */
735
736 static const struct drm_connector_funcs intel_crt_connector_funcs = {
737 .reset = intel_crt_reset,
738 .dpms = drm_atomic_helper_connector_dpms,
739 .detect = intel_crt_detect,
740 .fill_modes = drm_helper_probe_single_connector_modes,
741 .destroy = intel_crt_destroy,
742 .set_property = intel_crt_set_property,
743 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
744 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
745 .atomic_get_property = intel_connector_atomic_get_property,
746 };
747
748 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
749 .mode_valid = intel_crt_mode_valid,
750 .get_modes = intel_crt_get_modes,
751 .best_encoder = intel_best_encoder,
752 };
753
754 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
755 .destroy = intel_encoder_destroy,
756 };
757
intel_no_crt_dmi_callback(const struct dmi_system_id * id)758 static int intel_no_crt_dmi_callback(const struct dmi_system_id *id)
759 {
760 DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
761 return 1;
762 }
763
764 static const struct dmi_system_id intel_no_crt[] = {
765 {
766 .callback = intel_no_crt_dmi_callback,
767 .ident = "ACER ZGB",
768 .matches = {
769 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
770 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
771 },
772 },
773 {
774 .callback = intel_no_crt_dmi_callback,
775 .ident = "DELL XPS 8700",
776 .matches = {
777 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
778 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"),
779 },
780 },
781 { }
782 };
783
intel_crt_init(struct drm_device * dev)784 void intel_crt_init(struct drm_device *dev)
785 {
786 struct drm_connector *connector;
787 struct intel_crt *crt;
788 struct intel_connector *intel_connector;
789 struct drm_i915_private *dev_priv = dev->dev_private;
790
791 /* Skip machines without VGA that falsely report hotplug events */
792 if (dmi_check_system(intel_no_crt))
793 return;
794
795 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
796 if (!crt)
797 return;
798
799 intel_connector = intel_connector_alloc();
800 if (!intel_connector) {
801 kfree(crt);
802 return;
803 }
804
805 connector = &intel_connector->base;
806 crt->connector = intel_connector;
807 drm_connector_init(dev, &intel_connector->base,
808 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
809
810 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
811 DRM_MODE_ENCODER_DAC);
812
813 intel_connector_attach_encoder(intel_connector, &crt->base);
814
815 crt->base.type = INTEL_OUTPUT_ANALOG;
816 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
817 if (IS_I830(dev))
818 crt->base.crtc_mask = (1 << 0);
819 else
820 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
821
822 if (IS_GEN2(dev))
823 connector->interlace_allowed = 0;
824 else
825 connector->interlace_allowed = 1;
826 connector->doublescan_allowed = 0;
827
828 if (HAS_PCH_SPLIT(dev))
829 crt->adpa_reg = PCH_ADPA;
830 else if (IS_VALLEYVIEW(dev))
831 crt->adpa_reg = VLV_ADPA;
832 else
833 crt->adpa_reg = ADPA;
834
835 crt->base.compute_config = intel_crt_compute_config;
836 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) {
837 crt->base.disable = pch_disable_crt;
838 crt->base.post_disable = pch_post_disable_crt;
839 } else {
840 crt->base.disable = intel_disable_crt;
841 }
842 crt->base.enable = intel_enable_crt;
843 if (I915_HAS_HOTPLUG(dev))
844 crt->base.hpd_pin = HPD_CRT;
845 if (HAS_DDI(dev)) {
846 crt->base.get_config = hsw_crt_get_config;
847 crt->base.get_hw_state = intel_ddi_get_hw_state;
848 } else {
849 crt->base.get_config = intel_crt_get_config;
850 crt->base.get_hw_state = intel_crt_get_hw_state;
851 }
852 intel_connector->get_hw_state = intel_connector_get_hw_state;
853 intel_connector->unregister = intel_connector_unregister;
854
855 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
856
857 drm_connector_register(connector);
858
859 if (!I915_HAS_HOTPLUG(dev))
860 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
861
862 /*
863 * Configure the automatic hotplug detection stuff
864 */
865 crt->force_hotplug_required = 0;
866
867 /*
868 * TODO: find a proper way to discover whether we need to set the the
869 * polarity and link reversal bits or not, instead of relying on the
870 * BIOS.
871 */
872 if (HAS_PCH_LPT(dev)) {
873 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
874 FDI_RX_LINK_REVERSAL_OVERRIDE;
875
876 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
877 }
878
879 intel_crt_reset(connector);
880 }
881