1 /* Intel(R) Gigabit Ethernet Linux driver
2  * Copyright(c) 2007-2014 Intel Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License along with
14  * this program; if not, see <http://www.gnu.org/licenses/>.
15  *
16  * The full GNU General Public License is included in this distribution in
17  * the file called "COPYING".
18  *
19  * Contact Information:
20  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22  */
23 
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25 
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/bitops.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pagemap.h>
32 #include <linux/netdevice.h>
33 #include <linux/ipv6.h>
34 #include <linux/slab.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if.h>
41 #include <linux/if_vlan.h>
42 #include <linux/pci.h>
43 #include <linux/pci-aspm.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/ip.h>
47 #include <linux/tcp.h>
48 #include <linux/sctp.h>
49 #include <linux/if_ether.h>
50 #include <linux/aer.h>
51 #include <linux/prefetch.h>
52 #include <linux/pm_runtime.h>
53 #ifdef CONFIG_IGB_DCA
54 #include <linux/dca.h>
55 #endif
56 #include <linux/i2c.h>
57 #include "igb.h"
58 
59 #define MAJ 5
60 #define MIN 2
61 #define BUILD 15
62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
63 __stringify(BUILD) "-k"
64 char igb_driver_name[] = "igb";
65 char igb_driver_version[] = DRV_VERSION;
66 static const char igb_driver_string[] =
67 				"Intel(R) Gigabit Ethernet Network Driver";
68 static const char igb_copyright[] =
69 				"Copyright (c) 2007-2014 Intel Corporation.";
70 
71 static const struct e1000_info *igb_info_tbl[] = {
72 	[board_82575] = &e1000_82575_info,
73 };
74 
75 static const struct pci_device_id igb_pci_tbl[] = {
76 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
79 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
84 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
86 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
90 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
92 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
93 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
96 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
98 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
100 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
101 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
102 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
103 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
105 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
106 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
107 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
108 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 	/* required last entry */
112 	{0, }
113 };
114 
115 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116 
117 static int igb_setup_all_tx_resources(struct igb_adapter *);
118 static int igb_setup_all_rx_resources(struct igb_adapter *);
119 static void igb_free_all_tx_resources(struct igb_adapter *);
120 static void igb_free_all_rx_resources(struct igb_adapter *);
121 static void igb_setup_mrqc(struct igb_adapter *);
122 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
123 static void igb_remove(struct pci_dev *pdev);
124 static int igb_sw_init(struct igb_adapter *);
125 static int igb_open(struct net_device *);
126 static int igb_close(struct net_device *);
127 static void igb_configure(struct igb_adapter *);
128 static void igb_configure_tx(struct igb_adapter *);
129 static void igb_configure_rx(struct igb_adapter *);
130 static void igb_clean_all_tx_rings(struct igb_adapter *);
131 static void igb_clean_all_rx_rings(struct igb_adapter *);
132 static void igb_clean_tx_ring(struct igb_ring *);
133 static void igb_clean_rx_ring(struct igb_ring *);
134 static void igb_set_rx_mode(struct net_device *);
135 static void igb_update_phy_info(unsigned long);
136 static void igb_watchdog(unsigned long);
137 static void igb_watchdog_task(struct work_struct *);
138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 					  struct rtnl_link_stats64 *stats);
141 static int igb_change_mtu(struct net_device *, int);
142 static int igb_set_mac(struct net_device *, void *);
143 static void igb_set_uta(struct igb_adapter *adapter);
144 static irqreturn_t igb_intr(int irq, void *);
145 static irqreturn_t igb_intr_msi(int irq, void *);
146 static irqreturn_t igb_msix_other(int irq, void *);
147 static irqreturn_t igb_msix_ring(int irq, void *);
148 #ifdef CONFIG_IGB_DCA
149 static void igb_update_dca(struct igb_q_vector *);
150 static void igb_setup_dca(struct igb_adapter *);
151 #endif /* CONFIG_IGB_DCA */
152 static int igb_poll(struct napi_struct *, int);
153 static bool igb_clean_tx_irq(struct igb_q_vector *);
154 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156 static void igb_tx_timeout(struct net_device *);
157 static void igb_reset_task(struct work_struct *);
158 static void igb_vlan_mode(struct net_device *netdev,
159 			  netdev_features_t features);
160 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
162 static void igb_restore_vlan(struct igb_adapter *);
163 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
164 static void igb_ping_all_vfs(struct igb_adapter *);
165 static void igb_msg_task(struct igb_adapter *);
166 static void igb_vmm_control(struct igb_adapter *);
167 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
168 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
169 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 			       int vf, u16 vlan, u8 qos);
172 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
173 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 				   bool setting);
175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 				 struct ifla_vf_info *ivi);
177 static void igb_check_vf_rate_limit(struct igb_adapter *);
178 
179 #ifdef CONFIG_PCI_IOV
180 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
181 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
182 #endif
183 
184 #ifdef CONFIG_PM
185 #ifdef CONFIG_PM_SLEEP
186 static int igb_suspend(struct device *);
187 #endif
188 static int igb_resume(struct device *);
189 static int igb_runtime_suspend(struct device *dev);
190 static int igb_runtime_resume(struct device *dev);
191 static int igb_runtime_idle(struct device *dev);
192 static const struct dev_pm_ops igb_pm_ops = {
193 	SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
194 	SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
195 			igb_runtime_idle)
196 };
197 #endif
198 static void igb_shutdown(struct pci_dev *);
199 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
200 #ifdef CONFIG_IGB_DCA
201 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
202 static struct notifier_block dca_notifier = {
203 	.notifier_call	= igb_notify_dca,
204 	.next		= NULL,
205 	.priority	= 0
206 };
207 #endif
208 #ifdef CONFIG_NET_POLL_CONTROLLER
209 /* for netdump / net console */
210 static void igb_netpoll(struct net_device *);
211 #endif
212 #ifdef CONFIG_PCI_IOV
213 static unsigned int max_vfs;
214 module_param(max_vfs, uint, 0);
215 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
216 #endif /* CONFIG_PCI_IOV */
217 
218 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
219 		     pci_channel_state_t);
220 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
221 static void igb_io_resume(struct pci_dev *);
222 
223 static const struct pci_error_handlers igb_err_handler = {
224 	.error_detected = igb_io_error_detected,
225 	.slot_reset = igb_io_slot_reset,
226 	.resume = igb_io_resume,
227 };
228 
229 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
230 
231 static struct pci_driver igb_driver = {
232 	.name     = igb_driver_name,
233 	.id_table = igb_pci_tbl,
234 	.probe    = igb_probe,
235 	.remove   = igb_remove,
236 #ifdef CONFIG_PM
237 	.driver.pm = &igb_pm_ops,
238 #endif
239 	.shutdown = igb_shutdown,
240 	.sriov_configure = igb_pci_sriov_configure,
241 	.err_handler = &igb_err_handler
242 };
243 
244 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
245 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
246 MODULE_LICENSE("GPL");
247 MODULE_VERSION(DRV_VERSION);
248 
249 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
250 static int debug = -1;
251 module_param(debug, int, 0);
252 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
253 
254 struct igb_reg_info {
255 	u32 ofs;
256 	char *name;
257 };
258 
259 static const struct igb_reg_info igb_reg_info_tbl[] = {
260 
261 	/* General Registers */
262 	{E1000_CTRL, "CTRL"},
263 	{E1000_STATUS, "STATUS"},
264 	{E1000_CTRL_EXT, "CTRL_EXT"},
265 
266 	/* Interrupt Registers */
267 	{E1000_ICR, "ICR"},
268 
269 	/* RX Registers */
270 	{E1000_RCTL, "RCTL"},
271 	{E1000_RDLEN(0), "RDLEN"},
272 	{E1000_RDH(0), "RDH"},
273 	{E1000_RDT(0), "RDT"},
274 	{E1000_RXDCTL(0), "RXDCTL"},
275 	{E1000_RDBAL(0), "RDBAL"},
276 	{E1000_RDBAH(0), "RDBAH"},
277 
278 	/* TX Registers */
279 	{E1000_TCTL, "TCTL"},
280 	{E1000_TDBAL(0), "TDBAL"},
281 	{E1000_TDBAH(0), "TDBAH"},
282 	{E1000_TDLEN(0), "TDLEN"},
283 	{E1000_TDH(0), "TDH"},
284 	{E1000_TDT(0), "TDT"},
285 	{E1000_TXDCTL(0), "TXDCTL"},
286 	{E1000_TDFH, "TDFH"},
287 	{E1000_TDFT, "TDFT"},
288 	{E1000_TDFHS, "TDFHS"},
289 	{E1000_TDFPC, "TDFPC"},
290 
291 	/* List Terminator */
292 	{}
293 };
294 
295 /* igb_regdump - register printout routine */
igb_regdump(struct e1000_hw * hw,struct igb_reg_info * reginfo)296 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
297 {
298 	int n = 0;
299 	char rname[16];
300 	u32 regs[8];
301 
302 	switch (reginfo->ofs) {
303 	case E1000_RDLEN(0):
304 		for (n = 0; n < 4; n++)
305 			regs[n] = rd32(E1000_RDLEN(n));
306 		break;
307 	case E1000_RDH(0):
308 		for (n = 0; n < 4; n++)
309 			regs[n] = rd32(E1000_RDH(n));
310 		break;
311 	case E1000_RDT(0):
312 		for (n = 0; n < 4; n++)
313 			regs[n] = rd32(E1000_RDT(n));
314 		break;
315 	case E1000_RXDCTL(0):
316 		for (n = 0; n < 4; n++)
317 			regs[n] = rd32(E1000_RXDCTL(n));
318 		break;
319 	case E1000_RDBAL(0):
320 		for (n = 0; n < 4; n++)
321 			regs[n] = rd32(E1000_RDBAL(n));
322 		break;
323 	case E1000_RDBAH(0):
324 		for (n = 0; n < 4; n++)
325 			regs[n] = rd32(E1000_RDBAH(n));
326 		break;
327 	case E1000_TDBAL(0):
328 		for (n = 0; n < 4; n++)
329 			regs[n] = rd32(E1000_RDBAL(n));
330 		break;
331 	case E1000_TDBAH(0):
332 		for (n = 0; n < 4; n++)
333 			regs[n] = rd32(E1000_TDBAH(n));
334 		break;
335 	case E1000_TDLEN(0):
336 		for (n = 0; n < 4; n++)
337 			regs[n] = rd32(E1000_TDLEN(n));
338 		break;
339 	case E1000_TDH(0):
340 		for (n = 0; n < 4; n++)
341 			regs[n] = rd32(E1000_TDH(n));
342 		break;
343 	case E1000_TDT(0):
344 		for (n = 0; n < 4; n++)
345 			regs[n] = rd32(E1000_TDT(n));
346 		break;
347 	case E1000_TXDCTL(0):
348 		for (n = 0; n < 4; n++)
349 			regs[n] = rd32(E1000_TXDCTL(n));
350 		break;
351 	default:
352 		pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
353 		return;
354 	}
355 
356 	snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
357 	pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
358 		regs[2], regs[3]);
359 }
360 
361 /* igb_dump - Print registers, Tx-rings and Rx-rings */
igb_dump(struct igb_adapter * adapter)362 static void igb_dump(struct igb_adapter *adapter)
363 {
364 	struct net_device *netdev = adapter->netdev;
365 	struct e1000_hw *hw = &adapter->hw;
366 	struct igb_reg_info *reginfo;
367 	struct igb_ring *tx_ring;
368 	union e1000_adv_tx_desc *tx_desc;
369 	struct my_u0 { u64 a; u64 b; } *u0;
370 	struct igb_ring *rx_ring;
371 	union e1000_adv_rx_desc *rx_desc;
372 	u32 staterr;
373 	u16 i, n;
374 
375 	if (!netif_msg_hw(adapter))
376 		return;
377 
378 	/* Print netdevice Info */
379 	if (netdev) {
380 		dev_info(&adapter->pdev->dev, "Net device Info\n");
381 		pr_info("Device Name     state            trans_start      last_rx\n");
382 		pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
383 			netdev->state, netdev->trans_start, netdev->last_rx);
384 	}
385 
386 	/* Print Registers */
387 	dev_info(&adapter->pdev->dev, "Register Dump\n");
388 	pr_info(" Register Name   Value\n");
389 	for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
390 	     reginfo->name; reginfo++) {
391 		igb_regdump(hw, reginfo);
392 	}
393 
394 	/* Print TX Ring Summary */
395 	if (!netdev || !netif_running(netdev))
396 		goto exit;
397 
398 	dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
399 	pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
400 	for (n = 0; n < adapter->num_tx_queues; n++) {
401 		struct igb_tx_buffer *buffer_info;
402 		tx_ring = adapter->tx_ring[n];
403 		buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
404 		pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
405 			n, tx_ring->next_to_use, tx_ring->next_to_clean,
406 			(u64)dma_unmap_addr(buffer_info, dma),
407 			dma_unmap_len(buffer_info, len),
408 			buffer_info->next_to_watch,
409 			(u64)buffer_info->time_stamp);
410 	}
411 
412 	/* Print TX Rings */
413 	if (!netif_msg_tx_done(adapter))
414 		goto rx_ring_summary;
415 
416 	dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
417 
418 	/* Transmit Descriptor Formats
419 	 *
420 	 * Advanced Transmit Descriptor
421 	 *   +--------------------------------------------------------------+
422 	 * 0 |         Buffer Address [63:0]                                |
423 	 *   +--------------------------------------------------------------+
424 	 * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
425 	 *   +--------------------------------------------------------------+
426 	 *   63      46 45    40 39 38 36 35 32 31   24             15       0
427 	 */
428 
429 	for (n = 0; n < adapter->num_tx_queues; n++) {
430 		tx_ring = adapter->tx_ring[n];
431 		pr_info("------------------------------------\n");
432 		pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
433 		pr_info("------------------------------------\n");
434 		pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] [bi->dma       ] leng  ntw timestamp        bi->skb\n");
435 
436 		for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
437 			const char *next_desc;
438 			struct igb_tx_buffer *buffer_info;
439 			tx_desc = IGB_TX_DESC(tx_ring, i);
440 			buffer_info = &tx_ring->tx_buffer_info[i];
441 			u0 = (struct my_u0 *)tx_desc;
442 			if (i == tx_ring->next_to_use &&
443 			    i == tx_ring->next_to_clean)
444 				next_desc = " NTC/U";
445 			else if (i == tx_ring->next_to_use)
446 				next_desc = " NTU";
447 			else if (i == tx_ring->next_to_clean)
448 				next_desc = " NTC";
449 			else
450 				next_desc = "";
451 
452 			pr_info("T [0x%03X]    %016llX %016llX %016llX %04X  %p %016llX %p%s\n",
453 				i, le64_to_cpu(u0->a),
454 				le64_to_cpu(u0->b),
455 				(u64)dma_unmap_addr(buffer_info, dma),
456 				dma_unmap_len(buffer_info, len),
457 				buffer_info->next_to_watch,
458 				(u64)buffer_info->time_stamp,
459 				buffer_info->skb, next_desc);
460 
461 			if (netif_msg_pktdata(adapter) && buffer_info->skb)
462 				print_hex_dump(KERN_INFO, "",
463 					DUMP_PREFIX_ADDRESS,
464 					16, 1, buffer_info->skb->data,
465 					dma_unmap_len(buffer_info, len),
466 					true);
467 		}
468 	}
469 
470 	/* Print RX Rings Summary */
471 rx_ring_summary:
472 	dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
473 	pr_info("Queue [NTU] [NTC]\n");
474 	for (n = 0; n < adapter->num_rx_queues; n++) {
475 		rx_ring = adapter->rx_ring[n];
476 		pr_info(" %5d %5X %5X\n",
477 			n, rx_ring->next_to_use, rx_ring->next_to_clean);
478 	}
479 
480 	/* Print RX Rings */
481 	if (!netif_msg_rx_status(adapter))
482 		goto exit;
483 
484 	dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
485 
486 	/* Advanced Receive Descriptor (Read) Format
487 	 *    63                                           1        0
488 	 *    +-----------------------------------------------------+
489 	 *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
490 	 *    +----------------------------------------------+------+
491 	 *  8 |       Header Buffer Address [63:1]           |  DD  |
492 	 *    +-----------------------------------------------------+
493 	 *
494 	 *
495 	 * Advanced Receive Descriptor (Write-Back) Format
496 	 *
497 	 *   63       48 47    32 31  30      21 20 17 16   4 3     0
498 	 *   +------------------------------------------------------+
499 	 * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
500 	 *   | Checksum   Ident  |   |           |    | Type | Type |
501 	 *   +------------------------------------------------------+
502 	 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
503 	 *   +------------------------------------------------------+
504 	 *   63       48 47    32 31            20 19               0
505 	 */
506 
507 	for (n = 0; n < adapter->num_rx_queues; n++) {
508 		rx_ring = adapter->rx_ring[n];
509 		pr_info("------------------------------------\n");
510 		pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
511 		pr_info("------------------------------------\n");
512 		pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] [bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
513 		pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
514 
515 		for (i = 0; i < rx_ring->count; i++) {
516 			const char *next_desc;
517 			struct igb_rx_buffer *buffer_info;
518 			buffer_info = &rx_ring->rx_buffer_info[i];
519 			rx_desc = IGB_RX_DESC(rx_ring, i);
520 			u0 = (struct my_u0 *)rx_desc;
521 			staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
522 
523 			if (i == rx_ring->next_to_use)
524 				next_desc = " NTU";
525 			else if (i == rx_ring->next_to_clean)
526 				next_desc = " NTC";
527 			else
528 				next_desc = "";
529 
530 			if (staterr & E1000_RXD_STAT_DD) {
531 				/* Descriptor Done */
532 				pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
533 					"RWB", i,
534 					le64_to_cpu(u0->a),
535 					le64_to_cpu(u0->b),
536 					next_desc);
537 			} else {
538 				pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
539 					"R  ", i,
540 					le64_to_cpu(u0->a),
541 					le64_to_cpu(u0->b),
542 					(u64)buffer_info->dma,
543 					next_desc);
544 
545 				if (netif_msg_pktdata(adapter) &&
546 				    buffer_info->dma && buffer_info->page) {
547 					print_hex_dump(KERN_INFO, "",
548 					  DUMP_PREFIX_ADDRESS,
549 					  16, 1,
550 					  page_address(buffer_info->page) +
551 						      buffer_info->page_offset,
552 					  IGB_RX_BUFSZ, true);
553 				}
554 			}
555 		}
556 	}
557 
558 exit:
559 	return;
560 }
561 
562 /**
563  *  igb_get_i2c_data - Reads the I2C SDA data bit
564  *  @hw: pointer to hardware structure
565  *  @i2cctl: Current value of I2CCTL register
566  *
567  *  Returns the I2C data bit value
568  **/
igb_get_i2c_data(void * data)569 static int igb_get_i2c_data(void *data)
570 {
571 	struct igb_adapter *adapter = (struct igb_adapter *)data;
572 	struct e1000_hw *hw = &adapter->hw;
573 	s32 i2cctl = rd32(E1000_I2CPARAMS);
574 
575 	return !!(i2cctl & E1000_I2C_DATA_IN);
576 }
577 
578 /**
579  *  igb_set_i2c_data - Sets the I2C data bit
580  *  @data: pointer to hardware structure
581  *  @state: I2C data value (0 or 1) to set
582  *
583  *  Sets the I2C data bit
584  **/
igb_set_i2c_data(void * data,int state)585 static void igb_set_i2c_data(void *data, int state)
586 {
587 	struct igb_adapter *adapter = (struct igb_adapter *)data;
588 	struct e1000_hw *hw = &adapter->hw;
589 	s32 i2cctl = rd32(E1000_I2CPARAMS);
590 
591 	if (state)
592 		i2cctl |= E1000_I2C_DATA_OUT;
593 	else
594 		i2cctl &= ~E1000_I2C_DATA_OUT;
595 
596 	i2cctl &= ~E1000_I2C_DATA_OE_N;
597 	i2cctl |= E1000_I2C_CLK_OE_N;
598 	wr32(E1000_I2CPARAMS, i2cctl);
599 	wrfl();
600 
601 }
602 
603 /**
604  *  igb_set_i2c_clk - Sets the I2C SCL clock
605  *  @data: pointer to hardware structure
606  *  @state: state to set clock
607  *
608  *  Sets the I2C clock line to state
609  **/
igb_set_i2c_clk(void * data,int state)610 static void igb_set_i2c_clk(void *data, int state)
611 {
612 	struct igb_adapter *adapter = (struct igb_adapter *)data;
613 	struct e1000_hw *hw = &adapter->hw;
614 	s32 i2cctl = rd32(E1000_I2CPARAMS);
615 
616 	if (state) {
617 		i2cctl |= E1000_I2C_CLK_OUT;
618 		i2cctl &= ~E1000_I2C_CLK_OE_N;
619 	} else {
620 		i2cctl &= ~E1000_I2C_CLK_OUT;
621 		i2cctl &= ~E1000_I2C_CLK_OE_N;
622 	}
623 	wr32(E1000_I2CPARAMS, i2cctl);
624 	wrfl();
625 }
626 
627 /**
628  *  igb_get_i2c_clk - Gets the I2C SCL clock state
629  *  @data: pointer to hardware structure
630  *
631  *  Gets the I2C clock state
632  **/
igb_get_i2c_clk(void * data)633 static int igb_get_i2c_clk(void *data)
634 {
635 	struct igb_adapter *adapter = (struct igb_adapter *)data;
636 	struct e1000_hw *hw = &adapter->hw;
637 	s32 i2cctl = rd32(E1000_I2CPARAMS);
638 
639 	return !!(i2cctl & E1000_I2C_CLK_IN);
640 }
641 
642 static const struct i2c_algo_bit_data igb_i2c_algo = {
643 	.setsda		= igb_set_i2c_data,
644 	.setscl		= igb_set_i2c_clk,
645 	.getsda		= igb_get_i2c_data,
646 	.getscl		= igb_get_i2c_clk,
647 	.udelay		= 5,
648 	.timeout	= 20,
649 };
650 
651 /**
652  *  igb_get_hw_dev - return device
653  *  @hw: pointer to hardware structure
654  *
655  *  used by hardware layer to print debugging information
656  **/
igb_get_hw_dev(struct e1000_hw * hw)657 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
658 {
659 	struct igb_adapter *adapter = hw->back;
660 	return adapter->netdev;
661 }
662 
663 /**
664  *  igb_init_module - Driver Registration Routine
665  *
666  *  igb_init_module is the first routine called when the driver is
667  *  loaded. All it does is register with the PCI subsystem.
668  **/
igb_init_module(void)669 static int __init igb_init_module(void)
670 {
671 	int ret;
672 
673 	pr_info("%s - version %s\n",
674 	       igb_driver_string, igb_driver_version);
675 	pr_info("%s\n", igb_copyright);
676 
677 #ifdef CONFIG_IGB_DCA
678 	dca_register_notify(&dca_notifier);
679 #endif
680 	ret = pci_register_driver(&igb_driver);
681 	return ret;
682 }
683 
684 module_init(igb_init_module);
685 
686 /**
687  *  igb_exit_module - Driver Exit Cleanup Routine
688  *
689  *  igb_exit_module is called just before the driver is removed
690  *  from memory.
691  **/
igb_exit_module(void)692 static void __exit igb_exit_module(void)
693 {
694 #ifdef CONFIG_IGB_DCA
695 	dca_unregister_notify(&dca_notifier);
696 #endif
697 	pci_unregister_driver(&igb_driver);
698 }
699 
700 module_exit(igb_exit_module);
701 
702 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
703 /**
704  *  igb_cache_ring_register - Descriptor ring to register mapping
705  *  @adapter: board private structure to initialize
706  *
707  *  Once we know the feature-set enabled for the device, we'll cache
708  *  the register offset the descriptor ring is assigned to.
709  **/
igb_cache_ring_register(struct igb_adapter * adapter)710 static void igb_cache_ring_register(struct igb_adapter *adapter)
711 {
712 	int i = 0, j = 0;
713 	u32 rbase_offset = adapter->vfs_allocated_count;
714 
715 	switch (adapter->hw.mac.type) {
716 	case e1000_82576:
717 		/* The queues are allocated for virtualization such that VF 0
718 		 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
719 		 * In order to avoid collision we start at the first free queue
720 		 * and continue consuming queues in the same sequence
721 		 */
722 		if (adapter->vfs_allocated_count) {
723 			for (; i < adapter->rss_queues; i++)
724 				adapter->rx_ring[i]->reg_idx = rbase_offset +
725 							       Q_IDX_82576(i);
726 		}
727 		/* Fall through */
728 	case e1000_82575:
729 	case e1000_82580:
730 	case e1000_i350:
731 	case e1000_i354:
732 	case e1000_i210:
733 	case e1000_i211:
734 		/* Fall through */
735 	default:
736 		for (; i < adapter->num_rx_queues; i++)
737 			adapter->rx_ring[i]->reg_idx = rbase_offset + i;
738 		for (; j < adapter->num_tx_queues; j++)
739 			adapter->tx_ring[j]->reg_idx = rbase_offset + j;
740 		break;
741 	}
742 }
743 
igb_rd32(struct e1000_hw * hw,u32 reg)744 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
745 {
746 	struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
747 	u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
748 	u32 value = 0;
749 
750 	if (E1000_REMOVED(hw_addr))
751 		return ~value;
752 
753 	value = readl(&hw_addr[reg]);
754 
755 	/* reads should not return all F's */
756 	if (!(~value) && (!reg || !(~readl(hw_addr)))) {
757 		struct net_device *netdev = igb->netdev;
758 		hw->hw_addr = NULL;
759 		netif_device_detach(netdev);
760 		netdev_err(netdev, "PCIe link lost, device now detached\n");
761 	}
762 
763 	return value;
764 }
765 
766 /**
767  *  igb_write_ivar - configure ivar for given MSI-X vector
768  *  @hw: pointer to the HW structure
769  *  @msix_vector: vector number we are allocating to a given ring
770  *  @index: row index of IVAR register to write within IVAR table
771  *  @offset: column offset of in IVAR, should be multiple of 8
772  *
773  *  This function is intended to handle the writing of the IVAR register
774  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
775  *  each containing an cause allocation for an Rx and Tx ring, and a
776  *  variable number of rows depending on the number of queues supported.
777  **/
igb_write_ivar(struct e1000_hw * hw,int msix_vector,int index,int offset)778 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
779 			   int index, int offset)
780 {
781 	u32 ivar = array_rd32(E1000_IVAR0, index);
782 
783 	/* clear any bits that are currently set */
784 	ivar &= ~((u32)0xFF << offset);
785 
786 	/* write vector and valid bit */
787 	ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
788 
789 	array_wr32(E1000_IVAR0, index, ivar);
790 }
791 
792 #define IGB_N0_QUEUE -1
igb_assign_vector(struct igb_q_vector * q_vector,int msix_vector)793 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
794 {
795 	struct igb_adapter *adapter = q_vector->adapter;
796 	struct e1000_hw *hw = &adapter->hw;
797 	int rx_queue = IGB_N0_QUEUE;
798 	int tx_queue = IGB_N0_QUEUE;
799 	u32 msixbm = 0;
800 
801 	if (q_vector->rx.ring)
802 		rx_queue = q_vector->rx.ring->reg_idx;
803 	if (q_vector->tx.ring)
804 		tx_queue = q_vector->tx.ring->reg_idx;
805 
806 	switch (hw->mac.type) {
807 	case e1000_82575:
808 		/* The 82575 assigns vectors using a bitmask, which matches the
809 		 * bitmask for the EICR/EIMS/EIMC registers.  To assign one
810 		 * or more queues to a vector, we write the appropriate bits
811 		 * into the MSIXBM register for that vector.
812 		 */
813 		if (rx_queue > IGB_N0_QUEUE)
814 			msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
815 		if (tx_queue > IGB_N0_QUEUE)
816 			msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
817 		if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
818 			msixbm |= E1000_EIMS_OTHER;
819 		array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
820 		q_vector->eims_value = msixbm;
821 		break;
822 	case e1000_82576:
823 		/* 82576 uses a table that essentially consists of 2 columns
824 		 * with 8 rows.  The ordering is column-major so we use the
825 		 * lower 3 bits as the row index, and the 4th bit as the
826 		 * column offset.
827 		 */
828 		if (rx_queue > IGB_N0_QUEUE)
829 			igb_write_ivar(hw, msix_vector,
830 				       rx_queue & 0x7,
831 				       (rx_queue & 0x8) << 1);
832 		if (tx_queue > IGB_N0_QUEUE)
833 			igb_write_ivar(hw, msix_vector,
834 				       tx_queue & 0x7,
835 				       ((tx_queue & 0x8) << 1) + 8);
836 		q_vector->eims_value = 1 << msix_vector;
837 		break;
838 	case e1000_82580:
839 	case e1000_i350:
840 	case e1000_i354:
841 	case e1000_i210:
842 	case e1000_i211:
843 		/* On 82580 and newer adapters the scheme is similar to 82576
844 		 * however instead of ordering column-major we have things
845 		 * ordered row-major.  So we traverse the table by using
846 		 * bit 0 as the column offset, and the remaining bits as the
847 		 * row index.
848 		 */
849 		if (rx_queue > IGB_N0_QUEUE)
850 			igb_write_ivar(hw, msix_vector,
851 				       rx_queue >> 1,
852 				       (rx_queue & 0x1) << 4);
853 		if (tx_queue > IGB_N0_QUEUE)
854 			igb_write_ivar(hw, msix_vector,
855 				       tx_queue >> 1,
856 				       ((tx_queue & 0x1) << 4) + 8);
857 		q_vector->eims_value = 1 << msix_vector;
858 		break;
859 	default:
860 		BUG();
861 		break;
862 	}
863 
864 	/* add q_vector eims value to global eims_enable_mask */
865 	adapter->eims_enable_mask |= q_vector->eims_value;
866 
867 	/* configure q_vector to set itr on first interrupt */
868 	q_vector->set_itr = 1;
869 }
870 
871 /**
872  *  igb_configure_msix - Configure MSI-X hardware
873  *  @adapter: board private structure to initialize
874  *
875  *  igb_configure_msix sets up the hardware to properly
876  *  generate MSI-X interrupts.
877  **/
igb_configure_msix(struct igb_adapter * adapter)878 static void igb_configure_msix(struct igb_adapter *adapter)
879 {
880 	u32 tmp;
881 	int i, vector = 0;
882 	struct e1000_hw *hw = &adapter->hw;
883 
884 	adapter->eims_enable_mask = 0;
885 
886 	/* set vector for other causes, i.e. link changes */
887 	switch (hw->mac.type) {
888 	case e1000_82575:
889 		tmp = rd32(E1000_CTRL_EXT);
890 		/* enable MSI-X PBA support*/
891 		tmp |= E1000_CTRL_EXT_PBA_CLR;
892 
893 		/* Auto-Mask interrupts upon ICR read. */
894 		tmp |= E1000_CTRL_EXT_EIAME;
895 		tmp |= E1000_CTRL_EXT_IRCA;
896 
897 		wr32(E1000_CTRL_EXT, tmp);
898 
899 		/* enable msix_other interrupt */
900 		array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
901 		adapter->eims_other = E1000_EIMS_OTHER;
902 
903 		break;
904 
905 	case e1000_82576:
906 	case e1000_82580:
907 	case e1000_i350:
908 	case e1000_i354:
909 	case e1000_i210:
910 	case e1000_i211:
911 		/* Turn on MSI-X capability first, or our settings
912 		 * won't stick.  And it will take days to debug.
913 		 */
914 		wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
915 		     E1000_GPIE_PBA | E1000_GPIE_EIAME |
916 		     E1000_GPIE_NSICR);
917 
918 		/* enable msix_other interrupt */
919 		adapter->eims_other = 1 << vector;
920 		tmp = (vector++ | E1000_IVAR_VALID) << 8;
921 
922 		wr32(E1000_IVAR_MISC, tmp);
923 		break;
924 	default:
925 		/* do nothing, since nothing else supports MSI-X */
926 		break;
927 	} /* switch (hw->mac.type) */
928 
929 	adapter->eims_enable_mask |= adapter->eims_other;
930 
931 	for (i = 0; i < adapter->num_q_vectors; i++)
932 		igb_assign_vector(adapter->q_vector[i], vector++);
933 
934 	wrfl();
935 }
936 
937 /**
938  *  igb_request_msix - Initialize MSI-X interrupts
939  *  @adapter: board private structure to initialize
940  *
941  *  igb_request_msix allocates MSI-X vectors and requests interrupts from the
942  *  kernel.
943  **/
igb_request_msix(struct igb_adapter * adapter)944 static int igb_request_msix(struct igb_adapter *adapter)
945 {
946 	struct net_device *netdev = adapter->netdev;
947 	struct e1000_hw *hw = &adapter->hw;
948 	int i, err = 0, vector = 0, free_vector = 0;
949 
950 	err = request_irq(adapter->msix_entries[vector].vector,
951 			  igb_msix_other, 0, netdev->name, adapter);
952 	if (err)
953 		goto err_out;
954 
955 	for (i = 0; i < adapter->num_q_vectors; i++) {
956 		struct igb_q_vector *q_vector = adapter->q_vector[i];
957 
958 		vector++;
959 
960 		q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
961 
962 		if (q_vector->rx.ring && q_vector->tx.ring)
963 			sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
964 				q_vector->rx.ring->queue_index);
965 		else if (q_vector->tx.ring)
966 			sprintf(q_vector->name, "%s-tx-%u", netdev->name,
967 				q_vector->tx.ring->queue_index);
968 		else if (q_vector->rx.ring)
969 			sprintf(q_vector->name, "%s-rx-%u", netdev->name,
970 				q_vector->rx.ring->queue_index);
971 		else
972 			sprintf(q_vector->name, "%s-unused", netdev->name);
973 
974 		err = request_irq(adapter->msix_entries[vector].vector,
975 				  igb_msix_ring, 0, q_vector->name,
976 				  q_vector);
977 		if (err)
978 			goto err_free;
979 	}
980 
981 	igb_configure_msix(adapter);
982 	return 0;
983 
984 err_free:
985 	/* free already assigned IRQs */
986 	free_irq(adapter->msix_entries[free_vector++].vector, adapter);
987 
988 	vector--;
989 	for (i = 0; i < vector; i++) {
990 		free_irq(adapter->msix_entries[free_vector++].vector,
991 			 adapter->q_vector[i]);
992 	}
993 err_out:
994 	return err;
995 }
996 
997 /**
998  *  igb_free_q_vector - Free memory allocated for specific interrupt vector
999  *  @adapter: board private structure to initialize
1000  *  @v_idx: Index of vector to be freed
1001  *
1002  *  This function frees the memory allocated to the q_vector.
1003  **/
igb_free_q_vector(struct igb_adapter * adapter,int v_idx)1004 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1005 {
1006 	struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1007 
1008 	adapter->q_vector[v_idx] = NULL;
1009 
1010 	/* igb_get_stats64() might access the rings on this vector,
1011 	 * we must wait a grace period before freeing it.
1012 	 */
1013 	if (q_vector)
1014 		kfree_rcu(q_vector, rcu);
1015 }
1016 
1017 /**
1018  *  igb_reset_q_vector - Reset config for interrupt vector
1019  *  @adapter: board private structure to initialize
1020  *  @v_idx: Index of vector to be reset
1021  *
1022  *  If NAPI is enabled it will delete any references to the
1023  *  NAPI struct. This is preparation for igb_free_q_vector.
1024  **/
igb_reset_q_vector(struct igb_adapter * adapter,int v_idx)1025 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1026 {
1027 	struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1028 
1029 	/* Coming from igb_set_interrupt_capability, the vectors are not yet
1030 	 * allocated. So, q_vector is NULL so we should stop here.
1031 	 */
1032 	if (!q_vector)
1033 		return;
1034 
1035 	if (q_vector->tx.ring)
1036 		adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1037 
1038 	if (q_vector->rx.ring)
1039 		adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1040 
1041 	netif_napi_del(&q_vector->napi);
1042 
1043 }
1044 
igb_reset_interrupt_capability(struct igb_adapter * adapter)1045 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1046 {
1047 	int v_idx = adapter->num_q_vectors;
1048 
1049 	if (adapter->flags & IGB_FLAG_HAS_MSIX)
1050 		pci_disable_msix(adapter->pdev);
1051 	else if (adapter->flags & IGB_FLAG_HAS_MSI)
1052 		pci_disable_msi(adapter->pdev);
1053 
1054 	while (v_idx--)
1055 		igb_reset_q_vector(adapter, v_idx);
1056 }
1057 
1058 /**
1059  *  igb_free_q_vectors - Free memory allocated for interrupt vectors
1060  *  @adapter: board private structure to initialize
1061  *
1062  *  This function frees the memory allocated to the q_vectors.  In addition if
1063  *  NAPI is enabled it will delete any references to the NAPI struct prior
1064  *  to freeing the q_vector.
1065  **/
igb_free_q_vectors(struct igb_adapter * adapter)1066 static void igb_free_q_vectors(struct igb_adapter *adapter)
1067 {
1068 	int v_idx = adapter->num_q_vectors;
1069 
1070 	adapter->num_tx_queues = 0;
1071 	adapter->num_rx_queues = 0;
1072 	adapter->num_q_vectors = 0;
1073 
1074 	while (v_idx--) {
1075 		igb_reset_q_vector(adapter, v_idx);
1076 		igb_free_q_vector(adapter, v_idx);
1077 	}
1078 }
1079 
1080 /**
1081  *  igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1082  *  @adapter: board private structure to initialize
1083  *
1084  *  This function resets the device so that it has 0 Rx queues, Tx queues, and
1085  *  MSI-X interrupts allocated.
1086  */
igb_clear_interrupt_scheme(struct igb_adapter * adapter)1087 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1088 {
1089 	igb_free_q_vectors(adapter);
1090 	igb_reset_interrupt_capability(adapter);
1091 }
1092 
1093 /**
1094  *  igb_set_interrupt_capability - set MSI or MSI-X if supported
1095  *  @adapter: board private structure to initialize
1096  *  @msix: boolean value of MSIX capability
1097  *
1098  *  Attempt to configure interrupts using the best available
1099  *  capabilities of the hardware and kernel.
1100  **/
igb_set_interrupt_capability(struct igb_adapter * adapter,bool msix)1101 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1102 {
1103 	int err;
1104 	int numvecs, i;
1105 
1106 	if (!msix)
1107 		goto msi_only;
1108 	adapter->flags |= IGB_FLAG_HAS_MSIX;
1109 
1110 	/* Number of supported queues. */
1111 	adapter->num_rx_queues = adapter->rss_queues;
1112 	if (adapter->vfs_allocated_count)
1113 		adapter->num_tx_queues = 1;
1114 	else
1115 		adapter->num_tx_queues = adapter->rss_queues;
1116 
1117 	/* start with one vector for every Rx queue */
1118 	numvecs = adapter->num_rx_queues;
1119 
1120 	/* if Tx handler is separate add 1 for every Tx queue */
1121 	if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1122 		numvecs += adapter->num_tx_queues;
1123 
1124 	/* store the number of vectors reserved for queues */
1125 	adapter->num_q_vectors = numvecs;
1126 
1127 	/* add 1 vector for link status interrupts */
1128 	numvecs++;
1129 	for (i = 0; i < numvecs; i++)
1130 		adapter->msix_entries[i].entry = i;
1131 
1132 	err = pci_enable_msix_range(adapter->pdev,
1133 				    adapter->msix_entries,
1134 				    numvecs,
1135 				    numvecs);
1136 	if (err > 0)
1137 		return;
1138 
1139 	igb_reset_interrupt_capability(adapter);
1140 
1141 	/* If we can't do MSI-X, try MSI */
1142 msi_only:
1143 	adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1144 #ifdef CONFIG_PCI_IOV
1145 	/* disable SR-IOV for non MSI-X configurations */
1146 	if (adapter->vf_data) {
1147 		struct e1000_hw *hw = &adapter->hw;
1148 		/* disable iov and allow time for transactions to clear */
1149 		pci_disable_sriov(adapter->pdev);
1150 		msleep(500);
1151 
1152 		kfree(adapter->vf_data);
1153 		adapter->vf_data = NULL;
1154 		wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1155 		wrfl();
1156 		msleep(100);
1157 		dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1158 	}
1159 #endif
1160 	adapter->vfs_allocated_count = 0;
1161 	adapter->rss_queues = 1;
1162 	adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1163 	adapter->num_rx_queues = 1;
1164 	adapter->num_tx_queues = 1;
1165 	adapter->num_q_vectors = 1;
1166 	if (!pci_enable_msi(adapter->pdev))
1167 		adapter->flags |= IGB_FLAG_HAS_MSI;
1168 }
1169 
igb_add_ring(struct igb_ring * ring,struct igb_ring_container * head)1170 static void igb_add_ring(struct igb_ring *ring,
1171 			 struct igb_ring_container *head)
1172 {
1173 	head->ring = ring;
1174 	head->count++;
1175 }
1176 
1177 /**
1178  *  igb_alloc_q_vector - Allocate memory for a single interrupt vector
1179  *  @adapter: board private structure to initialize
1180  *  @v_count: q_vectors allocated on adapter, used for ring interleaving
1181  *  @v_idx: index of vector in adapter struct
1182  *  @txr_count: total number of Tx rings to allocate
1183  *  @txr_idx: index of first Tx ring to allocate
1184  *  @rxr_count: total number of Rx rings to allocate
1185  *  @rxr_idx: index of first Rx ring to allocate
1186  *
1187  *  We allocate one q_vector.  If allocation fails we return -ENOMEM.
1188  **/
igb_alloc_q_vector(struct igb_adapter * adapter,int v_count,int v_idx,int txr_count,int txr_idx,int rxr_count,int rxr_idx)1189 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1190 			      int v_count, int v_idx,
1191 			      int txr_count, int txr_idx,
1192 			      int rxr_count, int rxr_idx)
1193 {
1194 	struct igb_q_vector *q_vector;
1195 	struct igb_ring *ring;
1196 	int ring_count, size;
1197 
1198 	/* igb only supports 1 Tx and/or 1 Rx queue per vector */
1199 	if (txr_count > 1 || rxr_count > 1)
1200 		return -ENOMEM;
1201 
1202 	ring_count = txr_count + rxr_count;
1203 	size = sizeof(struct igb_q_vector) +
1204 	       (sizeof(struct igb_ring) * ring_count);
1205 
1206 	/* allocate q_vector and rings */
1207 	q_vector = adapter->q_vector[v_idx];
1208 	if (!q_vector) {
1209 		q_vector = kzalloc(size, GFP_KERNEL);
1210 	} else if (size > ksize(q_vector)) {
1211 		kfree_rcu(q_vector, rcu);
1212 		q_vector = kzalloc(size, GFP_KERNEL);
1213 	} else {
1214 		memset(q_vector, 0, size);
1215 	}
1216 	if (!q_vector)
1217 		return -ENOMEM;
1218 
1219 	/* initialize NAPI */
1220 	netif_napi_add(adapter->netdev, &q_vector->napi,
1221 		       igb_poll, 64);
1222 
1223 	/* tie q_vector and adapter together */
1224 	adapter->q_vector[v_idx] = q_vector;
1225 	q_vector->adapter = adapter;
1226 
1227 	/* initialize work limits */
1228 	q_vector->tx.work_limit = adapter->tx_work_limit;
1229 
1230 	/* initialize ITR configuration */
1231 	q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1232 	q_vector->itr_val = IGB_START_ITR;
1233 
1234 	/* initialize pointer to rings */
1235 	ring = q_vector->ring;
1236 
1237 	/* intialize ITR */
1238 	if (rxr_count) {
1239 		/* rx or rx/tx vector */
1240 		if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1241 			q_vector->itr_val = adapter->rx_itr_setting;
1242 	} else {
1243 		/* tx only vector */
1244 		if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1245 			q_vector->itr_val = adapter->tx_itr_setting;
1246 	}
1247 
1248 	if (txr_count) {
1249 		/* assign generic ring traits */
1250 		ring->dev = &adapter->pdev->dev;
1251 		ring->netdev = adapter->netdev;
1252 
1253 		/* configure backlink on ring */
1254 		ring->q_vector = q_vector;
1255 
1256 		/* update q_vector Tx values */
1257 		igb_add_ring(ring, &q_vector->tx);
1258 
1259 		/* For 82575, context index must be unique per ring. */
1260 		if (adapter->hw.mac.type == e1000_82575)
1261 			set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1262 
1263 		/* apply Tx specific ring traits */
1264 		ring->count = adapter->tx_ring_count;
1265 		ring->queue_index = txr_idx;
1266 
1267 		u64_stats_init(&ring->tx_syncp);
1268 		u64_stats_init(&ring->tx_syncp2);
1269 
1270 		/* assign ring to adapter */
1271 		adapter->tx_ring[txr_idx] = ring;
1272 
1273 		/* push pointer to next ring */
1274 		ring++;
1275 	}
1276 
1277 	if (rxr_count) {
1278 		/* assign generic ring traits */
1279 		ring->dev = &adapter->pdev->dev;
1280 		ring->netdev = adapter->netdev;
1281 
1282 		/* configure backlink on ring */
1283 		ring->q_vector = q_vector;
1284 
1285 		/* update q_vector Rx values */
1286 		igb_add_ring(ring, &q_vector->rx);
1287 
1288 		/* set flag indicating ring supports SCTP checksum offload */
1289 		if (adapter->hw.mac.type >= e1000_82576)
1290 			set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1291 
1292 		/* On i350, i354, i210, and i211, loopback VLAN packets
1293 		 * have the tag byte-swapped.
1294 		 */
1295 		if (adapter->hw.mac.type >= e1000_i350)
1296 			set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1297 
1298 		/* apply Rx specific ring traits */
1299 		ring->count = adapter->rx_ring_count;
1300 		ring->queue_index = rxr_idx;
1301 
1302 		u64_stats_init(&ring->rx_syncp);
1303 
1304 		/* assign ring to adapter */
1305 		adapter->rx_ring[rxr_idx] = ring;
1306 	}
1307 
1308 	return 0;
1309 }
1310 
1311 
1312 /**
1313  *  igb_alloc_q_vectors - Allocate memory for interrupt vectors
1314  *  @adapter: board private structure to initialize
1315  *
1316  *  We allocate one q_vector per queue interrupt.  If allocation fails we
1317  *  return -ENOMEM.
1318  **/
igb_alloc_q_vectors(struct igb_adapter * adapter)1319 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1320 {
1321 	int q_vectors = adapter->num_q_vectors;
1322 	int rxr_remaining = adapter->num_rx_queues;
1323 	int txr_remaining = adapter->num_tx_queues;
1324 	int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1325 	int err;
1326 
1327 	if (q_vectors >= (rxr_remaining + txr_remaining)) {
1328 		for (; rxr_remaining; v_idx++) {
1329 			err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1330 						 0, 0, 1, rxr_idx);
1331 
1332 			if (err)
1333 				goto err_out;
1334 
1335 			/* update counts and index */
1336 			rxr_remaining--;
1337 			rxr_idx++;
1338 		}
1339 	}
1340 
1341 	for (; v_idx < q_vectors; v_idx++) {
1342 		int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1343 		int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1344 
1345 		err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1346 					 tqpv, txr_idx, rqpv, rxr_idx);
1347 
1348 		if (err)
1349 			goto err_out;
1350 
1351 		/* update counts and index */
1352 		rxr_remaining -= rqpv;
1353 		txr_remaining -= tqpv;
1354 		rxr_idx++;
1355 		txr_idx++;
1356 	}
1357 
1358 	return 0;
1359 
1360 err_out:
1361 	adapter->num_tx_queues = 0;
1362 	adapter->num_rx_queues = 0;
1363 	adapter->num_q_vectors = 0;
1364 
1365 	while (v_idx--)
1366 		igb_free_q_vector(adapter, v_idx);
1367 
1368 	return -ENOMEM;
1369 }
1370 
1371 /**
1372  *  igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1373  *  @adapter: board private structure to initialize
1374  *  @msix: boolean value of MSIX capability
1375  *
1376  *  This function initializes the interrupts and allocates all of the queues.
1377  **/
igb_init_interrupt_scheme(struct igb_adapter * adapter,bool msix)1378 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1379 {
1380 	struct pci_dev *pdev = adapter->pdev;
1381 	int err;
1382 
1383 	igb_set_interrupt_capability(adapter, msix);
1384 
1385 	err = igb_alloc_q_vectors(adapter);
1386 	if (err) {
1387 		dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1388 		goto err_alloc_q_vectors;
1389 	}
1390 
1391 	igb_cache_ring_register(adapter);
1392 
1393 	return 0;
1394 
1395 err_alloc_q_vectors:
1396 	igb_reset_interrupt_capability(adapter);
1397 	return err;
1398 }
1399 
1400 /**
1401  *  igb_request_irq - initialize interrupts
1402  *  @adapter: board private structure to initialize
1403  *
1404  *  Attempts to configure interrupts using the best available
1405  *  capabilities of the hardware and kernel.
1406  **/
igb_request_irq(struct igb_adapter * adapter)1407 static int igb_request_irq(struct igb_adapter *adapter)
1408 {
1409 	struct net_device *netdev = adapter->netdev;
1410 	struct pci_dev *pdev = adapter->pdev;
1411 	int err = 0;
1412 
1413 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1414 		err = igb_request_msix(adapter);
1415 		if (!err)
1416 			goto request_done;
1417 		/* fall back to MSI */
1418 		igb_free_all_tx_resources(adapter);
1419 		igb_free_all_rx_resources(adapter);
1420 
1421 		igb_clear_interrupt_scheme(adapter);
1422 		err = igb_init_interrupt_scheme(adapter, false);
1423 		if (err)
1424 			goto request_done;
1425 
1426 		igb_setup_all_tx_resources(adapter);
1427 		igb_setup_all_rx_resources(adapter);
1428 		igb_configure(adapter);
1429 	}
1430 
1431 	igb_assign_vector(adapter->q_vector[0], 0);
1432 
1433 	if (adapter->flags & IGB_FLAG_HAS_MSI) {
1434 		err = request_irq(pdev->irq, igb_intr_msi, 0,
1435 				  netdev->name, adapter);
1436 		if (!err)
1437 			goto request_done;
1438 
1439 		/* fall back to legacy interrupts */
1440 		igb_reset_interrupt_capability(adapter);
1441 		adapter->flags &= ~IGB_FLAG_HAS_MSI;
1442 	}
1443 
1444 	err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1445 			  netdev->name, adapter);
1446 
1447 	if (err)
1448 		dev_err(&pdev->dev, "Error %d getting interrupt\n",
1449 			err);
1450 
1451 request_done:
1452 	return err;
1453 }
1454 
igb_free_irq(struct igb_adapter * adapter)1455 static void igb_free_irq(struct igb_adapter *adapter)
1456 {
1457 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1458 		int vector = 0, i;
1459 
1460 		free_irq(adapter->msix_entries[vector++].vector, adapter);
1461 
1462 		for (i = 0; i < adapter->num_q_vectors; i++)
1463 			free_irq(adapter->msix_entries[vector++].vector,
1464 				 adapter->q_vector[i]);
1465 	} else {
1466 		free_irq(adapter->pdev->irq, adapter);
1467 	}
1468 }
1469 
1470 /**
1471  *  igb_irq_disable - Mask off interrupt generation on the NIC
1472  *  @adapter: board private structure
1473  **/
igb_irq_disable(struct igb_adapter * adapter)1474 static void igb_irq_disable(struct igb_adapter *adapter)
1475 {
1476 	struct e1000_hw *hw = &adapter->hw;
1477 
1478 	/* we need to be careful when disabling interrupts.  The VFs are also
1479 	 * mapped into these registers and so clearing the bits can cause
1480 	 * issues on the VF drivers so we only need to clear what we set
1481 	 */
1482 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1483 		u32 regval = rd32(E1000_EIAM);
1484 
1485 		wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1486 		wr32(E1000_EIMC, adapter->eims_enable_mask);
1487 		regval = rd32(E1000_EIAC);
1488 		wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1489 	}
1490 
1491 	wr32(E1000_IAM, 0);
1492 	wr32(E1000_IMC, ~0);
1493 	wrfl();
1494 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1495 		int i;
1496 
1497 		for (i = 0; i < adapter->num_q_vectors; i++)
1498 			synchronize_irq(adapter->msix_entries[i].vector);
1499 	} else {
1500 		synchronize_irq(adapter->pdev->irq);
1501 	}
1502 }
1503 
1504 /**
1505  *  igb_irq_enable - Enable default interrupt generation settings
1506  *  @adapter: board private structure
1507  **/
igb_irq_enable(struct igb_adapter * adapter)1508 static void igb_irq_enable(struct igb_adapter *adapter)
1509 {
1510 	struct e1000_hw *hw = &adapter->hw;
1511 
1512 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1513 		u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1514 		u32 regval = rd32(E1000_EIAC);
1515 
1516 		wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1517 		regval = rd32(E1000_EIAM);
1518 		wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1519 		wr32(E1000_EIMS, adapter->eims_enable_mask);
1520 		if (adapter->vfs_allocated_count) {
1521 			wr32(E1000_MBVFIMR, 0xFF);
1522 			ims |= E1000_IMS_VMMB;
1523 		}
1524 		wr32(E1000_IMS, ims);
1525 	} else {
1526 		wr32(E1000_IMS, IMS_ENABLE_MASK |
1527 				E1000_IMS_DRSTA);
1528 		wr32(E1000_IAM, IMS_ENABLE_MASK |
1529 				E1000_IMS_DRSTA);
1530 	}
1531 }
1532 
igb_update_mng_vlan(struct igb_adapter * adapter)1533 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1534 {
1535 	struct e1000_hw *hw = &adapter->hw;
1536 	u16 vid = adapter->hw.mng_cookie.vlan_id;
1537 	u16 old_vid = adapter->mng_vlan_id;
1538 
1539 	if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1540 		/* add VID to filter table */
1541 		igb_vfta_set(hw, vid, true);
1542 		adapter->mng_vlan_id = vid;
1543 	} else {
1544 		adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1545 	}
1546 
1547 	if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1548 	    (vid != old_vid) &&
1549 	    !test_bit(old_vid, adapter->active_vlans)) {
1550 		/* remove VID from filter table */
1551 		igb_vfta_set(hw, old_vid, false);
1552 	}
1553 }
1554 
1555 /**
1556  *  igb_release_hw_control - release control of the h/w to f/w
1557  *  @adapter: address of board private structure
1558  *
1559  *  igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1560  *  For ASF and Pass Through versions of f/w this means that the
1561  *  driver is no longer loaded.
1562  **/
igb_release_hw_control(struct igb_adapter * adapter)1563 static void igb_release_hw_control(struct igb_adapter *adapter)
1564 {
1565 	struct e1000_hw *hw = &adapter->hw;
1566 	u32 ctrl_ext;
1567 
1568 	/* Let firmware take over control of h/w */
1569 	ctrl_ext = rd32(E1000_CTRL_EXT);
1570 	wr32(E1000_CTRL_EXT,
1571 			ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1572 }
1573 
1574 /**
1575  *  igb_get_hw_control - get control of the h/w from f/w
1576  *  @adapter: address of board private structure
1577  *
1578  *  igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1579  *  For ASF and Pass Through versions of f/w this means that
1580  *  the driver is loaded.
1581  **/
igb_get_hw_control(struct igb_adapter * adapter)1582 static void igb_get_hw_control(struct igb_adapter *adapter)
1583 {
1584 	struct e1000_hw *hw = &adapter->hw;
1585 	u32 ctrl_ext;
1586 
1587 	/* Let firmware know the driver has taken over */
1588 	ctrl_ext = rd32(E1000_CTRL_EXT);
1589 	wr32(E1000_CTRL_EXT,
1590 			ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1591 }
1592 
1593 /**
1594  *  igb_configure - configure the hardware for RX and TX
1595  *  @adapter: private board structure
1596  **/
igb_configure(struct igb_adapter * adapter)1597 static void igb_configure(struct igb_adapter *adapter)
1598 {
1599 	struct net_device *netdev = adapter->netdev;
1600 	int i;
1601 
1602 	igb_get_hw_control(adapter);
1603 	igb_set_rx_mode(netdev);
1604 
1605 	igb_restore_vlan(adapter);
1606 
1607 	igb_setup_tctl(adapter);
1608 	igb_setup_mrqc(adapter);
1609 	igb_setup_rctl(adapter);
1610 
1611 	igb_configure_tx(adapter);
1612 	igb_configure_rx(adapter);
1613 
1614 	igb_rx_fifo_flush_82575(&adapter->hw);
1615 
1616 	/* call igb_desc_unused which always leaves
1617 	 * at least 1 descriptor unused to make sure
1618 	 * next_to_use != next_to_clean
1619 	 */
1620 	for (i = 0; i < adapter->num_rx_queues; i++) {
1621 		struct igb_ring *ring = adapter->rx_ring[i];
1622 		igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1623 	}
1624 }
1625 
1626 /**
1627  *  igb_power_up_link - Power up the phy/serdes link
1628  *  @adapter: address of board private structure
1629  **/
igb_power_up_link(struct igb_adapter * adapter)1630 void igb_power_up_link(struct igb_adapter *adapter)
1631 {
1632 	igb_reset_phy(&adapter->hw);
1633 
1634 	if (adapter->hw.phy.media_type == e1000_media_type_copper)
1635 		igb_power_up_phy_copper(&adapter->hw);
1636 	else
1637 		igb_power_up_serdes_link_82575(&adapter->hw);
1638 
1639 	igb_setup_link(&adapter->hw);
1640 }
1641 
1642 /**
1643  *  igb_power_down_link - Power down the phy/serdes link
1644  *  @adapter: address of board private structure
1645  */
igb_power_down_link(struct igb_adapter * adapter)1646 static void igb_power_down_link(struct igb_adapter *adapter)
1647 {
1648 	if (adapter->hw.phy.media_type == e1000_media_type_copper)
1649 		igb_power_down_phy_copper_82575(&adapter->hw);
1650 	else
1651 		igb_shutdown_serdes_link_82575(&adapter->hw);
1652 }
1653 
1654 /**
1655  * Detect and switch function for Media Auto Sense
1656  * @adapter: address of the board private structure
1657  **/
igb_check_swap_media(struct igb_adapter * adapter)1658 static void igb_check_swap_media(struct igb_adapter *adapter)
1659 {
1660 	struct e1000_hw *hw = &adapter->hw;
1661 	u32 ctrl_ext, connsw;
1662 	bool swap_now = false;
1663 
1664 	ctrl_ext = rd32(E1000_CTRL_EXT);
1665 	connsw = rd32(E1000_CONNSW);
1666 
1667 	/* need to live swap if current media is copper and we have fiber/serdes
1668 	 * to go to.
1669 	 */
1670 
1671 	if ((hw->phy.media_type == e1000_media_type_copper) &&
1672 	    (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1673 		swap_now = true;
1674 	} else if (!(connsw & E1000_CONNSW_SERDESD)) {
1675 		/* copper signal takes time to appear */
1676 		if (adapter->copper_tries < 4) {
1677 			adapter->copper_tries++;
1678 			connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1679 			wr32(E1000_CONNSW, connsw);
1680 			return;
1681 		} else {
1682 			adapter->copper_tries = 0;
1683 			if ((connsw & E1000_CONNSW_PHYSD) &&
1684 			    (!(connsw & E1000_CONNSW_PHY_PDN))) {
1685 				swap_now = true;
1686 				connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1687 				wr32(E1000_CONNSW, connsw);
1688 			}
1689 		}
1690 	}
1691 
1692 	if (!swap_now)
1693 		return;
1694 
1695 	switch (hw->phy.media_type) {
1696 	case e1000_media_type_copper:
1697 		netdev_info(adapter->netdev,
1698 			"MAS: changing media to fiber/serdes\n");
1699 		ctrl_ext |=
1700 			E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1701 		adapter->flags |= IGB_FLAG_MEDIA_RESET;
1702 		adapter->copper_tries = 0;
1703 		break;
1704 	case e1000_media_type_internal_serdes:
1705 	case e1000_media_type_fiber:
1706 		netdev_info(adapter->netdev,
1707 			"MAS: changing media to copper\n");
1708 		ctrl_ext &=
1709 			~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1710 		adapter->flags |= IGB_FLAG_MEDIA_RESET;
1711 		break;
1712 	default:
1713 		/* shouldn't get here during regular operation */
1714 		netdev_err(adapter->netdev,
1715 			"AMS: Invalid media type found, returning\n");
1716 		break;
1717 	}
1718 	wr32(E1000_CTRL_EXT, ctrl_ext);
1719 }
1720 
1721 /**
1722  *  igb_up - Open the interface and prepare it to handle traffic
1723  *  @adapter: board private structure
1724  **/
igb_up(struct igb_adapter * adapter)1725 int igb_up(struct igb_adapter *adapter)
1726 {
1727 	struct e1000_hw *hw = &adapter->hw;
1728 	int i;
1729 
1730 	/* hardware has been reset, we need to reload some things */
1731 	igb_configure(adapter);
1732 
1733 	clear_bit(__IGB_DOWN, &adapter->state);
1734 
1735 	for (i = 0; i < adapter->num_q_vectors; i++)
1736 		napi_enable(&(adapter->q_vector[i]->napi));
1737 
1738 	if (adapter->flags & IGB_FLAG_HAS_MSIX)
1739 		igb_configure_msix(adapter);
1740 	else
1741 		igb_assign_vector(adapter->q_vector[0], 0);
1742 
1743 	/* Clear any pending interrupts. */
1744 	rd32(E1000_ICR);
1745 	igb_irq_enable(adapter);
1746 
1747 	/* notify VFs that reset has been completed */
1748 	if (adapter->vfs_allocated_count) {
1749 		u32 reg_data = rd32(E1000_CTRL_EXT);
1750 
1751 		reg_data |= E1000_CTRL_EXT_PFRSTD;
1752 		wr32(E1000_CTRL_EXT, reg_data);
1753 	}
1754 
1755 	netif_tx_start_all_queues(adapter->netdev);
1756 
1757 	/* start the watchdog. */
1758 	hw->mac.get_link_status = 1;
1759 	schedule_work(&adapter->watchdog_task);
1760 
1761 	if ((adapter->flags & IGB_FLAG_EEE) &&
1762 	    (!hw->dev_spec._82575.eee_disable))
1763 		adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1764 
1765 	return 0;
1766 }
1767 
igb_down(struct igb_adapter * adapter)1768 void igb_down(struct igb_adapter *adapter)
1769 {
1770 	struct net_device *netdev = adapter->netdev;
1771 	struct e1000_hw *hw = &adapter->hw;
1772 	u32 tctl, rctl;
1773 	int i;
1774 
1775 	/* signal that we're down so the interrupt handler does not
1776 	 * reschedule our watchdog timer
1777 	 */
1778 	set_bit(__IGB_DOWN, &adapter->state);
1779 
1780 	/* disable receives in the hardware */
1781 	rctl = rd32(E1000_RCTL);
1782 	wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1783 	/* flush and sleep below */
1784 
1785 	netif_carrier_off(netdev);
1786 	netif_tx_stop_all_queues(netdev);
1787 
1788 	/* disable transmits in the hardware */
1789 	tctl = rd32(E1000_TCTL);
1790 	tctl &= ~E1000_TCTL_EN;
1791 	wr32(E1000_TCTL, tctl);
1792 	/* flush both disables and wait for them to finish */
1793 	wrfl();
1794 	usleep_range(10000, 11000);
1795 
1796 	igb_irq_disable(adapter);
1797 
1798 	adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1799 
1800 	for (i = 0; i < adapter->num_q_vectors; i++) {
1801 		if (adapter->q_vector[i]) {
1802 			napi_synchronize(&adapter->q_vector[i]->napi);
1803 			napi_disable(&adapter->q_vector[i]->napi);
1804 		}
1805 	}
1806 
1807 	del_timer_sync(&adapter->watchdog_timer);
1808 	del_timer_sync(&adapter->phy_info_timer);
1809 
1810 	/* record the stats before reset*/
1811 	spin_lock(&adapter->stats64_lock);
1812 	igb_update_stats(adapter, &adapter->stats64);
1813 	spin_unlock(&adapter->stats64_lock);
1814 
1815 	adapter->link_speed = 0;
1816 	adapter->link_duplex = 0;
1817 
1818 	if (!pci_channel_offline(adapter->pdev))
1819 		igb_reset(adapter);
1820 	igb_clean_all_tx_rings(adapter);
1821 	igb_clean_all_rx_rings(adapter);
1822 #ifdef CONFIG_IGB_DCA
1823 
1824 	/* since we reset the hardware DCA settings were cleared */
1825 	igb_setup_dca(adapter);
1826 #endif
1827 }
1828 
igb_reinit_locked(struct igb_adapter * adapter)1829 void igb_reinit_locked(struct igb_adapter *adapter)
1830 {
1831 	WARN_ON(in_interrupt());
1832 	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1833 		usleep_range(1000, 2000);
1834 	igb_down(adapter);
1835 	igb_up(adapter);
1836 	clear_bit(__IGB_RESETTING, &adapter->state);
1837 }
1838 
1839 /** igb_enable_mas - Media Autosense re-enable after swap
1840  *
1841  * @adapter: adapter struct
1842  **/
igb_enable_mas(struct igb_adapter * adapter)1843 static s32 igb_enable_mas(struct igb_adapter *adapter)
1844 {
1845 	struct e1000_hw *hw = &adapter->hw;
1846 	u32 connsw;
1847 	s32 ret_val = 0;
1848 
1849 	connsw = rd32(E1000_CONNSW);
1850 	if (!(hw->phy.media_type == e1000_media_type_copper))
1851 		return ret_val;
1852 
1853 	/* configure for SerDes media detect */
1854 	if (!(connsw & E1000_CONNSW_SERDESD)) {
1855 		connsw |= E1000_CONNSW_ENRGSRC;
1856 		connsw |= E1000_CONNSW_AUTOSENSE_EN;
1857 		wr32(E1000_CONNSW, connsw);
1858 		wrfl();
1859 	} else if (connsw & E1000_CONNSW_SERDESD) {
1860 		/* already SerDes, no need to enable anything */
1861 		return ret_val;
1862 	} else {
1863 		netdev_info(adapter->netdev,
1864 			"MAS: Unable to configure feature, disabling..\n");
1865 		adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1866 	}
1867 	return ret_val;
1868 }
1869 
igb_reset(struct igb_adapter * adapter)1870 void igb_reset(struct igb_adapter *adapter)
1871 {
1872 	struct pci_dev *pdev = adapter->pdev;
1873 	struct e1000_hw *hw = &adapter->hw;
1874 	struct e1000_mac_info *mac = &hw->mac;
1875 	struct e1000_fc_info *fc = &hw->fc;
1876 	u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1877 
1878 	/* Repartition Pba for greater than 9k mtu
1879 	 * To take effect CTRL.RST is required.
1880 	 */
1881 	switch (mac->type) {
1882 	case e1000_i350:
1883 	case e1000_i354:
1884 	case e1000_82580:
1885 		pba = rd32(E1000_RXPBS);
1886 		pba = igb_rxpbs_adjust_82580(pba);
1887 		break;
1888 	case e1000_82576:
1889 		pba = rd32(E1000_RXPBS);
1890 		pba &= E1000_RXPBS_SIZE_MASK_82576;
1891 		break;
1892 	case e1000_82575:
1893 	case e1000_i210:
1894 	case e1000_i211:
1895 	default:
1896 		pba = E1000_PBA_34K;
1897 		break;
1898 	}
1899 
1900 	if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1901 	    (mac->type < e1000_82576)) {
1902 		/* adjust PBA for jumbo frames */
1903 		wr32(E1000_PBA, pba);
1904 
1905 		/* To maintain wire speed transmits, the Tx FIFO should be
1906 		 * large enough to accommodate two full transmit packets,
1907 		 * rounded up to the next 1KB and expressed in KB.  Likewise,
1908 		 * the Rx FIFO should be large enough to accommodate at least
1909 		 * one full receive packet and is similarly rounded up and
1910 		 * expressed in KB.
1911 		 */
1912 		pba = rd32(E1000_PBA);
1913 		/* upper 16 bits has Tx packet buffer allocation size in KB */
1914 		tx_space = pba >> 16;
1915 		/* lower 16 bits has Rx packet buffer allocation size in KB */
1916 		pba &= 0xffff;
1917 		/* the Tx fifo also stores 16 bytes of information about the Tx
1918 		 * but don't include ethernet FCS because hardware appends it
1919 		 */
1920 		min_tx_space = (adapter->max_frame_size +
1921 				sizeof(union e1000_adv_tx_desc) -
1922 				ETH_FCS_LEN) * 2;
1923 		min_tx_space = ALIGN(min_tx_space, 1024);
1924 		min_tx_space >>= 10;
1925 		/* software strips receive CRC, so leave room for it */
1926 		min_rx_space = adapter->max_frame_size;
1927 		min_rx_space = ALIGN(min_rx_space, 1024);
1928 		min_rx_space >>= 10;
1929 
1930 		/* If current Tx allocation is less than the min Tx FIFO size,
1931 		 * and the min Tx FIFO size is less than the current Rx FIFO
1932 		 * allocation, take space away from current Rx allocation
1933 		 */
1934 		if (tx_space < min_tx_space &&
1935 		    ((min_tx_space - tx_space) < pba)) {
1936 			pba = pba - (min_tx_space - tx_space);
1937 
1938 			/* if short on Rx space, Rx wins and must trump Tx
1939 			 * adjustment
1940 			 */
1941 			if (pba < min_rx_space)
1942 				pba = min_rx_space;
1943 		}
1944 		wr32(E1000_PBA, pba);
1945 	}
1946 
1947 	/* flow control settings */
1948 	/* The high water mark must be low enough to fit one full frame
1949 	 * (or the size used for early receive) above it in the Rx FIFO.
1950 	 * Set it to the lower of:
1951 	 * - 90% of the Rx FIFO size, or
1952 	 * - the full Rx FIFO size minus one full frame
1953 	 */
1954 	hwm = min(((pba << 10) * 9 / 10),
1955 			((pba << 10) - 2 * adapter->max_frame_size));
1956 
1957 	fc->high_water = hwm & 0xFFFFFFF0;	/* 16-byte granularity */
1958 	fc->low_water = fc->high_water - 16;
1959 	fc->pause_time = 0xFFFF;
1960 	fc->send_xon = 1;
1961 	fc->current_mode = fc->requested_mode;
1962 
1963 	/* disable receive for all VFs and wait one second */
1964 	if (adapter->vfs_allocated_count) {
1965 		int i;
1966 
1967 		for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1968 			adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1969 
1970 		/* ping all the active vfs to let them know we are going down */
1971 		igb_ping_all_vfs(adapter);
1972 
1973 		/* disable transmits and receives */
1974 		wr32(E1000_VFRE, 0);
1975 		wr32(E1000_VFTE, 0);
1976 	}
1977 
1978 	/* Allow time for pending master requests to run */
1979 	hw->mac.ops.reset_hw(hw);
1980 	wr32(E1000_WUC, 0);
1981 
1982 	if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1983 		/* need to resetup here after media swap */
1984 		adapter->ei.get_invariants(hw);
1985 		adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1986 	}
1987 	if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1988 		if (igb_enable_mas(adapter))
1989 			dev_err(&pdev->dev,
1990 				"Error enabling Media Auto Sense\n");
1991 	}
1992 	if (hw->mac.ops.init_hw(hw))
1993 		dev_err(&pdev->dev, "Hardware Error\n");
1994 
1995 	/* Flow control settings reset on hardware reset, so guarantee flow
1996 	 * control is off when forcing speed.
1997 	 */
1998 	if (!hw->mac.autoneg)
1999 		igb_force_mac_fc(hw);
2000 
2001 	igb_init_dmac(adapter, pba);
2002 #ifdef CONFIG_IGB_HWMON
2003 	/* Re-initialize the thermal sensor on i350 devices. */
2004 	if (!test_bit(__IGB_DOWN, &adapter->state)) {
2005 		if (mac->type == e1000_i350 && hw->bus.func == 0) {
2006 			/* If present, re-initialize the external thermal sensor
2007 			 * interface.
2008 			 */
2009 			if (adapter->ets)
2010 				mac->ops.init_thermal_sensor_thresh(hw);
2011 		}
2012 	}
2013 #endif
2014 	/* Re-establish EEE setting */
2015 	if (hw->phy.media_type == e1000_media_type_copper) {
2016 		switch (mac->type) {
2017 		case e1000_i350:
2018 		case e1000_i210:
2019 		case e1000_i211:
2020 			igb_set_eee_i350(hw, true, true);
2021 			break;
2022 		case e1000_i354:
2023 			igb_set_eee_i354(hw, true, true);
2024 			break;
2025 		default:
2026 			break;
2027 		}
2028 	}
2029 	if (!netif_running(adapter->netdev))
2030 		igb_power_down_link(adapter);
2031 
2032 	igb_update_mng_vlan(adapter);
2033 
2034 	/* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2035 	wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2036 
2037 	/* Re-enable PTP, where applicable. */
2038 	igb_ptp_reset(adapter);
2039 
2040 	igb_get_phy_info(hw);
2041 }
2042 
igb_fix_features(struct net_device * netdev,netdev_features_t features)2043 static netdev_features_t igb_fix_features(struct net_device *netdev,
2044 	netdev_features_t features)
2045 {
2046 	/* Since there is no support for separate Rx/Tx vlan accel
2047 	 * enable/disable make sure Tx flag is always in same state as Rx.
2048 	 */
2049 	if (features & NETIF_F_HW_VLAN_CTAG_RX)
2050 		features |= NETIF_F_HW_VLAN_CTAG_TX;
2051 	else
2052 		features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2053 
2054 	return features;
2055 }
2056 
igb_set_features(struct net_device * netdev,netdev_features_t features)2057 static int igb_set_features(struct net_device *netdev,
2058 	netdev_features_t features)
2059 {
2060 	netdev_features_t changed = netdev->features ^ features;
2061 	struct igb_adapter *adapter = netdev_priv(netdev);
2062 
2063 	if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2064 		igb_vlan_mode(netdev, features);
2065 
2066 	if (!(changed & NETIF_F_RXALL))
2067 		return 0;
2068 
2069 	netdev->features = features;
2070 
2071 	if (netif_running(netdev))
2072 		igb_reinit_locked(adapter);
2073 	else
2074 		igb_reset(adapter);
2075 
2076 	return 0;
2077 }
2078 
2079 static const struct net_device_ops igb_netdev_ops = {
2080 	.ndo_open		= igb_open,
2081 	.ndo_stop		= igb_close,
2082 	.ndo_start_xmit		= igb_xmit_frame,
2083 	.ndo_get_stats64	= igb_get_stats64,
2084 	.ndo_set_rx_mode	= igb_set_rx_mode,
2085 	.ndo_set_mac_address	= igb_set_mac,
2086 	.ndo_change_mtu		= igb_change_mtu,
2087 	.ndo_do_ioctl		= igb_ioctl,
2088 	.ndo_tx_timeout		= igb_tx_timeout,
2089 	.ndo_validate_addr	= eth_validate_addr,
2090 	.ndo_vlan_rx_add_vid	= igb_vlan_rx_add_vid,
2091 	.ndo_vlan_rx_kill_vid	= igb_vlan_rx_kill_vid,
2092 	.ndo_set_vf_mac		= igb_ndo_set_vf_mac,
2093 	.ndo_set_vf_vlan	= igb_ndo_set_vf_vlan,
2094 	.ndo_set_vf_rate	= igb_ndo_set_vf_bw,
2095 	.ndo_set_vf_spoofchk	= igb_ndo_set_vf_spoofchk,
2096 	.ndo_get_vf_config	= igb_ndo_get_vf_config,
2097 #ifdef CONFIG_NET_POLL_CONTROLLER
2098 	.ndo_poll_controller	= igb_netpoll,
2099 #endif
2100 	.ndo_fix_features	= igb_fix_features,
2101 	.ndo_set_features	= igb_set_features,
2102 	.ndo_features_check	= passthru_features_check,
2103 };
2104 
2105 /**
2106  * igb_set_fw_version - Configure version string for ethtool
2107  * @adapter: adapter struct
2108  **/
igb_set_fw_version(struct igb_adapter * adapter)2109 void igb_set_fw_version(struct igb_adapter *adapter)
2110 {
2111 	struct e1000_hw *hw = &adapter->hw;
2112 	struct e1000_fw_version fw;
2113 
2114 	igb_get_fw_version(hw, &fw);
2115 
2116 	switch (hw->mac.type) {
2117 	case e1000_i210:
2118 	case e1000_i211:
2119 		if (!(igb_get_flash_presence_i210(hw))) {
2120 			snprintf(adapter->fw_version,
2121 				 sizeof(adapter->fw_version),
2122 				 "%2d.%2d-%d",
2123 				 fw.invm_major, fw.invm_minor,
2124 				 fw.invm_img_type);
2125 			break;
2126 		}
2127 		/* fall through */
2128 	default:
2129 		/* if option is rom valid, display its version too */
2130 		if (fw.or_valid) {
2131 			snprintf(adapter->fw_version,
2132 				 sizeof(adapter->fw_version),
2133 				 "%d.%d, 0x%08x, %d.%d.%d",
2134 				 fw.eep_major, fw.eep_minor, fw.etrack_id,
2135 				 fw.or_major, fw.or_build, fw.or_patch);
2136 		/* no option rom */
2137 		} else if (fw.etrack_id != 0X0000) {
2138 			snprintf(adapter->fw_version,
2139 			    sizeof(adapter->fw_version),
2140 			    "%d.%d, 0x%08x",
2141 			    fw.eep_major, fw.eep_minor, fw.etrack_id);
2142 		} else {
2143 		snprintf(adapter->fw_version,
2144 		    sizeof(adapter->fw_version),
2145 		    "%d.%d.%d",
2146 		    fw.eep_major, fw.eep_minor, fw.eep_build);
2147 		}
2148 		break;
2149 	}
2150 }
2151 
2152 /**
2153  * igb_init_mas - init Media Autosense feature if enabled in the NVM
2154  *
2155  * @adapter: adapter struct
2156  **/
igb_init_mas(struct igb_adapter * adapter)2157 static void igb_init_mas(struct igb_adapter *adapter)
2158 {
2159 	struct e1000_hw *hw = &adapter->hw;
2160 	u16 eeprom_data;
2161 
2162 	hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2163 	switch (hw->bus.func) {
2164 	case E1000_FUNC_0:
2165 		if (eeprom_data & IGB_MAS_ENABLE_0) {
2166 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
2167 			netdev_info(adapter->netdev,
2168 				"MAS: Enabling Media Autosense for port %d\n",
2169 				hw->bus.func);
2170 		}
2171 		break;
2172 	case E1000_FUNC_1:
2173 		if (eeprom_data & IGB_MAS_ENABLE_1) {
2174 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
2175 			netdev_info(adapter->netdev,
2176 				"MAS: Enabling Media Autosense for port %d\n",
2177 				hw->bus.func);
2178 		}
2179 		break;
2180 	case E1000_FUNC_2:
2181 		if (eeprom_data & IGB_MAS_ENABLE_2) {
2182 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
2183 			netdev_info(adapter->netdev,
2184 				"MAS: Enabling Media Autosense for port %d\n",
2185 				hw->bus.func);
2186 		}
2187 		break;
2188 	case E1000_FUNC_3:
2189 		if (eeprom_data & IGB_MAS_ENABLE_3) {
2190 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
2191 			netdev_info(adapter->netdev,
2192 				"MAS: Enabling Media Autosense for port %d\n",
2193 				hw->bus.func);
2194 		}
2195 		break;
2196 	default:
2197 		/* Shouldn't get here */
2198 		netdev_err(adapter->netdev,
2199 			"MAS: Invalid port configuration, returning\n");
2200 		break;
2201 	}
2202 }
2203 
2204 /**
2205  *  igb_init_i2c - Init I2C interface
2206  *  @adapter: pointer to adapter structure
2207  **/
igb_init_i2c(struct igb_adapter * adapter)2208 static s32 igb_init_i2c(struct igb_adapter *adapter)
2209 {
2210 	s32 status = 0;
2211 
2212 	/* I2C interface supported on i350 devices */
2213 	if (adapter->hw.mac.type != e1000_i350)
2214 		return 0;
2215 
2216 	/* Initialize the i2c bus which is controlled by the registers.
2217 	 * This bus will use the i2c_algo_bit structue that implements
2218 	 * the protocol through toggling of the 4 bits in the register.
2219 	 */
2220 	adapter->i2c_adap.owner = THIS_MODULE;
2221 	adapter->i2c_algo = igb_i2c_algo;
2222 	adapter->i2c_algo.data = adapter;
2223 	adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2224 	adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2225 	strlcpy(adapter->i2c_adap.name, "igb BB",
2226 		sizeof(adapter->i2c_adap.name));
2227 	status = i2c_bit_add_bus(&adapter->i2c_adap);
2228 	return status;
2229 }
2230 
2231 /**
2232  *  igb_probe - Device Initialization Routine
2233  *  @pdev: PCI device information struct
2234  *  @ent: entry in igb_pci_tbl
2235  *
2236  *  Returns 0 on success, negative on failure
2237  *
2238  *  igb_probe initializes an adapter identified by a pci_dev structure.
2239  *  The OS initialization, configuring of the adapter private structure,
2240  *  and a hardware reset occur.
2241  **/
igb_probe(struct pci_dev * pdev,const struct pci_device_id * ent)2242 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2243 {
2244 	struct net_device *netdev;
2245 	struct igb_adapter *adapter;
2246 	struct e1000_hw *hw;
2247 	u16 eeprom_data = 0;
2248 	s32 ret_val;
2249 	static int global_quad_port_a; /* global quad port a indication */
2250 	const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2251 	int err, pci_using_dac;
2252 	u8 part_str[E1000_PBANUM_LENGTH];
2253 
2254 	/* Catch broken hardware that put the wrong VF device ID in
2255 	 * the PCIe SR-IOV capability.
2256 	 */
2257 	if (pdev->is_virtfn) {
2258 		WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2259 			pci_name(pdev), pdev->vendor, pdev->device);
2260 		return -EINVAL;
2261 	}
2262 
2263 	err = pci_enable_device_mem(pdev);
2264 	if (err)
2265 		return err;
2266 
2267 	pci_using_dac = 0;
2268 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2269 	if (!err) {
2270 		pci_using_dac = 1;
2271 	} else {
2272 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2273 		if (err) {
2274 			dev_err(&pdev->dev,
2275 				"No usable DMA configuration, aborting\n");
2276 			goto err_dma;
2277 		}
2278 	}
2279 
2280 	err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2281 					   IORESOURCE_MEM),
2282 					   igb_driver_name);
2283 	if (err)
2284 		goto err_pci_reg;
2285 
2286 	pci_enable_pcie_error_reporting(pdev);
2287 
2288 	pci_set_master(pdev);
2289 	pci_save_state(pdev);
2290 
2291 	err = -ENOMEM;
2292 	netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2293 				   IGB_MAX_TX_QUEUES);
2294 	if (!netdev)
2295 		goto err_alloc_etherdev;
2296 
2297 	SET_NETDEV_DEV(netdev, &pdev->dev);
2298 
2299 	pci_set_drvdata(pdev, netdev);
2300 	adapter = netdev_priv(netdev);
2301 	adapter->netdev = netdev;
2302 	adapter->pdev = pdev;
2303 	hw = &adapter->hw;
2304 	hw->back = adapter;
2305 	adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2306 
2307 	err = -EIO;
2308 	hw->hw_addr = pci_iomap(pdev, 0, 0);
2309 	if (!hw->hw_addr)
2310 		goto err_ioremap;
2311 
2312 	netdev->netdev_ops = &igb_netdev_ops;
2313 	igb_set_ethtool_ops(netdev);
2314 	netdev->watchdog_timeo = 5 * HZ;
2315 
2316 	strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2317 
2318 	netdev->mem_start = pci_resource_start(pdev, 0);
2319 	netdev->mem_end = pci_resource_end(pdev, 0);
2320 
2321 	/* PCI config space info */
2322 	hw->vendor_id = pdev->vendor;
2323 	hw->device_id = pdev->device;
2324 	hw->revision_id = pdev->revision;
2325 	hw->subsystem_vendor_id = pdev->subsystem_vendor;
2326 	hw->subsystem_device_id = pdev->subsystem_device;
2327 
2328 	/* Copy the default MAC, PHY and NVM function pointers */
2329 	memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2330 	memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2331 	memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2332 	/* Initialize skew-specific constants */
2333 	err = ei->get_invariants(hw);
2334 	if (err)
2335 		goto err_sw_init;
2336 
2337 	/* setup the private structure */
2338 	err = igb_sw_init(adapter);
2339 	if (err)
2340 		goto err_sw_init;
2341 
2342 	igb_get_bus_info_pcie(hw);
2343 
2344 	hw->phy.autoneg_wait_to_complete = false;
2345 
2346 	/* Copper options */
2347 	if (hw->phy.media_type == e1000_media_type_copper) {
2348 		hw->phy.mdix = AUTO_ALL_MODES;
2349 		hw->phy.disable_polarity_correction = false;
2350 		hw->phy.ms_type = e1000_ms_hw_default;
2351 	}
2352 
2353 	if (igb_check_reset_block(hw))
2354 		dev_info(&pdev->dev,
2355 			"PHY reset is blocked due to SOL/IDER session.\n");
2356 
2357 	/* features is initialized to 0 in allocation, it might have bits
2358 	 * set by igb_sw_init so we should use an or instead of an
2359 	 * assignment.
2360 	 */
2361 	netdev->features |= NETIF_F_SG |
2362 			    NETIF_F_IP_CSUM |
2363 			    NETIF_F_IPV6_CSUM |
2364 			    NETIF_F_TSO |
2365 			    NETIF_F_TSO6 |
2366 			    NETIF_F_RXHASH |
2367 			    NETIF_F_RXCSUM |
2368 			    NETIF_F_HW_VLAN_CTAG_RX |
2369 			    NETIF_F_HW_VLAN_CTAG_TX;
2370 
2371 	/* copy netdev features into list of user selectable features */
2372 	netdev->hw_features |= netdev->features;
2373 	netdev->hw_features |= NETIF_F_RXALL;
2374 
2375 	/* set this bit last since it cannot be part of hw_features */
2376 	netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2377 
2378 	netdev->vlan_features |= NETIF_F_TSO |
2379 				 NETIF_F_TSO6 |
2380 				 NETIF_F_IP_CSUM |
2381 				 NETIF_F_IPV6_CSUM |
2382 				 NETIF_F_SG;
2383 
2384 	netdev->priv_flags |= IFF_SUPP_NOFCS;
2385 
2386 	if (pci_using_dac) {
2387 		netdev->features |= NETIF_F_HIGHDMA;
2388 		netdev->vlan_features |= NETIF_F_HIGHDMA;
2389 	}
2390 
2391 	if (hw->mac.type >= e1000_82576) {
2392 		netdev->hw_features |= NETIF_F_SCTP_CSUM;
2393 		netdev->features |= NETIF_F_SCTP_CSUM;
2394 	}
2395 
2396 	netdev->priv_flags |= IFF_UNICAST_FLT;
2397 
2398 	adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2399 
2400 	/* before reading the NVM, reset the controller to put the device in a
2401 	 * known good starting state
2402 	 */
2403 	hw->mac.ops.reset_hw(hw);
2404 
2405 	/* make sure the NVM is good , i211/i210 parts can have special NVM
2406 	 * that doesn't contain a checksum
2407 	 */
2408 	switch (hw->mac.type) {
2409 	case e1000_i210:
2410 	case e1000_i211:
2411 		if (igb_get_flash_presence_i210(hw)) {
2412 			if (hw->nvm.ops.validate(hw) < 0) {
2413 				dev_err(&pdev->dev,
2414 					"The NVM Checksum Is Not Valid\n");
2415 				err = -EIO;
2416 				goto err_eeprom;
2417 			}
2418 		}
2419 		break;
2420 	default:
2421 		if (hw->nvm.ops.validate(hw) < 0) {
2422 			dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2423 			err = -EIO;
2424 			goto err_eeprom;
2425 		}
2426 		break;
2427 	}
2428 
2429 	/* copy the MAC address out of the NVM */
2430 	if (hw->mac.ops.read_mac_addr(hw))
2431 		dev_err(&pdev->dev, "NVM Read Error\n");
2432 
2433 	memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2434 
2435 	if (!is_valid_ether_addr(netdev->dev_addr)) {
2436 		dev_err(&pdev->dev, "Invalid MAC Address\n");
2437 		err = -EIO;
2438 		goto err_eeprom;
2439 	}
2440 
2441 	/* get firmware version for ethtool -i */
2442 	igb_set_fw_version(adapter);
2443 
2444 	/* configure RXPBSIZE and TXPBSIZE */
2445 	if (hw->mac.type == e1000_i210) {
2446 		wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2447 		wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2448 	}
2449 
2450 	setup_timer(&adapter->watchdog_timer, igb_watchdog,
2451 		    (unsigned long) adapter);
2452 	setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2453 		    (unsigned long) adapter);
2454 
2455 	INIT_WORK(&adapter->reset_task, igb_reset_task);
2456 	INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2457 
2458 	/* Initialize link properties that are user-changeable */
2459 	adapter->fc_autoneg = true;
2460 	hw->mac.autoneg = true;
2461 	hw->phy.autoneg_advertised = 0x2f;
2462 
2463 	hw->fc.requested_mode = e1000_fc_default;
2464 	hw->fc.current_mode = e1000_fc_default;
2465 
2466 	igb_validate_mdi_setting(hw);
2467 
2468 	/* By default, support wake on port A */
2469 	if (hw->bus.func == 0)
2470 		adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2471 
2472 	/* Check the NVM for wake support on non-port A ports */
2473 	if (hw->mac.type >= e1000_82580)
2474 		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2475 				 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2476 				 &eeprom_data);
2477 	else if (hw->bus.func == 1)
2478 		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2479 
2480 	if (eeprom_data & IGB_EEPROM_APME)
2481 		adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2482 
2483 	/* now that we have the eeprom settings, apply the special cases where
2484 	 * the eeprom may be wrong or the board simply won't support wake on
2485 	 * lan on a particular port
2486 	 */
2487 	switch (pdev->device) {
2488 	case E1000_DEV_ID_82575GB_QUAD_COPPER:
2489 		adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2490 		break;
2491 	case E1000_DEV_ID_82575EB_FIBER_SERDES:
2492 	case E1000_DEV_ID_82576_FIBER:
2493 	case E1000_DEV_ID_82576_SERDES:
2494 		/* Wake events only supported on port A for dual fiber
2495 		 * regardless of eeprom setting
2496 		 */
2497 		if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2498 			adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2499 		break;
2500 	case E1000_DEV_ID_82576_QUAD_COPPER:
2501 	case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2502 		/* if quad port adapter, disable WoL on all but port A */
2503 		if (global_quad_port_a != 0)
2504 			adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2505 		else
2506 			adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2507 		/* Reset for multiple quad port adapters */
2508 		if (++global_quad_port_a == 4)
2509 			global_quad_port_a = 0;
2510 		break;
2511 	default:
2512 		/* If the device can't wake, don't set software support */
2513 		if (!device_can_wakeup(&adapter->pdev->dev))
2514 			adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2515 	}
2516 
2517 	/* initialize the wol settings based on the eeprom settings */
2518 	if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2519 		adapter->wol |= E1000_WUFC_MAG;
2520 
2521 	/* Some vendors want WoL disabled by default, but still supported */
2522 	if ((hw->mac.type == e1000_i350) &&
2523 	    (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2524 		adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2525 		adapter->wol = 0;
2526 	}
2527 
2528 	device_set_wakeup_enable(&adapter->pdev->dev,
2529 				 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2530 
2531 	/* reset the hardware with the new settings */
2532 	igb_reset(adapter);
2533 
2534 	/* Init the I2C interface */
2535 	err = igb_init_i2c(adapter);
2536 	if (err) {
2537 		dev_err(&pdev->dev, "failed to init i2c interface\n");
2538 		goto err_eeprom;
2539 	}
2540 
2541 	/* let the f/w know that the h/w is now under the control of the
2542 	 * driver.
2543 	 */
2544 	igb_get_hw_control(adapter);
2545 
2546 	strcpy(netdev->name, "eth%d");
2547 	err = register_netdev(netdev);
2548 	if (err)
2549 		goto err_register;
2550 
2551 	/* carrier off reporting is important to ethtool even BEFORE open */
2552 	netif_carrier_off(netdev);
2553 
2554 #ifdef CONFIG_IGB_DCA
2555 	if (dca_add_requester(&pdev->dev) == 0) {
2556 		adapter->flags |= IGB_FLAG_DCA_ENABLED;
2557 		dev_info(&pdev->dev, "DCA enabled\n");
2558 		igb_setup_dca(adapter);
2559 	}
2560 
2561 #endif
2562 #ifdef CONFIG_IGB_HWMON
2563 	/* Initialize the thermal sensor on i350 devices. */
2564 	if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2565 		u16 ets_word;
2566 
2567 		/* Read the NVM to determine if this i350 device supports an
2568 		 * external thermal sensor.
2569 		 */
2570 		hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2571 		if (ets_word != 0x0000 && ets_word != 0xFFFF)
2572 			adapter->ets = true;
2573 		else
2574 			adapter->ets = false;
2575 		if (igb_sysfs_init(adapter))
2576 			dev_err(&pdev->dev,
2577 				"failed to allocate sysfs resources\n");
2578 	} else {
2579 		adapter->ets = false;
2580 	}
2581 #endif
2582 	/* Check if Media Autosense is enabled */
2583 	adapter->ei = *ei;
2584 	if (hw->dev_spec._82575.mas_capable)
2585 		igb_init_mas(adapter);
2586 
2587 	/* do hw tstamp init after resetting */
2588 	igb_ptp_init(adapter);
2589 
2590 	dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2591 	/* print bus type/speed/width info, not applicable to i354 */
2592 	if (hw->mac.type != e1000_i354) {
2593 		dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2594 			 netdev->name,
2595 			 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2596 			  (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2597 			   "unknown"),
2598 			 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2599 			  "Width x4" :
2600 			  (hw->bus.width == e1000_bus_width_pcie_x2) ?
2601 			  "Width x2" :
2602 			  (hw->bus.width == e1000_bus_width_pcie_x1) ?
2603 			  "Width x1" : "unknown"), netdev->dev_addr);
2604 	}
2605 
2606 	if ((hw->mac.type >= e1000_i210 ||
2607 	     igb_get_flash_presence_i210(hw))) {
2608 		ret_val = igb_read_part_string(hw, part_str,
2609 					       E1000_PBANUM_LENGTH);
2610 	} else {
2611 		ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2612 	}
2613 
2614 	if (ret_val)
2615 		strcpy(part_str, "Unknown");
2616 	dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2617 	dev_info(&pdev->dev,
2618 		"Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2619 		(adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
2620 		(adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2621 		adapter->num_rx_queues, adapter->num_tx_queues);
2622 	if (hw->phy.media_type == e1000_media_type_copper) {
2623 		switch (hw->mac.type) {
2624 		case e1000_i350:
2625 		case e1000_i210:
2626 		case e1000_i211:
2627 			/* Enable EEE for internal copper PHY devices */
2628 			err = igb_set_eee_i350(hw, true, true);
2629 			if ((!err) &&
2630 			    (!hw->dev_spec._82575.eee_disable)) {
2631 				adapter->eee_advert =
2632 					MDIO_EEE_100TX | MDIO_EEE_1000T;
2633 				adapter->flags |= IGB_FLAG_EEE;
2634 			}
2635 			break;
2636 		case e1000_i354:
2637 			if ((rd32(E1000_CTRL_EXT) &
2638 			    E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2639 				err = igb_set_eee_i354(hw, true, true);
2640 				if ((!err) &&
2641 					(!hw->dev_spec._82575.eee_disable)) {
2642 					adapter->eee_advert =
2643 					   MDIO_EEE_100TX | MDIO_EEE_1000T;
2644 					adapter->flags |= IGB_FLAG_EEE;
2645 				}
2646 			}
2647 			break;
2648 		default:
2649 			break;
2650 		}
2651 	}
2652 	pm_runtime_put_noidle(&pdev->dev);
2653 	return 0;
2654 
2655 err_register:
2656 	igb_release_hw_control(adapter);
2657 	memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2658 err_eeprom:
2659 	if (!igb_check_reset_block(hw))
2660 		igb_reset_phy(hw);
2661 
2662 	if (hw->flash_address)
2663 		iounmap(hw->flash_address);
2664 err_sw_init:
2665 	igb_clear_interrupt_scheme(adapter);
2666 	pci_iounmap(pdev, hw->hw_addr);
2667 err_ioremap:
2668 	free_netdev(netdev);
2669 err_alloc_etherdev:
2670 	pci_release_selected_regions(pdev,
2671 				     pci_select_bars(pdev, IORESOURCE_MEM));
2672 err_pci_reg:
2673 err_dma:
2674 	pci_disable_device(pdev);
2675 	return err;
2676 }
2677 
2678 #ifdef CONFIG_PCI_IOV
igb_disable_sriov(struct pci_dev * pdev)2679 static int igb_disable_sriov(struct pci_dev *pdev)
2680 {
2681 	struct net_device *netdev = pci_get_drvdata(pdev);
2682 	struct igb_adapter *adapter = netdev_priv(netdev);
2683 	struct e1000_hw *hw = &adapter->hw;
2684 
2685 	/* reclaim resources allocated to VFs */
2686 	if (adapter->vf_data) {
2687 		/* disable iov and allow time for transactions to clear */
2688 		if (pci_vfs_assigned(pdev)) {
2689 			dev_warn(&pdev->dev,
2690 				 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2691 			return -EPERM;
2692 		} else {
2693 			pci_disable_sriov(pdev);
2694 			msleep(500);
2695 		}
2696 
2697 		kfree(adapter->vf_data);
2698 		adapter->vf_data = NULL;
2699 		adapter->vfs_allocated_count = 0;
2700 		wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2701 		wrfl();
2702 		msleep(100);
2703 		dev_info(&pdev->dev, "IOV Disabled\n");
2704 
2705 		/* Re-enable DMA Coalescing flag since IOV is turned off */
2706 		adapter->flags |= IGB_FLAG_DMAC;
2707 	}
2708 
2709 	return 0;
2710 }
2711 
igb_enable_sriov(struct pci_dev * pdev,int num_vfs)2712 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2713 {
2714 	struct net_device *netdev = pci_get_drvdata(pdev);
2715 	struct igb_adapter *adapter = netdev_priv(netdev);
2716 	int old_vfs = pci_num_vf(pdev);
2717 	int err = 0;
2718 	int i;
2719 
2720 	if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
2721 		err = -EPERM;
2722 		goto out;
2723 	}
2724 	if (!num_vfs)
2725 		goto out;
2726 
2727 	if (old_vfs) {
2728 		dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2729 			 old_vfs, max_vfs);
2730 		adapter->vfs_allocated_count = old_vfs;
2731 	} else
2732 		adapter->vfs_allocated_count = num_vfs;
2733 
2734 	adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2735 				sizeof(struct vf_data_storage), GFP_KERNEL);
2736 
2737 	/* if allocation failed then we do not support SR-IOV */
2738 	if (!adapter->vf_data) {
2739 		adapter->vfs_allocated_count = 0;
2740 		dev_err(&pdev->dev,
2741 			"Unable to allocate memory for VF Data Storage\n");
2742 		err = -ENOMEM;
2743 		goto out;
2744 	}
2745 
2746 	/* only call pci_enable_sriov() if no VFs are allocated already */
2747 	if (!old_vfs) {
2748 		err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2749 		if (err)
2750 			goto err_out;
2751 	}
2752 	dev_info(&pdev->dev, "%d VFs allocated\n",
2753 		 adapter->vfs_allocated_count);
2754 	for (i = 0; i < adapter->vfs_allocated_count; i++)
2755 		igb_vf_configure(adapter, i);
2756 
2757 	/* DMA Coalescing is not supported in IOV mode. */
2758 	adapter->flags &= ~IGB_FLAG_DMAC;
2759 	goto out;
2760 
2761 err_out:
2762 	kfree(adapter->vf_data);
2763 	adapter->vf_data = NULL;
2764 	adapter->vfs_allocated_count = 0;
2765 out:
2766 	return err;
2767 }
2768 
2769 #endif
2770 /**
2771  *  igb_remove_i2c - Cleanup  I2C interface
2772  *  @adapter: pointer to adapter structure
2773  **/
igb_remove_i2c(struct igb_adapter * adapter)2774 static void igb_remove_i2c(struct igb_adapter *adapter)
2775 {
2776 	/* free the adapter bus structure */
2777 	i2c_del_adapter(&adapter->i2c_adap);
2778 }
2779 
2780 /**
2781  *  igb_remove - Device Removal Routine
2782  *  @pdev: PCI device information struct
2783  *
2784  *  igb_remove is called by the PCI subsystem to alert the driver
2785  *  that it should release a PCI device.  The could be caused by a
2786  *  Hot-Plug event, or because the driver is going to be removed from
2787  *  memory.
2788  **/
igb_remove(struct pci_dev * pdev)2789 static void igb_remove(struct pci_dev *pdev)
2790 {
2791 	struct net_device *netdev = pci_get_drvdata(pdev);
2792 	struct igb_adapter *adapter = netdev_priv(netdev);
2793 	struct e1000_hw *hw = &adapter->hw;
2794 
2795 	pm_runtime_get_noresume(&pdev->dev);
2796 #ifdef CONFIG_IGB_HWMON
2797 	igb_sysfs_exit(adapter);
2798 #endif
2799 	igb_remove_i2c(adapter);
2800 	igb_ptp_stop(adapter);
2801 	/* The watchdog timer may be rescheduled, so explicitly
2802 	 * disable watchdog from being rescheduled.
2803 	 */
2804 	set_bit(__IGB_DOWN, &adapter->state);
2805 	del_timer_sync(&adapter->watchdog_timer);
2806 	del_timer_sync(&adapter->phy_info_timer);
2807 
2808 	cancel_work_sync(&adapter->reset_task);
2809 	cancel_work_sync(&adapter->watchdog_task);
2810 
2811 #ifdef CONFIG_IGB_DCA
2812 	if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2813 		dev_info(&pdev->dev, "DCA disabled\n");
2814 		dca_remove_requester(&pdev->dev);
2815 		adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2816 		wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2817 	}
2818 #endif
2819 
2820 	/* Release control of h/w to f/w.  If f/w is AMT enabled, this
2821 	 * would have already happened in close and is redundant.
2822 	 */
2823 	igb_release_hw_control(adapter);
2824 
2825 	unregister_netdev(netdev);
2826 
2827 	igb_clear_interrupt_scheme(adapter);
2828 
2829 #ifdef CONFIG_PCI_IOV
2830 	igb_disable_sriov(pdev);
2831 #endif
2832 
2833 	pci_iounmap(pdev, hw->hw_addr);
2834 	if (hw->flash_address)
2835 		iounmap(hw->flash_address);
2836 	pci_release_selected_regions(pdev,
2837 				     pci_select_bars(pdev, IORESOURCE_MEM));
2838 
2839 	kfree(adapter->shadow_vfta);
2840 	free_netdev(netdev);
2841 
2842 	pci_disable_pcie_error_reporting(pdev);
2843 
2844 	pci_disable_device(pdev);
2845 }
2846 
2847 /**
2848  *  igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2849  *  @adapter: board private structure to initialize
2850  *
2851  *  This function initializes the vf specific data storage and then attempts to
2852  *  allocate the VFs.  The reason for ordering it this way is because it is much
2853  *  mor expensive time wise to disable SR-IOV than it is to allocate and free
2854  *  the memory for the VFs.
2855  **/
igb_probe_vfs(struct igb_adapter * adapter)2856 static void igb_probe_vfs(struct igb_adapter *adapter)
2857 {
2858 #ifdef CONFIG_PCI_IOV
2859 	struct pci_dev *pdev = adapter->pdev;
2860 	struct e1000_hw *hw = &adapter->hw;
2861 
2862 	/* Virtualization features not supported on i210 family. */
2863 	if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2864 		return;
2865 
2866 	pci_sriov_set_totalvfs(pdev, 7);
2867 	igb_enable_sriov(pdev, max_vfs);
2868 
2869 #endif /* CONFIG_PCI_IOV */
2870 }
2871 
igb_init_queue_configuration(struct igb_adapter * adapter)2872 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2873 {
2874 	struct e1000_hw *hw = &adapter->hw;
2875 	u32 max_rss_queues;
2876 
2877 	/* Determine the maximum number of RSS queues supported. */
2878 	switch (hw->mac.type) {
2879 	case e1000_i211:
2880 		max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2881 		break;
2882 	case e1000_82575:
2883 	case e1000_i210:
2884 		max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2885 		break;
2886 	case e1000_i350:
2887 		/* I350 cannot do RSS and SR-IOV at the same time */
2888 		if (!!adapter->vfs_allocated_count) {
2889 			max_rss_queues = 1;
2890 			break;
2891 		}
2892 		/* fall through */
2893 	case e1000_82576:
2894 		if (!!adapter->vfs_allocated_count) {
2895 			max_rss_queues = 2;
2896 			break;
2897 		}
2898 		/* fall through */
2899 	case e1000_82580:
2900 	case e1000_i354:
2901 	default:
2902 		max_rss_queues = IGB_MAX_RX_QUEUES;
2903 		break;
2904 	}
2905 
2906 	adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2907 
2908 	igb_set_flag_queue_pairs(adapter, max_rss_queues);
2909 }
2910 
igb_set_flag_queue_pairs(struct igb_adapter * adapter,const u32 max_rss_queues)2911 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2912 			      const u32 max_rss_queues)
2913 {
2914 	struct e1000_hw *hw = &adapter->hw;
2915 
2916 	/* Determine if we need to pair queues. */
2917 	switch (hw->mac.type) {
2918 	case e1000_82575:
2919 	case e1000_i211:
2920 		/* Device supports enough interrupts without queue pairing. */
2921 		break;
2922 	case e1000_82576:
2923 		/* If VFs are going to be allocated with RSS queues then we
2924 		 * should pair the queues in order to conserve interrupts due
2925 		 * to limited supply.
2926 		 */
2927 		if ((adapter->rss_queues > 1) &&
2928 		    (adapter->vfs_allocated_count > 6))
2929 			adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2930 		/* fall through */
2931 	case e1000_82580:
2932 	case e1000_i350:
2933 	case e1000_i354:
2934 	case e1000_i210:
2935 	default:
2936 		/* If rss_queues > half of max_rss_queues, pair the queues in
2937 		 * order to conserve interrupts due to limited supply.
2938 		 */
2939 		if (adapter->rss_queues > (max_rss_queues / 2))
2940 			adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2941 		break;
2942 	}
2943 }
2944 
2945 /**
2946  *  igb_sw_init - Initialize general software structures (struct igb_adapter)
2947  *  @adapter: board private structure to initialize
2948  *
2949  *  igb_sw_init initializes the Adapter private data structure.
2950  *  Fields are initialized based on PCI device information and
2951  *  OS network device settings (MTU size).
2952  **/
igb_sw_init(struct igb_adapter * adapter)2953 static int igb_sw_init(struct igb_adapter *adapter)
2954 {
2955 	struct e1000_hw *hw = &adapter->hw;
2956 	struct net_device *netdev = adapter->netdev;
2957 	struct pci_dev *pdev = adapter->pdev;
2958 
2959 	pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2960 
2961 	/* set default ring sizes */
2962 	adapter->tx_ring_count = IGB_DEFAULT_TXD;
2963 	adapter->rx_ring_count = IGB_DEFAULT_RXD;
2964 
2965 	/* set default ITR values */
2966 	adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2967 	adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2968 
2969 	/* set default work limits */
2970 	adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2971 
2972 	adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2973 				  VLAN_HLEN;
2974 	adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2975 
2976 	spin_lock_init(&adapter->stats64_lock);
2977 #ifdef CONFIG_PCI_IOV
2978 	switch (hw->mac.type) {
2979 	case e1000_82576:
2980 	case e1000_i350:
2981 		if (max_vfs > 7) {
2982 			dev_warn(&pdev->dev,
2983 				 "Maximum of 7 VFs per PF, using max\n");
2984 			max_vfs = adapter->vfs_allocated_count = 7;
2985 		} else
2986 			adapter->vfs_allocated_count = max_vfs;
2987 		if (adapter->vfs_allocated_count)
2988 			dev_warn(&pdev->dev,
2989 				 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2990 		break;
2991 	default:
2992 		break;
2993 	}
2994 #endif /* CONFIG_PCI_IOV */
2995 
2996 	igb_init_queue_configuration(adapter);
2997 
2998 	/* Setup and initialize a copy of the hw vlan table array */
2999 	adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3000 				       GFP_ATOMIC);
3001 
3002 	/* This call may decrease the number of queues */
3003 	if (igb_init_interrupt_scheme(adapter, true)) {
3004 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3005 		return -ENOMEM;
3006 	}
3007 
3008 	igb_probe_vfs(adapter);
3009 
3010 	/* Explicitly disable IRQ since the NIC can be in any state. */
3011 	igb_irq_disable(adapter);
3012 
3013 	if (hw->mac.type >= e1000_i350)
3014 		adapter->flags &= ~IGB_FLAG_DMAC;
3015 
3016 	set_bit(__IGB_DOWN, &adapter->state);
3017 	return 0;
3018 }
3019 
3020 /**
3021  *  igb_open - Called when a network interface is made active
3022  *  @netdev: network interface device structure
3023  *
3024  *  Returns 0 on success, negative value on failure
3025  *
3026  *  The open entry point is called when a network interface is made
3027  *  active by the system (IFF_UP).  At this point all resources needed
3028  *  for transmit and receive operations are allocated, the interrupt
3029  *  handler is registered with the OS, the watchdog timer is started,
3030  *  and the stack is notified that the interface is ready.
3031  **/
__igb_open(struct net_device * netdev,bool resuming)3032 static int __igb_open(struct net_device *netdev, bool resuming)
3033 {
3034 	struct igb_adapter *adapter = netdev_priv(netdev);
3035 	struct e1000_hw *hw = &adapter->hw;
3036 	struct pci_dev *pdev = adapter->pdev;
3037 	int err;
3038 	int i;
3039 
3040 	/* disallow open during test */
3041 	if (test_bit(__IGB_TESTING, &adapter->state)) {
3042 		WARN_ON(resuming);
3043 		return -EBUSY;
3044 	}
3045 
3046 	if (!resuming)
3047 		pm_runtime_get_sync(&pdev->dev);
3048 
3049 	netif_carrier_off(netdev);
3050 
3051 	/* allocate transmit descriptors */
3052 	err = igb_setup_all_tx_resources(adapter);
3053 	if (err)
3054 		goto err_setup_tx;
3055 
3056 	/* allocate receive descriptors */
3057 	err = igb_setup_all_rx_resources(adapter);
3058 	if (err)
3059 		goto err_setup_rx;
3060 
3061 	igb_power_up_link(adapter);
3062 
3063 	/* before we allocate an interrupt, we must be ready to handle it.
3064 	 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3065 	 * as soon as we call pci_request_irq, so we have to setup our
3066 	 * clean_rx handler before we do so.
3067 	 */
3068 	igb_configure(adapter);
3069 
3070 	err = igb_request_irq(adapter);
3071 	if (err)
3072 		goto err_req_irq;
3073 
3074 	/* Notify the stack of the actual queue counts. */
3075 	err = netif_set_real_num_tx_queues(adapter->netdev,
3076 					   adapter->num_tx_queues);
3077 	if (err)
3078 		goto err_set_queues;
3079 
3080 	err = netif_set_real_num_rx_queues(adapter->netdev,
3081 					   adapter->num_rx_queues);
3082 	if (err)
3083 		goto err_set_queues;
3084 
3085 	/* From here on the code is the same as igb_up() */
3086 	clear_bit(__IGB_DOWN, &adapter->state);
3087 
3088 	for (i = 0; i < adapter->num_q_vectors; i++)
3089 		napi_enable(&(adapter->q_vector[i]->napi));
3090 
3091 	/* Clear any pending interrupts. */
3092 	rd32(E1000_ICR);
3093 
3094 	igb_irq_enable(adapter);
3095 
3096 	/* notify VFs that reset has been completed */
3097 	if (adapter->vfs_allocated_count) {
3098 		u32 reg_data = rd32(E1000_CTRL_EXT);
3099 
3100 		reg_data |= E1000_CTRL_EXT_PFRSTD;
3101 		wr32(E1000_CTRL_EXT, reg_data);
3102 	}
3103 
3104 	netif_tx_start_all_queues(netdev);
3105 
3106 	if (!resuming)
3107 		pm_runtime_put(&pdev->dev);
3108 
3109 	/* start the watchdog. */
3110 	hw->mac.get_link_status = 1;
3111 	schedule_work(&adapter->watchdog_task);
3112 
3113 	return 0;
3114 
3115 err_set_queues:
3116 	igb_free_irq(adapter);
3117 err_req_irq:
3118 	igb_release_hw_control(adapter);
3119 	igb_power_down_link(adapter);
3120 	igb_free_all_rx_resources(adapter);
3121 err_setup_rx:
3122 	igb_free_all_tx_resources(adapter);
3123 err_setup_tx:
3124 	igb_reset(adapter);
3125 	if (!resuming)
3126 		pm_runtime_put(&pdev->dev);
3127 
3128 	return err;
3129 }
3130 
igb_open(struct net_device * netdev)3131 static int igb_open(struct net_device *netdev)
3132 {
3133 	return __igb_open(netdev, false);
3134 }
3135 
3136 /**
3137  *  igb_close - Disables a network interface
3138  *  @netdev: network interface device structure
3139  *
3140  *  Returns 0, this is not allowed to fail
3141  *
3142  *  The close entry point is called when an interface is de-activated
3143  *  by the OS.  The hardware is still under the driver's control, but
3144  *  needs to be disabled.  A global MAC reset is issued to stop the
3145  *  hardware, and all transmit and receive resources are freed.
3146  **/
__igb_close(struct net_device * netdev,bool suspending)3147 static int __igb_close(struct net_device *netdev, bool suspending)
3148 {
3149 	struct igb_adapter *adapter = netdev_priv(netdev);
3150 	struct pci_dev *pdev = adapter->pdev;
3151 
3152 	WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3153 
3154 	if (!suspending)
3155 		pm_runtime_get_sync(&pdev->dev);
3156 
3157 	igb_down(adapter);
3158 	igb_free_irq(adapter);
3159 
3160 	igb_free_all_tx_resources(adapter);
3161 	igb_free_all_rx_resources(adapter);
3162 
3163 	if (!suspending)
3164 		pm_runtime_put_sync(&pdev->dev);
3165 	return 0;
3166 }
3167 
igb_close(struct net_device * netdev)3168 static int igb_close(struct net_device *netdev)
3169 {
3170 	return __igb_close(netdev, false);
3171 }
3172 
3173 /**
3174  *  igb_setup_tx_resources - allocate Tx resources (Descriptors)
3175  *  @tx_ring: tx descriptor ring (for a specific queue) to setup
3176  *
3177  *  Return 0 on success, negative on failure
3178  **/
igb_setup_tx_resources(struct igb_ring * tx_ring)3179 int igb_setup_tx_resources(struct igb_ring *tx_ring)
3180 {
3181 	struct device *dev = tx_ring->dev;
3182 	int size;
3183 
3184 	size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3185 
3186 	tx_ring->tx_buffer_info = vzalloc(size);
3187 	if (!tx_ring->tx_buffer_info)
3188 		goto err;
3189 
3190 	/* round up to nearest 4K */
3191 	tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3192 	tx_ring->size = ALIGN(tx_ring->size, 4096);
3193 
3194 	tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3195 					   &tx_ring->dma, GFP_KERNEL);
3196 	if (!tx_ring->desc)
3197 		goto err;
3198 
3199 	tx_ring->next_to_use = 0;
3200 	tx_ring->next_to_clean = 0;
3201 
3202 	return 0;
3203 
3204 err:
3205 	vfree(tx_ring->tx_buffer_info);
3206 	tx_ring->tx_buffer_info = NULL;
3207 	dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3208 	return -ENOMEM;
3209 }
3210 
3211 /**
3212  *  igb_setup_all_tx_resources - wrapper to allocate Tx resources
3213  *				 (Descriptors) for all queues
3214  *  @adapter: board private structure
3215  *
3216  *  Return 0 on success, negative on failure
3217  **/
igb_setup_all_tx_resources(struct igb_adapter * adapter)3218 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3219 {
3220 	struct pci_dev *pdev = adapter->pdev;
3221 	int i, err = 0;
3222 
3223 	for (i = 0; i < adapter->num_tx_queues; i++) {
3224 		err = igb_setup_tx_resources(adapter->tx_ring[i]);
3225 		if (err) {
3226 			dev_err(&pdev->dev,
3227 				"Allocation for Tx Queue %u failed\n", i);
3228 			for (i--; i >= 0; i--)
3229 				igb_free_tx_resources(adapter->tx_ring[i]);
3230 			break;
3231 		}
3232 	}
3233 
3234 	return err;
3235 }
3236 
3237 /**
3238  *  igb_setup_tctl - configure the transmit control registers
3239  *  @adapter: Board private structure
3240  **/
igb_setup_tctl(struct igb_adapter * adapter)3241 void igb_setup_tctl(struct igb_adapter *adapter)
3242 {
3243 	struct e1000_hw *hw = &adapter->hw;
3244 	u32 tctl;
3245 
3246 	/* disable queue 0 which is enabled by default on 82575 and 82576 */
3247 	wr32(E1000_TXDCTL(0), 0);
3248 
3249 	/* Program the Transmit Control Register */
3250 	tctl = rd32(E1000_TCTL);
3251 	tctl &= ~E1000_TCTL_CT;
3252 	tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3253 		(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3254 
3255 	igb_config_collision_dist(hw);
3256 
3257 	/* Enable transmits */
3258 	tctl |= E1000_TCTL_EN;
3259 
3260 	wr32(E1000_TCTL, tctl);
3261 }
3262 
3263 /**
3264  *  igb_configure_tx_ring - Configure transmit ring after Reset
3265  *  @adapter: board private structure
3266  *  @ring: tx ring to configure
3267  *
3268  *  Configure a transmit ring after a reset.
3269  **/
igb_configure_tx_ring(struct igb_adapter * adapter,struct igb_ring * ring)3270 void igb_configure_tx_ring(struct igb_adapter *adapter,
3271 			   struct igb_ring *ring)
3272 {
3273 	struct e1000_hw *hw = &adapter->hw;
3274 	u32 txdctl = 0;
3275 	u64 tdba = ring->dma;
3276 	int reg_idx = ring->reg_idx;
3277 
3278 	/* disable the queue */
3279 	wr32(E1000_TXDCTL(reg_idx), 0);
3280 	wrfl();
3281 	mdelay(10);
3282 
3283 	wr32(E1000_TDLEN(reg_idx),
3284 	     ring->count * sizeof(union e1000_adv_tx_desc));
3285 	wr32(E1000_TDBAL(reg_idx),
3286 	     tdba & 0x00000000ffffffffULL);
3287 	wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3288 
3289 	ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3290 	wr32(E1000_TDH(reg_idx), 0);
3291 	writel(0, ring->tail);
3292 
3293 	txdctl |= IGB_TX_PTHRESH;
3294 	txdctl |= IGB_TX_HTHRESH << 8;
3295 	txdctl |= IGB_TX_WTHRESH << 16;
3296 
3297 	txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3298 	wr32(E1000_TXDCTL(reg_idx), txdctl);
3299 }
3300 
3301 /**
3302  *  igb_configure_tx - Configure transmit Unit after Reset
3303  *  @adapter: board private structure
3304  *
3305  *  Configure the Tx unit of the MAC after a reset.
3306  **/
igb_configure_tx(struct igb_adapter * adapter)3307 static void igb_configure_tx(struct igb_adapter *adapter)
3308 {
3309 	int i;
3310 
3311 	for (i = 0; i < adapter->num_tx_queues; i++)
3312 		igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3313 }
3314 
3315 /**
3316  *  igb_setup_rx_resources - allocate Rx resources (Descriptors)
3317  *  @rx_ring: Rx descriptor ring (for a specific queue) to setup
3318  *
3319  *  Returns 0 on success, negative on failure
3320  **/
igb_setup_rx_resources(struct igb_ring * rx_ring)3321 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3322 {
3323 	struct device *dev = rx_ring->dev;
3324 	int size;
3325 
3326 	size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3327 
3328 	rx_ring->rx_buffer_info = vzalloc(size);
3329 	if (!rx_ring->rx_buffer_info)
3330 		goto err;
3331 
3332 	/* Round up to nearest 4K */
3333 	rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3334 	rx_ring->size = ALIGN(rx_ring->size, 4096);
3335 
3336 	rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3337 					   &rx_ring->dma, GFP_KERNEL);
3338 	if (!rx_ring->desc)
3339 		goto err;
3340 
3341 	rx_ring->next_to_alloc = 0;
3342 	rx_ring->next_to_clean = 0;
3343 	rx_ring->next_to_use = 0;
3344 
3345 	return 0;
3346 
3347 err:
3348 	vfree(rx_ring->rx_buffer_info);
3349 	rx_ring->rx_buffer_info = NULL;
3350 	dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3351 	return -ENOMEM;
3352 }
3353 
3354 /**
3355  *  igb_setup_all_rx_resources - wrapper to allocate Rx resources
3356  *				 (Descriptors) for all queues
3357  *  @adapter: board private structure
3358  *
3359  *  Return 0 on success, negative on failure
3360  **/
igb_setup_all_rx_resources(struct igb_adapter * adapter)3361 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3362 {
3363 	struct pci_dev *pdev = adapter->pdev;
3364 	int i, err = 0;
3365 
3366 	for (i = 0; i < adapter->num_rx_queues; i++) {
3367 		err = igb_setup_rx_resources(adapter->rx_ring[i]);
3368 		if (err) {
3369 			dev_err(&pdev->dev,
3370 				"Allocation for Rx Queue %u failed\n", i);
3371 			for (i--; i >= 0; i--)
3372 				igb_free_rx_resources(adapter->rx_ring[i]);
3373 			break;
3374 		}
3375 	}
3376 
3377 	return err;
3378 }
3379 
3380 /**
3381  *  igb_setup_mrqc - configure the multiple receive queue control registers
3382  *  @adapter: Board private structure
3383  **/
igb_setup_mrqc(struct igb_adapter * adapter)3384 static void igb_setup_mrqc(struct igb_adapter *adapter)
3385 {
3386 	struct e1000_hw *hw = &adapter->hw;
3387 	u32 mrqc, rxcsum;
3388 	u32 j, num_rx_queues;
3389 	u32 rss_key[10];
3390 
3391 	netdev_rss_key_fill(rss_key, sizeof(rss_key));
3392 	for (j = 0; j < 10; j++)
3393 		wr32(E1000_RSSRK(j), rss_key[j]);
3394 
3395 	num_rx_queues = adapter->rss_queues;
3396 
3397 	switch (hw->mac.type) {
3398 	case e1000_82576:
3399 		/* 82576 supports 2 RSS queues for SR-IOV */
3400 		if (adapter->vfs_allocated_count)
3401 			num_rx_queues = 2;
3402 		break;
3403 	default:
3404 		break;
3405 	}
3406 
3407 	if (adapter->rss_indir_tbl_init != num_rx_queues) {
3408 		for (j = 0; j < IGB_RETA_SIZE; j++)
3409 			adapter->rss_indir_tbl[j] =
3410 			(j * num_rx_queues) / IGB_RETA_SIZE;
3411 		adapter->rss_indir_tbl_init = num_rx_queues;
3412 	}
3413 	igb_write_rss_indir_tbl(adapter);
3414 
3415 	/* Disable raw packet checksumming so that RSS hash is placed in
3416 	 * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
3417 	 * offloads as they are enabled by default
3418 	 */
3419 	rxcsum = rd32(E1000_RXCSUM);
3420 	rxcsum |= E1000_RXCSUM_PCSD;
3421 
3422 	if (adapter->hw.mac.type >= e1000_82576)
3423 		/* Enable Receive Checksum Offload for SCTP */
3424 		rxcsum |= E1000_RXCSUM_CRCOFL;
3425 
3426 	/* Don't need to set TUOFL or IPOFL, they default to 1 */
3427 	wr32(E1000_RXCSUM, rxcsum);
3428 
3429 	/* Generate RSS hash based on packet types, TCP/UDP
3430 	 * port numbers and/or IPv4/v6 src and dst addresses
3431 	 */
3432 	mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3433 	       E1000_MRQC_RSS_FIELD_IPV4_TCP |
3434 	       E1000_MRQC_RSS_FIELD_IPV6 |
3435 	       E1000_MRQC_RSS_FIELD_IPV6_TCP |
3436 	       E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3437 
3438 	if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3439 		mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3440 	if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3441 		mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3442 
3443 	/* If VMDq is enabled then we set the appropriate mode for that, else
3444 	 * we default to RSS so that an RSS hash is calculated per packet even
3445 	 * if we are only using one queue
3446 	 */
3447 	if (adapter->vfs_allocated_count) {
3448 		if (hw->mac.type > e1000_82575) {
3449 			/* Set the default pool for the PF's first queue */
3450 			u32 vtctl = rd32(E1000_VT_CTL);
3451 
3452 			vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3453 				   E1000_VT_CTL_DISABLE_DEF_POOL);
3454 			vtctl |= adapter->vfs_allocated_count <<
3455 				E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3456 			wr32(E1000_VT_CTL, vtctl);
3457 		}
3458 		if (adapter->rss_queues > 1)
3459 			mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3460 		else
3461 			mrqc |= E1000_MRQC_ENABLE_VMDQ;
3462 	} else {
3463 		if (hw->mac.type != e1000_i211)
3464 			mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3465 	}
3466 	igb_vmm_control(adapter);
3467 
3468 	wr32(E1000_MRQC, mrqc);
3469 }
3470 
3471 /**
3472  *  igb_setup_rctl - configure the receive control registers
3473  *  @adapter: Board private structure
3474  **/
igb_setup_rctl(struct igb_adapter * adapter)3475 void igb_setup_rctl(struct igb_adapter *adapter)
3476 {
3477 	struct e1000_hw *hw = &adapter->hw;
3478 	u32 rctl;
3479 
3480 	rctl = rd32(E1000_RCTL);
3481 
3482 	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3483 	rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3484 
3485 	rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3486 		(hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3487 
3488 	/* enable stripping of CRC. It's unlikely this will break BMC
3489 	 * redirection as it did with e1000. Newer features require
3490 	 * that the HW strips the CRC.
3491 	 */
3492 	rctl |= E1000_RCTL_SECRC;
3493 
3494 	/* disable store bad packets and clear size bits. */
3495 	rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3496 
3497 	/* enable LPE to prevent packets larger than max_frame_size */
3498 	rctl |= E1000_RCTL_LPE;
3499 
3500 	/* disable queue 0 to prevent tail write w/o re-config */
3501 	wr32(E1000_RXDCTL(0), 0);
3502 
3503 	/* Attention!!!  For SR-IOV PF driver operations you must enable
3504 	 * queue drop for all VF and PF queues to prevent head of line blocking
3505 	 * if an un-trusted VF does not provide descriptors to hardware.
3506 	 */
3507 	if (adapter->vfs_allocated_count) {
3508 		/* set all queue drop enable bits */
3509 		wr32(E1000_QDE, ALL_QUEUES);
3510 	}
3511 
3512 	/* This is useful for sniffing bad packets. */
3513 	if (adapter->netdev->features & NETIF_F_RXALL) {
3514 		/* UPE and MPE will be handled by normal PROMISC logic
3515 		 * in e1000e_set_rx_mode
3516 		 */
3517 		rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3518 			 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3519 			 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3520 
3521 		rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3522 			  E1000_RCTL_DPF | /* Allow filtered pause */
3523 			  E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3524 		/* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3525 		 * and that breaks VLANs.
3526 		 */
3527 	}
3528 
3529 	wr32(E1000_RCTL, rctl);
3530 }
3531 
igb_set_vf_rlpml(struct igb_adapter * adapter,int size,int vfn)3532 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3533 				   int vfn)
3534 {
3535 	struct e1000_hw *hw = &adapter->hw;
3536 	u32 vmolr;
3537 
3538 	/* if it isn't the PF check to see if VFs are enabled and
3539 	 * increase the size to support vlan tags
3540 	 */
3541 	if (vfn < adapter->vfs_allocated_count &&
3542 	    adapter->vf_data[vfn].vlans_enabled)
3543 		size += VLAN_TAG_SIZE;
3544 
3545 	vmolr = rd32(E1000_VMOLR(vfn));
3546 	vmolr &= ~E1000_VMOLR_RLPML_MASK;
3547 	vmolr |= size | E1000_VMOLR_LPE;
3548 	wr32(E1000_VMOLR(vfn), vmolr);
3549 
3550 	return 0;
3551 }
3552 
3553 /**
3554  *  igb_rlpml_set - set maximum receive packet size
3555  *  @adapter: board private structure
3556  *
3557  *  Configure maximum receivable packet size.
3558  **/
igb_rlpml_set(struct igb_adapter * adapter)3559 static void igb_rlpml_set(struct igb_adapter *adapter)
3560 {
3561 	u32 max_frame_size = adapter->max_frame_size;
3562 	struct e1000_hw *hw = &adapter->hw;
3563 	u16 pf_id = adapter->vfs_allocated_count;
3564 
3565 	if (pf_id) {
3566 		igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3567 		/* If we're in VMDQ or SR-IOV mode, then set global RLPML
3568 		 * to our max jumbo frame size, in case we need to enable
3569 		 * jumbo frames on one of the rings later.
3570 		 * This will not pass over-length frames into the default
3571 		 * queue because it's gated by the VMOLR.RLPML.
3572 		 */
3573 		max_frame_size = MAX_JUMBO_FRAME_SIZE;
3574 	}
3575 
3576 	wr32(E1000_RLPML, max_frame_size);
3577 }
3578 
igb_set_vmolr(struct igb_adapter * adapter,int vfn,bool aupe)3579 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3580 				 int vfn, bool aupe)
3581 {
3582 	struct e1000_hw *hw = &adapter->hw;
3583 	u32 vmolr;
3584 
3585 	/* This register exists only on 82576 and newer so if we are older then
3586 	 * we should exit and do nothing
3587 	 */
3588 	if (hw->mac.type < e1000_82576)
3589 		return;
3590 
3591 	vmolr = rd32(E1000_VMOLR(vfn));
3592 	vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3593 	if (hw->mac.type == e1000_i350) {
3594 		u32 dvmolr;
3595 
3596 		dvmolr = rd32(E1000_DVMOLR(vfn));
3597 		dvmolr |= E1000_DVMOLR_STRVLAN;
3598 		wr32(E1000_DVMOLR(vfn), dvmolr);
3599 	}
3600 	if (aupe)
3601 		vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3602 	else
3603 		vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3604 
3605 	/* clear all bits that might not be set */
3606 	vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3607 
3608 	if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3609 		vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3610 	/* for VMDq only allow the VFs and pool 0 to accept broadcast and
3611 	 * multicast packets
3612 	 */
3613 	if (vfn <= adapter->vfs_allocated_count)
3614 		vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3615 
3616 	wr32(E1000_VMOLR(vfn), vmolr);
3617 }
3618 
3619 /**
3620  *  igb_configure_rx_ring - Configure a receive ring after Reset
3621  *  @adapter: board private structure
3622  *  @ring: receive ring to be configured
3623  *
3624  *  Configure the Rx unit of the MAC after a reset.
3625  **/
igb_configure_rx_ring(struct igb_adapter * adapter,struct igb_ring * ring)3626 void igb_configure_rx_ring(struct igb_adapter *adapter,
3627 			   struct igb_ring *ring)
3628 {
3629 	struct e1000_hw *hw = &adapter->hw;
3630 	u64 rdba = ring->dma;
3631 	int reg_idx = ring->reg_idx;
3632 	u32 srrctl = 0, rxdctl = 0;
3633 
3634 	/* disable the queue */
3635 	wr32(E1000_RXDCTL(reg_idx), 0);
3636 
3637 	/* Set DMA base address registers */
3638 	wr32(E1000_RDBAL(reg_idx),
3639 	     rdba & 0x00000000ffffffffULL);
3640 	wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3641 	wr32(E1000_RDLEN(reg_idx),
3642 	     ring->count * sizeof(union e1000_adv_rx_desc));
3643 
3644 	/* initialize head and tail */
3645 	ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3646 	wr32(E1000_RDH(reg_idx), 0);
3647 	writel(0, ring->tail);
3648 
3649 	/* set descriptor configuration */
3650 	srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3651 	srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3652 	srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3653 	if (hw->mac.type >= e1000_82580)
3654 		srrctl |= E1000_SRRCTL_TIMESTAMP;
3655 	/* Only set Drop Enable if we are supporting multiple queues */
3656 	if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3657 		srrctl |= E1000_SRRCTL_DROP_EN;
3658 
3659 	wr32(E1000_SRRCTL(reg_idx), srrctl);
3660 
3661 	/* set filtering for VMDQ pools */
3662 	igb_set_vmolr(adapter, reg_idx & 0x7, true);
3663 
3664 	rxdctl |= IGB_RX_PTHRESH;
3665 	rxdctl |= IGB_RX_HTHRESH << 8;
3666 	rxdctl |= IGB_RX_WTHRESH << 16;
3667 
3668 	/* enable receive descriptor fetching */
3669 	rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3670 	wr32(E1000_RXDCTL(reg_idx), rxdctl);
3671 }
3672 
3673 /**
3674  *  igb_configure_rx - Configure receive Unit after Reset
3675  *  @adapter: board private structure
3676  *
3677  *  Configure the Rx unit of the MAC after a reset.
3678  **/
igb_configure_rx(struct igb_adapter * adapter)3679 static void igb_configure_rx(struct igb_adapter *adapter)
3680 {
3681 	int i;
3682 
3683 	/* set UTA to appropriate mode */
3684 	igb_set_uta(adapter);
3685 
3686 	/* set the correct pool for the PF default MAC address in entry 0 */
3687 	igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3688 			 adapter->vfs_allocated_count);
3689 
3690 	/* Setup the HW Rx Head and Tail Descriptor Pointers and
3691 	 * the Base and Length of the Rx Descriptor Ring
3692 	 */
3693 	for (i = 0; i < adapter->num_rx_queues; i++)
3694 		igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3695 }
3696 
3697 /**
3698  *  igb_free_tx_resources - Free Tx Resources per Queue
3699  *  @tx_ring: Tx descriptor ring for a specific queue
3700  *
3701  *  Free all transmit software resources
3702  **/
igb_free_tx_resources(struct igb_ring * tx_ring)3703 void igb_free_tx_resources(struct igb_ring *tx_ring)
3704 {
3705 	igb_clean_tx_ring(tx_ring);
3706 
3707 	vfree(tx_ring->tx_buffer_info);
3708 	tx_ring->tx_buffer_info = NULL;
3709 
3710 	/* if not set, then don't free */
3711 	if (!tx_ring->desc)
3712 		return;
3713 
3714 	dma_free_coherent(tx_ring->dev, tx_ring->size,
3715 			  tx_ring->desc, tx_ring->dma);
3716 
3717 	tx_ring->desc = NULL;
3718 }
3719 
3720 /**
3721  *  igb_free_all_tx_resources - Free Tx Resources for All Queues
3722  *  @adapter: board private structure
3723  *
3724  *  Free all transmit software resources
3725  **/
igb_free_all_tx_resources(struct igb_adapter * adapter)3726 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3727 {
3728 	int i;
3729 
3730 	for (i = 0; i < adapter->num_tx_queues; i++)
3731 		if (adapter->tx_ring[i])
3732 			igb_free_tx_resources(adapter->tx_ring[i]);
3733 }
3734 
igb_unmap_and_free_tx_resource(struct igb_ring * ring,struct igb_tx_buffer * tx_buffer)3735 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3736 				    struct igb_tx_buffer *tx_buffer)
3737 {
3738 	if (tx_buffer->skb) {
3739 		dev_kfree_skb_any(tx_buffer->skb);
3740 		if (dma_unmap_len(tx_buffer, len))
3741 			dma_unmap_single(ring->dev,
3742 					 dma_unmap_addr(tx_buffer, dma),
3743 					 dma_unmap_len(tx_buffer, len),
3744 					 DMA_TO_DEVICE);
3745 	} else if (dma_unmap_len(tx_buffer, len)) {
3746 		dma_unmap_page(ring->dev,
3747 			       dma_unmap_addr(tx_buffer, dma),
3748 			       dma_unmap_len(tx_buffer, len),
3749 			       DMA_TO_DEVICE);
3750 	}
3751 	tx_buffer->next_to_watch = NULL;
3752 	tx_buffer->skb = NULL;
3753 	dma_unmap_len_set(tx_buffer, len, 0);
3754 	/* buffer_info must be completely set up in the transmit path */
3755 }
3756 
3757 /**
3758  *  igb_clean_tx_ring - Free Tx Buffers
3759  *  @tx_ring: ring to be cleaned
3760  **/
igb_clean_tx_ring(struct igb_ring * tx_ring)3761 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3762 {
3763 	struct igb_tx_buffer *buffer_info;
3764 	unsigned long size;
3765 	u16 i;
3766 
3767 	if (!tx_ring->tx_buffer_info)
3768 		return;
3769 	/* Free all the Tx ring sk_buffs */
3770 
3771 	for (i = 0; i < tx_ring->count; i++) {
3772 		buffer_info = &tx_ring->tx_buffer_info[i];
3773 		igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3774 	}
3775 
3776 	netdev_tx_reset_queue(txring_txq(tx_ring));
3777 
3778 	size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3779 	memset(tx_ring->tx_buffer_info, 0, size);
3780 
3781 	/* Zero out the descriptor ring */
3782 	memset(tx_ring->desc, 0, tx_ring->size);
3783 
3784 	tx_ring->next_to_use = 0;
3785 	tx_ring->next_to_clean = 0;
3786 }
3787 
3788 /**
3789  *  igb_clean_all_tx_rings - Free Tx Buffers for all queues
3790  *  @adapter: board private structure
3791  **/
igb_clean_all_tx_rings(struct igb_adapter * adapter)3792 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3793 {
3794 	int i;
3795 
3796 	for (i = 0; i < adapter->num_tx_queues; i++)
3797 		if (adapter->tx_ring[i])
3798 			igb_clean_tx_ring(adapter->tx_ring[i]);
3799 }
3800 
3801 /**
3802  *  igb_free_rx_resources - Free Rx Resources
3803  *  @rx_ring: ring to clean the resources from
3804  *
3805  *  Free all receive software resources
3806  **/
igb_free_rx_resources(struct igb_ring * rx_ring)3807 void igb_free_rx_resources(struct igb_ring *rx_ring)
3808 {
3809 	igb_clean_rx_ring(rx_ring);
3810 
3811 	vfree(rx_ring->rx_buffer_info);
3812 	rx_ring->rx_buffer_info = NULL;
3813 
3814 	/* if not set, then don't free */
3815 	if (!rx_ring->desc)
3816 		return;
3817 
3818 	dma_free_coherent(rx_ring->dev, rx_ring->size,
3819 			  rx_ring->desc, rx_ring->dma);
3820 
3821 	rx_ring->desc = NULL;
3822 }
3823 
3824 /**
3825  *  igb_free_all_rx_resources - Free Rx Resources for All Queues
3826  *  @adapter: board private structure
3827  *
3828  *  Free all receive software resources
3829  **/
igb_free_all_rx_resources(struct igb_adapter * adapter)3830 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3831 {
3832 	int i;
3833 
3834 	for (i = 0; i < adapter->num_rx_queues; i++)
3835 		if (adapter->rx_ring[i])
3836 			igb_free_rx_resources(adapter->rx_ring[i]);
3837 }
3838 
3839 /**
3840  *  igb_clean_rx_ring - Free Rx Buffers per Queue
3841  *  @rx_ring: ring to free buffers from
3842  **/
igb_clean_rx_ring(struct igb_ring * rx_ring)3843 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3844 {
3845 	unsigned long size;
3846 	u16 i;
3847 
3848 	if (rx_ring->skb)
3849 		dev_kfree_skb(rx_ring->skb);
3850 	rx_ring->skb = NULL;
3851 
3852 	if (!rx_ring->rx_buffer_info)
3853 		return;
3854 
3855 	/* Free all the Rx ring sk_buffs */
3856 	for (i = 0; i < rx_ring->count; i++) {
3857 		struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3858 
3859 		if (!buffer_info->page)
3860 			continue;
3861 
3862 		dma_unmap_page(rx_ring->dev,
3863 			       buffer_info->dma,
3864 			       PAGE_SIZE,
3865 			       DMA_FROM_DEVICE);
3866 		__free_page(buffer_info->page);
3867 
3868 		buffer_info->page = NULL;
3869 	}
3870 
3871 	size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3872 	memset(rx_ring->rx_buffer_info, 0, size);
3873 
3874 	/* Zero out the descriptor ring */
3875 	memset(rx_ring->desc, 0, rx_ring->size);
3876 
3877 	rx_ring->next_to_alloc = 0;
3878 	rx_ring->next_to_clean = 0;
3879 	rx_ring->next_to_use = 0;
3880 }
3881 
3882 /**
3883  *  igb_clean_all_rx_rings - Free Rx Buffers for all queues
3884  *  @adapter: board private structure
3885  **/
igb_clean_all_rx_rings(struct igb_adapter * adapter)3886 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3887 {
3888 	int i;
3889 
3890 	for (i = 0; i < adapter->num_rx_queues; i++)
3891 		if (adapter->rx_ring[i])
3892 			igb_clean_rx_ring(adapter->rx_ring[i]);
3893 }
3894 
3895 /**
3896  *  igb_set_mac - Change the Ethernet Address of the NIC
3897  *  @netdev: network interface device structure
3898  *  @p: pointer to an address structure
3899  *
3900  *  Returns 0 on success, negative on failure
3901  **/
igb_set_mac(struct net_device * netdev,void * p)3902 static int igb_set_mac(struct net_device *netdev, void *p)
3903 {
3904 	struct igb_adapter *adapter = netdev_priv(netdev);
3905 	struct e1000_hw *hw = &adapter->hw;
3906 	struct sockaddr *addr = p;
3907 
3908 	if (!is_valid_ether_addr(addr->sa_data))
3909 		return -EADDRNOTAVAIL;
3910 
3911 	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3912 	memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3913 
3914 	/* set the correct pool for the new PF MAC address in entry 0 */
3915 	igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3916 			 adapter->vfs_allocated_count);
3917 
3918 	return 0;
3919 }
3920 
3921 /**
3922  *  igb_write_mc_addr_list - write multicast addresses to MTA
3923  *  @netdev: network interface device structure
3924  *
3925  *  Writes multicast address list to the MTA hash table.
3926  *  Returns: -ENOMEM on failure
3927  *           0 on no addresses written
3928  *           X on writing X addresses to MTA
3929  **/
igb_write_mc_addr_list(struct net_device * netdev)3930 static int igb_write_mc_addr_list(struct net_device *netdev)
3931 {
3932 	struct igb_adapter *adapter = netdev_priv(netdev);
3933 	struct e1000_hw *hw = &adapter->hw;
3934 	struct netdev_hw_addr *ha;
3935 	u8  *mta_list;
3936 	int i;
3937 
3938 	if (netdev_mc_empty(netdev)) {
3939 		/* nothing to program, so clear mc list */
3940 		igb_update_mc_addr_list(hw, NULL, 0);
3941 		igb_restore_vf_multicasts(adapter);
3942 		return 0;
3943 	}
3944 
3945 	mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3946 	if (!mta_list)
3947 		return -ENOMEM;
3948 
3949 	/* The shared function expects a packed array of only addresses. */
3950 	i = 0;
3951 	netdev_for_each_mc_addr(ha, netdev)
3952 		memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3953 
3954 	igb_update_mc_addr_list(hw, mta_list, i);
3955 	kfree(mta_list);
3956 
3957 	return netdev_mc_count(netdev);
3958 }
3959 
3960 /**
3961  *  igb_write_uc_addr_list - write unicast addresses to RAR table
3962  *  @netdev: network interface device structure
3963  *
3964  *  Writes unicast address list to the RAR table.
3965  *  Returns: -ENOMEM on failure/insufficient address space
3966  *           0 on no addresses written
3967  *           X on writing X addresses to the RAR table
3968  **/
igb_write_uc_addr_list(struct net_device * netdev)3969 static int igb_write_uc_addr_list(struct net_device *netdev)
3970 {
3971 	struct igb_adapter *adapter = netdev_priv(netdev);
3972 	struct e1000_hw *hw = &adapter->hw;
3973 	unsigned int vfn = adapter->vfs_allocated_count;
3974 	unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3975 	int count = 0;
3976 
3977 	/* return ENOMEM indicating insufficient memory for addresses */
3978 	if (netdev_uc_count(netdev) > rar_entries)
3979 		return -ENOMEM;
3980 
3981 	if (!netdev_uc_empty(netdev) && rar_entries) {
3982 		struct netdev_hw_addr *ha;
3983 
3984 		netdev_for_each_uc_addr(ha, netdev) {
3985 			if (!rar_entries)
3986 				break;
3987 			igb_rar_set_qsel(adapter, ha->addr,
3988 					 rar_entries--,
3989 					 vfn);
3990 			count++;
3991 		}
3992 	}
3993 	/* write the addresses in reverse order to avoid write combining */
3994 	for (; rar_entries > 0 ; rar_entries--) {
3995 		wr32(E1000_RAH(rar_entries), 0);
3996 		wr32(E1000_RAL(rar_entries), 0);
3997 	}
3998 	wrfl();
3999 
4000 	return count;
4001 }
4002 
4003 /**
4004  *  igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4005  *  @netdev: network interface device structure
4006  *
4007  *  The set_rx_mode entry point is called whenever the unicast or multicast
4008  *  address lists or the network interface flags are updated.  This routine is
4009  *  responsible for configuring the hardware for proper unicast, multicast,
4010  *  promiscuous mode, and all-multi behavior.
4011  **/
igb_set_rx_mode(struct net_device * netdev)4012 static void igb_set_rx_mode(struct net_device *netdev)
4013 {
4014 	struct igb_adapter *adapter = netdev_priv(netdev);
4015 	struct e1000_hw *hw = &adapter->hw;
4016 	unsigned int vfn = adapter->vfs_allocated_count;
4017 	u32 rctl, vmolr = 0;
4018 	int count;
4019 
4020 	/* Check for Promiscuous and All Multicast modes */
4021 	rctl = rd32(E1000_RCTL);
4022 
4023 	/* clear the effected bits */
4024 	rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4025 
4026 	if (netdev->flags & IFF_PROMISC) {
4027 		/* retain VLAN HW filtering if in VT mode */
4028 		if (adapter->vfs_allocated_count)
4029 			rctl |= E1000_RCTL_VFE;
4030 		rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4031 		vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4032 	} else {
4033 		if (netdev->flags & IFF_ALLMULTI) {
4034 			rctl |= E1000_RCTL_MPE;
4035 			vmolr |= E1000_VMOLR_MPME;
4036 		} else {
4037 			/* Write addresses to the MTA, if the attempt fails
4038 			 * then we should just turn on promiscuous mode so
4039 			 * that we can at least receive multicast traffic
4040 			 */
4041 			count = igb_write_mc_addr_list(netdev);
4042 			if (count < 0) {
4043 				rctl |= E1000_RCTL_MPE;
4044 				vmolr |= E1000_VMOLR_MPME;
4045 			} else if (count) {
4046 				vmolr |= E1000_VMOLR_ROMPE;
4047 			}
4048 		}
4049 		/* Write addresses to available RAR registers, if there is not
4050 		 * sufficient space to store all the addresses then enable
4051 		 * unicast promiscuous mode
4052 		 */
4053 		count = igb_write_uc_addr_list(netdev);
4054 		if (count < 0) {
4055 			rctl |= E1000_RCTL_UPE;
4056 			vmolr |= E1000_VMOLR_ROPE;
4057 		}
4058 		rctl |= E1000_RCTL_VFE;
4059 	}
4060 	wr32(E1000_RCTL, rctl);
4061 
4062 	/* In order to support SR-IOV and eventually VMDq it is necessary to set
4063 	 * the VMOLR to enable the appropriate modes.  Without this workaround
4064 	 * we will have issues with VLAN tag stripping not being done for frames
4065 	 * that are only arriving because we are the default pool
4066 	 */
4067 	if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4068 		return;
4069 
4070 	vmolr |= rd32(E1000_VMOLR(vfn)) &
4071 		 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4072 	wr32(E1000_VMOLR(vfn), vmolr);
4073 	igb_restore_vf_multicasts(adapter);
4074 }
4075 
igb_check_wvbr(struct igb_adapter * adapter)4076 static void igb_check_wvbr(struct igb_adapter *adapter)
4077 {
4078 	struct e1000_hw *hw = &adapter->hw;
4079 	u32 wvbr = 0;
4080 
4081 	switch (hw->mac.type) {
4082 	case e1000_82576:
4083 	case e1000_i350:
4084 		wvbr = rd32(E1000_WVBR);
4085 		if (!wvbr)
4086 			return;
4087 		break;
4088 	default:
4089 		break;
4090 	}
4091 
4092 	adapter->wvbr |= wvbr;
4093 }
4094 
4095 #define IGB_STAGGERED_QUEUE_OFFSET 8
4096 
igb_spoof_check(struct igb_adapter * adapter)4097 static void igb_spoof_check(struct igb_adapter *adapter)
4098 {
4099 	int j;
4100 
4101 	if (!adapter->wvbr)
4102 		return;
4103 
4104 	for (j = 0; j < adapter->vfs_allocated_count; j++) {
4105 		if (adapter->wvbr & (1 << j) ||
4106 		    adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4107 			dev_warn(&adapter->pdev->dev,
4108 				"Spoof event(s) detected on VF %d\n", j);
4109 			adapter->wvbr &=
4110 				~((1 << j) |
4111 				  (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4112 		}
4113 	}
4114 }
4115 
4116 /* Need to wait a few seconds after link up to get diagnostic information from
4117  * the phy
4118  */
igb_update_phy_info(unsigned long data)4119 static void igb_update_phy_info(unsigned long data)
4120 {
4121 	struct igb_adapter *adapter = (struct igb_adapter *) data;
4122 	igb_get_phy_info(&adapter->hw);
4123 }
4124 
4125 /**
4126  *  igb_has_link - check shared code for link and determine up/down
4127  *  @adapter: pointer to driver private info
4128  **/
igb_has_link(struct igb_adapter * adapter)4129 bool igb_has_link(struct igb_adapter *adapter)
4130 {
4131 	struct e1000_hw *hw = &adapter->hw;
4132 	bool link_active = false;
4133 
4134 	/* get_link_status is set on LSC (link status) interrupt or
4135 	 * rx sequence error interrupt.  get_link_status will stay
4136 	 * false until the e1000_check_for_link establishes link
4137 	 * for copper adapters ONLY
4138 	 */
4139 	switch (hw->phy.media_type) {
4140 	case e1000_media_type_copper:
4141 		if (!hw->mac.get_link_status)
4142 			return true;
4143 	case e1000_media_type_internal_serdes:
4144 		hw->mac.ops.check_for_link(hw);
4145 		link_active = !hw->mac.get_link_status;
4146 		break;
4147 	default:
4148 	case e1000_media_type_unknown:
4149 		break;
4150 	}
4151 
4152 	if (((hw->mac.type == e1000_i210) ||
4153 	     (hw->mac.type == e1000_i211)) &&
4154 	     (hw->phy.id == I210_I_PHY_ID)) {
4155 		if (!netif_carrier_ok(adapter->netdev)) {
4156 			adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4157 		} else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4158 			adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4159 			adapter->link_check_timeout = jiffies;
4160 		}
4161 	}
4162 
4163 	return link_active;
4164 }
4165 
igb_thermal_sensor_event(struct e1000_hw * hw,u32 event)4166 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4167 {
4168 	bool ret = false;
4169 	u32 ctrl_ext, thstat;
4170 
4171 	/* check for thermal sensor event on i350 copper only */
4172 	if (hw->mac.type == e1000_i350) {
4173 		thstat = rd32(E1000_THSTAT);
4174 		ctrl_ext = rd32(E1000_CTRL_EXT);
4175 
4176 		if ((hw->phy.media_type == e1000_media_type_copper) &&
4177 		    !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4178 			ret = !!(thstat & event);
4179 	}
4180 
4181 	return ret;
4182 }
4183 
4184 /**
4185  *  igb_check_lvmmc - check for malformed packets received
4186  *  and indicated in LVMMC register
4187  *  @adapter: pointer to adapter
4188  **/
igb_check_lvmmc(struct igb_adapter * adapter)4189 static void igb_check_lvmmc(struct igb_adapter *adapter)
4190 {
4191 	struct e1000_hw *hw = &adapter->hw;
4192 	u32 lvmmc;
4193 
4194 	lvmmc = rd32(E1000_LVMMC);
4195 	if (lvmmc) {
4196 		if (unlikely(net_ratelimit())) {
4197 			netdev_warn(adapter->netdev,
4198 				    "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4199 				    lvmmc);
4200 		}
4201 	}
4202 }
4203 
4204 /**
4205  *  igb_watchdog - Timer Call-back
4206  *  @data: pointer to adapter cast into an unsigned long
4207  **/
igb_watchdog(unsigned long data)4208 static void igb_watchdog(unsigned long data)
4209 {
4210 	struct igb_adapter *adapter = (struct igb_adapter *)data;
4211 	/* Do the rest outside of interrupt context */
4212 	schedule_work(&adapter->watchdog_task);
4213 }
4214 
igb_watchdog_task(struct work_struct * work)4215 static void igb_watchdog_task(struct work_struct *work)
4216 {
4217 	struct igb_adapter *adapter = container_of(work,
4218 						   struct igb_adapter,
4219 						   watchdog_task);
4220 	struct e1000_hw *hw = &adapter->hw;
4221 	struct e1000_phy_info *phy = &hw->phy;
4222 	struct net_device *netdev = adapter->netdev;
4223 	u32 link;
4224 	int i;
4225 	u32 connsw;
4226 
4227 	link = igb_has_link(adapter);
4228 
4229 	if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4230 		if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4231 			adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4232 		else
4233 			link = false;
4234 	}
4235 
4236 	/* Force link down if we have fiber to swap to */
4237 	if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4238 		if (hw->phy.media_type == e1000_media_type_copper) {
4239 			connsw = rd32(E1000_CONNSW);
4240 			if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4241 				link = 0;
4242 		}
4243 	}
4244 	if (link) {
4245 		/* Perform a reset if the media type changed. */
4246 		if (hw->dev_spec._82575.media_changed) {
4247 			hw->dev_spec._82575.media_changed = false;
4248 			adapter->flags |= IGB_FLAG_MEDIA_RESET;
4249 			igb_reset(adapter);
4250 		}
4251 		/* Cancel scheduled suspend requests. */
4252 		pm_runtime_resume(netdev->dev.parent);
4253 
4254 		if (!netif_carrier_ok(netdev)) {
4255 			u32 ctrl;
4256 
4257 			hw->mac.ops.get_speed_and_duplex(hw,
4258 							 &adapter->link_speed,
4259 							 &adapter->link_duplex);
4260 
4261 			ctrl = rd32(E1000_CTRL);
4262 			/* Links status message must follow this format */
4263 			netdev_info(netdev,
4264 			       "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4265 			       netdev->name,
4266 			       adapter->link_speed,
4267 			       adapter->link_duplex == FULL_DUPLEX ?
4268 			       "Full" : "Half",
4269 			       (ctrl & E1000_CTRL_TFCE) &&
4270 			       (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4271 			       (ctrl & E1000_CTRL_RFCE) ?  "RX" :
4272 			       (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
4273 
4274 			/* disable EEE if enabled */
4275 			if ((adapter->flags & IGB_FLAG_EEE) &&
4276 				(adapter->link_duplex == HALF_DUPLEX)) {
4277 				dev_info(&adapter->pdev->dev,
4278 				"EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4279 				adapter->hw.dev_spec._82575.eee_disable = true;
4280 				adapter->flags &= ~IGB_FLAG_EEE;
4281 			}
4282 
4283 			/* check if SmartSpeed worked */
4284 			igb_check_downshift(hw);
4285 			if (phy->speed_downgraded)
4286 				netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4287 
4288 			/* check for thermal sensor event */
4289 			if (igb_thermal_sensor_event(hw,
4290 			    E1000_THSTAT_LINK_THROTTLE))
4291 				netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4292 
4293 			/* adjust timeout factor according to speed/duplex */
4294 			adapter->tx_timeout_factor = 1;
4295 			switch (adapter->link_speed) {
4296 			case SPEED_10:
4297 				adapter->tx_timeout_factor = 14;
4298 				break;
4299 			case SPEED_100:
4300 				/* maybe add some timeout factor ? */
4301 				break;
4302 			}
4303 
4304 			netif_carrier_on(netdev);
4305 
4306 			igb_ping_all_vfs(adapter);
4307 			igb_check_vf_rate_limit(adapter);
4308 
4309 			/* link state has changed, schedule phy info update */
4310 			if (!test_bit(__IGB_DOWN, &adapter->state))
4311 				mod_timer(&adapter->phy_info_timer,
4312 					  round_jiffies(jiffies + 2 * HZ));
4313 		}
4314 	} else {
4315 		if (netif_carrier_ok(netdev)) {
4316 			adapter->link_speed = 0;
4317 			adapter->link_duplex = 0;
4318 
4319 			/* check for thermal sensor event */
4320 			if (igb_thermal_sensor_event(hw,
4321 			    E1000_THSTAT_PWR_DOWN)) {
4322 				netdev_err(netdev, "The network adapter was stopped because it overheated\n");
4323 			}
4324 
4325 			/* Links status message must follow this format */
4326 			netdev_info(netdev, "igb: %s NIC Link is Down\n",
4327 			       netdev->name);
4328 			netif_carrier_off(netdev);
4329 
4330 			igb_ping_all_vfs(adapter);
4331 
4332 			/* link state has changed, schedule phy info update */
4333 			if (!test_bit(__IGB_DOWN, &adapter->state))
4334 				mod_timer(&adapter->phy_info_timer,
4335 					  round_jiffies(jiffies + 2 * HZ));
4336 
4337 			/* link is down, time to check for alternate media */
4338 			if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4339 				igb_check_swap_media(adapter);
4340 				if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4341 					schedule_work(&adapter->reset_task);
4342 					/* return immediately */
4343 					return;
4344 				}
4345 			}
4346 			pm_schedule_suspend(netdev->dev.parent,
4347 					    MSEC_PER_SEC * 5);
4348 
4349 		/* also check for alternate media here */
4350 		} else if (!netif_carrier_ok(netdev) &&
4351 			   (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4352 			igb_check_swap_media(adapter);
4353 			if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4354 				schedule_work(&adapter->reset_task);
4355 				/* return immediately */
4356 				return;
4357 			}
4358 		}
4359 	}
4360 
4361 	spin_lock(&adapter->stats64_lock);
4362 	igb_update_stats(adapter, &adapter->stats64);
4363 	spin_unlock(&adapter->stats64_lock);
4364 
4365 	for (i = 0; i < adapter->num_tx_queues; i++) {
4366 		struct igb_ring *tx_ring = adapter->tx_ring[i];
4367 		if (!netif_carrier_ok(netdev)) {
4368 			/* We've lost link, so the controller stops DMA,
4369 			 * but we've got queued Tx work that's never going
4370 			 * to get done, so reset controller to flush Tx.
4371 			 * (Do the reset outside of interrupt context).
4372 			 */
4373 			if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4374 				adapter->tx_timeout_count++;
4375 				schedule_work(&adapter->reset_task);
4376 				/* return immediately since reset is imminent */
4377 				return;
4378 			}
4379 		}
4380 
4381 		/* Force detection of hung controller every watchdog period */
4382 		set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4383 	}
4384 
4385 	/* Cause software interrupt to ensure Rx ring is cleaned */
4386 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4387 		u32 eics = 0;
4388 
4389 		for (i = 0; i < adapter->num_q_vectors; i++)
4390 			eics |= adapter->q_vector[i]->eims_value;
4391 		wr32(E1000_EICS, eics);
4392 	} else {
4393 		wr32(E1000_ICS, E1000_ICS_RXDMT0);
4394 	}
4395 
4396 	igb_spoof_check(adapter);
4397 	igb_ptp_rx_hang(adapter);
4398 
4399 	/* Check LVMMC register on i350/i354 only */
4400 	if ((adapter->hw.mac.type == e1000_i350) ||
4401 	    (adapter->hw.mac.type == e1000_i354))
4402 		igb_check_lvmmc(adapter);
4403 
4404 	/* Reset the timer */
4405 	if (!test_bit(__IGB_DOWN, &adapter->state)) {
4406 		if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4407 			mod_timer(&adapter->watchdog_timer,
4408 				  round_jiffies(jiffies +  HZ));
4409 		else
4410 			mod_timer(&adapter->watchdog_timer,
4411 				  round_jiffies(jiffies + 2 * HZ));
4412 	}
4413 }
4414 
4415 enum latency_range {
4416 	lowest_latency = 0,
4417 	low_latency = 1,
4418 	bulk_latency = 2,
4419 	latency_invalid = 255
4420 };
4421 
4422 /**
4423  *  igb_update_ring_itr - update the dynamic ITR value based on packet size
4424  *  @q_vector: pointer to q_vector
4425  *
4426  *  Stores a new ITR value based on strictly on packet size.  This
4427  *  algorithm is less sophisticated than that used in igb_update_itr,
4428  *  due to the difficulty of synchronizing statistics across multiple
4429  *  receive rings.  The divisors and thresholds used by this function
4430  *  were determined based on theoretical maximum wire speed and testing
4431  *  data, in order to minimize response time while increasing bulk
4432  *  throughput.
4433  *  This functionality is controlled by ethtool's coalescing settings.
4434  *  NOTE:  This function is called only when operating in a multiqueue
4435  *         receive environment.
4436  **/
igb_update_ring_itr(struct igb_q_vector * q_vector)4437 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4438 {
4439 	int new_val = q_vector->itr_val;
4440 	int avg_wire_size = 0;
4441 	struct igb_adapter *adapter = q_vector->adapter;
4442 	unsigned int packets;
4443 
4444 	/* For non-gigabit speeds, just fix the interrupt rate at 4000
4445 	 * ints/sec - ITR timer value of 120 ticks.
4446 	 */
4447 	if (adapter->link_speed != SPEED_1000) {
4448 		new_val = IGB_4K_ITR;
4449 		goto set_itr_val;
4450 	}
4451 
4452 	packets = q_vector->rx.total_packets;
4453 	if (packets)
4454 		avg_wire_size = q_vector->rx.total_bytes / packets;
4455 
4456 	packets = q_vector->tx.total_packets;
4457 	if (packets)
4458 		avg_wire_size = max_t(u32, avg_wire_size,
4459 				      q_vector->tx.total_bytes / packets);
4460 
4461 	/* if avg_wire_size isn't set no work was done */
4462 	if (!avg_wire_size)
4463 		goto clear_counts;
4464 
4465 	/* Add 24 bytes to size to account for CRC, preamble, and gap */
4466 	avg_wire_size += 24;
4467 
4468 	/* Don't starve jumbo frames */
4469 	avg_wire_size = min(avg_wire_size, 3000);
4470 
4471 	/* Give a little boost to mid-size frames */
4472 	if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4473 		new_val = avg_wire_size / 3;
4474 	else
4475 		new_val = avg_wire_size / 2;
4476 
4477 	/* conservative mode (itr 3) eliminates the lowest_latency setting */
4478 	if (new_val < IGB_20K_ITR &&
4479 	    ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4480 	     (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4481 		new_val = IGB_20K_ITR;
4482 
4483 set_itr_val:
4484 	if (new_val != q_vector->itr_val) {
4485 		q_vector->itr_val = new_val;
4486 		q_vector->set_itr = 1;
4487 	}
4488 clear_counts:
4489 	q_vector->rx.total_bytes = 0;
4490 	q_vector->rx.total_packets = 0;
4491 	q_vector->tx.total_bytes = 0;
4492 	q_vector->tx.total_packets = 0;
4493 }
4494 
4495 /**
4496  *  igb_update_itr - update the dynamic ITR value based on statistics
4497  *  @q_vector: pointer to q_vector
4498  *  @ring_container: ring info to update the itr for
4499  *
4500  *  Stores a new ITR value based on packets and byte
4501  *  counts during the last interrupt.  The advantage of per interrupt
4502  *  computation is faster updates and more accurate ITR for the current
4503  *  traffic pattern.  Constants in this function were computed
4504  *  based on theoretical maximum wire speed and thresholds were set based
4505  *  on testing data as well as attempting to minimize response time
4506  *  while increasing bulk throughput.
4507  *  This functionality is controlled by ethtool's coalescing settings.
4508  *  NOTE:  These calculations are only valid when operating in a single-
4509  *         queue environment.
4510  **/
igb_update_itr(struct igb_q_vector * q_vector,struct igb_ring_container * ring_container)4511 static void igb_update_itr(struct igb_q_vector *q_vector,
4512 			   struct igb_ring_container *ring_container)
4513 {
4514 	unsigned int packets = ring_container->total_packets;
4515 	unsigned int bytes = ring_container->total_bytes;
4516 	u8 itrval = ring_container->itr;
4517 
4518 	/* no packets, exit with status unchanged */
4519 	if (packets == 0)
4520 		return;
4521 
4522 	switch (itrval) {
4523 	case lowest_latency:
4524 		/* handle TSO and jumbo frames */
4525 		if (bytes/packets > 8000)
4526 			itrval = bulk_latency;
4527 		else if ((packets < 5) && (bytes > 512))
4528 			itrval = low_latency;
4529 		break;
4530 	case low_latency:  /* 50 usec aka 20000 ints/s */
4531 		if (bytes > 10000) {
4532 			/* this if handles the TSO accounting */
4533 			if (bytes/packets > 8000)
4534 				itrval = bulk_latency;
4535 			else if ((packets < 10) || ((bytes/packets) > 1200))
4536 				itrval = bulk_latency;
4537 			else if ((packets > 35))
4538 				itrval = lowest_latency;
4539 		} else if (bytes/packets > 2000) {
4540 			itrval = bulk_latency;
4541 		} else if (packets <= 2 && bytes < 512) {
4542 			itrval = lowest_latency;
4543 		}
4544 		break;
4545 	case bulk_latency: /* 250 usec aka 4000 ints/s */
4546 		if (bytes > 25000) {
4547 			if (packets > 35)
4548 				itrval = low_latency;
4549 		} else if (bytes < 1500) {
4550 			itrval = low_latency;
4551 		}
4552 		break;
4553 	}
4554 
4555 	/* clear work counters since we have the values we need */
4556 	ring_container->total_bytes = 0;
4557 	ring_container->total_packets = 0;
4558 
4559 	/* write updated itr to ring container */
4560 	ring_container->itr = itrval;
4561 }
4562 
igb_set_itr(struct igb_q_vector * q_vector)4563 static void igb_set_itr(struct igb_q_vector *q_vector)
4564 {
4565 	struct igb_adapter *adapter = q_vector->adapter;
4566 	u32 new_itr = q_vector->itr_val;
4567 	u8 current_itr = 0;
4568 
4569 	/* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4570 	if (adapter->link_speed != SPEED_1000) {
4571 		current_itr = 0;
4572 		new_itr = IGB_4K_ITR;
4573 		goto set_itr_now;
4574 	}
4575 
4576 	igb_update_itr(q_vector, &q_vector->tx);
4577 	igb_update_itr(q_vector, &q_vector->rx);
4578 
4579 	current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4580 
4581 	/* conservative mode (itr 3) eliminates the lowest_latency setting */
4582 	if (current_itr == lowest_latency &&
4583 	    ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4584 	     (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4585 		current_itr = low_latency;
4586 
4587 	switch (current_itr) {
4588 	/* counts and packets in update_itr are dependent on these numbers */
4589 	case lowest_latency:
4590 		new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4591 		break;
4592 	case low_latency:
4593 		new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4594 		break;
4595 	case bulk_latency:
4596 		new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
4597 		break;
4598 	default:
4599 		break;
4600 	}
4601 
4602 set_itr_now:
4603 	if (new_itr != q_vector->itr_val) {
4604 		/* this attempts to bias the interrupt rate towards Bulk
4605 		 * by adding intermediate steps when interrupt rate is
4606 		 * increasing
4607 		 */
4608 		new_itr = new_itr > q_vector->itr_val ?
4609 			  max((new_itr * q_vector->itr_val) /
4610 			  (new_itr + (q_vector->itr_val >> 2)),
4611 			  new_itr) : new_itr;
4612 		/* Don't write the value here; it resets the adapter's
4613 		 * internal timer, and causes us to delay far longer than
4614 		 * we should between interrupts.  Instead, we write the ITR
4615 		 * value at the beginning of the next interrupt so the timing
4616 		 * ends up being correct.
4617 		 */
4618 		q_vector->itr_val = new_itr;
4619 		q_vector->set_itr = 1;
4620 	}
4621 }
4622 
igb_tx_ctxtdesc(struct igb_ring * tx_ring,u32 vlan_macip_lens,u32 type_tucmd,u32 mss_l4len_idx)4623 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4624 			    u32 type_tucmd, u32 mss_l4len_idx)
4625 {
4626 	struct e1000_adv_tx_context_desc *context_desc;
4627 	u16 i = tx_ring->next_to_use;
4628 
4629 	context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4630 
4631 	i++;
4632 	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4633 
4634 	/* set bits to identify this as an advanced context descriptor */
4635 	type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4636 
4637 	/* For 82575, context index must be unique per ring. */
4638 	if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4639 		mss_l4len_idx |= tx_ring->reg_idx << 4;
4640 
4641 	context_desc->vlan_macip_lens	= cpu_to_le32(vlan_macip_lens);
4642 	context_desc->seqnum_seed	= 0;
4643 	context_desc->type_tucmd_mlhl	= cpu_to_le32(type_tucmd);
4644 	context_desc->mss_l4len_idx	= cpu_to_le32(mss_l4len_idx);
4645 }
4646 
igb_tso(struct igb_ring * tx_ring,struct igb_tx_buffer * first,u8 * hdr_len)4647 static int igb_tso(struct igb_ring *tx_ring,
4648 		   struct igb_tx_buffer *first,
4649 		   u8 *hdr_len)
4650 {
4651 	struct sk_buff *skb = first->skb;
4652 	u32 vlan_macip_lens, type_tucmd;
4653 	u32 mss_l4len_idx, l4len;
4654 	int err;
4655 
4656 	if (skb->ip_summed != CHECKSUM_PARTIAL)
4657 		return 0;
4658 
4659 	if (!skb_is_gso(skb))
4660 		return 0;
4661 
4662 	err = skb_cow_head(skb, 0);
4663 	if (err < 0)
4664 		return err;
4665 
4666 	/* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4667 	type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4668 
4669 	if (first->protocol == htons(ETH_P_IP)) {
4670 		struct iphdr *iph = ip_hdr(skb);
4671 		iph->tot_len = 0;
4672 		iph->check = 0;
4673 		tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4674 							 iph->daddr, 0,
4675 							 IPPROTO_TCP,
4676 							 0);
4677 		type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4678 		first->tx_flags |= IGB_TX_FLAGS_TSO |
4679 				   IGB_TX_FLAGS_CSUM |
4680 				   IGB_TX_FLAGS_IPV4;
4681 	} else if (skb_is_gso_v6(skb)) {
4682 		ipv6_hdr(skb)->payload_len = 0;
4683 		tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4684 						       &ipv6_hdr(skb)->daddr,
4685 						       0, IPPROTO_TCP, 0);
4686 		first->tx_flags |= IGB_TX_FLAGS_TSO |
4687 				   IGB_TX_FLAGS_CSUM;
4688 	}
4689 
4690 	/* compute header lengths */
4691 	l4len = tcp_hdrlen(skb);
4692 	*hdr_len = skb_transport_offset(skb) + l4len;
4693 
4694 	/* update gso size and bytecount with header size */
4695 	first->gso_segs = skb_shinfo(skb)->gso_segs;
4696 	first->bytecount += (first->gso_segs - 1) * *hdr_len;
4697 
4698 	/* MSS L4LEN IDX */
4699 	mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4700 	mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4701 
4702 	/* VLAN MACLEN IPLEN */
4703 	vlan_macip_lens = skb_network_header_len(skb);
4704 	vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4705 	vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4706 
4707 	igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4708 
4709 	return 1;
4710 }
4711 
igb_tx_csum(struct igb_ring * tx_ring,struct igb_tx_buffer * first)4712 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4713 {
4714 	struct sk_buff *skb = first->skb;
4715 	u32 vlan_macip_lens = 0;
4716 	u32 mss_l4len_idx = 0;
4717 	u32 type_tucmd = 0;
4718 
4719 	if (skb->ip_summed != CHECKSUM_PARTIAL) {
4720 		if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4721 			return;
4722 	} else {
4723 		u8 l4_hdr = 0;
4724 
4725 		switch (first->protocol) {
4726 		case htons(ETH_P_IP):
4727 			vlan_macip_lens |= skb_network_header_len(skb);
4728 			type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4729 			l4_hdr = ip_hdr(skb)->protocol;
4730 			break;
4731 		case htons(ETH_P_IPV6):
4732 			vlan_macip_lens |= skb_network_header_len(skb);
4733 			l4_hdr = ipv6_hdr(skb)->nexthdr;
4734 			break;
4735 		default:
4736 			if (unlikely(net_ratelimit())) {
4737 				dev_warn(tx_ring->dev,
4738 					 "partial checksum but proto=%x!\n",
4739 					 first->protocol);
4740 			}
4741 			break;
4742 		}
4743 
4744 		switch (l4_hdr) {
4745 		case IPPROTO_TCP:
4746 			type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4747 			mss_l4len_idx = tcp_hdrlen(skb) <<
4748 					E1000_ADVTXD_L4LEN_SHIFT;
4749 			break;
4750 		case IPPROTO_SCTP:
4751 			type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4752 			mss_l4len_idx = sizeof(struct sctphdr) <<
4753 					E1000_ADVTXD_L4LEN_SHIFT;
4754 			break;
4755 		case IPPROTO_UDP:
4756 			mss_l4len_idx = sizeof(struct udphdr) <<
4757 					E1000_ADVTXD_L4LEN_SHIFT;
4758 			break;
4759 		default:
4760 			if (unlikely(net_ratelimit())) {
4761 				dev_warn(tx_ring->dev,
4762 					 "partial checksum but l4 proto=%x!\n",
4763 					 l4_hdr);
4764 			}
4765 			break;
4766 		}
4767 
4768 		/* update TX checksum flag */
4769 		first->tx_flags |= IGB_TX_FLAGS_CSUM;
4770 	}
4771 
4772 	vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4773 	vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4774 
4775 	igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4776 }
4777 
4778 #define IGB_SET_FLAG(_input, _flag, _result) \
4779 	((_flag <= _result) ? \
4780 	 ((u32)(_input & _flag) * (_result / _flag)) : \
4781 	 ((u32)(_input & _flag) / (_flag / _result)))
4782 
igb_tx_cmd_type(struct sk_buff * skb,u32 tx_flags)4783 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4784 {
4785 	/* set type for advanced descriptor with frame checksum insertion */
4786 	u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4787 		       E1000_ADVTXD_DCMD_DEXT |
4788 		       E1000_ADVTXD_DCMD_IFCS;
4789 
4790 	/* set HW vlan bit if vlan is present */
4791 	cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4792 				 (E1000_ADVTXD_DCMD_VLE));
4793 
4794 	/* set segmentation bits for TSO */
4795 	cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4796 				 (E1000_ADVTXD_DCMD_TSE));
4797 
4798 	/* set timestamp bit if present */
4799 	cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4800 				 (E1000_ADVTXD_MAC_TSTAMP));
4801 
4802 	/* insert frame checksum */
4803 	cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4804 
4805 	return cmd_type;
4806 }
4807 
igb_tx_olinfo_status(struct igb_ring * tx_ring,union e1000_adv_tx_desc * tx_desc,u32 tx_flags,unsigned int paylen)4808 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4809 				 union e1000_adv_tx_desc *tx_desc,
4810 				 u32 tx_flags, unsigned int paylen)
4811 {
4812 	u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4813 
4814 	/* 82575 requires a unique index per ring */
4815 	if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4816 		olinfo_status |= tx_ring->reg_idx << 4;
4817 
4818 	/* insert L4 checksum */
4819 	olinfo_status |= IGB_SET_FLAG(tx_flags,
4820 				      IGB_TX_FLAGS_CSUM,
4821 				      (E1000_TXD_POPTS_TXSM << 8));
4822 
4823 	/* insert IPv4 checksum */
4824 	olinfo_status |= IGB_SET_FLAG(tx_flags,
4825 				      IGB_TX_FLAGS_IPV4,
4826 				      (E1000_TXD_POPTS_IXSM << 8));
4827 
4828 	tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4829 }
4830 
__igb_maybe_stop_tx(struct igb_ring * tx_ring,const u16 size)4831 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4832 {
4833 	struct net_device *netdev = tx_ring->netdev;
4834 
4835 	netif_stop_subqueue(netdev, tx_ring->queue_index);
4836 
4837 	/* Herbert's original patch had:
4838 	 *  smp_mb__after_netif_stop_queue();
4839 	 * but since that doesn't exist yet, just open code it.
4840 	 */
4841 	smp_mb();
4842 
4843 	/* We need to check again in a case another CPU has just
4844 	 * made room available.
4845 	 */
4846 	if (igb_desc_unused(tx_ring) < size)
4847 		return -EBUSY;
4848 
4849 	/* A reprieve! */
4850 	netif_wake_subqueue(netdev, tx_ring->queue_index);
4851 
4852 	u64_stats_update_begin(&tx_ring->tx_syncp2);
4853 	tx_ring->tx_stats.restart_queue2++;
4854 	u64_stats_update_end(&tx_ring->tx_syncp2);
4855 
4856 	return 0;
4857 }
4858 
igb_maybe_stop_tx(struct igb_ring * tx_ring,const u16 size)4859 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4860 {
4861 	if (igb_desc_unused(tx_ring) >= size)
4862 		return 0;
4863 	return __igb_maybe_stop_tx(tx_ring, size);
4864 }
4865 
igb_tx_map(struct igb_ring * tx_ring,struct igb_tx_buffer * first,const u8 hdr_len)4866 static void igb_tx_map(struct igb_ring *tx_ring,
4867 		       struct igb_tx_buffer *first,
4868 		       const u8 hdr_len)
4869 {
4870 	struct sk_buff *skb = first->skb;
4871 	struct igb_tx_buffer *tx_buffer;
4872 	union e1000_adv_tx_desc *tx_desc;
4873 	struct skb_frag_struct *frag;
4874 	dma_addr_t dma;
4875 	unsigned int data_len, size;
4876 	u32 tx_flags = first->tx_flags;
4877 	u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4878 	u16 i = tx_ring->next_to_use;
4879 
4880 	tx_desc = IGB_TX_DESC(tx_ring, i);
4881 
4882 	igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4883 
4884 	size = skb_headlen(skb);
4885 	data_len = skb->data_len;
4886 
4887 	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4888 
4889 	tx_buffer = first;
4890 
4891 	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4892 		if (dma_mapping_error(tx_ring->dev, dma))
4893 			goto dma_error;
4894 
4895 		/* record length, and DMA address */
4896 		dma_unmap_len_set(tx_buffer, len, size);
4897 		dma_unmap_addr_set(tx_buffer, dma, dma);
4898 
4899 		tx_desc->read.buffer_addr = cpu_to_le64(dma);
4900 
4901 		while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4902 			tx_desc->read.cmd_type_len =
4903 				cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4904 
4905 			i++;
4906 			tx_desc++;
4907 			if (i == tx_ring->count) {
4908 				tx_desc = IGB_TX_DESC(tx_ring, 0);
4909 				i = 0;
4910 			}
4911 			tx_desc->read.olinfo_status = 0;
4912 
4913 			dma += IGB_MAX_DATA_PER_TXD;
4914 			size -= IGB_MAX_DATA_PER_TXD;
4915 
4916 			tx_desc->read.buffer_addr = cpu_to_le64(dma);
4917 		}
4918 
4919 		if (likely(!data_len))
4920 			break;
4921 
4922 		tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4923 
4924 		i++;
4925 		tx_desc++;
4926 		if (i == tx_ring->count) {
4927 			tx_desc = IGB_TX_DESC(tx_ring, 0);
4928 			i = 0;
4929 		}
4930 		tx_desc->read.olinfo_status = 0;
4931 
4932 		size = skb_frag_size(frag);
4933 		data_len -= size;
4934 
4935 		dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4936 				       size, DMA_TO_DEVICE);
4937 
4938 		tx_buffer = &tx_ring->tx_buffer_info[i];
4939 	}
4940 
4941 	/* write last descriptor with RS and EOP bits */
4942 	cmd_type |= size | IGB_TXD_DCMD;
4943 	tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4944 
4945 	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4946 
4947 	/* set the timestamp */
4948 	first->time_stamp = jiffies;
4949 
4950 	/* Force memory writes to complete before letting h/w know there
4951 	 * are new descriptors to fetch.  (Only applicable for weak-ordered
4952 	 * memory model archs, such as IA-64).
4953 	 *
4954 	 * We also need this memory barrier to make certain all of the
4955 	 * status bits have been updated before next_to_watch is written.
4956 	 */
4957 	wmb();
4958 
4959 	/* set next_to_watch value indicating a packet is present */
4960 	first->next_to_watch = tx_desc;
4961 
4962 	i++;
4963 	if (i == tx_ring->count)
4964 		i = 0;
4965 
4966 	tx_ring->next_to_use = i;
4967 
4968 	/* Make sure there is space in the ring for the next send. */
4969 	igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4970 
4971 	if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
4972 		writel(i, tx_ring->tail);
4973 
4974 		/* we need this if more than one processor can write to our tail
4975 		 * at a time, it synchronizes IO on IA64/Altix systems
4976 		 */
4977 		mmiowb();
4978 	}
4979 	return;
4980 
4981 dma_error:
4982 	dev_err(tx_ring->dev, "TX DMA map failed\n");
4983 
4984 	/* clear dma mappings for failed tx_buffer_info map */
4985 	for (;;) {
4986 		tx_buffer = &tx_ring->tx_buffer_info[i];
4987 		igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4988 		if (tx_buffer == first)
4989 			break;
4990 		if (i == 0)
4991 			i = tx_ring->count;
4992 		i--;
4993 	}
4994 
4995 	tx_ring->next_to_use = i;
4996 }
4997 
igb_xmit_frame_ring(struct sk_buff * skb,struct igb_ring * tx_ring)4998 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4999 				struct igb_ring *tx_ring)
5000 {
5001 	struct igb_tx_buffer *first;
5002 	int tso;
5003 	u32 tx_flags = 0;
5004 	u16 count = TXD_USE_COUNT(skb_headlen(skb));
5005 	__be16 protocol = vlan_get_protocol(skb);
5006 	u8 hdr_len = 0;
5007 
5008 	/* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5009 	 *       + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
5010 	 *       + 2 desc gap to keep tail from touching head,
5011 	 *       + 1 desc for context descriptor,
5012 	 * otherwise try next time
5013 	 */
5014 	if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
5015 		unsigned short f;
5016 
5017 		for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5018 			count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5019 	} else {
5020 		count += skb_shinfo(skb)->nr_frags;
5021 	}
5022 
5023 	if (igb_maybe_stop_tx(tx_ring, count + 3)) {
5024 		/* this is a hard error */
5025 		return NETDEV_TX_BUSY;
5026 	}
5027 
5028 	/* record the location of the first descriptor for this packet */
5029 	first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5030 	first->skb = skb;
5031 	first->bytecount = skb->len;
5032 	first->gso_segs = 1;
5033 
5034 	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5035 		struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5036 
5037 		if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5038 					   &adapter->state)) {
5039 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5040 			tx_flags |= IGB_TX_FLAGS_TSTAMP;
5041 
5042 			adapter->ptp_tx_skb = skb_get(skb);
5043 			adapter->ptp_tx_start = jiffies;
5044 			if (adapter->hw.mac.type == e1000_82576)
5045 				schedule_work(&adapter->ptp_tx_work);
5046 		}
5047 	}
5048 
5049 	skb_tx_timestamp(skb);
5050 
5051 	if (skb_vlan_tag_present(skb)) {
5052 		tx_flags |= IGB_TX_FLAGS_VLAN;
5053 		tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5054 	}
5055 
5056 	/* record initial flags and protocol */
5057 	first->tx_flags = tx_flags;
5058 	first->protocol = protocol;
5059 
5060 	tso = igb_tso(tx_ring, first, &hdr_len);
5061 	if (tso < 0)
5062 		goto out_drop;
5063 	else if (!tso)
5064 		igb_tx_csum(tx_ring, first);
5065 
5066 	igb_tx_map(tx_ring, first, hdr_len);
5067 
5068 	return NETDEV_TX_OK;
5069 
5070 out_drop:
5071 	igb_unmap_and_free_tx_resource(tx_ring, first);
5072 
5073 	return NETDEV_TX_OK;
5074 }
5075 
igb_tx_queue_mapping(struct igb_adapter * adapter,struct sk_buff * skb)5076 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5077 						    struct sk_buff *skb)
5078 {
5079 	unsigned int r_idx = skb->queue_mapping;
5080 
5081 	if (r_idx >= adapter->num_tx_queues)
5082 		r_idx = r_idx % adapter->num_tx_queues;
5083 
5084 	return adapter->tx_ring[r_idx];
5085 }
5086 
igb_xmit_frame(struct sk_buff * skb,struct net_device * netdev)5087 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5088 				  struct net_device *netdev)
5089 {
5090 	struct igb_adapter *adapter = netdev_priv(netdev);
5091 
5092 	if (test_bit(__IGB_DOWN, &adapter->state)) {
5093 		dev_kfree_skb_any(skb);
5094 		return NETDEV_TX_OK;
5095 	}
5096 
5097 	if (skb->len <= 0) {
5098 		dev_kfree_skb_any(skb);
5099 		return NETDEV_TX_OK;
5100 	}
5101 
5102 	/* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5103 	 * in order to meet this minimum size requirement.
5104 	 */
5105 	if (skb_put_padto(skb, 17))
5106 		return NETDEV_TX_OK;
5107 
5108 	return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5109 }
5110 
5111 /**
5112  *  igb_tx_timeout - Respond to a Tx Hang
5113  *  @netdev: network interface device structure
5114  **/
igb_tx_timeout(struct net_device * netdev)5115 static void igb_tx_timeout(struct net_device *netdev)
5116 {
5117 	struct igb_adapter *adapter = netdev_priv(netdev);
5118 	struct e1000_hw *hw = &adapter->hw;
5119 
5120 	/* Do the reset outside of interrupt context */
5121 	adapter->tx_timeout_count++;
5122 
5123 	if (hw->mac.type >= e1000_82580)
5124 		hw->dev_spec._82575.global_device_reset = true;
5125 
5126 	schedule_work(&adapter->reset_task);
5127 	wr32(E1000_EICS,
5128 	     (adapter->eims_enable_mask & ~adapter->eims_other));
5129 }
5130 
igb_reset_task(struct work_struct * work)5131 static void igb_reset_task(struct work_struct *work)
5132 {
5133 	struct igb_adapter *adapter;
5134 	adapter = container_of(work, struct igb_adapter, reset_task);
5135 
5136 	igb_dump(adapter);
5137 	netdev_err(adapter->netdev, "Reset adapter\n");
5138 	igb_reinit_locked(adapter);
5139 }
5140 
5141 /**
5142  *  igb_get_stats64 - Get System Network Statistics
5143  *  @netdev: network interface device structure
5144  *  @stats: rtnl_link_stats64 pointer
5145  **/
igb_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)5146 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
5147 						struct rtnl_link_stats64 *stats)
5148 {
5149 	struct igb_adapter *adapter = netdev_priv(netdev);
5150 
5151 	spin_lock(&adapter->stats64_lock);
5152 	igb_update_stats(adapter, &adapter->stats64);
5153 	memcpy(stats, &adapter->stats64, sizeof(*stats));
5154 	spin_unlock(&adapter->stats64_lock);
5155 
5156 	return stats;
5157 }
5158 
5159 /**
5160  *  igb_change_mtu - Change the Maximum Transfer Unit
5161  *  @netdev: network interface device structure
5162  *  @new_mtu: new value for maximum frame size
5163  *
5164  *  Returns 0 on success, negative on failure
5165  **/
igb_change_mtu(struct net_device * netdev,int new_mtu)5166 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5167 {
5168 	struct igb_adapter *adapter = netdev_priv(netdev);
5169 	struct pci_dev *pdev = adapter->pdev;
5170 	int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5171 
5172 	if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
5173 		dev_err(&pdev->dev, "Invalid MTU setting\n");
5174 		return -EINVAL;
5175 	}
5176 
5177 #define MAX_STD_JUMBO_FRAME_SIZE 9238
5178 	if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
5179 		dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
5180 		return -EINVAL;
5181 	}
5182 
5183 	/* adjust max frame to be at least the size of a standard frame */
5184 	if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5185 		max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5186 
5187 	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5188 		usleep_range(1000, 2000);
5189 
5190 	/* igb_down has a dependency on max_frame_size */
5191 	adapter->max_frame_size = max_frame;
5192 
5193 	if (netif_running(netdev))
5194 		igb_down(adapter);
5195 
5196 	dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5197 		 netdev->mtu, new_mtu);
5198 	netdev->mtu = new_mtu;
5199 
5200 	if (netif_running(netdev))
5201 		igb_up(adapter);
5202 	else
5203 		igb_reset(adapter);
5204 
5205 	clear_bit(__IGB_RESETTING, &adapter->state);
5206 
5207 	return 0;
5208 }
5209 
5210 /**
5211  *  igb_update_stats - Update the board statistics counters
5212  *  @adapter: board private structure
5213  **/
igb_update_stats(struct igb_adapter * adapter,struct rtnl_link_stats64 * net_stats)5214 void igb_update_stats(struct igb_adapter *adapter,
5215 		      struct rtnl_link_stats64 *net_stats)
5216 {
5217 	struct e1000_hw *hw = &adapter->hw;
5218 	struct pci_dev *pdev = adapter->pdev;
5219 	u32 reg, mpc;
5220 	int i;
5221 	u64 bytes, packets;
5222 	unsigned int start;
5223 	u64 _bytes, _packets;
5224 
5225 	/* Prevent stats update while adapter is being reset, or if the pci
5226 	 * connection is down.
5227 	 */
5228 	if (adapter->link_speed == 0)
5229 		return;
5230 	if (pci_channel_offline(pdev))
5231 		return;
5232 
5233 	bytes = 0;
5234 	packets = 0;
5235 
5236 	rcu_read_lock();
5237 	for (i = 0; i < adapter->num_rx_queues; i++) {
5238 		struct igb_ring *ring = adapter->rx_ring[i];
5239 		u32 rqdpc = rd32(E1000_RQDPC(i));
5240 		if (hw->mac.type >= e1000_i210)
5241 			wr32(E1000_RQDPC(i), 0);
5242 
5243 		if (rqdpc) {
5244 			ring->rx_stats.drops += rqdpc;
5245 			net_stats->rx_fifo_errors += rqdpc;
5246 		}
5247 
5248 		do {
5249 			start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5250 			_bytes = ring->rx_stats.bytes;
5251 			_packets = ring->rx_stats.packets;
5252 		} while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5253 		bytes += _bytes;
5254 		packets += _packets;
5255 	}
5256 
5257 	net_stats->rx_bytes = bytes;
5258 	net_stats->rx_packets = packets;
5259 
5260 	bytes = 0;
5261 	packets = 0;
5262 	for (i = 0; i < adapter->num_tx_queues; i++) {
5263 		struct igb_ring *ring = adapter->tx_ring[i];
5264 		do {
5265 			start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5266 			_bytes = ring->tx_stats.bytes;
5267 			_packets = ring->tx_stats.packets;
5268 		} while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5269 		bytes += _bytes;
5270 		packets += _packets;
5271 	}
5272 	net_stats->tx_bytes = bytes;
5273 	net_stats->tx_packets = packets;
5274 	rcu_read_unlock();
5275 
5276 	/* read stats registers */
5277 	adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5278 	adapter->stats.gprc += rd32(E1000_GPRC);
5279 	adapter->stats.gorc += rd32(E1000_GORCL);
5280 	rd32(E1000_GORCH); /* clear GORCL */
5281 	adapter->stats.bprc += rd32(E1000_BPRC);
5282 	adapter->stats.mprc += rd32(E1000_MPRC);
5283 	adapter->stats.roc += rd32(E1000_ROC);
5284 
5285 	adapter->stats.prc64 += rd32(E1000_PRC64);
5286 	adapter->stats.prc127 += rd32(E1000_PRC127);
5287 	adapter->stats.prc255 += rd32(E1000_PRC255);
5288 	adapter->stats.prc511 += rd32(E1000_PRC511);
5289 	adapter->stats.prc1023 += rd32(E1000_PRC1023);
5290 	adapter->stats.prc1522 += rd32(E1000_PRC1522);
5291 	adapter->stats.symerrs += rd32(E1000_SYMERRS);
5292 	adapter->stats.sec += rd32(E1000_SEC);
5293 
5294 	mpc = rd32(E1000_MPC);
5295 	adapter->stats.mpc += mpc;
5296 	net_stats->rx_fifo_errors += mpc;
5297 	adapter->stats.scc += rd32(E1000_SCC);
5298 	adapter->stats.ecol += rd32(E1000_ECOL);
5299 	adapter->stats.mcc += rd32(E1000_MCC);
5300 	adapter->stats.latecol += rd32(E1000_LATECOL);
5301 	adapter->stats.dc += rd32(E1000_DC);
5302 	adapter->stats.rlec += rd32(E1000_RLEC);
5303 	adapter->stats.xonrxc += rd32(E1000_XONRXC);
5304 	adapter->stats.xontxc += rd32(E1000_XONTXC);
5305 	adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5306 	adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5307 	adapter->stats.fcruc += rd32(E1000_FCRUC);
5308 	adapter->stats.gptc += rd32(E1000_GPTC);
5309 	adapter->stats.gotc += rd32(E1000_GOTCL);
5310 	rd32(E1000_GOTCH); /* clear GOTCL */
5311 	adapter->stats.rnbc += rd32(E1000_RNBC);
5312 	adapter->stats.ruc += rd32(E1000_RUC);
5313 	adapter->stats.rfc += rd32(E1000_RFC);
5314 	adapter->stats.rjc += rd32(E1000_RJC);
5315 	adapter->stats.tor += rd32(E1000_TORH);
5316 	adapter->stats.tot += rd32(E1000_TOTH);
5317 	adapter->stats.tpr += rd32(E1000_TPR);
5318 
5319 	adapter->stats.ptc64 += rd32(E1000_PTC64);
5320 	adapter->stats.ptc127 += rd32(E1000_PTC127);
5321 	adapter->stats.ptc255 += rd32(E1000_PTC255);
5322 	adapter->stats.ptc511 += rd32(E1000_PTC511);
5323 	adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5324 	adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5325 
5326 	adapter->stats.mptc += rd32(E1000_MPTC);
5327 	adapter->stats.bptc += rd32(E1000_BPTC);
5328 
5329 	adapter->stats.tpt += rd32(E1000_TPT);
5330 	adapter->stats.colc += rd32(E1000_COLC);
5331 
5332 	adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5333 	/* read internal phy specific stats */
5334 	reg = rd32(E1000_CTRL_EXT);
5335 	if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5336 		adapter->stats.rxerrc += rd32(E1000_RXERRC);
5337 
5338 		/* this stat has invalid values on i210/i211 */
5339 		if ((hw->mac.type != e1000_i210) &&
5340 		    (hw->mac.type != e1000_i211))
5341 			adapter->stats.tncrs += rd32(E1000_TNCRS);
5342 	}
5343 
5344 	adapter->stats.tsctc += rd32(E1000_TSCTC);
5345 	adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5346 
5347 	adapter->stats.iac += rd32(E1000_IAC);
5348 	adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5349 	adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5350 	adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5351 	adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5352 	adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5353 	adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5354 	adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5355 	adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5356 
5357 	/* Fill out the OS statistics structure */
5358 	net_stats->multicast = adapter->stats.mprc;
5359 	net_stats->collisions = adapter->stats.colc;
5360 
5361 	/* Rx Errors */
5362 
5363 	/* RLEC on some newer hardware can be incorrect so build
5364 	 * our own version based on RUC and ROC
5365 	 */
5366 	net_stats->rx_errors = adapter->stats.rxerrc +
5367 		adapter->stats.crcerrs + adapter->stats.algnerrc +
5368 		adapter->stats.ruc + adapter->stats.roc +
5369 		adapter->stats.cexterr;
5370 	net_stats->rx_length_errors = adapter->stats.ruc +
5371 				      adapter->stats.roc;
5372 	net_stats->rx_crc_errors = adapter->stats.crcerrs;
5373 	net_stats->rx_frame_errors = adapter->stats.algnerrc;
5374 	net_stats->rx_missed_errors = adapter->stats.mpc;
5375 
5376 	/* Tx Errors */
5377 	net_stats->tx_errors = adapter->stats.ecol +
5378 			       adapter->stats.latecol;
5379 	net_stats->tx_aborted_errors = adapter->stats.ecol;
5380 	net_stats->tx_window_errors = adapter->stats.latecol;
5381 	net_stats->tx_carrier_errors = adapter->stats.tncrs;
5382 
5383 	/* Tx Dropped needs to be maintained elsewhere */
5384 
5385 	/* Management Stats */
5386 	adapter->stats.mgptc += rd32(E1000_MGTPTC);
5387 	adapter->stats.mgprc += rd32(E1000_MGTPRC);
5388 	adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5389 
5390 	/* OS2BMC Stats */
5391 	reg = rd32(E1000_MANC);
5392 	if (reg & E1000_MANC_EN_BMC2OS) {
5393 		adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5394 		adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5395 		adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5396 		adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5397 	}
5398 }
5399 
igb_tsync_interrupt(struct igb_adapter * adapter)5400 static void igb_tsync_interrupt(struct igb_adapter *adapter)
5401 {
5402 	struct e1000_hw *hw = &adapter->hw;
5403 	struct ptp_clock_event event;
5404 	struct timespec ts;
5405 	u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
5406 
5407 	if (tsicr & TSINTR_SYS_WRAP) {
5408 		event.type = PTP_CLOCK_PPS;
5409 		if (adapter->ptp_caps.pps)
5410 			ptp_clock_event(adapter->ptp_clock, &event);
5411 		else
5412 			dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5413 		ack |= TSINTR_SYS_WRAP;
5414 	}
5415 
5416 	if (tsicr & E1000_TSICR_TXTS) {
5417 		/* retrieve hardware timestamp */
5418 		schedule_work(&adapter->ptp_tx_work);
5419 		ack |= E1000_TSICR_TXTS;
5420 	}
5421 
5422 	if (tsicr & TSINTR_TT0) {
5423 		spin_lock(&adapter->tmreg_lock);
5424 		ts = timespec_add(adapter->perout[0].start,
5425 				  adapter->perout[0].period);
5426 		wr32(E1000_TRGTTIML0, ts.tv_nsec);
5427 		wr32(E1000_TRGTTIMH0, ts.tv_sec);
5428 		tsauxc = rd32(E1000_TSAUXC);
5429 		tsauxc |= TSAUXC_EN_TT0;
5430 		wr32(E1000_TSAUXC, tsauxc);
5431 		adapter->perout[0].start = ts;
5432 		spin_unlock(&adapter->tmreg_lock);
5433 		ack |= TSINTR_TT0;
5434 	}
5435 
5436 	if (tsicr & TSINTR_TT1) {
5437 		spin_lock(&adapter->tmreg_lock);
5438 		ts = timespec_add(adapter->perout[1].start,
5439 				  adapter->perout[1].period);
5440 		wr32(E1000_TRGTTIML1, ts.tv_nsec);
5441 		wr32(E1000_TRGTTIMH1, ts.tv_sec);
5442 		tsauxc = rd32(E1000_TSAUXC);
5443 		tsauxc |= TSAUXC_EN_TT1;
5444 		wr32(E1000_TSAUXC, tsauxc);
5445 		adapter->perout[1].start = ts;
5446 		spin_unlock(&adapter->tmreg_lock);
5447 		ack |= TSINTR_TT1;
5448 	}
5449 
5450 	if (tsicr & TSINTR_AUTT0) {
5451 		nsec = rd32(E1000_AUXSTMPL0);
5452 		sec  = rd32(E1000_AUXSTMPH0);
5453 		event.type = PTP_CLOCK_EXTTS;
5454 		event.index = 0;
5455 		event.timestamp = sec * 1000000000ULL + nsec;
5456 		ptp_clock_event(adapter->ptp_clock, &event);
5457 		ack |= TSINTR_AUTT0;
5458 	}
5459 
5460 	if (tsicr & TSINTR_AUTT1) {
5461 		nsec = rd32(E1000_AUXSTMPL1);
5462 		sec  = rd32(E1000_AUXSTMPH1);
5463 		event.type = PTP_CLOCK_EXTTS;
5464 		event.index = 1;
5465 		event.timestamp = sec * 1000000000ULL + nsec;
5466 		ptp_clock_event(adapter->ptp_clock, &event);
5467 		ack |= TSINTR_AUTT1;
5468 	}
5469 
5470 	/* acknowledge the interrupts */
5471 	wr32(E1000_TSICR, ack);
5472 }
5473 
igb_msix_other(int irq,void * data)5474 static irqreturn_t igb_msix_other(int irq, void *data)
5475 {
5476 	struct igb_adapter *adapter = data;
5477 	struct e1000_hw *hw = &adapter->hw;
5478 	u32 icr = rd32(E1000_ICR);
5479 	/* reading ICR causes bit 31 of EICR to be cleared */
5480 
5481 	if (icr & E1000_ICR_DRSTA)
5482 		schedule_work(&adapter->reset_task);
5483 
5484 	if (icr & E1000_ICR_DOUTSYNC) {
5485 		/* HW is reporting DMA is out of sync */
5486 		adapter->stats.doosync++;
5487 		/* The DMA Out of Sync is also indication of a spoof event
5488 		 * in IOV mode. Check the Wrong VM Behavior register to
5489 		 * see if it is really a spoof event.
5490 		 */
5491 		igb_check_wvbr(adapter);
5492 	}
5493 
5494 	/* Check for a mailbox event */
5495 	if (icr & E1000_ICR_VMMB)
5496 		igb_msg_task(adapter);
5497 
5498 	if (icr & E1000_ICR_LSC) {
5499 		hw->mac.get_link_status = 1;
5500 		/* guard against interrupt when we're going down */
5501 		if (!test_bit(__IGB_DOWN, &adapter->state))
5502 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
5503 	}
5504 
5505 	if (icr & E1000_ICR_TS)
5506 		igb_tsync_interrupt(adapter);
5507 
5508 	wr32(E1000_EIMS, adapter->eims_other);
5509 
5510 	return IRQ_HANDLED;
5511 }
5512 
igb_write_itr(struct igb_q_vector * q_vector)5513 static void igb_write_itr(struct igb_q_vector *q_vector)
5514 {
5515 	struct igb_adapter *adapter = q_vector->adapter;
5516 	u32 itr_val = q_vector->itr_val & 0x7FFC;
5517 
5518 	if (!q_vector->set_itr)
5519 		return;
5520 
5521 	if (!itr_val)
5522 		itr_val = 0x4;
5523 
5524 	if (adapter->hw.mac.type == e1000_82575)
5525 		itr_val |= itr_val << 16;
5526 	else
5527 		itr_val |= E1000_EITR_CNT_IGNR;
5528 
5529 	writel(itr_val, q_vector->itr_register);
5530 	q_vector->set_itr = 0;
5531 }
5532 
igb_msix_ring(int irq,void * data)5533 static irqreturn_t igb_msix_ring(int irq, void *data)
5534 {
5535 	struct igb_q_vector *q_vector = data;
5536 
5537 	/* Write the ITR value calculated from the previous interrupt. */
5538 	igb_write_itr(q_vector);
5539 
5540 	napi_schedule(&q_vector->napi);
5541 
5542 	return IRQ_HANDLED;
5543 }
5544 
5545 #ifdef CONFIG_IGB_DCA
igb_update_tx_dca(struct igb_adapter * adapter,struct igb_ring * tx_ring,int cpu)5546 static void igb_update_tx_dca(struct igb_adapter *adapter,
5547 			      struct igb_ring *tx_ring,
5548 			      int cpu)
5549 {
5550 	struct e1000_hw *hw = &adapter->hw;
5551 	u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5552 
5553 	if (hw->mac.type != e1000_82575)
5554 		txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5555 
5556 	/* We can enable relaxed ordering for reads, but not writes when
5557 	 * DCA is enabled.  This is due to a known issue in some chipsets
5558 	 * which will cause the DCA tag to be cleared.
5559 	 */
5560 	txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5561 		  E1000_DCA_TXCTRL_DATA_RRO_EN |
5562 		  E1000_DCA_TXCTRL_DESC_DCA_EN;
5563 
5564 	wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5565 }
5566 
igb_update_rx_dca(struct igb_adapter * adapter,struct igb_ring * rx_ring,int cpu)5567 static void igb_update_rx_dca(struct igb_adapter *adapter,
5568 			      struct igb_ring *rx_ring,
5569 			      int cpu)
5570 {
5571 	struct e1000_hw *hw = &adapter->hw;
5572 	u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5573 
5574 	if (hw->mac.type != e1000_82575)
5575 		rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5576 
5577 	/* We can enable relaxed ordering for reads, but not writes when
5578 	 * DCA is enabled.  This is due to a known issue in some chipsets
5579 	 * which will cause the DCA tag to be cleared.
5580 	 */
5581 	rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5582 		  E1000_DCA_RXCTRL_DESC_DCA_EN;
5583 
5584 	wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5585 }
5586 
igb_update_dca(struct igb_q_vector * q_vector)5587 static void igb_update_dca(struct igb_q_vector *q_vector)
5588 {
5589 	struct igb_adapter *adapter = q_vector->adapter;
5590 	int cpu = get_cpu();
5591 
5592 	if (q_vector->cpu == cpu)
5593 		goto out_no_update;
5594 
5595 	if (q_vector->tx.ring)
5596 		igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5597 
5598 	if (q_vector->rx.ring)
5599 		igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5600 
5601 	q_vector->cpu = cpu;
5602 out_no_update:
5603 	put_cpu();
5604 }
5605 
igb_setup_dca(struct igb_adapter * adapter)5606 static void igb_setup_dca(struct igb_adapter *adapter)
5607 {
5608 	struct e1000_hw *hw = &adapter->hw;
5609 	int i;
5610 
5611 	if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5612 		return;
5613 
5614 	/* Always use CB2 mode, difference is masked in the CB driver. */
5615 	wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5616 
5617 	for (i = 0; i < adapter->num_q_vectors; i++) {
5618 		adapter->q_vector[i]->cpu = -1;
5619 		igb_update_dca(adapter->q_vector[i]);
5620 	}
5621 }
5622 
__igb_notify_dca(struct device * dev,void * data)5623 static int __igb_notify_dca(struct device *dev, void *data)
5624 {
5625 	struct net_device *netdev = dev_get_drvdata(dev);
5626 	struct igb_adapter *adapter = netdev_priv(netdev);
5627 	struct pci_dev *pdev = adapter->pdev;
5628 	struct e1000_hw *hw = &adapter->hw;
5629 	unsigned long event = *(unsigned long *)data;
5630 
5631 	switch (event) {
5632 	case DCA_PROVIDER_ADD:
5633 		/* if already enabled, don't do it again */
5634 		if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5635 			break;
5636 		if (dca_add_requester(dev) == 0) {
5637 			adapter->flags |= IGB_FLAG_DCA_ENABLED;
5638 			dev_info(&pdev->dev, "DCA enabled\n");
5639 			igb_setup_dca(adapter);
5640 			break;
5641 		}
5642 		/* Fall Through since DCA is disabled. */
5643 	case DCA_PROVIDER_REMOVE:
5644 		if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5645 			/* without this a class_device is left
5646 			 * hanging around in the sysfs model
5647 			 */
5648 			dca_remove_requester(dev);
5649 			dev_info(&pdev->dev, "DCA disabled\n");
5650 			adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5651 			wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5652 		}
5653 		break;
5654 	}
5655 
5656 	return 0;
5657 }
5658 
igb_notify_dca(struct notifier_block * nb,unsigned long event,void * p)5659 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5660 			  void *p)
5661 {
5662 	int ret_val;
5663 
5664 	ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5665 					 __igb_notify_dca);
5666 
5667 	return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5668 }
5669 #endif /* CONFIG_IGB_DCA */
5670 
5671 #ifdef CONFIG_PCI_IOV
igb_vf_configure(struct igb_adapter * adapter,int vf)5672 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5673 {
5674 	unsigned char mac_addr[ETH_ALEN];
5675 
5676 	eth_zero_addr(mac_addr);
5677 	igb_set_vf_mac(adapter, vf, mac_addr);
5678 
5679 	/* By default spoof check is enabled for all VFs */
5680 	adapter->vf_data[vf].spoofchk_enabled = true;
5681 
5682 	return 0;
5683 }
5684 
5685 #endif
igb_ping_all_vfs(struct igb_adapter * adapter)5686 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5687 {
5688 	struct e1000_hw *hw = &adapter->hw;
5689 	u32 ping;
5690 	int i;
5691 
5692 	for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5693 		ping = E1000_PF_CONTROL_MSG;
5694 		if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5695 			ping |= E1000_VT_MSGTYPE_CTS;
5696 		igb_write_mbx(hw, &ping, 1, i);
5697 	}
5698 }
5699 
igb_set_vf_promisc(struct igb_adapter * adapter,u32 * msgbuf,u32 vf)5700 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5701 {
5702 	struct e1000_hw *hw = &adapter->hw;
5703 	u32 vmolr = rd32(E1000_VMOLR(vf));
5704 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5705 
5706 	vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5707 			    IGB_VF_FLAG_MULTI_PROMISC);
5708 	vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5709 
5710 	if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5711 		vmolr |= E1000_VMOLR_MPME;
5712 		vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5713 		*msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5714 	} else {
5715 		/* if we have hashes and we are clearing a multicast promisc
5716 		 * flag we need to write the hashes to the MTA as this step
5717 		 * was previously skipped
5718 		 */
5719 		if (vf_data->num_vf_mc_hashes > 30) {
5720 			vmolr |= E1000_VMOLR_MPME;
5721 		} else if (vf_data->num_vf_mc_hashes) {
5722 			int j;
5723 
5724 			vmolr |= E1000_VMOLR_ROMPE;
5725 			for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5726 				igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5727 		}
5728 	}
5729 
5730 	wr32(E1000_VMOLR(vf), vmolr);
5731 
5732 	/* there are flags left unprocessed, likely not supported */
5733 	if (*msgbuf & E1000_VT_MSGINFO_MASK)
5734 		return -EINVAL;
5735 
5736 	return 0;
5737 }
5738 
igb_set_vf_multicasts(struct igb_adapter * adapter,u32 * msgbuf,u32 vf)5739 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5740 				  u32 *msgbuf, u32 vf)
5741 {
5742 	int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5743 	u16 *hash_list = (u16 *)&msgbuf[1];
5744 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5745 	int i;
5746 
5747 	/* salt away the number of multicast addresses assigned
5748 	 * to this VF for later use to restore when the PF multi cast
5749 	 * list changes
5750 	 */
5751 	vf_data->num_vf_mc_hashes = n;
5752 
5753 	/* only up to 30 hash values supported */
5754 	if (n > 30)
5755 		n = 30;
5756 
5757 	/* store the hashes for later use */
5758 	for (i = 0; i < n; i++)
5759 		vf_data->vf_mc_hashes[i] = hash_list[i];
5760 
5761 	/* Flush and reset the mta with the new values */
5762 	igb_set_rx_mode(adapter->netdev);
5763 
5764 	return 0;
5765 }
5766 
igb_restore_vf_multicasts(struct igb_adapter * adapter)5767 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5768 {
5769 	struct e1000_hw *hw = &adapter->hw;
5770 	struct vf_data_storage *vf_data;
5771 	int i, j;
5772 
5773 	for (i = 0; i < adapter->vfs_allocated_count; i++) {
5774 		u32 vmolr = rd32(E1000_VMOLR(i));
5775 
5776 		vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5777 
5778 		vf_data = &adapter->vf_data[i];
5779 
5780 		if ((vf_data->num_vf_mc_hashes > 30) ||
5781 		    (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5782 			vmolr |= E1000_VMOLR_MPME;
5783 		} else if (vf_data->num_vf_mc_hashes) {
5784 			vmolr |= E1000_VMOLR_ROMPE;
5785 			for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5786 				igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5787 		}
5788 		wr32(E1000_VMOLR(i), vmolr);
5789 	}
5790 }
5791 
igb_clear_vf_vfta(struct igb_adapter * adapter,u32 vf)5792 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5793 {
5794 	struct e1000_hw *hw = &adapter->hw;
5795 	u32 pool_mask, reg, vid;
5796 	int i;
5797 
5798 	pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5799 
5800 	/* Find the vlan filter for this id */
5801 	for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5802 		reg = rd32(E1000_VLVF(i));
5803 
5804 		/* remove the vf from the pool */
5805 		reg &= ~pool_mask;
5806 
5807 		/* if pool is empty then remove entry from vfta */
5808 		if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5809 		    (reg & E1000_VLVF_VLANID_ENABLE)) {
5810 			reg = 0;
5811 			vid = reg & E1000_VLVF_VLANID_MASK;
5812 			igb_vfta_set(hw, vid, false);
5813 		}
5814 
5815 		wr32(E1000_VLVF(i), reg);
5816 	}
5817 
5818 	adapter->vf_data[vf].vlans_enabled = 0;
5819 }
5820 
igb_vlvf_set(struct igb_adapter * adapter,u32 vid,bool add,u32 vf)5821 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5822 {
5823 	struct e1000_hw *hw = &adapter->hw;
5824 	u32 reg, i;
5825 
5826 	/* The vlvf table only exists on 82576 hardware and newer */
5827 	if (hw->mac.type < e1000_82576)
5828 		return -1;
5829 
5830 	/* we only need to do this if VMDq is enabled */
5831 	if (!adapter->vfs_allocated_count)
5832 		return -1;
5833 
5834 	/* Find the vlan filter for this id */
5835 	for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5836 		reg = rd32(E1000_VLVF(i));
5837 		if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5838 		    vid == (reg & E1000_VLVF_VLANID_MASK))
5839 			break;
5840 	}
5841 
5842 	if (add) {
5843 		if (i == E1000_VLVF_ARRAY_SIZE) {
5844 			/* Did not find a matching VLAN ID entry that was
5845 			 * enabled.  Search for a free filter entry, i.e.
5846 			 * one without the enable bit set
5847 			 */
5848 			for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5849 				reg = rd32(E1000_VLVF(i));
5850 				if (!(reg & E1000_VLVF_VLANID_ENABLE))
5851 					break;
5852 			}
5853 		}
5854 		if (i < E1000_VLVF_ARRAY_SIZE) {
5855 			/* Found an enabled/available entry */
5856 			reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5857 
5858 			/* if !enabled we need to set this up in vfta */
5859 			if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5860 				/* add VID to filter table */
5861 				igb_vfta_set(hw, vid, true);
5862 				reg |= E1000_VLVF_VLANID_ENABLE;
5863 			}
5864 			reg &= ~E1000_VLVF_VLANID_MASK;
5865 			reg |= vid;
5866 			wr32(E1000_VLVF(i), reg);
5867 
5868 			/* do not modify RLPML for PF devices */
5869 			if (vf >= adapter->vfs_allocated_count)
5870 				return 0;
5871 
5872 			if (!adapter->vf_data[vf].vlans_enabled) {
5873 				u32 size;
5874 
5875 				reg = rd32(E1000_VMOLR(vf));
5876 				size = reg & E1000_VMOLR_RLPML_MASK;
5877 				size += 4;
5878 				reg &= ~E1000_VMOLR_RLPML_MASK;
5879 				reg |= size;
5880 				wr32(E1000_VMOLR(vf), reg);
5881 			}
5882 
5883 			adapter->vf_data[vf].vlans_enabled++;
5884 		}
5885 	} else {
5886 		if (i < E1000_VLVF_ARRAY_SIZE) {
5887 			/* remove vf from the pool */
5888 			reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5889 			/* if pool is empty then remove entry from vfta */
5890 			if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5891 				reg = 0;
5892 				igb_vfta_set(hw, vid, false);
5893 			}
5894 			wr32(E1000_VLVF(i), reg);
5895 
5896 			/* do not modify RLPML for PF devices */
5897 			if (vf >= adapter->vfs_allocated_count)
5898 				return 0;
5899 
5900 			adapter->vf_data[vf].vlans_enabled--;
5901 			if (!adapter->vf_data[vf].vlans_enabled) {
5902 				u32 size;
5903 
5904 				reg = rd32(E1000_VMOLR(vf));
5905 				size = reg & E1000_VMOLR_RLPML_MASK;
5906 				size -= 4;
5907 				reg &= ~E1000_VMOLR_RLPML_MASK;
5908 				reg |= size;
5909 				wr32(E1000_VMOLR(vf), reg);
5910 			}
5911 		}
5912 	}
5913 	return 0;
5914 }
5915 
igb_set_vmvir(struct igb_adapter * adapter,u32 vid,u32 vf)5916 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5917 {
5918 	struct e1000_hw *hw = &adapter->hw;
5919 
5920 	if (vid)
5921 		wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5922 	else
5923 		wr32(E1000_VMVIR(vf), 0);
5924 }
5925 
igb_ndo_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos)5926 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5927 			       int vf, u16 vlan, u8 qos)
5928 {
5929 	int err = 0;
5930 	struct igb_adapter *adapter = netdev_priv(netdev);
5931 
5932 	if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5933 		return -EINVAL;
5934 	if (vlan || qos) {
5935 		err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5936 		if (err)
5937 			goto out;
5938 		igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5939 		igb_set_vmolr(adapter, vf, !vlan);
5940 		adapter->vf_data[vf].pf_vlan = vlan;
5941 		adapter->vf_data[vf].pf_qos = qos;
5942 		dev_info(&adapter->pdev->dev,
5943 			 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5944 		if (test_bit(__IGB_DOWN, &adapter->state)) {
5945 			dev_warn(&adapter->pdev->dev,
5946 				 "The VF VLAN has been set, but the PF device is not up.\n");
5947 			dev_warn(&adapter->pdev->dev,
5948 				 "Bring the PF device up before attempting to use the VF device.\n");
5949 		}
5950 	} else {
5951 		igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5952 			     false, vf);
5953 		igb_set_vmvir(adapter, vlan, vf);
5954 		igb_set_vmolr(adapter, vf, true);
5955 		adapter->vf_data[vf].pf_vlan = 0;
5956 		adapter->vf_data[vf].pf_qos = 0;
5957 	}
5958 out:
5959 	return err;
5960 }
5961 
igb_find_vlvf_entry(struct igb_adapter * adapter,int vid)5962 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5963 {
5964 	struct e1000_hw *hw = &adapter->hw;
5965 	int i;
5966 	u32 reg;
5967 
5968 	/* Find the vlan filter for this id */
5969 	for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5970 		reg = rd32(E1000_VLVF(i));
5971 		if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5972 		    vid == (reg & E1000_VLVF_VLANID_MASK))
5973 			break;
5974 	}
5975 
5976 	if (i >= E1000_VLVF_ARRAY_SIZE)
5977 		i = -1;
5978 
5979 	return i;
5980 }
5981 
igb_set_vf_vlan(struct igb_adapter * adapter,u32 * msgbuf,u32 vf)5982 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5983 {
5984 	struct e1000_hw *hw = &adapter->hw;
5985 	int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5986 	int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5987 	int err = 0;
5988 
5989 	/* If in promiscuous mode we need to make sure the PF also has
5990 	 * the VLAN filter set.
5991 	 */
5992 	if (add && (adapter->netdev->flags & IFF_PROMISC))
5993 		err = igb_vlvf_set(adapter, vid, add,
5994 				   adapter->vfs_allocated_count);
5995 	if (err)
5996 		goto out;
5997 
5998 	err = igb_vlvf_set(adapter, vid, add, vf);
5999 
6000 	if (err)
6001 		goto out;
6002 
6003 	/* Go through all the checks to see if the VLAN filter should
6004 	 * be wiped completely.
6005 	 */
6006 	if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
6007 		u32 vlvf, bits;
6008 		int regndx = igb_find_vlvf_entry(adapter, vid);
6009 
6010 		if (regndx < 0)
6011 			goto out;
6012 		/* See if any other pools are set for this VLAN filter
6013 		 * entry other than the PF.
6014 		 */
6015 		vlvf = bits = rd32(E1000_VLVF(regndx));
6016 		bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
6017 			      adapter->vfs_allocated_count);
6018 		/* If the filter was removed then ensure PF pool bit
6019 		 * is cleared if the PF only added itself to the pool
6020 		 * because the PF is in promiscuous mode.
6021 		 */
6022 		if ((vlvf & VLAN_VID_MASK) == vid &&
6023 		    !test_bit(vid, adapter->active_vlans) &&
6024 		    !bits)
6025 			igb_vlvf_set(adapter, vid, add,
6026 				     adapter->vfs_allocated_count);
6027 	}
6028 
6029 out:
6030 	return err;
6031 }
6032 
igb_vf_reset(struct igb_adapter * adapter,u32 vf)6033 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6034 {
6035 	/* clear flags - except flag that indicates PF has set the MAC */
6036 	adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
6037 	adapter->vf_data[vf].last_nack = jiffies;
6038 
6039 	/* reset offloads to defaults */
6040 	igb_set_vmolr(adapter, vf, true);
6041 
6042 	/* reset vlans for device */
6043 	igb_clear_vf_vfta(adapter, vf);
6044 	if (adapter->vf_data[vf].pf_vlan)
6045 		igb_ndo_set_vf_vlan(adapter->netdev, vf,
6046 				    adapter->vf_data[vf].pf_vlan,
6047 				    adapter->vf_data[vf].pf_qos);
6048 	else
6049 		igb_clear_vf_vfta(adapter, vf);
6050 
6051 	/* reset multicast table array for vf */
6052 	adapter->vf_data[vf].num_vf_mc_hashes = 0;
6053 
6054 	/* Flush and reset the mta with the new values */
6055 	igb_set_rx_mode(adapter->netdev);
6056 }
6057 
igb_vf_reset_event(struct igb_adapter * adapter,u32 vf)6058 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6059 {
6060 	unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6061 
6062 	/* clear mac address as we were hotplug removed/added */
6063 	if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
6064 		eth_zero_addr(vf_mac);
6065 
6066 	/* process remaining reset events */
6067 	igb_vf_reset(adapter, vf);
6068 }
6069 
igb_vf_reset_msg(struct igb_adapter * adapter,u32 vf)6070 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
6071 {
6072 	struct e1000_hw *hw = &adapter->hw;
6073 	unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6074 	int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6075 	u32 reg, msgbuf[3];
6076 	u8 *addr = (u8 *)(&msgbuf[1]);
6077 
6078 	/* process all the same items cleared in a function level reset */
6079 	igb_vf_reset(adapter, vf);
6080 
6081 	/* set vf mac address */
6082 	igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
6083 
6084 	/* enable transmit and receive for vf */
6085 	reg = rd32(E1000_VFTE);
6086 	wr32(E1000_VFTE, reg | (1 << vf));
6087 	reg = rd32(E1000_VFRE);
6088 	wr32(E1000_VFRE, reg | (1 << vf));
6089 
6090 	adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6091 
6092 	/* reply to reset with ack and vf mac address */
6093 	if (!is_zero_ether_addr(vf_mac)) {
6094 		msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6095 		memcpy(addr, vf_mac, ETH_ALEN);
6096 	} else {
6097 		msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6098 	}
6099 	igb_write_mbx(hw, msgbuf, 3, vf);
6100 }
6101 
igb_set_vf_mac_addr(struct igb_adapter * adapter,u32 * msg,int vf)6102 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6103 {
6104 	/* The VF MAC Address is stored in a packed array of bytes
6105 	 * starting at the second 32 bit word of the msg array
6106 	 */
6107 	unsigned char *addr = (char *)&msg[1];
6108 	int err = -1;
6109 
6110 	if (is_valid_ether_addr(addr))
6111 		err = igb_set_vf_mac(adapter, vf, addr);
6112 
6113 	return err;
6114 }
6115 
igb_rcv_ack_from_vf(struct igb_adapter * adapter,u32 vf)6116 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6117 {
6118 	struct e1000_hw *hw = &adapter->hw;
6119 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6120 	u32 msg = E1000_VT_MSGTYPE_NACK;
6121 
6122 	/* if device isn't clear to send it shouldn't be reading either */
6123 	if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6124 	    time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
6125 		igb_write_mbx(hw, &msg, 1, vf);
6126 		vf_data->last_nack = jiffies;
6127 	}
6128 }
6129 
igb_rcv_msg_from_vf(struct igb_adapter * adapter,u32 vf)6130 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
6131 {
6132 	struct pci_dev *pdev = adapter->pdev;
6133 	u32 msgbuf[E1000_VFMAILBOX_SIZE];
6134 	struct e1000_hw *hw = &adapter->hw;
6135 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6136 	s32 retval;
6137 
6138 	retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
6139 
6140 	if (retval) {
6141 		/* if receive failed revoke VF CTS stats and restart init */
6142 		dev_err(&pdev->dev, "Error receiving message from VF\n");
6143 		vf_data->flags &= ~IGB_VF_FLAG_CTS;
6144 		if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6145 			return;
6146 		goto out;
6147 	}
6148 
6149 	/* this is a message we already processed, do nothing */
6150 	if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
6151 		return;
6152 
6153 	/* until the vf completes a reset it should not be
6154 	 * allowed to start any configuration.
6155 	 */
6156 	if (msgbuf[0] == E1000_VF_RESET) {
6157 		igb_vf_reset_msg(adapter, vf);
6158 		return;
6159 	}
6160 
6161 	if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
6162 		if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6163 			return;
6164 		retval = -1;
6165 		goto out;
6166 	}
6167 
6168 	switch ((msgbuf[0] & 0xFFFF)) {
6169 	case E1000_VF_SET_MAC_ADDR:
6170 		retval = -EINVAL;
6171 		if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6172 			retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6173 		else
6174 			dev_warn(&pdev->dev,
6175 				 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6176 				 vf);
6177 		break;
6178 	case E1000_VF_SET_PROMISC:
6179 		retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6180 		break;
6181 	case E1000_VF_SET_MULTICAST:
6182 		retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6183 		break;
6184 	case E1000_VF_SET_LPE:
6185 		retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6186 		break;
6187 	case E1000_VF_SET_VLAN:
6188 		retval = -1;
6189 		if (vf_data->pf_vlan)
6190 			dev_warn(&pdev->dev,
6191 				 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6192 				 vf);
6193 		else
6194 			retval = igb_set_vf_vlan(adapter, msgbuf, vf);
6195 		break;
6196 	default:
6197 		dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
6198 		retval = -1;
6199 		break;
6200 	}
6201 
6202 	msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6203 out:
6204 	/* notify the VF of the results of what it sent us */
6205 	if (retval)
6206 		msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6207 	else
6208 		msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6209 
6210 	igb_write_mbx(hw, msgbuf, 1, vf);
6211 }
6212 
igb_msg_task(struct igb_adapter * adapter)6213 static void igb_msg_task(struct igb_adapter *adapter)
6214 {
6215 	struct e1000_hw *hw = &adapter->hw;
6216 	u32 vf;
6217 
6218 	for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6219 		/* process any reset requests */
6220 		if (!igb_check_for_rst(hw, vf))
6221 			igb_vf_reset_event(adapter, vf);
6222 
6223 		/* process any messages pending */
6224 		if (!igb_check_for_msg(hw, vf))
6225 			igb_rcv_msg_from_vf(adapter, vf);
6226 
6227 		/* process any acks */
6228 		if (!igb_check_for_ack(hw, vf))
6229 			igb_rcv_ack_from_vf(adapter, vf);
6230 	}
6231 }
6232 
6233 /**
6234  *  igb_set_uta - Set unicast filter table address
6235  *  @adapter: board private structure
6236  *
6237  *  The unicast table address is a register array of 32-bit registers.
6238  *  The table is meant to be used in a way similar to how the MTA is used
6239  *  however due to certain limitations in the hardware it is necessary to
6240  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6241  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
6242  **/
igb_set_uta(struct igb_adapter * adapter)6243 static void igb_set_uta(struct igb_adapter *adapter)
6244 {
6245 	struct e1000_hw *hw = &adapter->hw;
6246 	int i;
6247 
6248 	/* The UTA table only exists on 82576 hardware and newer */
6249 	if (hw->mac.type < e1000_82576)
6250 		return;
6251 
6252 	/* we only need to do this if VMDq is enabled */
6253 	if (!adapter->vfs_allocated_count)
6254 		return;
6255 
6256 	for (i = 0; i < hw->mac.uta_reg_count; i++)
6257 		array_wr32(E1000_UTA, i, ~0);
6258 }
6259 
6260 /**
6261  *  igb_intr_msi - Interrupt Handler
6262  *  @irq: interrupt number
6263  *  @data: pointer to a network interface device structure
6264  **/
igb_intr_msi(int irq,void * data)6265 static irqreturn_t igb_intr_msi(int irq, void *data)
6266 {
6267 	struct igb_adapter *adapter = data;
6268 	struct igb_q_vector *q_vector = adapter->q_vector[0];
6269 	struct e1000_hw *hw = &adapter->hw;
6270 	/* read ICR disables interrupts using IAM */
6271 	u32 icr = rd32(E1000_ICR);
6272 
6273 	igb_write_itr(q_vector);
6274 
6275 	if (icr & E1000_ICR_DRSTA)
6276 		schedule_work(&adapter->reset_task);
6277 
6278 	if (icr & E1000_ICR_DOUTSYNC) {
6279 		/* HW is reporting DMA is out of sync */
6280 		adapter->stats.doosync++;
6281 	}
6282 
6283 	if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6284 		hw->mac.get_link_status = 1;
6285 		if (!test_bit(__IGB_DOWN, &adapter->state))
6286 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
6287 	}
6288 
6289 	if (icr & E1000_ICR_TS)
6290 		igb_tsync_interrupt(adapter);
6291 
6292 	napi_schedule(&q_vector->napi);
6293 
6294 	return IRQ_HANDLED;
6295 }
6296 
6297 /**
6298  *  igb_intr - Legacy Interrupt Handler
6299  *  @irq: interrupt number
6300  *  @data: pointer to a network interface device structure
6301  **/
igb_intr(int irq,void * data)6302 static irqreturn_t igb_intr(int irq, void *data)
6303 {
6304 	struct igb_adapter *adapter = data;
6305 	struct igb_q_vector *q_vector = adapter->q_vector[0];
6306 	struct e1000_hw *hw = &adapter->hw;
6307 	/* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
6308 	 * need for the IMC write
6309 	 */
6310 	u32 icr = rd32(E1000_ICR);
6311 
6312 	/* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6313 	 * not set, then the adapter didn't send an interrupt
6314 	 */
6315 	if (!(icr & E1000_ICR_INT_ASSERTED))
6316 		return IRQ_NONE;
6317 
6318 	igb_write_itr(q_vector);
6319 
6320 	if (icr & E1000_ICR_DRSTA)
6321 		schedule_work(&adapter->reset_task);
6322 
6323 	if (icr & E1000_ICR_DOUTSYNC) {
6324 		/* HW is reporting DMA is out of sync */
6325 		adapter->stats.doosync++;
6326 	}
6327 
6328 	if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6329 		hw->mac.get_link_status = 1;
6330 		/* guard against interrupt when we're going down */
6331 		if (!test_bit(__IGB_DOWN, &adapter->state))
6332 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
6333 	}
6334 
6335 	if (icr & E1000_ICR_TS)
6336 		igb_tsync_interrupt(adapter);
6337 
6338 	napi_schedule(&q_vector->napi);
6339 
6340 	return IRQ_HANDLED;
6341 }
6342 
igb_ring_irq_enable(struct igb_q_vector * q_vector)6343 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
6344 {
6345 	struct igb_adapter *adapter = q_vector->adapter;
6346 	struct e1000_hw *hw = &adapter->hw;
6347 
6348 	if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6349 	    (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6350 		if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6351 			igb_set_itr(q_vector);
6352 		else
6353 			igb_update_ring_itr(q_vector);
6354 	}
6355 
6356 	if (!test_bit(__IGB_DOWN, &adapter->state)) {
6357 		if (adapter->flags & IGB_FLAG_HAS_MSIX)
6358 			wr32(E1000_EIMS, q_vector->eims_value);
6359 		else
6360 			igb_irq_enable(adapter);
6361 	}
6362 }
6363 
6364 /**
6365  *  igb_poll - NAPI Rx polling callback
6366  *  @napi: napi polling structure
6367  *  @budget: count of how many packets we should handle
6368  **/
igb_poll(struct napi_struct * napi,int budget)6369 static int igb_poll(struct napi_struct *napi, int budget)
6370 {
6371 	struct igb_q_vector *q_vector = container_of(napi,
6372 						     struct igb_q_vector,
6373 						     napi);
6374 	bool clean_complete = true;
6375 
6376 #ifdef CONFIG_IGB_DCA
6377 	if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6378 		igb_update_dca(q_vector);
6379 #endif
6380 	if (q_vector->tx.ring)
6381 		clean_complete = igb_clean_tx_irq(q_vector);
6382 
6383 	if (q_vector->rx.ring)
6384 		clean_complete &= igb_clean_rx_irq(q_vector, budget);
6385 
6386 	/* If all work not completed, return budget and keep polling */
6387 	if (!clean_complete)
6388 		return budget;
6389 
6390 	/* If not enough Rx work done, exit the polling mode */
6391 	napi_complete(napi);
6392 	igb_ring_irq_enable(q_vector);
6393 
6394 	return 0;
6395 }
6396 
6397 /**
6398  *  igb_clean_tx_irq - Reclaim resources after transmit completes
6399  *  @q_vector: pointer to q_vector containing needed info
6400  *
6401  *  returns true if ring is completely cleaned
6402  **/
igb_clean_tx_irq(struct igb_q_vector * q_vector)6403 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6404 {
6405 	struct igb_adapter *adapter = q_vector->adapter;
6406 	struct igb_ring *tx_ring = q_vector->tx.ring;
6407 	struct igb_tx_buffer *tx_buffer;
6408 	union e1000_adv_tx_desc *tx_desc;
6409 	unsigned int total_bytes = 0, total_packets = 0;
6410 	unsigned int budget = q_vector->tx.work_limit;
6411 	unsigned int i = tx_ring->next_to_clean;
6412 
6413 	if (test_bit(__IGB_DOWN, &adapter->state))
6414 		return true;
6415 
6416 	tx_buffer = &tx_ring->tx_buffer_info[i];
6417 	tx_desc = IGB_TX_DESC(tx_ring, i);
6418 	i -= tx_ring->count;
6419 
6420 	do {
6421 		union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6422 
6423 		/* if next_to_watch is not set then there is no work pending */
6424 		if (!eop_desc)
6425 			break;
6426 
6427 		/* prevent any other reads prior to eop_desc */
6428 		read_barrier_depends();
6429 
6430 		/* if DD is not set pending work has not been completed */
6431 		if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6432 			break;
6433 
6434 		/* clear next_to_watch to prevent false hangs */
6435 		tx_buffer->next_to_watch = NULL;
6436 
6437 		/* update the statistics for this packet */
6438 		total_bytes += tx_buffer->bytecount;
6439 		total_packets += tx_buffer->gso_segs;
6440 
6441 		/* free the skb */
6442 		dev_consume_skb_any(tx_buffer->skb);
6443 
6444 		/* unmap skb header data */
6445 		dma_unmap_single(tx_ring->dev,
6446 				 dma_unmap_addr(tx_buffer, dma),
6447 				 dma_unmap_len(tx_buffer, len),
6448 				 DMA_TO_DEVICE);
6449 
6450 		/* clear tx_buffer data */
6451 		tx_buffer->skb = NULL;
6452 		dma_unmap_len_set(tx_buffer, len, 0);
6453 
6454 		/* clear last DMA location and unmap remaining buffers */
6455 		while (tx_desc != eop_desc) {
6456 			tx_buffer++;
6457 			tx_desc++;
6458 			i++;
6459 			if (unlikely(!i)) {
6460 				i -= tx_ring->count;
6461 				tx_buffer = tx_ring->tx_buffer_info;
6462 				tx_desc = IGB_TX_DESC(tx_ring, 0);
6463 			}
6464 
6465 			/* unmap any remaining paged data */
6466 			if (dma_unmap_len(tx_buffer, len)) {
6467 				dma_unmap_page(tx_ring->dev,
6468 					       dma_unmap_addr(tx_buffer, dma),
6469 					       dma_unmap_len(tx_buffer, len),
6470 					       DMA_TO_DEVICE);
6471 				dma_unmap_len_set(tx_buffer, len, 0);
6472 			}
6473 		}
6474 
6475 		/* move us one more past the eop_desc for start of next pkt */
6476 		tx_buffer++;
6477 		tx_desc++;
6478 		i++;
6479 		if (unlikely(!i)) {
6480 			i -= tx_ring->count;
6481 			tx_buffer = tx_ring->tx_buffer_info;
6482 			tx_desc = IGB_TX_DESC(tx_ring, 0);
6483 		}
6484 
6485 		/* issue prefetch for next Tx descriptor */
6486 		prefetch(tx_desc);
6487 
6488 		/* update budget accounting */
6489 		budget--;
6490 	} while (likely(budget));
6491 
6492 	netdev_tx_completed_queue(txring_txq(tx_ring),
6493 				  total_packets, total_bytes);
6494 	i += tx_ring->count;
6495 	tx_ring->next_to_clean = i;
6496 	u64_stats_update_begin(&tx_ring->tx_syncp);
6497 	tx_ring->tx_stats.bytes += total_bytes;
6498 	tx_ring->tx_stats.packets += total_packets;
6499 	u64_stats_update_end(&tx_ring->tx_syncp);
6500 	q_vector->tx.total_bytes += total_bytes;
6501 	q_vector->tx.total_packets += total_packets;
6502 
6503 	if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6504 		struct e1000_hw *hw = &adapter->hw;
6505 
6506 		/* Detect a transmit hang in hardware, this serializes the
6507 		 * check with the clearing of time_stamp and movement of i
6508 		 */
6509 		clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6510 		if (tx_buffer->next_to_watch &&
6511 		    time_after(jiffies, tx_buffer->time_stamp +
6512 			       (adapter->tx_timeout_factor * HZ)) &&
6513 		    !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6514 
6515 			/* detected Tx unit hang */
6516 			dev_err(tx_ring->dev,
6517 				"Detected Tx Unit Hang\n"
6518 				"  Tx Queue             <%d>\n"
6519 				"  TDH                  <%x>\n"
6520 				"  TDT                  <%x>\n"
6521 				"  next_to_use          <%x>\n"
6522 				"  next_to_clean        <%x>\n"
6523 				"buffer_info[next_to_clean]\n"
6524 				"  time_stamp           <%lx>\n"
6525 				"  next_to_watch        <%p>\n"
6526 				"  jiffies              <%lx>\n"
6527 				"  desc.status          <%x>\n",
6528 				tx_ring->queue_index,
6529 				rd32(E1000_TDH(tx_ring->reg_idx)),
6530 				readl(tx_ring->tail),
6531 				tx_ring->next_to_use,
6532 				tx_ring->next_to_clean,
6533 				tx_buffer->time_stamp,
6534 				tx_buffer->next_to_watch,
6535 				jiffies,
6536 				tx_buffer->next_to_watch->wb.status);
6537 			netif_stop_subqueue(tx_ring->netdev,
6538 					    tx_ring->queue_index);
6539 
6540 			/* we are about to reset, no point in enabling stuff */
6541 			return true;
6542 		}
6543 	}
6544 
6545 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6546 	if (unlikely(total_packets &&
6547 	    netif_carrier_ok(tx_ring->netdev) &&
6548 	    igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6549 		/* Make sure that anybody stopping the queue after this
6550 		 * sees the new next_to_clean.
6551 		 */
6552 		smp_mb();
6553 		if (__netif_subqueue_stopped(tx_ring->netdev,
6554 					     tx_ring->queue_index) &&
6555 		    !(test_bit(__IGB_DOWN, &adapter->state))) {
6556 			netif_wake_subqueue(tx_ring->netdev,
6557 					    tx_ring->queue_index);
6558 
6559 			u64_stats_update_begin(&tx_ring->tx_syncp);
6560 			tx_ring->tx_stats.restart_queue++;
6561 			u64_stats_update_end(&tx_ring->tx_syncp);
6562 		}
6563 	}
6564 
6565 	return !!budget;
6566 }
6567 
6568 /**
6569  *  igb_reuse_rx_page - page flip buffer and store it back on the ring
6570  *  @rx_ring: rx descriptor ring to store buffers on
6571  *  @old_buff: donor buffer to have page reused
6572  *
6573  *  Synchronizes page for reuse by the adapter
6574  **/
igb_reuse_rx_page(struct igb_ring * rx_ring,struct igb_rx_buffer * old_buff)6575 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6576 			      struct igb_rx_buffer *old_buff)
6577 {
6578 	struct igb_rx_buffer *new_buff;
6579 	u16 nta = rx_ring->next_to_alloc;
6580 
6581 	new_buff = &rx_ring->rx_buffer_info[nta];
6582 
6583 	/* update, and store next to alloc */
6584 	nta++;
6585 	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6586 
6587 	/* transfer page from old buffer to new buffer */
6588 	*new_buff = *old_buff;
6589 
6590 	/* sync the buffer for use by the device */
6591 	dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6592 					 old_buff->page_offset,
6593 					 IGB_RX_BUFSZ,
6594 					 DMA_FROM_DEVICE);
6595 }
6596 
igb_page_is_reserved(struct page * page)6597 static inline bool igb_page_is_reserved(struct page *page)
6598 {
6599 	return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
6600 }
6601 
igb_can_reuse_rx_page(struct igb_rx_buffer * rx_buffer,struct page * page,unsigned int truesize)6602 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6603 				  struct page *page,
6604 				  unsigned int truesize)
6605 {
6606 	/* avoid re-using remote pages */
6607 	if (unlikely(igb_page_is_reserved(page)))
6608 		return false;
6609 
6610 #if (PAGE_SIZE < 8192)
6611 	/* if we are only owner of page we can reuse it */
6612 	if (unlikely(page_count(page) != 1))
6613 		return false;
6614 
6615 	/* flip page offset to other buffer */
6616 	rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6617 #else
6618 	/* move offset up to the next cache line */
6619 	rx_buffer->page_offset += truesize;
6620 
6621 	if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6622 		return false;
6623 #endif
6624 
6625 	/* Even if we own the page, we are not allowed to use atomic_set()
6626 	 * This would break get_page_unless_zero() users.
6627 	 */
6628 	atomic_inc(&page->_count);
6629 
6630 	return true;
6631 }
6632 
6633 /**
6634  *  igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6635  *  @rx_ring: rx descriptor ring to transact packets on
6636  *  @rx_buffer: buffer containing page to add
6637  *  @rx_desc: descriptor containing length of buffer written by hardware
6638  *  @skb: sk_buff to place the data into
6639  *
6640  *  This function will add the data contained in rx_buffer->page to the skb.
6641  *  This is done either through a direct copy if the data in the buffer is
6642  *  less than the skb header size, otherwise it will just attach the page as
6643  *  a frag to the skb.
6644  *
6645  *  The function will then update the page offset if necessary and return
6646  *  true if the buffer can be reused by the adapter.
6647  **/
igb_add_rx_frag(struct igb_ring * rx_ring,struct igb_rx_buffer * rx_buffer,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)6648 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6649 			    struct igb_rx_buffer *rx_buffer,
6650 			    union e1000_adv_rx_desc *rx_desc,
6651 			    struct sk_buff *skb)
6652 {
6653 	struct page *page = rx_buffer->page;
6654 	unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6655 #if (PAGE_SIZE < 8192)
6656 	unsigned int truesize = IGB_RX_BUFSZ;
6657 #else
6658 	unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6659 #endif
6660 
6661 	if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6662 		unsigned char *va = page_address(page) + rx_buffer->page_offset;
6663 
6664 		if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6665 			igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6666 			va += IGB_TS_HDR_LEN;
6667 			size -= IGB_TS_HDR_LEN;
6668 		}
6669 
6670 		memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6671 
6672 		/* page is not reserved, we can reuse buffer as-is */
6673 		if (likely(!igb_page_is_reserved(page)))
6674 			return true;
6675 
6676 		/* this page cannot be reused so discard it */
6677 		__free_page(page);
6678 		return false;
6679 	}
6680 
6681 	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6682 			rx_buffer->page_offset, size, truesize);
6683 
6684 	return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6685 }
6686 
igb_fetch_rx_buffer(struct igb_ring * rx_ring,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)6687 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6688 					   union e1000_adv_rx_desc *rx_desc,
6689 					   struct sk_buff *skb)
6690 {
6691 	struct igb_rx_buffer *rx_buffer;
6692 	struct page *page;
6693 
6694 	rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6695 	page = rx_buffer->page;
6696 	prefetchw(page);
6697 
6698 	if (likely(!skb)) {
6699 		void *page_addr = page_address(page) +
6700 				  rx_buffer->page_offset;
6701 
6702 		/* prefetch first cache line of first page */
6703 		prefetch(page_addr);
6704 #if L1_CACHE_BYTES < 128
6705 		prefetch(page_addr + L1_CACHE_BYTES);
6706 #endif
6707 
6708 		/* allocate a skb to store the frags */
6709 		skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
6710 		if (unlikely(!skb)) {
6711 			rx_ring->rx_stats.alloc_failed++;
6712 			return NULL;
6713 		}
6714 
6715 		/* we will be copying header into skb->data in
6716 		 * pskb_may_pull so it is in our interest to prefetch
6717 		 * it now to avoid a possible cache miss
6718 		 */
6719 		prefetchw(skb->data);
6720 	}
6721 
6722 	/* we are reusing so sync this buffer for CPU use */
6723 	dma_sync_single_range_for_cpu(rx_ring->dev,
6724 				      rx_buffer->dma,
6725 				      rx_buffer->page_offset,
6726 				      IGB_RX_BUFSZ,
6727 				      DMA_FROM_DEVICE);
6728 
6729 	/* pull page into skb */
6730 	if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6731 		/* hand second half of page back to the ring */
6732 		igb_reuse_rx_page(rx_ring, rx_buffer);
6733 	} else {
6734 		/* we are not reusing the buffer so unmap it */
6735 		dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6736 			       PAGE_SIZE, DMA_FROM_DEVICE);
6737 	}
6738 
6739 	/* clear contents of rx_buffer */
6740 	rx_buffer->page = NULL;
6741 
6742 	return skb;
6743 }
6744 
igb_rx_checksum(struct igb_ring * ring,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)6745 static inline void igb_rx_checksum(struct igb_ring *ring,
6746 				   union e1000_adv_rx_desc *rx_desc,
6747 				   struct sk_buff *skb)
6748 {
6749 	skb_checksum_none_assert(skb);
6750 
6751 	/* Ignore Checksum bit is set */
6752 	if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6753 		return;
6754 
6755 	/* Rx checksum disabled via ethtool */
6756 	if (!(ring->netdev->features & NETIF_F_RXCSUM))
6757 		return;
6758 
6759 	/* TCP/UDP checksum error bit is set */
6760 	if (igb_test_staterr(rx_desc,
6761 			     E1000_RXDEXT_STATERR_TCPE |
6762 			     E1000_RXDEXT_STATERR_IPE)) {
6763 		/* work around errata with sctp packets where the TCPE aka
6764 		 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6765 		 * packets, (aka let the stack check the crc32c)
6766 		 */
6767 		if (!((skb->len == 60) &&
6768 		      test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6769 			u64_stats_update_begin(&ring->rx_syncp);
6770 			ring->rx_stats.csum_err++;
6771 			u64_stats_update_end(&ring->rx_syncp);
6772 		}
6773 		/* let the stack verify checksum errors */
6774 		return;
6775 	}
6776 	/* It must be a TCP or UDP packet with a valid checksum */
6777 	if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6778 				      E1000_RXD_STAT_UDPCS))
6779 		skb->ip_summed = CHECKSUM_UNNECESSARY;
6780 
6781 	dev_dbg(ring->dev, "cksum success: bits %08X\n",
6782 		le32_to_cpu(rx_desc->wb.upper.status_error));
6783 }
6784 
igb_rx_hash(struct igb_ring * ring,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)6785 static inline void igb_rx_hash(struct igb_ring *ring,
6786 			       union e1000_adv_rx_desc *rx_desc,
6787 			       struct sk_buff *skb)
6788 {
6789 	if (ring->netdev->features & NETIF_F_RXHASH)
6790 		skb_set_hash(skb,
6791 			     le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6792 			     PKT_HASH_TYPE_L3);
6793 }
6794 
6795 /**
6796  *  igb_is_non_eop - process handling of non-EOP buffers
6797  *  @rx_ring: Rx ring being processed
6798  *  @rx_desc: Rx descriptor for current buffer
6799  *  @skb: current socket buffer containing buffer in progress
6800  *
6801  *  This function updates next to clean.  If the buffer is an EOP buffer
6802  *  this function exits returning false, otherwise it will place the
6803  *  sk_buff in the next buffer to be chained and return true indicating
6804  *  that this is in fact a non-EOP buffer.
6805  **/
igb_is_non_eop(struct igb_ring * rx_ring,union e1000_adv_rx_desc * rx_desc)6806 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6807 			   union e1000_adv_rx_desc *rx_desc)
6808 {
6809 	u32 ntc = rx_ring->next_to_clean + 1;
6810 
6811 	/* fetch, update, and store next to clean */
6812 	ntc = (ntc < rx_ring->count) ? ntc : 0;
6813 	rx_ring->next_to_clean = ntc;
6814 
6815 	prefetch(IGB_RX_DESC(rx_ring, ntc));
6816 
6817 	if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6818 		return false;
6819 
6820 	return true;
6821 }
6822 
6823 /**
6824  *  igb_pull_tail - igb specific version of skb_pull_tail
6825  *  @rx_ring: rx descriptor ring packet is being transacted on
6826  *  @rx_desc: pointer to the EOP Rx descriptor
6827  *  @skb: pointer to current skb being adjusted
6828  *
6829  *  This function is an igb specific version of __pskb_pull_tail.  The
6830  *  main difference between this version and the original function is that
6831  *  this function can make several assumptions about the state of things
6832  *  that allow for significant optimizations versus the standard function.
6833  *  As a result we can do things like drop a frag and maintain an accurate
6834  *  truesize for the skb.
6835  */
igb_pull_tail(struct igb_ring * rx_ring,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)6836 static void igb_pull_tail(struct igb_ring *rx_ring,
6837 			  union e1000_adv_rx_desc *rx_desc,
6838 			  struct sk_buff *skb)
6839 {
6840 	struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6841 	unsigned char *va;
6842 	unsigned int pull_len;
6843 
6844 	/* it is valid to use page_address instead of kmap since we are
6845 	 * working with pages allocated out of the lomem pool per
6846 	 * alloc_page(GFP_ATOMIC)
6847 	 */
6848 	va = skb_frag_address(frag);
6849 
6850 	if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6851 		/* retrieve timestamp from buffer */
6852 		igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6853 
6854 		/* update pointers to remove timestamp header */
6855 		skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6856 		frag->page_offset += IGB_TS_HDR_LEN;
6857 		skb->data_len -= IGB_TS_HDR_LEN;
6858 		skb->len -= IGB_TS_HDR_LEN;
6859 
6860 		/* move va to start of packet data */
6861 		va += IGB_TS_HDR_LEN;
6862 	}
6863 
6864 	/* we need the header to contain the greater of either ETH_HLEN or
6865 	 * 60 bytes if the skb->len is less than 60 for skb_pad.
6866 	 */
6867 	pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6868 
6869 	/* align pull length to size of long to optimize memcpy performance */
6870 	skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6871 
6872 	/* update all of the pointers */
6873 	skb_frag_size_sub(frag, pull_len);
6874 	frag->page_offset += pull_len;
6875 	skb->data_len -= pull_len;
6876 	skb->tail += pull_len;
6877 }
6878 
6879 /**
6880  *  igb_cleanup_headers - Correct corrupted or empty headers
6881  *  @rx_ring: rx descriptor ring packet is being transacted on
6882  *  @rx_desc: pointer to the EOP Rx descriptor
6883  *  @skb: pointer to current skb being fixed
6884  *
6885  *  Address the case where we are pulling data in on pages only
6886  *  and as such no data is present in the skb header.
6887  *
6888  *  In addition if skb is not at least 60 bytes we need to pad it so that
6889  *  it is large enough to qualify as a valid Ethernet frame.
6890  *
6891  *  Returns true if an error was encountered and skb was freed.
6892  **/
igb_cleanup_headers(struct igb_ring * rx_ring,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)6893 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6894 				union e1000_adv_rx_desc *rx_desc,
6895 				struct sk_buff *skb)
6896 {
6897 	if (unlikely((igb_test_staterr(rx_desc,
6898 				       E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6899 		struct net_device *netdev = rx_ring->netdev;
6900 		if (!(netdev->features & NETIF_F_RXALL)) {
6901 			dev_kfree_skb_any(skb);
6902 			return true;
6903 		}
6904 	}
6905 
6906 	/* place header in linear portion of buffer */
6907 	if (skb_is_nonlinear(skb))
6908 		igb_pull_tail(rx_ring, rx_desc, skb);
6909 
6910 	/* if eth_skb_pad returns an error the skb was freed */
6911 	if (eth_skb_pad(skb))
6912 		return true;
6913 
6914 	return false;
6915 }
6916 
6917 /**
6918  *  igb_process_skb_fields - Populate skb header fields from Rx descriptor
6919  *  @rx_ring: rx descriptor ring packet is being transacted on
6920  *  @rx_desc: pointer to the EOP Rx descriptor
6921  *  @skb: pointer to current skb being populated
6922  *
6923  *  This function checks the ring, descriptor, and packet information in
6924  *  order to populate the hash, checksum, VLAN, timestamp, protocol, and
6925  *  other fields within the skb.
6926  **/
igb_process_skb_fields(struct igb_ring * rx_ring,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)6927 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6928 				   union e1000_adv_rx_desc *rx_desc,
6929 				   struct sk_buff *skb)
6930 {
6931 	struct net_device *dev = rx_ring->netdev;
6932 
6933 	igb_rx_hash(rx_ring, rx_desc, skb);
6934 
6935 	igb_rx_checksum(rx_ring, rx_desc, skb);
6936 
6937 	if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6938 	    !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6939 		igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
6940 
6941 	if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6942 	    igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6943 		u16 vid;
6944 
6945 		if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6946 		    test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6947 			vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6948 		else
6949 			vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6950 
6951 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6952 	}
6953 
6954 	skb_record_rx_queue(skb, rx_ring->queue_index);
6955 
6956 	skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6957 }
6958 
igb_clean_rx_irq(struct igb_q_vector * q_vector,const int budget)6959 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6960 {
6961 	struct igb_ring *rx_ring = q_vector->rx.ring;
6962 	struct sk_buff *skb = rx_ring->skb;
6963 	unsigned int total_bytes = 0, total_packets = 0;
6964 	u16 cleaned_count = igb_desc_unused(rx_ring);
6965 
6966 	while (likely(total_packets < budget)) {
6967 		union e1000_adv_rx_desc *rx_desc;
6968 
6969 		/* return some buffers to hardware, one at a time is too slow */
6970 		if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6971 			igb_alloc_rx_buffers(rx_ring, cleaned_count);
6972 			cleaned_count = 0;
6973 		}
6974 
6975 		rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6976 
6977 		if (!rx_desc->wb.upper.status_error)
6978 			break;
6979 
6980 		/* This memory barrier is needed to keep us from reading
6981 		 * any other fields out of the rx_desc until we know the
6982 		 * descriptor has been written back
6983 		 */
6984 		dma_rmb();
6985 
6986 		/* retrieve a buffer from the ring */
6987 		skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6988 
6989 		/* exit if we failed to retrieve a buffer */
6990 		if (!skb)
6991 			break;
6992 
6993 		cleaned_count++;
6994 
6995 		/* fetch next buffer in frame if non-eop */
6996 		if (igb_is_non_eop(rx_ring, rx_desc))
6997 			continue;
6998 
6999 		/* verify the packet layout is correct */
7000 		if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7001 			skb = NULL;
7002 			continue;
7003 		}
7004 
7005 		/* probably a little skewed due to removing CRC */
7006 		total_bytes += skb->len;
7007 
7008 		/* populate checksum, timestamp, VLAN, and protocol */
7009 		igb_process_skb_fields(rx_ring, rx_desc, skb);
7010 
7011 		napi_gro_receive(&q_vector->napi, skb);
7012 
7013 		/* reset skb pointer */
7014 		skb = NULL;
7015 
7016 		/* update budget accounting */
7017 		total_packets++;
7018 	}
7019 
7020 	/* place incomplete frames back on ring for completion */
7021 	rx_ring->skb = skb;
7022 
7023 	u64_stats_update_begin(&rx_ring->rx_syncp);
7024 	rx_ring->rx_stats.packets += total_packets;
7025 	rx_ring->rx_stats.bytes += total_bytes;
7026 	u64_stats_update_end(&rx_ring->rx_syncp);
7027 	q_vector->rx.total_packets += total_packets;
7028 	q_vector->rx.total_bytes += total_bytes;
7029 
7030 	if (cleaned_count)
7031 		igb_alloc_rx_buffers(rx_ring, cleaned_count);
7032 
7033 	return total_packets < budget;
7034 }
7035 
igb_alloc_mapped_page(struct igb_ring * rx_ring,struct igb_rx_buffer * bi)7036 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
7037 				  struct igb_rx_buffer *bi)
7038 {
7039 	struct page *page = bi->page;
7040 	dma_addr_t dma;
7041 
7042 	/* since we are recycling buffers we should seldom need to alloc */
7043 	if (likely(page))
7044 		return true;
7045 
7046 	/* alloc new page for storage */
7047 	page = dev_alloc_page();
7048 	if (unlikely(!page)) {
7049 		rx_ring->rx_stats.alloc_failed++;
7050 		return false;
7051 	}
7052 
7053 	/* map page for use */
7054 	dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
7055 
7056 	/* if mapping failed free memory back to system since
7057 	 * there isn't much point in holding memory we can't use
7058 	 */
7059 	if (dma_mapping_error(rx_ring->dev, dma)) {
7060 		__free_page(page);
7061 
7062 		rx_ring->rx_stats.alloc_failed++;
7063 		return false;
7064 	}
7065 
7066 	bi->dma = dma;
7067 	bi->page = page;
7068 	bi->page_offset = 0;
7069 
7070 	return true;
7071 }
7072 
7073 /**
7074  *  igb_alloc_rx_buffers - Replace used receive buffers; packet split
7075  *  @adapter: address of board private structure
7076  **/
igb_alloc_rx_buffers(struct igb_ring * rx_ring,u16 cleaned_count)7077 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
7078 {
7079 	union e1000_adv_rx_desc *rx_desc;
7080 	struct igb_rx_buffer *bi;
7081 	u16 i = rx_ring->next_to_use;
7082 
7083 	/* nothing to do */
7084 	if (!cleaned_count)
7085 		return;
7086 
7087 	rx_desc = IGB_RX_DESC(rx_ring, i);
7088 	bi = &rx_ring->rx_buffer_info[i];
7089 	i -= rx_ring->count;
7090 
7091 	do {
7092 		if (!igb_alloc_mapped_page(rx_ring, bi))
7093 			break;
7094 
7095 		/* Refresh the desc even if buffer_addrs didn't change
7096 		 * because each write-back erases this info.
7097 		 */
7098 		rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
7099 
7100 		rx_desc++;
7101 		bi++;
7102 		i++;
7103 		if (unlikely(!i)) {
7104 			rx_desc = IGB_RX_DESC(rx_ring, 0);
7105 			bi = rx_ring->rx_buffer_info;
7106 			i -= rx_ring->count;
7107 		}
7108 
7109 		/* clear the status bits for the next_to_use descriptor */
7110 		rx_desc->wb.upper.status_error = 0;
7111 
7112 		cleaned_count--;
7113 	} while (cleaned_count);
7114 
7115 	i += rx_ring->count;
7116 
7117 	if (rx_ring->next_to_use != i) {
7118 		/* record the next descriptor to use */
7119 		rx_ring->next_to_use = i;
7120 
7121 		/* update next to alloc since we have filled the ring */
7122 		rx_ring->next_to_alloc = i;
7123 
7124 		/* Force memory writes to complete before letting h/w
7125 		 * know there are new descriptors to fetch.  (Only
7126 		 * applicable for weak-ordered memory model archs,
7127 		 * such as IA-64).
7128 		 */
7129 		wmb();
7130 		writel(i, rx_ring->tail);
7131 	}
7132 }
7133 
7134 /**
7135  * igb_mii_ioctl -
7136  * @netdev:
7137  * @ifreq:
7138  * @cmd:
7139  **/
igb_mii_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)7140 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7141 {
7142 	struct igb_adapter *adapter = netdev_priv(netdev);
7143 	struct mii_ioctl_data *data = if_mii(ifr);
7144 
7145 	if (adapter->hw.phy.media_type != e1000_media_type_copper)
7146 		return -EOPNOTSUPP;
7147 
7148 	switch (cmd) {
7149 	case SIOCGMIIPHY:
7150 		data->phy_id = adapter->hw.phy.addr;
7151 		break;
7152 	case SIOCGMIIREG:
7153 		if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7154 				     &data->val_out))
7155 			return -EIO;
7156 		break;
7157 	case SIOCSMIIREG:
7158 	default:
7159 		return -EOPNOTSUPP;
7160 	}
7161 	return 0;
7162 }
7163 
7164 /**
7165  * igb_ioctl -
7166  * @netdev:
7167  * @ifreq:
7168  * @cmd:
7169  **/
igb_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)7170 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7171 {
7172 	switch (cmd) {
7173 	case SIOCGMIIPHY:
7174 	case SIOCGMIIREG:
7175 	case SIOCSMIIREG:
7176 		return igb_mii_ioctl(netdev, ifr, cmd);
7177 	case SIOCGHWTSTAMP:
7178 		return igb_ptp_get_ts_config(netdev, ifr);
7179 	case SIOCSHWTSTAMP:
7180 		return igb_ptp_set_ts_config(netdev, ifr);
7181 	default:
7182 		return -EOPNOTSUPP;
7183 	}
7184 }
7185 
igb_read_pci_cfg(struct e1000_hw * hw,u32 reg,u16 * value)7186 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7187 {
7188 	struct igb_adapter *adapter = hw->back;
7189 
7190 	pci_read_config_word(adapter->pdev, reg, value);
7191 }
7192 
igb_write_pci_cfg(struct e1000_hw * hw,u32 reg,u16 * value)7193 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7194 {
7195 	struct igb_adapter *adapter = hw->back;
7196 
7197 	pci_write_config_word(adapter->pdev, reg, *value);
7198 }
7199 
igb_read_pcie_cap_reg(struct e1000_hw * hw,u32 reg,u16 * value)7200 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7201 {
7202 	struct igb_adapter *adapter = hw->back;
7203 
7204 	if (pcie_capability_read_word(adapter->pdev, reg, value))
7205 		return -E1000_ERR_CONFIG;
7206 
7207 	return 0;
7208 }
7209 
igb_write_pcie_cap_reg(struct e1000_hw * hw,u32 reg,u16 * value)7210 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7211 {
7212 	struct igb_adapter *adapter = hw->back;
7213 
7214 	if (pcie_capability_write_word(adapter->pdev, reg, *value))
7215 		return -E1000_ERR_CONFIG;
7216 
7217 	return 0;
7218 }
7219 
igb_vlan_mode(struct net_device * netdev,netdev_features_t features)7220 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
7221 {
7222 	struct igb_adapter *adapter = netdev_priv(netdev);
7223 	struct e1000_hw *hw = &adapter->hw;
7224 	u32 ctrl, rctl;
7225 	bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
7226 
7227 	if (enable) {
7228 		/* enable VLAN tag insert/strip */
7229 		ctrl = rd32(E1000_CTRL);
7230 		ctrl |= E1000_CTRL_VME;
7231 		wr32(E1000_CTRL, ctrl);
7232 
7233 		/* Disable CFI check */
7234 		rctl = rd32(E1000_RCTL);
7235 		rctl &= ~E1000_RCTL_CFIEN;
7236 		wr32(E1000_RCTL, rctl);
7237 	} else {
7238 		/* disable VLAN tag insert/strip */
7239 		ctrl = rd32(E1000_CTRL);
7240 		ctrl &= ~E1000_CTRL_VME;
7241 		wr32(E1000_CTRL, ctrl);
7242 	}
7243 
7244 	igb_rlpml_set(adapter);
7245 }
7246 
igb_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)7247 static int igb_vlan_rx_add_vid(struct net_device *netdev,
7248 			       __be16 proto, u16 vid)
7249 {
7250 	struct igb_adapter *adapter = netdev_priv(netdev);
7251 	struct e1000_hw *hw = &adapter->hw;
7252 	int pf_id = adapter->vfs_allocated_count;
7253 
7254 	/* attempt to add filter to vlvf array */
7255 	igb_vlvf_set(adapter, vid, true, pf_id);
7256 
7257 	/* add the filter since PF can receive vlans w/o entry in vlvf */
7258 	igb_vfta_set(hw, vid, true);
7259 
7260 	set_bit(vid, adapter->active_vlans);
7261 
7262 	return 0;
7263 }
7264 
igb_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)7265 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7266 				__be16 proto, u16 vid)
7267 {
7268 	struct igb_adapter *adapter = netdev_priv(netdev);
7269 	struct e1000_hw *hw = &adapter->hw;
7270 	int pf_id = adapter->vfs_allocated_count;
7271 	s32 err;
7272 
7273 	/* remove vlan from VLVF table array */
7274 	err = igb_vlvf_set(adapter, vid, false, pf_id);
7275 
7276 	/* if vid was not present in VLVF just remove it from table */
7277 	if (err)
7278 		igb_vfta_set(hw, vid, false);
7279 
7280 	clear_bit(vid, adapter->active_vlans);
7281 
7282 	return 0;
7283 }
7284 
igb_restore_vlan(struct igb_adapter * adapter)7285 static void igb_restore_vlan(struct igb_adapter *adapter)
7286 {
7287 	u16 vid;
7288 
7289 	igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7290 
7291 	for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7292 		igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7293 }
7294 
igb_set_spd_dplx(struct igb_adapter * adapter,u32 spd,u8 dplx)7295 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7296 {
7297 	struct pci_dev *pdev = adapter->pdev;
7298 	struct e1000_mac_info *mac = &adapter->hw.mac;
7299 
7300 	mac->autoneg = 0;
7301 
7302 	/* Make sure dplx is at most 1 bit and lsb of speed is not set
7303 	 * for the switch() below to work
7304 	 */
7305 	if ((spd & 1) || (dplx & ~1))
7306 		goto err_inval;
7307 
7308 	/* Fiber NIC's only allow 1000 gbps Full duplex
7309 	 * and 100Mbps Full duplex for 100baseFx sfp
7310 	 */
7311 	if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7312 		switch (spd + dplx) {
7313 		case SPEED_10 + DUPLEX_HALF:
7314 		case SPEED_10 + DUPLEX_FULL:
7315 		case SPEED_100 + DUPLEX_HALF:
7316 			goto err_inval;
7317 		default:
7318 			break;
7319 		}
7320 	}
7321 
7322 	switch (spd + dplx) {
7323 	case SPEED_10 + DUPLEX_HALF:
7324 		mac->forced_speed_duplex = ADVERTISE_10_HALF;
7325 		break;
7326 	case SPEED_10 + DUPLEX_FULL:
7327 		mac->forced_speed_duplex = ADVERTISE_10_FULL;
7328 		break;
7329 	case SPEED_100 + DUPLEX_HALF:
7330 		mac->forced_speed_duplex = ADVERTISE_100_HALF;
7331 		break;
7332 	case SPEED_100 + DUPLEX_FULL:
7333 		mac->forced_speed_duplex = ADVERTISE_100_FULL;
7334 		break;
7335 	case SPEED_1000 + DUPLEX_FULL:
7336 		mac->autoneg = 1;
7337 		adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7338 		break;
7339 	case SPEED_1000 + DUPLEX_HALF: /* not supported */
7340 	default:
7341 		goto err_inval;
7342 	}
7343 
7344 	/* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7345 	adapter->hw.phy.mdix = AUTO_ALL_MODES;
7346 
7347 	return 0;
7348 
7349 err_inval:
7350 	dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7351 	return -EINVAL;
7352 }
7353 
__igb_shutdown(struct pci_dev * pdev,bool * enable_wake,bool runtime)7354 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7355 			  bool runtime)
7356 {
7357 	struct net_device *netdev = pci_get_drvdata(pdev);
7358 	struct igb_adapter *adapter = netdev_priv(netdev);
7359 	struct e1000_hw *hw = &adapter->hw;
7360 	u32 ctrl, rctl, status;
7361 	u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7362 #ifdef CONFIG_PM
7363 	int retval = 0;
7364 #endif
7365 
7366 	netif_device_detach(netdev);
7367 
7368 	if (netif_running(netdev))
7369 		__igb_close(netdev, true);
7370 
7371 	igb_clear_interrupt_scheme(adapter);
7372 
7373 #ifdef CONFIG_PM
7374 	retval = pci_save_state(pdev);
7375 	if (retval)
7376 		return retval;
7377 #endif
7378 
7379 	status = rd32(E1000_STATUS);
7380 	if (status & E1000_STATUS_LU)
7381 		wufc &= ~E1000_WUFC_LNKC;
7382 
7383 	if (wufc) {
7384 		igb_setup_rctl(adapter);
7385 		igb_set_rx_mode(netdev);
7386 
7387 		/* turn on all-multi mode if wake on multicast is enabled */
7388 		if (wufc & E1000_WUFC_MC) {
7389 			rctl = rd32(E1000_RCTL);
7390 			rctl |= E1000_RCTL_MPE;
7391 			wr32(E1000_RCTL, rctl);
7392 		}
7393 
7394 		ctrl = rd32(E1000_CTRL);
7395 		/* advertise wake from D3Cold */
7396 		#define E1000_CTRL_ADVD3WUC 0x00100000
7397 		/* phy power management enable */
7398 		#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7399 		ctrl |= E1000_CTRL_ADVD3WUC;
7400 		wr32(E1000_CTRL, ctrl);
7401 
7402 		/* Allow time for pending master requests to run */
7403 		igb_disable_pcie_master(hw);
7404 
7405 		wr32(E1000_WUC, E1000_WUC_PME_EN);
7406 		wr32(E1000_WUFC, wufc);
7407 	} else {
7408 		wr32(E1000_WUC, 0);
7409 		wr32(E1000_WUFC, 0);
7410 	}
7411 
7412 	*enable_wake = wufc || adapter->en_mng_pt;
7413 	if (!*enable_wake)
7414 		igb_power_down_link(adapter);
7415 	else
7416 		igb_power_up_link(adapter);
7417 
7418 	/* Release control of h/w to f/w.  If f/w is AMT enabled, this
7419 	 * would have already happened in close and is redundant.
7420 	 */
7421 	igb_release_hw_control(adapter);
7422 
7423 	pci_disable_device(pdev);
7424 
7425 	return 0;
7426 }
7427 
7428 #ifdef CONFIG_PM
7429 #ifdef CONFIG_PM_SLEEP
igb_suspend(struct device * dev)7430 static int igb_suspend(struct device *dev)
7431 {
7432 	int retval;
7433 	bool wake;
7434 	struct pci_dev *pdev = to_pci_dev(dev);
7435 
7436 	retval = __igb_shutdown(pdev, &wake, 0);
7437 	if (retval)
7438 		return retval;
7439 
7440 	if (wake) {
7441 		pci_prepare_to_sleep(pdev);
7442 	} else {
7443 		pci_wake_from_d3(pdev, false);
7444 		pci_set_power_state(pdev, PCI_D3hot);
7445 	}
7446 
7447 	return 0;
7448 }
7449 #endif /* CONFIG_PM_SLEEP */
7450 
igb_resume(struct device * dev)7451 static int igb_resume(struct device *dev)
7452 {
7453 	struct pci_dev *pdev = to_pci_dev(dev);
7454 	struct net_device *netdev = pci_get_drvdata(pdev);
7455 	struct igb_adapter *adapter = netdev_priv(netdev);
7456 	struct e1000_hw *hw = &adapter->hw;
7457 	u32 err;
7458 
7459 	pci_set_power_state(pdev, PCI_D0);
7460 	pci_restore_state(pdev);
7461 	pci_save_state(pdev);
7462 
7463 	if (!pci_device_is_present(pdev))
7464 		return -ENODEV;
7465 	err = pci_enable_device_mem(pdev);
7466 	if (err) {
7467 		dev_err(&pdev->dev,
7468 			"igb: Cannot enable PCI device from suspend\n");
7469 		return err;
7470 	}
7471 	pci_set_master(pdev);
7472 
7473 	pci_enable_wake(pdev, PCI_D3hot, 0);
7474 	pci_enable_wake(pdev, PCI_D3cold, 0);
7475 
7476 	if (igb_init_interrupt_scheme(adapter, true)) {
7477 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7478 		return -ENOMEM;
7479 	}
7480 
7481 	igb_reset(adapter);
7482 
7483 	/* let the f/w know that the h/w is now under the control of the
7484 	 * driver.
7485 	 */
7486 	igb_get_hw_control(adapter);
7487 
7488 	wr32(E1000_WUS, ~0);
7489 
7490 	if (netdev->flags & IFF_UP) {
7491 		rtnl_lock();
7492 		err = __igb_open(netdev, true);
7493 		rtnl_unlock();
7494 		if (err)
7495 			return err;
7496 	}
7497 
7498 	netif_device_attach(netdev);
7499 	return 0;
7500 }
7501 
igb_runtime_idle(struct device * dev)7502 static int igb_runtime_idle(struct device *dev)
7503 {
7504 	struct pci_dev *pdev = to_pci_dev(dev);
7505 	struct net_device *netdev = pci_get_drvdata(pdev);
7506 	struct igb_adapter *adapter = netdev_priv(netdev);
7507 
7508 	if (!igb_has_link(adapter))
7509 		pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7510 
7511 	return -EBUSY;
7512 }
7513 
igb_runtime_suspend(struct device * dev)7514 static int igb_runtime_suspend(struct device *dev)
7515 {
7516 	struct pci_dev *pdev = to_pci_dev(dev);
7517 	int retval;
7518 	bool wake;
7519 
7520 	retval = __igb_shutdown(pdev, &wake, 1);
7521 	if (retval)
7522 		return retval;
7523 
7524 	if (wake) {
7525 		pci_prepare_to_sleep(pdev);
7526 	} else {
7527 		pci_wake_from_d3(pdev, false);
7528 		pci_set_power_state(pdev, PCI_D3hot);
7529 	}
7530 
7531 	return 0;
7532 }
7533 
igb_runtime_resume(struct device * dev)7534 static int igb_runtime_resume(struct device *dev)
7535 {
7536 	return igb_resume(dev);
7537 }
7538 #endif /* CONFIG_PM */
7539 
igb_shutdown(struct pci_dev * pdev)7540 static void igb_shutdown(struct pci_dev *pdev)
7541 {
7542 	bool wake;
7543 
7544 	__igb_shutdown(pdev, &wake, 0);
7545 
7546 	if (system_state == SYSTEM_POWER_OFF) {
7547 		pci_wake_from_d3(pdev, wake);
7548 		pci_set_power_state(pdev, PCI_D3hot);
7549 	}
7550 }
7551 
7552 #ifdef CONFIG_PCI_IOV
igb_sriov_reinit(struct pci_dev * dev)7553 static int igb_sriov_reinit(struct pci_dev *dev)
7554 {
7555 	struct net_device *netdev = pci_get_drvdata(dev);
7556 	struct igb_adapter *adapter = netdev_priv(netdev);
7557 	struct pci_dev *pdev = adapter->pdev;
7558 
7559 	rtnl_lock();
7560 
7561 	if (netif_running(netdev))
7562 		igb_close(netdev);
7563 	else
7564 		igb_reset(adapter);
7565 
7566 	igb_clear_interrupt_scheme(adapter);
7567 
7568 	igb_init_queue_configuration(adapter);
7569 
7570 	if (igb_init_interrupt_scheme(adapter, true)) {
7571 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7572 		return -ENOMEM;
7573 	}
7574 
7575 	if (netif_running(netdev))
7576 		igb_open(netdev);
7577 
7578 	rtnl_unlock();
7579 
7580 	return 0;
7581 }
7582 
igb_pci_disable_sriov(struct pci_dev * dev)7583 static int igb_pci_disable_sriov(struct pci_dev *dev)
7584 {
7585 	int err = igb_disable_sriov(dev);
7586 
7587 	if (!err)
7588 		err = igb_sriov_reinit(dev);
7589 
7590 	return err;
7591 }
7592 
igb_pci_enable_sriov(struct pci_dev * dev,int num_vfs)7593 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7594 {
7595 	int err = igb_enable_sriov(dev, num_vfs);
7596 
7597 	if (err)
7598 		goto out;
7599 
7600 	err = igb_sriov_reinit(dev);
7601 	if (!err)
7602 		return num_vfs;
7603 
7604 out:
7605 	return err;
7606 }
7607 
7608 #endif
igb_pci_sriov_configure(struct pci_dev * dev,int num_vfs)7609 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7610 {
7611 #ifdef CONFIG_PCI_IOV
7612 	if (num_vfs == 0)
7613 		return igb_pci_disable_sriov(dev);
7614 	else
7615 		return igb_pci_enable_sriov(dev, num_vfs);
7616 #endif
7617 	return 0;
7618 }
7619 
7620 #ifdef CONFIG_NET_POLL_CONTROLLER
7621 /* Polling 'interrupt' - used by things like netconsole to send skbs
7622  * without having to re-enable interrupts. It's not called while
7623  * the interrupt routine is executing.
7624  */
igb_netpoll(struct net_device * netdev)7625 static void igb_netpoll(struct net_device *netdev)
7626 {
7627 	struct igb_adapter *adapter = netdev_priv(netdev);
7628 	struct e1000_hw *hw = &adapter->hw;
7629 	struct igb_q_vector *q_vector;
7630 	int i;
7631 
7632 	for (i = 0; i < adapter->num_q_vectors; i++) {
7633 		q_vector = adapter->q_vector[i];
7634 		if (adapter->flags & IGB_FLAG_HAS_MSIX)
7635 			wr32(E1000_EIMC, q_vector->eims_value);
7636 		else
7637 			igb_irq_disable(adapter);
7638 		napi_schedule(&q_vector->napi);
7639 	}
7640 }
7641 #endif /* CONFIG_NET_POLL_CONTROLLER */
7642 
7643 /**
7644  *  igb_io_error_detected - called when PCI error is detected
7645  *  @pdev: Pointer to PCI device
7646  *  @state: The current pci connection state
7647  *
7648  *  This function is called after a PCI bus error affecting
7649  *  this device has been detected.
7650  **/
igb_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7651 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7652 					      pci_channel_state_t state)
7653 {
7654 	struct net_device *netdev = pci_get_drvdata(pdev);
7655 	struct igb_adapter *adapter = netdev_priv(netdev);
7656 
7657 	netif_device_detach(netdev);
7658 
7659 	if (state == pci_channel_io_perm_failure)
7660 		return PCI_ERS_RESULT_DISCONNECT;
7661 
7662 	if (netif_running(netdev))
7663 		igb_down(adapter);
7664 	pci_disable_device(pdev);
7665 
7666 	/* Request a slot slot reset. */
7667 	return PCI_ERS_RESULT_NEED_RESET;
7668 }
7669 
7670 /**
7671  *  igb_io_slot_reset - called after the pci bus has been reset.
7672  *  @pdev: Pointer to PCI device
7673  *
7674  *  Restart the card from scratch, as if from a cold-boot. Implementation
7675  *  resembles the first-half of the igb_resume routine.
7676  **/
igb_io_slot_reset(struct pci_dev * pdev)7677 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7678 {
7679 	struct net_device *netdev = pci_get_drvdata(pdev);
7680 	struct igb_adapter *adapter = netdev_priv(netdev);
7681 	struct e1000_hw *hw = &adapter->hw;
7682 	pci_ers_result_t result;
7683 	int err;
7684 
7685 	if (pci_enable_device_mem(pdev)) {
7686 		dev_err(&pdev->dev,
7687 			"Cannot re-enable PCI device after reset.\n");
7688 		result = PCI_ERS_RESULT_DISCONNECT;
7689 	} else {
7690 		pci_set_master(pdev);
7691 		pci_restore_state(pdev);
7692 		pci_save_state(pdev);
7693 
7694 		pci_enable_wake(pdev, PCI_D3hot, 0);
7695 		pci_enable_wake(pdev, PCI_D3cold, 0);
7696 
7697 		igb_reset(adapter);
7698 		wr32(E1000_WUS, ~0);
7699 		result = PCI_ERS_RESULT_RECOVERED;
7700 	}
7701 
7702 	err = pci_cleanup_aer_uncorrect_error_status(pdev);
7703 	if (err) {
7704 		dev_err(&pdev->dev,
7705 			"pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7706 			err);
7707 		/* non-fatal, continue */
7708 	}
7709 
7710 	return result;
7711 }
7712 
7713 /**
7714  *  igb_io_resume - called when traffic can start flowing again.
7715  *  @pdev: Pointer to PCI device
7716  *
7717  *  This callback is called when the error recovery driver tells us that
7718  *  its OK to resume normal operation. Implementation resembles the
7719  *  second-half of the igb_resume routine.
7720  */
igb_io_resume(struct pci_dev * pdev)7721 static void igb_io_resume(struct pci_dev *pdev)
7722 {
7723 	struct net_device *netdev = pci_get_drvdata(pdev);
7724 	struct igb_adapter *adapter = netdev_priv(netdev);
7725 
7726 	if (netif_running(netdev)) {
7727 		if (igb_up(adapter)) {
7728 			dev_err(&pdev->dev, "igb_up failed after reset\n");
7729 			return;
7730 		}
7731 	}
7732 
7733 	netif_device_attach(netdev);
7734 
7735 	/* let the f/w know that the h/w is now under the control of the
7736 	 * driver.
7737 	 */
7738 	igb_get_hw_control(adapter);
7739 }
7740 
igb_rar_set_qsel(struct igb_adapter * adapter,u8 * addr,u32 index,u8 qsel)7741 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7742 			     u8 qsel)
7743 {
7744 	u32 rar_low, rar_high;
7745 	struct e1000_hw *hw = &adapter->hw;
7746 
7747 	/* HW expects these in little endian so we reverse the byte order
7748 	 * from network order (big endian) to little endian
7749 	 */
7750 	rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7751 		   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7752 	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7753 
7754 	/* Indicate to hardware the Address is Valid. */
7755 	rar_high |= E1000_RAH_AV;
7756 
7757 	if (hw->mac.type == e1000_82575)
7758 		rar_high |= E1000_RAH_POOL_1 * qsel;
7759 	else
7760 		rar_high |= E1000_RAH_POOL_1 << qsel;
7761 
7762 	wr32(E1000_RAL(index), rar_low);
7763 	wrfl();
7764 	wr32(E1000_RAH(index), rar_high);
7765 	wrfl();
7766 }
7767 
igb_set_vf_mac(struct igb_adapter * adapter,int vf,unsigned char * mac_addr)7768 static int igb_set_vf_mac(struct igb_adapter *adapter,
7769 			  int vf, unsigned char *mac_addr)
7770 {
7771 	struct e1000_hw *hw = &adapter->hw;
7772 	/* VF MAC addresses start at end of receive addresses and moves
7773 	 * towards the first, as a result a collision should not be possible
7774 	 */
7775 	int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7776 
7777 	memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7778 
7779 	igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7780 
7781 	return 0;
7782 }
7783 
igb_ndo_set_vf_mac(struct net_device * netdev,int vf,u8 * mac)7784 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7785 {
7786 	struct igb_adapter *adapter = netdev_priv(netdev);
7787 	if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7788 		return -EINVAL;
7789 	adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7790 	dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7791 	dev_info(&adapter->pdev->dev,
7792 		 "Reload the VF driver to make this change effective.");
7793 	if (test_bit(__IGB_DOWN, &adapter->state)) {
7794 		dev_warn(&adapter->pdev->dev,
7795 			 "The VF MAC address has been set, but the PF device is not up.\n");
7796 		dev_warn(&adapter->pdev->dev,
7797 			 "Bring the PF device up before attempting to use the VF device.\n");
7798 	}
7799 	return igb_set_vf_mac(adapter, vf, mac);
7800 }
7801 
igb_link_mbps(int internal_link_speed)7802 static int igb_link_mbps(int internal_link_speed)
7803 {
7804 	switch (internal_link_speed) {
7805 	case SPEED_100:
7806 		return 100;
7807 	case SPEED_1000:
7808 		return 1000;
7809 	default:
7810 		return 0;
7811 	}
7812 }
7813 
igb_set_vf_rate_limit(struct e1000_hw * hw,int vf,int tx_rate,int link_speed)7814 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7815 				  int link_speed)
7816 {
7817 	int rf_dec, rf_int;
7818 	u32 bcnrc_val;
7819 
7820 	if (tx_rate != 0) {
7821 		/* Calculate the rate factor values to set */
7822 		rf_int = link_speed / tx_rate;
7823 		rf_dec = (link_speed - (rf_int * tx_rate));
7824 		rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7825 			 tx_rate;
7826 
7827 		bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7828 		bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7829 			      E1000_RTTBCNRC_RF_INT_MASK);
7830 		bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7831 	} else {
7832 		bcnrc_val = 0;
7833 	}
7834 
7835 	wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7836 	/* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7837 	 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7838 	 */
7839 	wr32(E1000_RTTBCNRM, 0x14);
7840 	wr32(E1000_RTTBCNRC, bcnrc_val);
7841 }
7842 
igb_check_vf_rate_limit(struct igb_adapter * adapter)7843 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7844 {
7845 	int actual_link_speed, i;
7846 	bool reset_rate = false;
7847 
7848 	/* VF TX rate limit was not set or not supported */
7849 	if ((adapter->vf_rate_link_speed == 0) ||
7850 	    (adapter->hw.mac.type != e1000_82576))
7851 		return;
7852 
7853 	actual_link_speed = igb_link_mbps(adapter->link_speed);
7854 	if (actual_link_speed != adapter->vf_rate_link_speed) {
7855 		reset_rate = true;
7856 		adapter->vf_rate_link_speed = 0;
7857 		dev_info(&adapter->pdev->dev,
7858 			 "Link speed has been changed. VF Transmit rate is disabled\n");
7859 	}
7860 
7861 	for (i = 0; i < adapter->vfs_allocated_count; i++) {
7862 		if (reset_rate)
7863 			adapter->vf_data[i].tx_rate = 0;
7864 
7865 		igb_set_vf_rate_limit(&adapter->hw, i,
7866 				      adapter->vf_data[i].tx_rate,
7867 				      actual_link_speed);
7868 	}
7869 }
7870 
igb_ndo_set_vf_bw(struct net_device * netdev,int vf,int min_tx_rate,int max_tx_rate)7871 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7872 			     int min_tx_rate, int max_tx_rate)
7873 {
7874 	struct igb_adapter *adapter = netdev_priv(netdev);
7875 	struct e1000_hw *hw = &adapter->hw;
7876 	int actual_link_speed;
7877 
7878 	if (hw->mac.type != e1000_82576)
7879 		return -EOPNOTSUPP;
7880 
7881 	if (min_tx_rate)
7882 		return -EINVAL;
7883 
7884 	actual_link_speed = igb_link_mbps(adapter->link_speed);
7885 	if ((vf >= adapter->vfs_allocated_count) ||
7886 	    (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7887 	    (max_tx_rate < 0) ||
7888 	    (max_tx_rate > actual_link_speed))
7889 		return -EINVAL;
7890 
7891 	adapter->vf_rate_link_speed = actual_link_speed;
7892 	adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7893 	igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
7894 
7895 	return 0;
7896 }
7897 
igb_ndo_set_vf_spoofchk(struct net_device * netdev,int vf,bool setting)7898 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7899 				   bool setting)
7900 {
7901 	struct igb_adapter *adapter = netdev_priv(netdev);
7902 	struct e1000_hw *hw = &adapter->hw;
7903 	u32 reg_val, reg_offset;
7904 
7905 	if (!adapter->vfs_allocated_count)
7906 		return -EOPNOTSUPP;
7907 
7908 	if (vf >= adapter->vfs_allocated_count)
7909 		return -EINVAL;
7910 
7911 	reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7912 	reg_val = rd32(reg_offset);
7913 	if (setting)
7914 		reg_val |= ((1 << vf) |
7915 			    (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7916 	else
7917 		reg_val &= ~((1 << vf) |
7918 			     (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7919 	wr32(reg_offset, reg_val);
7920 
7921 	adapter->vf_data[vf].spoofchk_enabled = setting;
7922 	return 0;
7923 }
7924 
igb_ndo_get_vf_config(struct net_device * netdev,int vf,struct ifla_vf_info * ivi)7925 static int igb_ndo_get_vf_config(struct net_device *netdev,
7926 				 int vf, struct ifla_vf_info *ivi)
7927 {
7928 	struct igb_adapter *adapter = netdev_priv(netdev);
7929 	if (vf >= adapter->vfs_allocated_count)
7930 		return -EINVAL;
7931 	ivi->vf = vf;
7932 	memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7933 	ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7934 	ivi->min_tx_rate = 0;
7935 	ivi->vlan = adapter->vf_data[vf].pf_vlan;
7936 	ivi->qos = adapter->vf_data[vf].pf_qos;
7937 	ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7938 	return 0;
7939 }
7940 
igb_vmm_control(struct igb_adapter * adapter)7941 static void igb_vmm_control(struct igb_adapter *adapter)
7942 {
7943 	struct e1000_hw *hw = &adapter->hw;
7944 	u32 reg;
7945 
7946 	switch (hw->mac.type) {
7947 	case e1000_82575:
7948 	case e1000_i210:
7949 	case e1000_i211:
7950 	case e1000_i354:
7951 	default:
7952 		/* replication is not supported for 82575 */
7953 		return;
7954 	case e1000_82576:
7955 		/* notify HW that the MAC is adding vlan tags */
7956 		reg = rd32(E1000_DTXCTL);
7957 		reg |= E1000_DTXCTL_VLAN_ADDED;
7958 		wr32(E1000_DTXCTL, reg);
7959 		/* Fall through */
7960 	case e1000_82580:
7961 		/* enable replication vlan tag stripping */
7962 		reg = rd32(E1000_RPLOLR);
7963 		reg |= E1000_RPLOLR_STRVLAN;
7964 		wr32(E1000_RPLOLR, reg);
7965 		/* Fall through */
7966 	case e1000_i350:
7967 		/* none of the above registers are supported by i350 */
7968 		break;
7969 	}
7970 
7971 	if (adapter->vfs_allocated_count) {
7972 		igb_vmdq_set_loopback_pf(hw, true);
7973 		igb_vmdq_set_replication_pf(hw, true);
7974 		igb_vmdq_set_anti_spoofing_pf(hw, true,
7975 					      adapter->vfs_allocated_count);
7976 	} else {
7977 		igb_vmdq_set_loopback_pf(hw, false);
7978 		igb_vmdq_set_replication_pf(hw, false);
7979 	}
7980 }
7981 
igb_init_dmac(struct igb_adapter * adapter,u32 pba)7982 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7983 {
7984 	struct e1000_hw *hw = &adapter->hw;
7985 	u32 dmac_thr;
7986 	u16 hwm;
7987 
7988 	if (hw->mac.type > e1000_82580) {
7989 		if (adapter->flags & IGB_FLAG_DMAC) {
7990 			u32 reg;
7991 
7992 			/* force threshold to 0. */
7993 			wr32(E1000_DMCTXTH, 0);
7994 
7995 			/* DMA Coalescing high water mark needs to be greater
7996 			 * than the Rx threshold. Set hwm to PBA - max frame
7997 			 * size in 16B units, capping it at PBA - 6KB.
7998 			 */
7999 			hwm = 64 * pba - adapter->max_frame_size / 16;
8000 			if (hwm < 64 * (pba - 6))
8001 				hwm = 64 * (pba - 6);
8002 			reg = rd32(E1000_FCRTC);
8003 			reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8004 			reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8005 				& E1000_FCRTC_RTH_COAL_MASK);
8006 			wr32(E1000_FCRTC, reg);
8007 
8008 			/* Set the DMA Coalescing Rx threshold to PBA - 2 * max
8009 			 * frame size, capping it at PBA - 10KB.
8010 			 */
8011 			dmac_thr = pba - adapter->max_frame_size / 512;
8012 			if (dmac_thr < pba - 10)
8013 				dmac_thr = pba - 10;
8014 			reg = rd32(E1000_DMACR);
8015 			reg &= ~E1000_DMACR_DMACTHR_MASK;
8016 			reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8017 				& E1000_DMACR_DMACTHR_MASK);
8018 
8019 			/* transition to L0x or L1 if available..*/
8020 			reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8021 
8022 			/* watchdog timer= +-1000 usec in 32usec intervals */
8023 			reg |= (1000 >> 5);
8024 
8025 			/* Disable BMC-to-OS Watchdog Enable */
8026 			if (hw->mac.type != e1000_i354)
8027 				reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8028 
8029 			wr32(E1000_DMACR, reg);
8030 
8031 			/* no lower threshold to disable
8032 			 * coalescing(smart fifb)-UTRESH=0
8033 			 */
8034 			wr32(E1000_DMCRTRH, 0);
8035 
8036 			reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8037 
8038 			wr32(E1000_DMCTLX, reg);
8039 
8040 			/* free space in tx packet buffer to wake from
8041 			 * DMA coal
8042 			 */
8043 			wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8044 			     (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8045 
8046 			/* make low power state decision controlled
8047 			 * by DMA coal
8048 			 */
8049 			reg = rd32(E1000_PCIEMISC);
8050 			reg &= ~E1000_PCIEMISC_LX_DECISION;
8051 			wr32(E1000_PCIEMISC, reg);
8052 		} /* endif adapter->dmac is not disabled */
8053 	} else if (hw->mac.type == e1000_82580) {
8054 		u32 reg = rd32(E1000_PCIEMISC);
8055 
8056 		wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8057 		wr32(E1000_DMACR, 0);
8058 	}
8059 }
8060 
8061 /**
8062  *  igb_read_i2c_byte - Reads 8 bit word over I2C
8063  *  @hw: pointer to hardware structure
8064  *  @byte_offset: byte offset to read
8065  *  @dev_addr: device address
8066  *  @data: value read
8067  *
8068  *  Performs byte read operation over I2C interface at
8069  *  a specified device address.
8070  **/
igb_read_i2c_byte(struct e1000_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)8071 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8072 		      u8 dev_addr, u8 *data)
8073 {
8074 	struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8075 	struct i2c_client *this_client = adapter->i2c_client;
8076 	s32 status;
8077 	u16 swfw_mask = 0;
8078 
8079 	if (!this_client)
8080 		return E1000_ERR_I2C;
8081 
8082 	swfw_mask = E1000_SWFW_PHY0_SM;
8083 
8084 	if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8085 		return E1000_ERR_SWFW_SYNC;
8086 
8087 	status = i2c_smbus_read_byte_data(this_client, byte_offset);
8088 	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8089 
8090 	if (status < 0)
8091 		return E1000_ERR_I2C;
8092 	else {
8093 		*data = status;
8094 		return 0;
8095 	}
8096 }
8097 
8098 /**
8099  *  igb_write_i2c_byte - Writes 8 bit word over I2C
8100  *  @hw: pointer to hardware structure
8101  *  @byte_offset: byte offset to write
8102  *  @dev_addr: device address
8103  *  @data: value to write
8104  *
8105  *  Performs byte write operation over I2C interface at
8106  *  a specified device address.
8107  **/
igb_write_i2c_byte(struct e1000_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)8108 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8109 		       u8 dev_addr, u8 data)
8110 {
8111 	struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8112 	struct i2c_client *this_client = adapter->i2c_client;
8113 	s32 status;
8114 	u16 swfw_mask = E1000_SWFW_PHY0_SM;
8115 
8116 	if (!this_client)
8117 		return E1000_ERR_I2C;
8118 
8119 	if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8120 		return E1000_ERR_SWFW_SYNC;
8121 	status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8122 	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8123 
8124 	if (status)
8125 		return E1000_ERR_I2C;
8126 	else
8127 		return 0;
8128 
8129 }
8130 
igb_reinit_queues(struct igb_adapter * adapter)8131 int igb_reinit_queues(struct igb_adapter *adapter)
8132 {
8133 	struct net_device *netdev = adapter->netdev;
8134 	struct pci_dev *pdev = adapter->pdev;
8135 	int err = 0;
8136 
8137 	if (netif_running(netdev))
8138 		igb_close(netdev);
8139 
8140 	igb_reset_interrupt_capability(adapter);
8141 
8142 	if (igb_init_interrupt_scheme(adapter, true)) {
8143 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8144 		return -ENOMEM;
8145 	}
8146 
8147 	if (netif_running(netdev))
8148 		err = igb_open(netdev);
8149 
8150 	return err;
8151 }
8152 /* igb_main.c */
8153