1 #ifndef WILC_WLAN_H
2 #define WILC_WLAN_H
3 
4 
5 
6 #define ISWILC1000(id)   (((id & 0xfffff000) == 0x100000) ? 1 : 0)
7 
8 
9 /********************************************
10  *
11  *      Mac eth header length
12  *
13  ********************************************/
14 #define DRIVER_HANDLER_SIZE 4
15 #define MAX_MAC_HDR_LEN         26 /* QOS_MAC_HDR_LEN */
16 #define SUB_MSDU_HEADER_LENGTH  14
17 #define SNAP_HDR_LEN            8
18 #define ETHERNET_HDR_LEN          14
19 #define WORD_ALIGNMENT_PAD        0
20 
21 #define ETH_ETHERNET_HDR_OFFSET   (MAX_MAC_HDR_LEN + SUB_MSDU_HEADER_LENGTH + \
22 				   SNAP_HDR_LEN - ETHERNET_HDR_LEN + WORD_ALIGNMENT_PAD)
23 
24 #define HOST_HDR_OFFSET		4
25 #define ETHERNET_HDR_LEN          14
26 #define IP_HDR_LEN                20
27 #define IP_HDR_OFFSET             ETHERNET_HDR_LEN
28 #define UDP_HDR_OFFSET            (IP_HDR_LEN + IP_HDR_OFFSET)
29 #define UDP_HDR_LEN               8
30 #define UDP_DATA_OFFSET           (UDP_HDR_OFFSET + UDP_HDR_LEN)
31 #define ETH_CONFIG_PKT_HDR_LEN    UDP_DATA_OFFSET
32 
33 #define ETH_CONFIG_PKT_HDR_OFFSET (ETH_ETHERNET_HDR_OFFSET + \
34 				   ETH_CONFIG_PKT_HDR_LEN)
35 
36 /********************************************
37  *
38  *      Endian Conversion
39  *
40  ********************************************/
41 
42 #define BYTE_SWAP(val) ((((val) & 0x000000FF) << 24) + \
43 			(((val) & 0x0000FF00) << 8)  + \
44 			(((val) & 0x00FF0000) >> 8)   +	\
45 			(((val) & 0xFF000000) >> 24))
46 
47 /********************************************
48  *
49  *      Register Defines
50  *
51  ********************************************/
52 #define WILC_PERIPH_REG_BASE 0x1000
53 #define WILC_CHANGING_VIR_IF                     (0x108c)
54 #define WILC_CHIPID	(WILC_PERIPH_REG_BASE)
55 #define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400)
56 #define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408)
57 #define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c)
58 #define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70)
59 #define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74)
60 #define WILC_HOST_VMM_CTL	(WILC_PERIPH_REG_BASE + 0x78)
61 #define WILC_HOST_RX_CTRL	(WILC_PERIPH_REG_BASE + 0x80)
62 #define WILC_HOST_RX_EXTRA_SIZE	(WILC_PERIPH_REG_BASE + 0x84)
63 #define WILC_HOST_TX_CTRL_1	(WILC_PERIPH_REG_BASE + 0x88)
64 #define WILC_MISC	(WILC_PERIPH_REG_BASE + 0x428)
65 #define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00)
66 #define WILC_INTR_ENABLE (WILC_INTR_REG_BASE)
67 #define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4)
68 
69 #define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10)
70 #define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20)
71 #define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30)
72 #define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40)
73 
74 #define WILC_VMM_TBL_SIZE 64
75 #define WILC_VMM_TX_TBL_BASE (0x150400)
76 #define WILC_VMM_RX_TBL_BASE (0x150500)
77 
78 #define WILC_VMM_BASE 0x150000
79 #define WILC_VMM_CORE_CTL (WILC_VMM_BASE)
80 #define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4)
81 #define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8)
82 #define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc)
83 #define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10)
84 #define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14)
85 #define WILC_VMM_TBL_ACTIVE (WILC_VMM_BASE + 040)
86 #define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44)
87 
88 #define WILC_SPI_REG_BASE 0xe800
89 #define WILC_SPI_CTL (WILC_SPI_REG_BASE)
90 #define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4)
91 #define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8)
92 #define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc)
93 #define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10)
94 #define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20)
95 #define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24)
96 #define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c)
97 
98 #define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - WILC_SPI_REG_BASE)
99 
100 #define WILC_AHB_DATA_MEM_BASE 0x30000
101 #define WILC_AHB_SHARE_MEM_BASE 0xd0000
102 
103 #define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE
104 #define WILC_VMM_TBL_RX_SHADOW_SIZE (256)
105 
106 #define WILC_GP_REG_0   0x149c
107 #define WILC_GP_REG_1   0x14a0
108 
109 #define rHAVE_SDIO_IRQ_GPIO_BIT      (0)
110 #define rHAVE_USE_PMU_BIT            (1)
111 #define rHAVE_SLEEP_CLK_SRC_RTC_BIT  (2)
112 #define rHAVE_SLEEP_CLK_SRC_XO_BIT   (3)
113 #define rHAVE_EXT_PA_INV_TX_RX_BIT   (4)
114 #define rHAVE_LEGACY_RF_SETTINGS_BIT (5)
115 #define rHAVE_XTAL_24_BIT            (6)
116 #define rHAVE_DISABLE_WILC_UART_BIT   (7)
117 
118 
119 #define WILC_HAVE_SDIO_IRQ_GPIO       (1 << rHAVE_SDIO_IRQ_GPIO_BIT)
120 #define WILC_HAVE_USE_PMU             (1 << rHAVE_USE_PMU_BIT)
121 #define WILC_HAVE_SLEEP_CLK_SRC_RTC   (1 << rHAVE_SLEEP_CLK_SRC_RTC_BIT)
122 #define WILC_HAVE_SLEEP_CLK_SRC_XO    (1 << rHAVE_SLEEP_CLK_SRC_XO_BIT)
123 #define WILC_HAVE_EXT_PA_INV_TX_RX    (1 << rHAVE_EXT_PA_INV_TX_RX_BIT)
124 #define WILC_HAVE_LEGACY_RF_SETTINGS  (1 << rHAVE_LEGACY_RF_SETTINGS_BIT)
125 #define WILC_HAVE_XTAL_24             (1 << rHAVE_XTAL_24_BIT)
126 #define WILC_HAVE_DISABLE_WILC_UART    (1 << rHAVE_DISABLE_WILC_UART_BIT)
127 
128 
129 /********************************************
130  *
131  *      Wlan Defines
132  *
133  ********************************************/
134 #define WILC_CFG_PKT	1
135 #define WILC_NET_PKT 0
136 #define WILC_MGMT_PKT 2
137 
138 #define WILC_CFG_SET 1
139 #define WILC_CFG_QUERY 0
140 
141 #define WILC_CFG_RSP	1
142 #define WILC_CFG_RSP_STATUS 2
143 #define WILC_CFG_RSP_SCAN 3
144 
145 #ifdef WILC_SDIO
146 #define WILC_PLL_TO	4
147 #else
148 #define WILC_PLL_TO	2
149 #endif
150 
151 
152 #define ABORT_INT   BIT(31)
153 
154 /*******************************************/
155 /*        E0 and later Interrupt flags.    */
156 /*******************************************/
157 /*******************************************/
158 /*        E0 and later Interrupt flags.    */
159 /*           IRQ Status word               */
160 /* 15:0 = DMA count in words.              */
161 /* 16: INT0 flag                           */
162 /* 17: INT1 flag                           */
163 /* 18: INT2 flag                           */
164 /* 19: INT3 flag                           */
165 /* 20: INT4 flag                           */
166 /* 21: INT5 flag                           */
167 /*******************************************/
168 #define                 IRG_FLAGS_OFFSET 16
169 #define IRQ_DMA_WD_CNT_MASK ((1ul << IRG_FLAGS_OFFSET) - 1)
170 #define INT_0           (1 << (IRG_FLAGS_OFFSET))
171 #define INT_1           (1 << (IRG_FLAGS_OFFSET + 1))
172 #define INT_2           (1 << (IRG_FLAGS_OFFSET + 2))
173 #define INT_3           (1 << (IRG_FLAGS_OFFSET + 3))
174 #define INT_4           (1 << (IRG_FLAGS_OFFSET + 4))
175 #define INT_5           (1 << (IRG_FLAGS_OFFSET + 5))
176 #define MAX_NUM_INT     (6)
177 
178 /*******************************************/
179 /*        E0 and later Interrupt flags.    */
180 /*           IRQ Clear word                */
181 /* 0: Clear INT0                           */
182 /* 1: Clear INT1                           */
183 /* 2: Clear INT2                           */
184 /* 3: Clear INT3                           */
185 /* 4: Clear INT4                           */
186 /* 5: Clear INT5                           */
187 /* 6: Select VMM table 1                   */
188 /* 7: Select VMM table 2                   */
189 /* 8: Enable VMM                           */
190 /*******************************************/
191 #define CLR_INT0             BIT(0)
192 #define CLR_INT1             BIT(1)
193 #define CLR_INT2             BIT(2)
194 #define CLR_INT3             BIT(3)
195 #define CLR_INT4             BIT(4)
196 #define CLR_INT5             BIT(5)
197 #define SEL_VMM_TBL0         BIT(6)
198 #define SEL_VMM_TBL1         BIT(7)
199 #define EN_VMM               BIT(8)
200 
201 #define DATA_INT_EXT	INT_0
202 #define PLL_INT_EXT         INT_1
203 #define SLEEP_INT_EXT	INT_2
204 #define ALL_INT_EXT     (DATA_INT_EXT | PLL_INT_EXT | SLEEP_INT_EXT)
205 #define NUM_INT_EXT     (3)
206 
207 #define DATA_INT_CLR	CLR_INT0
208 #define PLL_INT_CLR         CLR_INT1
209 #define SLEEP_INT_CLR	CLR_INT2
210 
211 #define ENABLE_RX_VMM   (SEL_VMM_TBL1 | EN_VMM)
212 #define ENABLE_TX_VMM   (SEL_VMM_TBL0 | EN_VMM)
213 
214 
215 /*time for expiring the semaphores of cfg packets*/
216 #define CFG_PKTS_TIMEOUT	2000
217 /********************************************
218  *
219  *      Debug Type
220  *
221  ********************************************/
222 typedef void (*wilc_debug_func)(u32, char *, ...);
223 
224 /********************************************
225  *
226  *      Tx/Rx Queue Structure
227  *
228  ********************************************/
229 
230 struct txq_entry_t {
231 	struct txq_entry_t *next;
232 	struct txq_entry_t *prev;
233 	int type;
234 	int tcp_PendingAck_index;
235 	u8 *buffer;
236 	int buffer_size;
237 	void *priv;
238 	int status;
239 	void (*tx_complete_func)(void *, int);
240 };
241 
242 struct rxq_entry_t {
243 	struct rxq_entry_t *next;
244 	u8 *buffer;
245 	int buffer_size;
246 };
247 
248 /********************************************
249  *
250  *      Host IF Structure
251  *
252  ********************************************/
253 
254 typedef struct {
255 	int (*hif_init)(wilc_wlan_inp_t *, wilc_debug_func);
256 	int (*hif_deinit)(void *);
257 	int (*hif_read_reg)(u32, u32 *);
258 	int (*hif_write_reg)(u32, u32);
259 	int (*hif_block_rx)(u32, u8 *, u32);
260 	int (*hif_block_tx)(u32, u8 *, u32);
261 	int (*hif_sync)(void);
262 	int (*hif_clear_int)(void);
263 	int (*hif_read_int)(u32 *);
264 	int (*hif_clear_int_ext)(u32);
265 	int (*hif_read_size)(u32 *);
266 	int (*hif_block_tx_ext)(u32, u8 *, u32);
267 	int (*hif_block_rx_ext)(u32, u8 *, u32);
268 	int (*hif_sync_ext)(int);
269 	void (*hif_set_max_bus_speed)(void);
270 	void (*hif_set_default_bus_speed)(void);
271 } wilc_hif_func_t;
272 
273 /********************************************
274  *
275  *      Configuration Structure
276  *
277  ********************************************/
278 
279 #define MAX_CFG_FRAME_SIZE 1468
280 
281 typedef struct {
282 	u8 ether_header[14];
283 	u8 ip_header[20];
284 	u8 udp_header[8];
285 	u8 wid_header[8];
286 	u8 frame[MAX_CFG_FRAME_SIZE];
287 } wilc_cfg_frame_t;
288 
289 typedef struct {
290 	int (*wlan_tx)(u8 *, u32, wilc_tx_complete_func_t);
291 } wilc_wlan_cfg_func_t;
292 
293 typedef struct {
294 	int type;
295 	u32 seq_no;
296 } wilc_cfg_rsp_t;
297 
298 int wilc_wlan_firmware_download(const u8 *buffer, u32 buffer_size);
299 int wilc_wlan_start(void);
300 int wilc_wlan_stop(void);
301 int wilc_wlan_txq_add_net_pkt(struct net_device *dev, void *priv, u8 *buffer,
302 			      u32 buffer_size, wilc_tx_complete_func_t func);
303 int wilc_wlan_handle_txq(struct net_device *dev, u32 *pu32TxqCount);
304 void wilc_handle_isr(void *wilc);
305 void wilc_wlan_cleanup(struct net_device *dev);
306 int wilc_wlan_cfg_set(int start, u32 wid, u8 *buffer, u32 buffer_size,
307 		      int commit, u32 drvHandler);
308 int wilc_wlan_cfg_get(int start, u32 wid, int commit, u32 drvHandler);
309 int wilc_wlan_cfg_get_val(u32 wid, u8 *buffer, u32 buffer_size);
310 int wilc_wlan_txq_add_mgmt_pkt(void *priv, u8 *buffer, u32 buffer_size,
311 			       wilc_tx_complete_func_t func);
312 #endif
313