1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DEVICE_H
34 #define MLX5_DEVICE_H
35
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
38 #include <linux/mlx5/mlx5_ifc.h>
39
40 #if defined(__LITTLE_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0
42 #elif defined(__BIG_ENDIAN)
43 #define MLX5_SET_HOST_ENDIANNESS 0x80
44 #else
45 #error Host endianness not defined
46 #endif
47
48 /* helper macros */
49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
62 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
63 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
64 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
65 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
66
67 /* insert a value to a struct */
68 #define MLX5_SET(typ, p, fld, v) do { \
69 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
73 << __mlx5_dw_bit_off(typ, fld))); \
74 } while (0)
75
76 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
78 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
79 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
80 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
81 << __mlx5_dw_bit_off(typ, fld))); \
82 } while (0)
83
84 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
85 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
86 __mlx5_mask(typ, fld))
87
88 #define MLX5_GET_PR(typ, p, fld) ({ \
89 u32 ___t = MLX5_GET(typ, p, fld); \
90 pr_debug(#fld " = 0x%x\n", ___t); \
91 ___t; \
92 })
93
94 #define MLX5_SET64(typ, p, fld, v) do { \
95 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
96 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
98 } while (0)
99
100 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
101
102 #define MLX5_GET64_PR(typ, p, fld) ({ \
103 u64 ___t = MLX5_GET64(typ, p, fld); \
104 pr_debug(#fld " = 0x%llx\n", ___t); \
105 ___t; \
106 })
107
108 enum {
109 MLX5_MAX_COMMANDS = 32,
110 MLX5_CMD_DATA_BLOCK_SIZE = 512,
111 MLX5_PCI_CMD_XPORT = 7,
112 MLX5_MKEY_BSF_OCTO_SIZE = 4,
113 MLX5_MAX_PSVS = 4,
114 };
115
116 enum {
117 MLX5_EXTENDED_UD_AV = 0x80000000,
118 };
119
120 enum {
121 MLX5_CQ_STATE_ARMED = 9,
122 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
123 MLX5_CQ_STATE_FIRED = 0xa,
124 };
125
126 enum {
127 MLX5_STAT_RATE_OFFSET = 5,
128 };
129
130 enum {
131 MLX5_INLINE_SEG = 0x80000000,
132 };
133
134 enum {
135 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
136 };
137
138 enum {
139 MLX5_MIN_PKEY_TABLE_SIZE = 128,
140 MLX5_MAX_LOG_PKEY_TABLE = 5,
141 };
142
143 enum {
144 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
145 };
146
147 enum {
148 MLX5_PFAULT_SUBTYPE_WQE = 0,
149 MLX5_PFAULT_SUBTYPE_RDMA = 1,
150 };
151
152 enum {
153 MLX5_PERM_LOCAL_READ = 1 << 2,
154 MLX5_PERM_LOCAL_WRITE = 1 << 3,
155 MLX5_PERM_REMOTE_READ = 1 << 4,
156 MLX5_PERM_REMOTE_WRITE = 1 << 5,
157 MLX5_PERM_ATOMIC = 1 << 6,
158 MLX5_PERM_UMR_EN = 1 << 7,
159 };
160
161 enum {
162 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
163 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
164 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
165 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
166 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
167 };
168
169 enum {
170 MLX5_ACCESS_MODE_PA = 0,
171 MLX5_ACCESS_MODE_MTT = 1,
172 MLX5_ACCESS_MODE_KLM = 2
173 };
174
175 enum {
176 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
177 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
178 MLX5_MKEY_BSF_EN = 1 << 30,
179 MLX5_MKEY_LEN64 = 1 << 31,
180 };
181
182 enum {
183 MLX5_EN_RD = (u64)1,
184 MLX5_EN_WR = (u64)2
185 };
186
187 enum {
188 MLX5_BF_REGS_PER_PAGE = 4,
189 MLX5_MAX_UAR_PAGES = 1 << 8,
190 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
191 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
192 };
193
194 enum {
195 MLX5_MKEY_MASK_LEN = 1ull << 0,
196 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
197 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
198 MLX5_MKEY_MASK_PD = 1ull << 7,
199 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
200 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
201 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
202 MLX5_MKEY_MASK_KEY = 1ull << 13,
203 MLX5_MKEY_MASK_QPN = 1ull << 14,
204 MLX5_MKEY_MASK_LR = 1ull << 17,
205 MLX5_MKEY_MASK_LW = 1ull << 18,
206 MLX5_MKEY_MASK_RR = 1ull << 19,
207 MLX5_MKEY_MASK_RW = 1ull << 20,
208 MLX5_MKEY_MASK_A = 1ull << 21,
209 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
210 MLX5_MKEY_MASK_FREE = 1ull << 29,
211 };
212
213 enum {
214 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
215
216 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
217 MLX5_UMR_CHECK_FREE = (2 << 5),
218
219 MLX5_UMR_INLINE = (1 << 7),
220 };
221
222 #define MLX5_UMR_MTT_ALIGNMENT 0x40
223 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
224 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
225
226 enum mlx5_event {
227 MLX5_EVENT_TYPE_COMP = 0x0,
228
229 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
230 MLX5_EVENT_TYPE_COMM_EST = 0x02,
231 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
232 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
233 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
234
235 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
236 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
237 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
238 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
239 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
240 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
241
242 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
243 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
244 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
245 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
246
247 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
248 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
249
250 MLX5_EVENT_TYPE_CMD = 0x0a,
251 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
252
253 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
254 };
255
256 enum {
257 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
258 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
259 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
260 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
261 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
262 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
263 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
264 };
265
266 enum {
267 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
268 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
269 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
270 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
271 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
272 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
273 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
274 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
275 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
276 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
277 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
278 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
279 };
280
281 enum {
282 MLX5_OPCODE_NOP = 0x00,
283 MLX5_OPCODE_SEND_INVAL = 0x01,
284 MLX5_OPCODE_RDMA_WRITE = 0x08,
285 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
286 MLX5_OPCODE_SEND = 0x0a,
287 MLX5_OPCODE_SEND_IMM = 0x0b,
288 MLX5_OPCODE_LSO = 0x0e,
289 MLX5_OPCODE_RDMA_READ = 0x10,
290 MLX5_OPCODE_ATOMIC_CS = 0x11,
291 MLX5_OPCODE_ATOMIC_FA = 0x12,
292 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
293 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
294 MLX5_OPCODE_BIND_MW = 0x18,
295 MLX5_OPCODE_CONFIG_CMD = 0x1f,
296
297 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
298 MLX5_RECV_OPCODE_SEND = 0x01,
299 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
300 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
301
302 MLX5_CQE_OPCODE_ERROR = 0x1e,
303 MLX5_CQE_OPCODE_RESIZE = 0x16,
304
305 MLX5_OPCODE_SET_PSV = 0x20,
306 MLX5_OPCODE_GET_PSV = 0x21,
307 MLX5_OPCODE_CHECK_PSV = 0x22,
308 MLX5_OPCODE_RGET_PSV = 0x26,
309 MLX5_OPCODE_RCHECK_PSV = 0x27,
310
311 MLX5_OPCODE_UMR = 0x25,
312
313 };
314
315 enum {
316 MLX5_SET_PORT_RESET_QKEY = 0,
317 MLX5_SET_PORT_GUID0 = 16,
318 MLX5_SET_PORT_NODE_GUID = 17,
319 MLX5_SET_PORT_SYS_GUID = 18,
320 MLX5_SET_PORT_GID_TABLE = 19,
321 MLX5_SET_PORT_PKEY_TABLE = 20,
322 };
323
324 enum {
325 MLX5_MAX_PAGE_SHIFT = 31
326 };
327
328 enum {
329 MLX5_ADAPTER_PAGE_SHIFT = 12,
330 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
331 };
332
333 enum {
334 MLX5_CAP_OFF_CMDIF_CSUM = 46,
335 };
336
337 enum {
338 /*
339 * Max wqe size for rdma read is 512 bytes, so this
340 * limits our max_sge_rd as the wqe needs to fit:
341 * - ctrl segment (16 bytes)
342 * - rdma segment (16 bytes)
343 * - scatter elements (16 bytes each)
344 */
345 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
346 };
347
348 struct mlx5_inbox_hdr {
349 __be16 opcode;
350 u8 rsvd[4];
351 __be16 opmod;
352 };
353
354 struct mlx5_outbox_hdr {
355 u8 status;
356 u8 rsvd[3];
357 __be32 syndrome;
358 };
359
360 struct mlx5_cmd_query_adapter_mbox_in {
361 struct mlx5_inbox_hdr hdr;
362 u8 rsvd[8];
363 };
364
365 struct mlx5_cmd_query_adapter_mbox_out {
366 struct mlx5_outbox_hdr hdr;
367 u8 rsvd0[24];
368 u8 intapin;
369 u8 rsvd1[13];
370 __be16 vsd_vendor_id;
371 u8 vsd[208];
372 u8 vsd_psid[16];
373 };
374
375 enum mlx5_odp_transport_cap_bits {
376 MLX5_ODP_SUPPORT_SEND = 1 << 31,
377 MLX5_ODP_SUPPORT_RECV = 1 << 30,
378 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
379 MLX5_ODP_SUPPORT_READ = 1 << 28,
380 };
381
382 struct mlx5_odp_caps {
383 char reserved[0x10];
384 struct {
385 __be32 rc_odp_caps;
386 __be32 uc_odp_caps;
387 __be32 ud_odp_caps;
388 } per_transport_caps;
389 char reserved2[0xe4];
390 };
391
392 struct mlx5_cmd_init_hca_mbox_in {
393 struct mlx5_inbox_hdr hdr;
394 u8 rsvd0[2];
395 __be16 profile;
396 u8 rsvd1[4];
397 };
398
399 struct mlx5_cmd_init_hca_mbox_out {
400 struct mlx5_outbox_hdr hdr;
401 u8 rsvd[8];
402 };
403
404 struct mlx5_cmd_teardown_hca_mbox_in {
405 struct mlx5_inbox_hdr hdr;
406 u8 rsvd0[2];
407 __be16 profile;
408 u8 rsvd1[4];
409 };
410
411 struct mlx5_cmd_teardown_hca_mbox_out {
412 struct mlx5_outbox_hdr hdr;
413 u8 rsvd[8];
414 };
415
416 struct mlx5_cmd_layout {
417 u8 type;
418 u8 rsvd0[3];
419 __be32 inlen;
420 __be64 in_ptr;
421 __be32 in[4];
422 __be32 out[4];
423 __be64 out_ptr;
424 __be32 outlen;
425 u8 token;
426 u8 sig;
427 u8 rsvd1;
428 u8 status_own;
429 };
430
431
432 struct health_buffer {
433 __be32 assert_var[5];
434 __be32 rsvd0[3];
435 __be32 assert_exit_ptr;
436 __be32 assert_callra;
437 __be32 rsvd1[2];
438 __be32 fw_ver;
439 __be32 hw_id;
440 __be32 rsvd2;
441 u8 irisc_index;
442 u8 synd;
443 __be16 ext_synd;
444 };
445
446 struct mlx5_init_seg {
447 __be32 fw_rev;
448 __be32 cmdif_rev_fw_sub;
449 __be32 rsvd0[2];
450 __be32 cmdq_addr_h;
451 __be32 cmdq_addr_l_sz;
452 __be32 cmd_dbell;
453 __be32 rsvd1[120];
454 __be32 initializing;
455 struct health_buffer health;
456 __be32 rsvd2[884];
457 __be32 health_counter;
458 __be32 rsvd3[1019];
459 __be64 ieee1588_clk;
460 __be32 ieee1588_clk_type;
461 __be32 clr_intx;
462 };
463
464 struct mlx5_eqe_comp {
465 __be32 reserved[6];
466 __be32 cqn;
467 };
468
469 struct mlx5_eqe_qp_srq {
470 __be32 reserved[6];
471 __be32 qp_srq_n;
472 };
473
474 struct mlx5_eqe_cq_err {
475 __be32 cqn;
476 u8 reserved1[7];
477 u8 syndrome;
478 };
479
480 struct mlx5_eqe_port_state {
481 u8 reserved0[8];
482 u8 port;
483 };
484
485 struct mlx5_eqe_gpio {
486 __be32 reserved0[2];
487 __be64 gpio_event;
488 };
489
490 struct mlx5_eqe_congestion {
491 u8 type;
492 u8 rsvd0;
493 u8 congestion_level;
494 };
495
496 struct mlx5_eqe_stall_vl {
497 u8 rsvd0[3];
498 u8 port_vl;
499 };
500
501 struct mlx5_eqe_cmd {
502 __be32 vector;
503 __be32 rsvd[6];
504 };
505
506 struct mlx5_eqe_page_req {
507 u8 rsvd0[2];
508 __be16 func_id;
509 __be32 num_pages;
510 __be32 rsvd1[5];
511 };
512
513 struct mlx5_eqe_page_fault {
514 __be32 bytes_committed;
515 union {
516 struct {
517 u16 reserved1;
518 __be16 wqe_index;
519 u16 reserved2;
520 __be16 packet_length;
521 u8 reserved3[12];
522 } __packed wqe;
523 struct {
524 __be32 r_key;
525 u16 reserved1;
526 __be16 packet_length;
527 __be32 rdma_op_len;
528 __be64 rdma_va;
529 } __packed rdma;
530 } __packed;
531 __be32 flags_qpn;
532 } __packed;
533
534 union ev_data {
535 __be32 raw[7];
536 struct mlx5_eqe_cmd cmd;
537 struct mlx5_eqe_comp comp;
538 struct mlx5_eqe_qp_srq qp_srq;
539 struct mlx5_eqe_cq_err cq_err;
540 struct mlx5_eqe_port_state port;
541 struct mlx5_eqe_gpio gpio;
542 struct mlx5_eqe_congestion cong;
543 struct mlx5_eqe_stall_vl stall_vl;
544 struct mlx5_eqe_page_req req_pages;
545 struct mlx5_eqe_page_fault page_fault;
546 } __packed;
547
548 struct mlx5_eqe {
549 u8 rsvd0;
550 u8 type;
551 u8 rsvd1;
552 u8 sub_type;
553 __be32 rsvd2[7];
554 union ev_data data;
555 __be16 rsvd3;
556 u8 signature;
557 u8 owner;
558 } __packed;
559
560 struct mlx5_cmd_prot_block {
561 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
562 u8 rsvd0[48];
563 __be64 next;
564 __be32 block_num;
565 u8 rsvd1;
566 u8 token;
567 u8 ctrl_sig;
568 u8 sig;
569 };
570
571 enum {
572 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
573 };
574
575 struct mlx5_err_cqe {
576 u8 rsvd0[32];
577 __be32 srqn;
578 u8 rsvd1[18];
579 u8 vendor_err_synd;
580 u8 syndrome;
581 __be32 s_wqe_opcode_qpn;
582 __be16 wqe_counter;
583 u8 signature;
584 u8 op_own;
585 };
586
587 struct mlx5_cqe64 {
588 u8 rsvd0[4];
589 u8 lro_tcppsh_abort_dupack;
590 u8 lro_min_ttl;
591 __be16 lro_tcp_win;
592 __be32 lro_ack_seq_num;
593 __be32 rss_hash_result;
594 u8 rss_hash_type;
595 u8 ml_path;
596 u8 rsvd20[2];
597 __be16 check_sum;
598 __be16 slid;
599 __be32 flags_rqpn;
600 u8 hds_ip_ext;
601 u8 l4_hdr_type_etc;
602 __be16 vlan_info;
603 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
604 __be32 imm_inval_pkey;
605 u8 rsvd40[4];
606 __be32 byte_cnt;
607 __be64 timestamp;
608 __be32 sop_drop_qpn;
609 __be16 wqe_counter;
610 u8 signature;
611 u8 op_own;
612 };
613
get_cqe_lro_tcppsh(struct mlx5_cqe64 * cqe)614 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
615 {
616 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
617 }
618
get_cqe_l4_hdr_type(struct mlx5_cqe64 * cqe)619 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
620 {
621 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
622 }
623
cqe_has_vlan(struct mlx5_cqe64 * cqe)624 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
625 {
626 return !!(cqe->l4_hdr_type_etc & 0x1);
627 }
628
629 enum {
630 CQE_L4_HDR_TYPE_NONE = 0x0,
631 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
632 CQE_L4_HDR_TYPE_UDP = 0x2,
633 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
634 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
635 };
636
637 enum {
638 CQE_RSS_HTYPE_IP = 0x3 << 6,
639 CQE_RSS_HTYPE_L4 = 0x3 << 2,
640 };
641
642 enum {
643 CQE_L2_OK = 1 << 0,
644 CQE_L3_OK = 1 << 1,
645 CQE_L4_OK = 1 << 2,
646 };
647
648 struct mlx5_sig_err_cqe {
649 u8 rsvd0[16];
650 __be32 expected_trans_sig;
651 __be32 actual_trans_sig;
652 __be32 expected_reftag;
653 __be32 actual_reftag;
654 __be16 syndrome;
655 u8 rsvd22[2];
656 __be32 mkey;
657 __be64 err_offset;
658 u8 rsvd30[8];
659 __be32 qpn;
660 u8 rsvd38[2];
661 u8 signature;
662 u8 op_own;
663 };
664
665 struct mlx5_wqe_srq_next_seg {
666 u8 rsvd0[2];
667 __be16 next_wqe_index;
668 u8 signature;
669 u8 rsvd1[11];
670 };
671
672 union mlx5_ext_cqe {
673 struct ib_grh grh;
674 u8 inl[64];
675 };
676
677 struct mlx5_cqe128 {
678 union mlx5_ext_cqe inl_grh;
679 struct mlx5_cqe64 cqe64;
680 };
681
682 struct mlx5_srq_ctx {
683 u8 state_log_sz;
684 u8 rsvd0[3];
685 __be32 flags_xrcd;
686 __be32 pgoff_cqn;
687 u8 rsvd1[4];
688 u8 log_pg_sz;
689 u8 rsvd2[7];
690 __be32 pd;
691 __be16 lwm;
692 __be16 wqe_cnt;
693 u8 rsvd3[8];
694 __be64 db_record;
695 };
696
697 struct mlx5_create_srq_mbox_in {
698 struct mlx5_inbox_hdr hdr;
699 __be32 input_srqn;
700 u8 rsvd0[4];
701 struct mlx5_srq_ctx ctx;
702 u8 rsvd1[208];
703 __be64 pas[0];
704 };
705
706 struct mlx5_create_srq_mbox_out {
707 struct mlx5_outbox_hdr hdr;
708 __be32 srqn;
709 u8 rsvd[4];
710 };
711
712 struct mlx5_destroy_srq_mbox_in {
713 struct mlx5_inbox_hdr hdr;
714 __be32 srqn;
715 u8 rsvd[4];
716 };
717
718 struct mlx5_destroy_srq_mbox_out {
719 struct mlx5_outbox_hdr hdr;
720 u8 rsvd[8];
721 };
722
723 struct mlx5_query_srq_mbox_in {
724 struct mlx5_inbox_hdr hdr;
725 __be32 srqn;
726 u8 rsvd0[4];
727 };
728
729 struct mlx5_query_srq_mbox_out {
730 struct mlx5_outbox_hdr hdr;
731 u8 rsvd0[8];
732 struct mlx5_srq_ctx ctx;
733 u8 rsvd1[32];
734 __be64 pas[0];
735 };
736
737 struct mlx5_arm_srq_mbox_in {
738 struct mlx5_inbox_hdr hdr;
739 __be32 srqn;
740 __be16 rsvd;
741 __be16 lwm;
742 };
743
744 struct mlx5_arm_srq_mbox_out {
745 struct mlx5_outbox_hdr hdr;
746 u8 rsvd[8];
747 };
748
749 struct mlx5_cq_context {
750 u8 status;
751 u8 cqe_sz_flags;
752 u8 st;
753 u8 rsvd3;
754 u8 rsvd4[6];
755 __be16 page_offset;
756 __be32 log_sz_usr_page;
757 __be16 cq_period;
758 __be16 cq_max_count;
759 __be16 rsvd20;
760 __be16 c_eqn;
761 u8 log_pg_sz;
762 u8 rsvd25[7];
763 __be32 last_notified_index;
764 __be32 solicit_producer_index;
765 __be32 consumer_counter;
766 __be32 producer_counter;
767 u8 rsvd48[8];
768 __be64 db_record_addr;
769 };
770
771 struct mlx5_create_cq_mbox_in {
772 struct mlx5_inbox_hdr hdr;
773 __be32 input_cqn;
774 u8 rsvdx[4];
775 struct mlx5_cq_context ctx;
776 u8 rsvd6[192];
777 __be64 pas[0];
778 };
779
780 struct mlx5_create_cq_mbox_out {
781 struct mlx5_outbox_hdr hdr;
782 __be32 cqn;
783 u8 rsvd0[4];
784 };
785
786 struct mlx5_destroy_cq_mbox_in {
787 struct mlx5_inbox_hdr hdr;
788 __be32 cqn;
789 u8 rsvd0[4];
790 };
791
792 struct mlx5_destroy_cq_mbox_out {
793 struct mlx5_outbox_hdr hdr;
794 u8 rsvd0[8];
795 };
796
797 struct mlx5_query_cq_mbox_in {
798 struct mlx5_inbox_hdr hdr;
799 __be32 cqn;
800 u8 rsvd0[4];
801 };
802
803 struct mlx5_query_cq_mbox_out {
804 struct mlx5_outbox_hdr hdr;
805 u8 rsvd0[8];
806 struct mlx5_cq_context ctx;
807 u8 rsvd6[16];
808 __be64 pas[0];
809 };
810
811 struct mlx5_modify_cq_mbox_in {
812 struct mlx5_inbox_hdr hdr;
813 __be32 cqn;
814 __be32 field_select;
815 struct mlx5_cq_context ctx;
816 u8 rsvd[192];
817 __be64 pas[0];
818 };
819
820 struct mlx5_modify_cq_mbox_out {
821 struct mlx5_outbox_hdr hdr;
822 u8 rsvd[8];
823 };
824
825 struct mlx5_enable_hca_mbox_in {
826 struct mlx5_inbox_hdr hdr;
827 u8 rsvd[8];
828 };
829
830 struct mlx5_enable_hca_mbox_out {
831 struct mlx5_outbox_hdr hdr;
832 u8 rsvd[8];
833 };
834
835 struct mlx5_disable_hca_mbox_in {
836 struct mlx5_inbox_hdr hdr;
837 u8 rsvd[8];
838 };
839
840 struct mlx5_disable_hca_mbox_out {
841 struct mlx5_outbox_hdr hdr;
842 u8 rsvd[8];
843 };
844
845 struct mlx5_eq_context {
846 u8 status;
847 u8 ec_oi;
848 u8 st;
849 u8 rsvd2[7];
850 __be16 page_pffset;
851 __be32 log_sz_usr_page;
852 u8 rsvd3[7];
853 u8 intr;
854 u8 log_page_size;
855 u8 rsvd4[15];
856 __be32 consumer_counter;
857 __be32 produser_counter;
858 u8 rsvd5[16];
859 };
860
861 struct mlx5_create_eq_mbox_in {
862 struct mlx5_inbox_hdr hdr;
863 u8 rsvd0[3];
864 u8 input_eqn;
865 u8 rsvd1[4];
866 struct mlx5_eq_context ctx;
867 u8 rsvd2[8];
868 __be64 events_mask;
869 u8 rsvd3[176];
870 __be64 pas[0];
871 };
872
873 struct mlx5_create_eq_mbox_out {
874 struct mlx5_outbox_hdr hdr;
875 u8 rsvd0[3];
876 u8 eq_number;
877 u8 rsvd1[4];
878 };
879
880 struct mlx5_destroy_eq_mbox_in {
881 struct mlx5_inbox_hdr hdr;
882 u8 rsvd0[3];
883 u8 eqn;
884 u8 rsvd1[4];
885 };
886
887 struct mlx5_destroy_eq_mbox_out {
888 struct mlx5_outbox_hdr hdr;
889 u8 rsvd[8];
890 };
891
892 struct mlx5_map_eq_mbox_in {
893 struct mlx5_inbox_hdr hdr;
894 __be64 mask;
895 u8 mu;
896 u8 rsvd0[2];
897 u8 eqn;
898 u8 rsvd1[24];
899 };
900
901 struct mlx5_map_eq_mbox_out {
902 struct mlx5_outbox_hdr hdr;
903 u8 rsvd[8];
904 };
905
906 struct mlx5_query_eq_mbox_in {
907 struct mlx5_inbox_hdr hdr;
908 u8 rsvd0[3];
909 u8 eqn;
910 u8 rsvd1[4];
911 };
912
913 struct mlx5_query_eq_mbox_out {
914 struct mlx5_outbox_hdr hdr;
915 u8 rsvd[8];
916 struct mlx5_eq_context ctx;
917 };
918
919 enum {
920 MLX5_MKEY_STATUS_FREE = 1 << 6,
921 };
922
923 struct mlx5_mkey_seg {
924 /* This is a two bit field occupying bits 31-30.
925 * bit 31 is always 0,
926 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
927 */
928 u8 status;
929 u8 pcie_control;
930 u8 flags;
931 u8 version;
932 __be32 qpn_mkey7_0;
933 u8 rsvd1[4];
934 __be32 flags_pd;
935 __be64 start_addr;
936 __be64 len;
937 __be32 bsfs_octo_size;
938 u8 rsvd2[16];
939 __be32 xlt_oct_size;
940 u8 rsvd3[3];
941 u8 log2_page_size;
942 u8 rsvd4[4];
943 };
944
945 struct mlx5_query_special_ctxs_mbox_in {
946 struct mlx5_inbox_hdr hdr;
947 u8 rsvd[8];
948 };
949
950 struct mlx5_query_special_ctxs_mbox_out {
951 struct mlx5_outbox_hdr hdr;
952 __be32 dump_fill_mkey;
953 __be32 reserved_lkey;
954 };
955
956 struct mlx5_create_mkey_mbox_in {
957 struct mlx5_inbox_hdr hdr;
958 __be32 input_mkey_index;
959 __be32 flags;
960 struct mlx5_mkey_seg seg;
961 u8 rsvd1[16];
962 __be32 xlat_oct_act_size;
963 __be32 rsvd2;
964 u8 rsvd3[168];
965 __be64 pas[0];
966 };
967
968 struct mlx5_create_mkey_mbox_out {
969 struct mlx5_outbox_hdr hdr;
970 __be32 mkey;
971 u8 rsvd[4];
972 };
973
974 struct mlx5_destroy_mkey_mbox_in {
975 struct mlx5_inbox_hdr hdr;
976 __be32 mkey;
977 u8 rsvd[4];
978 };
979
980 struct mlx5_destroy_mkey_mbox_out {
981 struct mlx5_outbox_hdr hdr;
982 u8 rsvd[8];
983 };
984
985 struct mlx5_query_mkey_mbox_in {
986 struct mlx5_inbox_hdr hdr;
987 __be32 mkey;
988 };
989
990 struct mlx5_query_mkey_mbox_out {
991 struct mlx5_outbox_hdr hdr;
992 __be64 pas[0];
993 };
994
995 struct mlx5_modify_mkey_mbox_in {
996 struct mlx5_inbox_hdr hdr;
997 __be32 mkey;
998 __be64 pas[0];
999 };
1000
1001 struct mlx5_modify_mkey_mbox_out {
1002 struct mlx5_outbox_hdr hdr;
1003 u8 rsvd[8];
1004 };
1005
1006 struct mlx5_dump_mkey_mbox_in {
1007 struct mlx5_inbox_hdr hdr;
1008 };
1009
1010 struct mlx5_dump_mkey_mbox_out {
1011 struct mlx5_outbox_hdr hdr;
1012 __be32 mkey;
1013 };
1014
1015 struct mlx5_mad_ifc_mbox_in {
1016 struct mlx5_inbox_hdr hdr;
1017 __be16 remote_lid;
1018 u8 rsvd0;
1019 u8 port;
1020 u8 rsvd1[4];
1021 u8 data[256];
1022 };
1023
1024 struct mlx5_mad_ifc_mbox_out {
1025 struct mlx5_outbox_hdr hdr;
1026 u8 rsvd[8];
1027 u8 data[256];
1028 };
1029
1030 struct mlx5_access_reg_mbox_in {
1031 struct mlx5_inbox_hdr hdr;
1032 u8 rsvd0[2];
1033 __be16 register_id;
1034 __be32 arg;
1035 __be32 data[0];
1036 };
1037
1038 struct mlx5_access_reg_mbox_out {
1039 struct mlx5_outbox_hdr hdr;
1040 u8 rsvd[8];
1041 __be32 data[0];
1042 };
1043
1044 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1045
1046 enum {
1047 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1048 };
1049
1050 struct mlx5_allocate_psv_in {
1051 struct mlx5_inbox_hdr hdr;
1052 __be32 npsv_pd;
1053 __be32 rsvd_psv0;
1054 };
1055
1056 struct mlx5_allocate_psv_out {
1057 struct mlx5_outbox_hdr hdr;
1058 u8 rsvd[8];
1059 __be32 psv_idx[4];
1060 };
1061
1062 struct mlx5_destroy_psv_in {
1063 struct mlx5_inbox_hdr hdr;
1064 __be32 psv_number;
1065 u8 rsvd[4];
1066 };
1067
1068 struct mlx5_destroy_psv_out {
1069 struct mlx5_outbox_hdr hdr;
1070 u8 rsvd[8];
1071 };
1072
1073 #define MLX5_CMD_OP_MAX 0x920
1074
1075 enum {
1076 VPORT_STATE_DOWN = 0x0,
1077 VPORT_STATE_UP = 0x1,
1078 };
1079
1080 enum {
1081 MLX5_L3_PROT_TYPE_IPV4 = 0,
1082 MLX5_L3_PROT_TYPE_IPV6 = 1,
1083 };
1084
1085 enum {
1086 MLX5_L4_PROT_TYPE_TCP = 0,
1087 MLX5_L4_PROT_TYPE_UDP = 1,
1088 };
1089
1090 enum {
1091 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1092 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1093 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1094 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1095 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1096 };
1097
1098 enum {
1099 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1100 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1101 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1102
1103 };
1104
1105 enum {
1106 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1107 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1108 };
1109
1110 enum {
1111 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1112 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1113 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1114 };
1115
1116 enum {
1117 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1118 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1119 };
1120
1121 /* MLX5 DEV CAPs */
1122
1123 /* TODO: EAT.ME */
1124 enum mlx5_cap_mode {
1125 HCA_CAP_OPMOD_GET_MAX = 0,
1126 HCA_CAP_OPMOD_GET_CUR = 1,
1127 };
1128
1129 enum mlx5_cap_type {
1130 MLX5_CAP_GENERAL = 0,
1131 MLX5_CAP_ETHERNET_OFFLOADS,
1132 MLX5_CAP_ODP,
1133 MLX5_CAP_ATOMIC,
1134 MLX5_CAP_ROCE,
1135 MLX5_CAP_IPOIB_OFFLOADS,
1136 MLX5_CAP_EOIB_OFFLOADS,
1137 MLX5_CAP_FLOW_TABLE,
1138 /* NUM OF CAP Types */
1139 MLX5_CAP_NUM
1140 };
1141
1142 /* GET Dev Caps macros */
1143 #define MLX5_CAP_GEN(mdev, cap) \
1144 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1145
1146 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1147 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1148
1149 #define MLX5_CAP_ETH(mdev, cap) \
1150 MLX5_GET(per_protocol_networking_offload_caps,\
1151 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1152
1153 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1154 MLX5_GET(per_protocol_networking_offload_caps,\
1155 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1156
1157 #define MLX5_CAP_ROCE(mdev, cap) \
1158 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1159
1160 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1161 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1162
1163 #define MLX5_CAP_ATOMIC(mdev, cap) \
1164 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1165
1166 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1167 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1168
1169 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1170 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1171
1172 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1173 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1174
1175 #define MLX5_CAP_ODP(mdev, cap)\
1176 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1177
1178 enum {
1179 MLX5_CMD_STAT_OK = 0x0,
1180 MLX5_CMD_STAT_INT_ERR = 0x1,
1181 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1182 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1183 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1184 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1185 MLX5_CMD_STAT_RES_BUSY = 0x6,
1186 MLX5_CMD_STAT_LIM_ERR = 0x8,
1187 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1188 MLX5_CMD_STAT_IX_ERR = 0xa,
1189 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1190 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1191 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1192 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1193 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1194 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1195 };
1196
1197 enum {
1198 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1199 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1200 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1201 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1202 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1203 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1204 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11
1205 };
1206
mlx5_to_sw_pkey_sz(int pkey_sz)1207 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1208 {
1209 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1210 return 0;
1211 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1212 }
1213
1214 #endif /* MLX5_DEVICE_H */
1215