1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
24 *
25 */
26
27 #include <drm/drmP.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_panel.h>
32 #include <linux/slab.h>
33 #include <video/mipi_display.h>
34 #include <asm/intel-mid.h>
35 #include <video/mipi_display.h>
36 #include "i915_drv.h"
37 #include "intel_drv.h"
38 #include "intel_dsi.h"
39
40 struct vbt_panel {
41 struct drm_panel panel;
42 struct intel_dsi *intel_dsi;
43 };
44
to_vbt_panel(struct drm_panel * panel)45 static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
46 {
47 return container_of(panel, struct vbt_panel, panel);
48 }
49
50 #define MIPI_TRANSFER_MODE_SHIFT 0
51 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
52 #define MIPI_PORT_SHIFT 3
53
54 #define PREPARE_CNT_MAX 0x3F
55 #define EXIT_ZERO_CNT_MAX 0x3F
56 #define CLK_ZERO_CNT_MAX 0xFF
57 #define TRAIL_CNT_MAX 0x1F
58
59 #define NS_KHZ_RATIO 1000000
60
61 #define GPI0_NC_0_HV_DDI0_HPD 0x4130
62 #define GPIO_NC_0_HV_DDI0_PAD 0x4138
63 #define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
64 #define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
65 #define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
66 #define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
67 #define GPIO_NC_3_PANEL0_VDDEN 0x4140
68 #define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
69 #define GPIO_NC_4_PANEL0_BLKEN 0x4150
70 #define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
71 #define GPIO_NC_5_PANEL0_BLKCTL 0x4160
72 #define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
73 #define GPIO_NC_6_PCONF0 0x4180
74 #define GPIO_NC_6_PAD 0x4188
75 #define GPIO_NC_7_PCONF0 0x4190
76 #define GPIO_NC_7_PAD 0x4198
77 #define GPIO_NC_8_PCONF0 0x4170
78 #define GPIO_NC_8_PAD 0x4178
79 #define GPIO_NC_9_PCONF0 0x4100
80 #define GPIO_NC_9_PAD 0x4108
81 #define GPIO_NC_10_PCONF0 0x40E0
82 #define GPIO_NC_10_PAD 0x40E8
83 #define GPIO_NC_11_PCONF0 0x40F0
84 #define GPIO_NC_11_PAD 0x40F8
85
86 struct gpio_table {
87 u16 function_reg;
88 u16 pad_reg;
89 u8 init;
90 };
91
92 static struct gpio_table gtable[] = {
93 { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
94 { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
95 { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
96 { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
97 { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
98 { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
99 { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
100 { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
101 { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
102 { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
103 { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
104 { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
105 };
106
intel_dsi_seq_port_to_port(u8 port)107 static inline enum port intel_dsi_seq_port_to_port(u8 port)
108 {
109 return port ? PORT_C : PORT_A;
110 }
111
mipi_exec_send_packet(struct intel_dsi * intel_dsi,const u8 * data)112 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
113 const u8 *data)
114 {
115 struct mipi_dsi_device *dsi_device;
116 u8 type, flags, seq_port;
117 u16 len;
118 enum port port;
119
120 flags = *data++;
121 type = *data++;
122
123 len = *((u16 *) data);
124 data += 2;
125
126 seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
127
128 /* For DSI single link on Port A & C, the seq_port value which is
129 * parsed from Sequence Block#53 of VBT has been set to 0
130 * Now, read/write of packets for the DSI single link on Port A and
131 * Port C will based on the DVO port from VBT block 2.
132 */
133 if (intel_dsi->ports == (1 << PORT_C))
134 port = PORT_C;
135 else
136 port = intel_dsi_seq_port_to_port(seq_port);
137
138 dsi_device = intel_dsi->dsi_hosts[port]->device;
139 if (!dsi_device) {
140 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
141 goto out;
142 }
143
144 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
145 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
146 else
147 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
148
149 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
150
151 switch (type) {
152 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
153 mipi_dsi_generic_write(dsi_device, NULL, 0);
154 break;
155 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
156 mipi_dsi_generic_write(dsi_device, data, 1);
157 break;
158 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
159 mipi_dsi_generic_write(dsi_device, data, 2);
160 break;
161 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
162 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
163 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
164 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
165 break;
166 case MIPI_DSI_GENERIC_LONG_WRITE:
167 mipi_dsi_generic_write(dsi_device, data, len);
168 break;
169 case MIPI_DSI_DCS_SHORT_WRITE:
170 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
171 break;
172 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
173 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
174 break;
175 case MIPI_DSI_DCS_READ:
176 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
177 break;
178 case MIPI_DSI_DCS_LONG_WRITE:
179 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
180 break;
181 }
182
183 out:
184 data += len;
185
186 return data;
187 }
188
mipi_exec_delay(struct intel_dsi * intel_dsi,const u8 * data)189 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
190 {
191 u32 delay = *((const u32 *) data);
192
193 usleep_range(delay, delay + 10);
194 data += 4;
195
196 return data;
197 }
198
mipi_exec_gpio(struct intel_dsi * intel_dsi,const u8 * data)199 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
200 {
201 u8 gpio, action;
202 u16 function, pad;
203 u32 val;
204 struct drm_device *dev = intel_dsi->base.base.dev;
205 struct drm_i915_private *dev_priv = dev->dev_private;
206
207 gpio = *data++;
208
209 /* pull up/down */
210 action = *data++ & 1;
211
212 if (gpio >= ARRAY_SIZE(gtable)) {
213 DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
214 goto out;
215 }
216
217 function = gtable[gpio].function_reg;
218 pad = gtable[gpio].pad_reg;
219
220 mutex_lock(&dev_priv->sb_lock);
221 if (!gtable[gpio].init) {
222 /* program the function */
223 /* FIXME: remove constant below */
224 vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
225 gtable[gpio].init = 1;
226 }
227
228 val = 0x4 | action;
229
230 /* pull up/down */
231 vlv_gpio_nc_write(dev_priv, pad, val);
232 mutex_unlock(&dev_priv->sb_lock);
233
234 out:
235 return data;
236 }
237
238 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
239 const u8 *data);
240 static const fn_mipi_elem_exec exec_elem[] = {
241 NULL, /* reserved */
242 mipi_exec_send_packet,
243 mipi_exec_delay,
244 mipi_exec_gpio,
245 NULL, /* status read; later */
246 };
247
248 /*
249 * MIPI Sequence from VBT #53 parsing logic
250 * We have already separated each seqence during bios parsing
251 * Following is generic execution function for any sequence
252 */
253
254 static const char * const seq_name[] = {
255 "UNDEFINED",
256 "MIPI_SEQ_ASSERT_RESET",
257 "MIPI_SEQ_INIT_OTP",
258 "MIPI_SEQ_DISPLAY_ON",
259 "MIPI_SEQ_DISPLAY_OFF",
260 "MIPI_SEQ_DEASSERT_RESET"
261 };
262
generic_exec_sequence(struct intel_dsi * intel_dsi,const u8 * data)263 static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data)
264 {
265 fn_mipi_elem_exec mipi_elem_exec;
266 int index;
267
268 if (!data)
269 return;
270
271 DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]);
272
273 /* go to the first element of the sequence */
274 data++;
275
276 /* parse each byte till we reach end of sequence byte - 0x00 */
277 while (1) {
278 index = *data;
279 mipi_elem_exec = exec_elem[index];
280 if (!mipi_elem_exec) {
281 DRM_ERROR("Unsupported MIPI element, skipping sequence execution\n");
282 return;
283 }
284
285 /* goto element payload */
286 data++;
287
288 /* execute the element specific rotines */
289 data = mipi_elem_exec(intel_dsi, data);
290
291 /*
292 * After processing the element, data should point to
293 * next element or end of sequence
294 * check if have we reached end of sequence
295 */
296 if (*data == 0x00)
297 break;
298 }
299 }
300
vbt_panel_prepare(struct drm_panel * panel)301 static int vbt_panel_prepare(struct drm_panel *panel)
302 {
303 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
304 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
305 struct drm_device *dev = intel_dsi->base.base.dev;
306 struct drm_i915_private *dev_priv = dev->dev_private;
307 const u8 *sequence;
308
309 sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET];
310 generic_exec_sequence(intel_dsi, sequence);
311
312 sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
313 generic_exec_sequence(intel_dsi, sequence);
314
315 return 0;
316 }
317
vbt_panel_unprepare(struct drm_panel * panel)318 static int vbt_panel_unprepare(struct drm_panel *panel)
319 {
320 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
321 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
322 struct drm_device *dev = intel_dsi->base.base.dev;
323 struct drm_i915_private *dev_priv = dev->dev_private;
324 const u8 *sequence;
325
326 sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET];
327 generic_exec_sequence(intel_dsi, sequence);
328
329 return 0;
330 }
331
vbt_panel_enable(struct drm_panel * panel)332 static int vbt_panel_enable(struct drm_panel *panel)
333 {
334 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
335 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
336 struct drm_device *dev = intel_dsi->base.base.dev;
337 struct drm_i915_private *dev_priv = dev->dev_private;
338 const u8 *sequence;
339
340 sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON];
341 generic_exec_sequence(intel_dsi, sequence);
342
343 return 0;
344 }
345
vbt_panel_disable(struct drm_panel * panel)346 static int vbt_panel_disable(struct drm_panel *panel)
347 {
348 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
349 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
350 struct drm_device *dev = intel_dsi->base.base.dev;
351 struct drm_i915_private *dev_priv = dev->dev_private;
352 const u8 *sequence;
353
354 sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF];
355 generic_exec_sequence(intel_dsi, sequence);
356
357 return 0;
358 }
359
vbt_panel_get_modes(struct drm_panel * panel)360 static int vbt_panel_get_modes(struct drm_panel *panel)
361 {
362 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
363 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
364 struct drm_device *dev = intel_dsi->base.base.dev;
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 struct drm_display_mode *mode;
367
368 if (!panel->connector)
369 return 0;
370
371 mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
372 if (!mode)
373 return 0;
374
375 mode->type |= DRM_MODE_TYPE_PREFERRED;
376
377 drm_mode_probed_add(panel->connector, mode);
378
379 return 1;
380 }
381
382 static const struct drm_panel_funcs vbt_panel_funcs = {
383 .disable = vbt_panel_disable,
384 .unprepare = vbt_panel_unprepare,
385 .prepare = vbt_panel_prepare,
386 .enable = vbt_panel_enable,
387 .get_modes = vbt_panel_get_modes,
388 };
389
vbt_panel_init(struct intel_dsi * intel_dsi,u16 panel_id)390 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
391 {
392 struct drm_device *dev = intel_dsi->base.base.dev;
393 struct drm_i915_private *dev_priv = dev->dev_private;
394 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
395 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
396 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
397 struct vbt_panel *vbt_panel;
398 u32 bits_per_pixel = 24;
399 u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
400 u32 ui_num, ui_den;
401 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
402 u32 ths_prepare_ns, tclk_trail_ns;
403 u32 tclk_prepare_clkzero, ths_prepare_hszero;
404 u32 lp_to_hs_switch, hs_to_lp_switch;
405 u32 pclk, computed_ddr;
406 u16 burst_mode_ratio;
407 enum port port;
408
409 DRM_DEBUG_KMS("\n");
410
411 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
412 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
413 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
414 intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
415 intel_dsi->dual_link = mipi_config->dual_link;
416 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
417
418 if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
419 bits_per_pixel = 18;
420 else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
421 bits_per_pixel = 16;
422
423 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
424 intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
425 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
426 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
427 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
428 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
429 intel_dsi->init_count = mipi_config->master_init_timer;
430 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
431 intel_dsi->video_frmt_cfg_bits =
432 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
433
434 pclk = mode->clock;
435
436 /* In dual link mode each port needs half of pixel clock */
437 if (intel_dsi->dual_link) {
438 pclk = pclk / 2;
439
440 /* we can enable pixel_overlap if needed by panel. In this
441 * case we need to increase the pixelclock for extra pixels
442 */
443 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
444 pclk += DIV_ROUND_UP(mode->vtotal *
445 intel_dsi->pixel_overlap *
446 60, 1000);
447 }
448 }
449
450 /* Burst Mode Ratio
451 * Target ddr frequency from VBT / non burst ddr freq
452 * multiply by 100 to preserve remainder
453 */
454 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
455 if (mipi_config->target_burst_mode_freq) {
456 computed_ddr =
457 (pclk * bits_per_pixel) / intel_dsi->lane_count;
458
459 if (mipi_config->target_burst_mode_freq <
460 computed_ddr) {
461 DRM_ERROR("Burst mode freq is less than computed\n");
462 return NULL;
463 }
464
465 burst_mode_ratio = DIV_ROUND_UP(
466 mipi_config->target_burst_mode_freq * 100,
467 computed_ddr);
468
469 pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
470 } else {
471 DRM_ERROR("Burst mode target is not set\n");
472 return NULL;
473 }
474 } else
475 burst_mode_ratio = 100;
476
477 intel_dsi->burst_mode_ratio = burst_mode_ratio;
478 intel_dsi->pclk = pclk;
479
480 bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count;
481
482 switch (intel_dsi->escape_clk_div) {
483 case 0:
484 tlpx_ns = 50;
485 break;
486 case 1:
487 tlpx_ns = 100;
488 break;
489
490 case 2:
491 tlpx_ns = 200;
492 break;
493 default:
494 tlpx_ns = 50;
495 break;
496 }
497
498 switch (intel_dsi->lane_count) {
499 case 1:
500 case 2:
501 extra_byte_count = 2;
502 break;
503 case 3:
504 extra_byte_count = 4;
505 break;
506 case 4:
507 default:
508 extra_byte_count = 3;
509 break;
510 }
511
512 /*
513 * ui(s) = 1/f [f in hz]
514 * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
515 */
516
517 /* in Kbps */
518 ui_num = NS_KHZ_RATIO;
519 ui_den = bitrate;
520
521 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
522 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
523
524 /*
525 * B060
526 * LP byte clock = TLPX/ (8UI)
527 */
528 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
529
530 /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
531 *
532 * Since txddrclkhs_i is 2xUI, all the count values programmed in
533 * DPHY param register are divided by 2
534 *
535 * prepare count
536 */
537 ths_prepare_ns = max(mipi_config->ths_prepare,
538 mipi_config->tclk_prepare);
539 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
540
541 /* exit zero count */
542 exit_zero_cnt = DIV_ROUND_UP(
543 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
544 ui_num * 2
545 );
546
547 /*
548 * Exit zero is unified val ths_zero and ths_exit
549 * minimum value for ths_exit = 110ns
550 * min (exit_zero_cnt * 2) = 110/UI
551 * exit_zero_cnt = 55/UI
552 */
553 if (exit_zero_cnt < (55 * ui_den / ui_num))
554 if ((55 * ui_den) % ui_num)
555 exit_zero_cnt += 1;
556
557 /* clk zero count */
558 clk_zero_cnt = DIV_ROUND_UP(
559 (tclk_prepare_clkzero - ths_prepare_ns)
560 * ui_den, 2 * ui_num);
561
562 /* trail count */
563 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
564 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
565
566 if (prepare_cnt > PREPARE_CNT_MAX ||
567 exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
568 clk_zero_cnt > CLK_ZERO_CNT_MAX ||
569 trail_cnt > TRAIL_CNT_MAX)
570 DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
571
572 if (prepare_cnt > PREPARE_CNT_MAX)
573 prepare_cnt = PREPARE_CNT_MAX;
574
575 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
576 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
577
578 if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
579 clk_zero_cnt = CLK_ZERO_CNT_MAX;
580
581 if (trail_cnt > TRAIL_CNT_MAX)
582 trail_cnt = TRAIL_CNT_MAX;
583
584 /* B080 */
585 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
586 clk_zero_cnt << 8 | prepare_cnt;
587
588 /*
589 * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
590 * + 10UI + Extra Byte Count
591 *
592 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
593 * Extra Byte Count is calculated according to number of lanes.
594 * High Low Switch Count is the Max of LP to HS and
595 * HS to LP switch count
596 *
597 */
598 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
599
600 /* B044 */
601 /* FIXME:
602 * The comment above does not match with the code */
603 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
604 exit_zero_cnt * 2 + 10, 8);
605
606 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
607
608 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
609 intel_dsi->hs_to_lp_count += extra_byte_count;
610
611 /* B088 */
612 /* LP -> HS for clock lanes
613 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
614 * extra byte count
615 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
616 * 2(in UI) + extra byte count
617 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
618 * 8 + extra byte count
619 */
620 intel_dsi->clk_lp_to_hs_count =
621 DIV_ROUND_UP(
622 4 * tlpx_ui + prepare_cnt * 2 +
623 clk_zero_cnt * 2,
624 8);
625
626 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
627
628 /* HS->LP for Clock Lanes
629 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
630 * Extra byte count
631 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
632 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
633 * Extra byte count
634 */
635 intel_dsi->clk_hs_to_lp_count =
636 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
637 8);
638 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
639
640 DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled");
641 DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
642 "disabled" : "enabled");
643 DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
644 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
645 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
646 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
647 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
648 else
649 DRM_DEBUG_KMS("Dual link: NONE\n");
650 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
651 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
652 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
653 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
654 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
655 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
656 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
657 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
658 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
659 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
660 DRM_DEBUG_KMS("BTA %s\n",
661 intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ?
662 "disabled" : "enabled");
663
664 /* delays in VBT are in unit of 100us, so need to convert
665 * here in ms
666 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
667 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
668 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
669 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
670 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
671 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
672
673 /* This is cheating a bit with the cleanup. */
674 vbt_panel = devm_kzalloc(dev->dev, sizeof(*vbt_panel), GFP_KERNEL);
675
676 vbt_panel->intel_dsi = intel_dsi;
677 drm_panel_init(&vbt_panel->panel);
678 vbt_panel->panel.funcs = &vbt_panel_funcs;
679 drm_panel_add(&vbt_panel->panel);
680
681 /* a regular driver would get the device in probe */
682 for_each_dsi_port(port, intel_dsi->ports) {
683 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
684 }
685
686 return &vbt_panel->panel;
687 }
688