1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "nv50.h"
25
26 #include <nvif/class.h>
27
28 /*******************************************************************************
29 * EVO overlay channel objects
30 ******************************************************************************/
31
32 static const struct nv50_disp_mthd_list
33 gt200_disp_ovly_mthd_base = {
34 .mthd = 0x0000,
35 .addr = 0x000000,
36 .data = {
37 { 0x0080, 0x000000 },
38 { 0x0084, 0x6109a0 },
39 { 0x0088, 0x6109c0 },
40 { 0x008c, 0x6109c8 },
41 { 0x0090, 0x6109b4 },
42 { 0x0094, 0x610970 },
43 { 0x00a0, 0x610998 },
44 { 0x00a4, 0x610964 },
45 { 0x00b0, 0x610c98 },
46 { 0x00b4, 0x610ca4 },
47 { 0x00b8, 0x610cac },
48 { 0x00c0, 0x610958 },
49 { 0x00e0, 0x6109a8 },
50 { 0x00e4, 0x6109d0 },
51 { 0x00e8, 0x6109d8 },
52 { 0x0100, 0x61094c },
53 { 0x0104, 0x610984 },
54 { 0x0108, 0x61098c },
55 { 0x0800, 0x6109f8 },
56 { 0x0808, 0x610a08 },
57 { 0x080c, 0x610a10 },
58 { 0x0810, 0x610a00 },
59 {}
60 }
61 };
62
63 static const struct nv50_disp_mthd_chan
64 gt200_disp_ovly_mthd_chan = {
65 .name = "Overlay",
66 .addr = 0x000540,
67 .data = {
68 { "Global", 1, >200_disp_ovly_mthd_base },
69 {}
70 }
71 };
72
73 /*******************************************************************************
74 * Base display object
75 ******************************************************************************/
76
77 static struct nvkm_oclass
78 gt200_disp_sclass[] = {
79 { GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
80 { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
81 { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
82 { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
83 { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
84 {}
85 };
86
87 static struct nvkm_oclass
88 gt200_disp_main_oclass[] = {
89 { GT200_DISP, &nv50_disp_main_ofuncs },
90 {}
91 };
92
93 /*******************************************************************************
94 * Display engine implementation
95 ******************************************************************************/
96
97 static int
gt200_disp_ctor(struct nvkm_object * parent,struct nvkm_object * engine,struct nvkm_oclass * oclass,void * data,u32 size,struct nvkm_object ** pobject)98 gt200_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
99 struct nvkm_oclass *oclass, void *data, u32 size,
100 struct nvkm_object **pobject)
101 {
102 struct nv50_disp_priv *priv;
103 int ret;
104
105 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
106 "display", &priv);
107 *pobject = nv_object(priv);
108 if (ret)
109 return ret;
110
111 ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
112 if (ret)
113 return ret;
114
115 nv_engine(priv)->sclass = gt200_disp_main_oclass;
116 nv_engine(priv)->cclass = &nv50_disp_cclass;
117 nv_subdev(priv)->intr = nv50_disp_intr;
118 INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
119 priv->sclass = gt200_disp_sclass;
120 priv->head.nr = 2;
121 priv->dac.nr = 3;
122 priv->sor.nr = 2;
123 priv->pior.nr = 3;
124 priv->dac.power = nv50_dac_power;
125 priv->dac.sense = nv50_dac_sense;
126 priv->sor.power = nv50_sor_power;
127 priv->sor.hdmi = g84_hdmi_ctrl;
128 priv->pior.power = nv50_pior_power;
129 return 0;
130 }
131
132 struct nvkm_oclass *
133 gt200_disp_oclass = &(struct nv50_disp_impl) {
134 .base.base.handle = NV_ENGINE(DISP, 0x83),
135 .base.base.ofuncs = &(struct nvkm_ofuncs) {
136 .ctor = gt200_disp_ctor,
137 .dtor = _nvkm_disp_dtor,
138 .init = _nvkm_disp_init,
139 .fini = _nvkm_disp_fini,
140 },
141 .base.vblank = &nv50_disp_vblank_func,
142 .base.outp = nv50_disp_outp_sclass,
143 .mthd.core = &g84_disp_core_mthd_chan,
144 .mthd.base = &g84_disp_base_mthd_chan,
145 .mthd.ovly = >200_disp_ovly_mthd_chan,
146 .mthd.prev = 0x000004,
147 .head.scanoutpos = nv50_disp_main_scanoutpos,
148 }.base.base;
149