1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include "drmP.h"
25 #include "amdgpu.h"
26 #include "cikd.h"
27 #include "cik.h"
28 #include "gmc_v7_0.h"
29 #include "amdgpu_ucode.h"
30
31 #include "bif/bif_4_1_d.h"
32 #include "bif/bif_4_1_sh_mask.h"
33
34 #include "gmc/gmc_7_1_d.h"
35 #include "gmc/gmc_7_1_sh_mask.h"
36
37 #include "oss/oss_2_0_d.h"
38 #include "oss/oss_2_0_sh_mask.h"
39
40 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
41 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
42
43 MODULE_FIRMWARE("radeon/bonaire_mc.bin");
44 MODULE_FIRMWARE("radeon/hawaii_mc.bin");
45 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
46
47 static const u32 golden_settings_iceland_a11[] =
48 {
49 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
50 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
51 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
52 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
53 };
54
55 static const u32 iceland_mgcg_cgcg_init[] =
56 {
57 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
58 };
59
gmc_v7_0_init_golden_registers(struct amdgpu_device * adev)60 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
61 {
62 switch (adev->asic_type) {
63 case CHIP_TOPAZ:
64 amdgpu_program_register_sequence(adev,
65 iceland_mgcg_cgcg_init,
66 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
67 amdgpu_program_register_sequence(adev,
68 golden_settings_iceland_a11,
69 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
70 break;
71 default:
72 break;
73 }
74 }
75
76 /**
77 * gmc7_mc_wait_for_idle - wait for MC idle callback.
78 *
79 * @adev: amdgpu_device pointer
80 *
81 * Wait for the MC (memory controller) to be idle.
82 * (evergreen+).
83 * Returns 0 if the MC is idle, -1 if not.
84 */
gmc_v7_0_mc_wait_for_idle(struct amdgpu_device * adev)85 int gmc_v7_0_mc_wait_for_idle(struct amdgpu_device *adev)
86 {
87 unsigned i;
88 u32 tmp;
89
90 for (i = 0; i < adev->usec_timeout; i++) {
91 /* read MC_STATUS */
92 tmp = RREG32(mmSRBM_STATUS) & 0x1F00;
93 if (!tmp)
94 return 0;
95 udelay(1);
96 }
97 return -1;
98 }
99
gmc_v7_0_mc_stop(struct amdgpu_device * adev,struct amdgpu_mode_mc_save * save)100 void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
101 struct amdgpu_mode_mc_save *save)
102 {
103 u32 blackout;
104
105 if (adev->mode_info.num_crtc)
106 amdgpu_display_stop_mc_access(adev, save);
107
108 amdgpu_asic_wait_for_mc_idle(adev);
109
110 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
111 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
112 /* Block CPU access */
113 WREG32(mmBIF_FB_EN, 0);
114 /* blackout the MC */
115 blackout = REG_SET_FIELD(blackout,
116 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
117 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
118 }
119 /* wait for the MC to settle */
120 udelay(100);
121 }
122
gmc_v7_0_mc_resume(struct amdgpu_device * adev,struct amdgpu_mode_mc_save * save)123 void gmc_v7_0_mc_resume(struct amdgpu_device *adev,
124 struct amdgpu_mode_mc_save *save)
125 {
126 u32 tmp;
127
128 /* unblackout the MC */
129 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
130 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
131 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
132 /* allow CPU access */
133 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
134 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
135 WREG32(mmBIF_FB_EN, tmp);
136
137 if (adev->mode_info.num_crtc)
138 amdgpu_display_resume_mc_access(adev, save);
139 }
140
141 /**
142 * gmc_v7_0_init_microcode - load ucode images from disk
143 *
144 * @adev: amdgpu_device pointer
145 *
146 * Use the firmware interface to load the ucode images into
147 * the driver (not loaded into hw).
148 * Returns 0 on success, error on failure.
149 */
gmc_v7_0_init_microcode(struct amdgpu_device * adev)150 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
151 {
152 const char *chip_name;
153 char fw_name[30];
154 int err;
155
156 DRM_DEBUG("\n");
157
158 switch (adev->asic_type) {
159 case CHIP_BONAIRE:
160 chip_name = "bonaire";
161 break;
162 case CHIP_HAWAII:
163 chip_name = "hawaii";
164 break;
165 case CHIP_TOPAZ:
166 chip_name = "topaz";
167 break;
168 case CHIP_KAVERI:
169 case CHIP_KABINI:
170 return 0;
171 default: BUG();
172 }
173
174 if (adev->asic_type == CHIP_TOPAZ)
175 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
176 else
177 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
178
179 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
180 if (err)
181 goto out;
182 err = amdgpu_ucode_validate(adev->mc.fw);
183
184 out:
185 if (err) {
186 printk(KERN_ERR
187 "cik_mc: Failed to load firmware \"%s\"\n",
188 fw_name);
189 release_firmware(adev->mc.fw);
190 adev->mc.fw = NULL;
191 }
192 return err;
193 }
194
195 /**
196 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
197 *
198 * @adev: amdgpu_device pointer
199 *
200 * Load the GDDR MC ucode into the hw (CIK).
201 * Returns 0 on success, error on failure.
202 */
gmc_v7_0_mc_load_microcode(struct amdgpu_device * adev)203 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
204 {
205 const struct mc_firmware_header_v1_0 *hdr;
206 const __le32 *fw_data = NULL;
207 const __le32 *io_mc_regs = NULL;
208 u32 running, blackout = 0;
209 int i, ucode_size, regs_size;
210
211 if (!adev->mc.fw)
212 return -EINVAL;
213
214 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
215 amdgpu_ucode_print_mc_hdr(&hdr->header);
216
217 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
218 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
219 io_mc_regs = (const __le32 *)
220 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
221 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
222 fw_data = (const __le32 *)
223 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
224
225 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
226
227 if (running == 0) {
228 if (running) {
229 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
230 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
231 }
232
233 /* reset the engine and set to writable */
234 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
235 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
236
237 /* load mc io regs */
238 for (i = 0; i < regs_size; i++) {
239 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
240 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
241 }
242 /* load the MC ucode */
243 for (i = 0; i < ucode_size; i++)
244 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
245
246 /* put the engine back into the active state */
247 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
248 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
249 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
250
251 /* wait for training to complete */
252 for (i = 0; i < adev->usec_timeout; i++) {
253 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
254 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
255 break;
256 udelay(1);
257 }
258 for (i = 0; i < adev->usec_timeout; i++) {
259 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
260 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
261 break;
262 udelay(1);
263 }
264
265 if (running)
266 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
267 }
268
269 return 0;
270 }
271
gmc_v7_0_vram_gtt_location(struct amdgpu_device * adev,struct amdgpu_mc * mc)272 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
273 struct amdgpu_mc *mc)
274 {
275 if (mc->mc_vram_size > 0xFFC0000000ULL) {
276 /* leave room for at least 1024M GTT */
277 dev_warn(adev->dev, "limiting VRAM\n");
278 mc->real_vram_size = 0xFFC0000000ULL;
279 mc->mc_vram_size = 0xFFC0000000ULL;
280 }
281 amdgpu_vram_location(adev, &adev->mc, 0);
282 adev->mc.gtt_base_align = 0;
283 amdgpu_gtt_location(adev, mc);
284 }
285
286 /**
287 * gmc_v7_0_mc_program - program the GPU memory controller
288 *
289 * @adev: amdgpu_device pointer
290 *
291 * Set the location of vram, gart, and AGP in the GPU's
292 * physical address space (CIK).
293 */
gmc_v7_0_mc_program(struct amdgpu_device * adev)294 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
295 {
296 struct amdgpu_mode_mc_save save;
297 u32 tmp;
298 int i, j;
299
300 /* Initialize HDP */
301 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
302 WREG32((0xb05 + j), 0x00000000);
303 WREG32((0xb06 + j), 0x00000000);
304 WREG32((0xb07 + j), 0x00000000);
305 WREG32((0xb08 + j), 0x00000000);
306 WREG32((0xb09 + j), 0x00000000);
307 }
308 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
309
310 if (adev->mode_info.num_crtc)
311 amdgpu_display_set_vga_render_state(adev, false);
312
313 gmc_v7_0_mc_stop(adev, &save);
314 if (amdgpu_asic_wait_for_mc_idle(adev)) {
315 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
316 }
317 /* Update configuration */
318 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
319 adev->mc.vram_start >> 12);
320 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
321 adev->mc.vram_end >> 12);
322 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
323 adev->vram_scratch.gpu_addr >> 12);
324 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
325 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
326 WREG32(mmMC_VM_FB_LOCATION, tmp);
327 /* XXX double check these! */
328 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
329 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
330 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
331 WREG32(mmMC_VM_AGP_BASE, 0);
332 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
333 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
334 if (amdgpu_asic_wait_for_mc_idle(adev)) {
335 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
336 }
337 gmc_v7_0_mc_resume(adev, &save);
338
339 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
340
341 tmp = RREG32(mmHDP_MISC_CNTL);
342 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
343 WREG32(mmHDP_MISC_CNTL, tmp);
344
345 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
346 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
347 }
348
349 /**
350 * gmc_v7_0_mc_init - initialize the memory controller driver params
351 *
352 * @adev: amdgpu_device pointer
353 *
354 * Look up the amount of vram, vram width, and decide how to place
355 * vram and gart within the GPU's physical address space (CIK).
356 * Returns 0 for success.
357 */
gmc_v7_0_mc_init(struct amdgpu_device * adev)358 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
359 {
360 u32 tmp;
361 int chansize, numchan;
362
363 /* Get VRAM informations */
364 tmp = RREG32(mmMC_ARB_RAMCFG);
365 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
366 chansize = 64;
367 } else {
368 chansize = 32;
369 }
370 tmp = RREG32(mmMC_SHARED_CHMAP);
371 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
372 case 0:
373 default:
374 numchan = 1;
375 break;
376 case 1:
377 numchan = 2;
378 break;
379 case 2:
380 numchan = 4;
381 break;
382 case 3:
383 numchan = 8;
384 break;
385 case 4:
386 numchan = 3;
387 break;
388 case 5:
389 numchan = 6;
390 break;
391 case 6:
392 numchan = 10;
393 break;
394 case 7:
395 numchan = 12;
396 break;
397 case 8:
398 numchan = 16;
399 break;
400 }
401 adev->mc.vram_width = numchan * chansize;
402 /* Could aper size report 0 ? */
403 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
404 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
405 /* size in MB on si */
406 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
407 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
408 adev->mc.visible_vram_size = adev->mc.aper_size;
409
410 /* unless the user had overridden it, set the gart
411 * size equal to the 1024 or vram, whichever is larger.
412 */
413 if (amdgpu_gart_size == -1)
414 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
415 else
416 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
417
418 gmc_v7_0_vram_gtt_location(adev, &adev->mc);
419
420 return 0;
421 }
422
423 /*
424 * GART
425 * VMID 0 is the physical GPU addresses as used by the kernel.
426 * VMIDs 1-15 are used for userspace clients and are handled
427 * by the amdgpu vm/hsa code.
428 */
429
430 /**
431 * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
432 *
433 * @adev: amdgpu_device pointer
434 * @vmid: vm instance to flush
435 *
436 * Flush the TLB for the requested page table (CIK).
437 */
gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device * adev,uint32_t vmid)438 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
439 uint32_t vmid)
440 {
441 /* flush hdp cache */
442 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
443
444 /* bits 0-15 are the VM contexts0-15 */
445 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
446 }
447
448 /**
449 * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
450 *
451 * @adev: amdgpu_device pointer
452 * @cpu_pt_addr: cpu address of the page table
453 * @gpu_page_idx: entry in the page table to update
454 * @addr: dst addr to write into pte/pde
455 * @flags: access flags
456 *
457 * Update the page tables using the CPU.
458 */
gmc_v7_0_gart_set_pte_pde(struct amdgpu_device * adev,void * cpu_pt_addr,uint32_t gpu_page_idx,uint64_t addr,uint32_t flags)459 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
460 void *cpu_pt_addr,
461 uint32_t gpu_page_idx,
462 uint64_t addr,
463 uint32_t flags)
464 {
465 void __iomem *ptr = (void *)cpu_pt_addr;
466 uint64_t value;
467
468 value = addr & 0xFFFFFFFFFFFFF000ULL;
469 value |= flags;
470 writeq(value, ptr + (gpu_page_idx * 8));
471
472 return 0;
473 }
474
475 /**
476 * gmc_v8_0_set_fault_enable_default - update VM fault handling
477 *
478 * @adev: amdgpu_device pointer
479 * @value: true redirects VM faults to the default page
480 */
gmc_v7_0_set_fault_enable_default(struct amdgpu_device * adev,bool value)481 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
482 bool value)
483 {
484 u32 tmp;
485
486 tmp = RREG32(mmVM_CONTEXT1_CNTL);
487 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
488 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
489 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
490 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
491 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
492 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
493 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
494 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
495 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
496 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
497 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
498 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
499 WREG32(mmVM_CONTEXT1_CNTL, tmp);
500 }
501
502 /**
503 * gmc_v7_0_gart_enable - gart enable
504 *
505 * @adev: amdgpu_device pointer
506 *
507 * This sets up the TLBs, programs the page tables for VMID0,
508 * sets up the hw for VMIDs 1-15 which are allocated on
509 * demand, and sets up the global locations for the LDS, GDS,
510 * and GPUVM for FSA64 clients (CIK).
511 * Returns 0 for success, errors for failure.
512 */
gmc_v7_0_gart_enable(struct amdgpu_device * adev)513 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
514 {
515 int r, i;
516 u32 tmp;
517
518 if (adev->gart.robj == NULL) {
519 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
520 return -EINVAL;
521 }
522 r = amdgpu_gart_table_vram_pin(adev);
523 if (r)
524 return r;
525 /* Setup TLB control */
526 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
527 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
528 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
529 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
530 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
531 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
532 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
533 /* Setup L2 cache */
534 tmp = RREG32(mmVM_L2_CNTL);
535 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
536 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
537 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
538 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
539 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
540 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
541 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
542 WREG32(mmVM_L2_CNTL, tmp);
543 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
544 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
545 WREG32(mmVM_L2_CNTL2, tmp);
546 tmp = RREG32(mmVM_L2_CNTL3);
547 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
548 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
549 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
550 WREG32(mmVM_L2_CNTL3, tmp);
551 /* setup context0 */
552 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
553 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
554 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
555 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
556 (u32)(adev->dummy_page.addr >> 12));
557 WREG32(mmVM_CONTEXT0_CNTL2, 0);
558 tmp = RREG32(mmVM_CONTEXT0_CNTL);
559 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
560 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
561 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
562 WREG32(mmVM_CONTEXT0_CNTL, tmp);
563
564 WREG32(0x575, 0);
565 WREG32(0x576, 0);
566 WREG32(0x577, 0);
567
568 /* empty context1-15 */
569 /* FIXME start with 4G, once using 2 level pt switch to full
570 * vm size space
571 */
572 /* set vm size, must be a multiple of 4 */
573 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
574 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
575 for (i = 1; i < 16; i++) {
576 if (i < 8)
577 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
578 adev->gart.table_addr >> 12);
579 else
580 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
581 adev->gart.table_addr >> 12);
582 }
583
584 /* enable context1-15 */
585 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
586 (u32)(adev->dummy_page.addr >> 12));
587 WREG32(mmVM_CONTEXT1_CNTL2, 4);
588 tmp = RREG32(mmVM_CONTEXT1_CNTL);
589 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
590 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
591 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
592 amdgpu_vm_block_size - 9);
593 WREG32(mmVM_CONTEXT1_CNTL, tmp);
594 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
595 gmc_v7_0_set_fault_enable_default(adev, false);
596 else
597 gmc_v7_0_set_fault_enable_default(adev, true);
598
599 if (adev->asic_type == CHIP_KAVERI) {
600 tmp = RREG32(mmCHUB_CONTROL);
601 tmp &= ~BYPASS_VM;
602 WREG32(mmCHUB_CONTROL, tmp);
603 }
604
605 gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
606 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
607 (unsigned)(adev->mc.gtt_size >> 20),
608 (unsigned long long)adev->gart.table_addr);
609 adev->gart.ready = true;
610 return 0;
611 }
612
gmc_v7_0_gart_init(struct amdgpu_device * adev)613 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
614 {
615 int r;
616
617 if (adev->gart.robj) {
618 WARN(1, "R600 PCIE GART already initialized\n");
619 return 0;
620 }
621 /* Initialize common gart structure */
622 r = amdgpu_gart_init(adev);
623 if (r)
624 return r;
625 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
626 return amdgpu_gart_table_vram_alloc(adev);
627 }
628
629 /**
630 * gmc_v7_0_gart_disable - gart disable
631 *
632 * @adev: amdgpu_device pointer
633 *
634 * This disables all VM page table (CIK).
635 */
gmc_v7_0_gart_disable(struct amdgpu_device * adev)636 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
637 {
638 u32 tmp;
639
640 /* Disable all tables */
641 WREG32(mmVM_CONTEXT0_CNTL, 0);
642 WREG32(mmVM_CONTEXT1_CNTL, 0);
643 /* Setup TLB control */
644 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
645 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
646 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
647 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
648 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
649 /* Setup L2 cache */
650 tmp = RREG32(mmVM_L2_CNTL);
651 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
652 WREG32(mmVM_L2_CNTL, tmp);
653 WREG32(mmVM_L2_CNTL2, 0);
654 amdgpu_gart_table_vram_unpin(adev);
655 }
656
657 /**
658 * gmc_v7_0_gart_fini - vm fini callback
659 *
660 * @adev: amdgpu_device pointer
661 *
662 * Tears down the driver GART/VM setup (CIK).
663 */
gmc_v7_0_gart_fini(struct amdgpu_device * adev)664 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
665 {
666 amdgpu_gart_table_vram_free(adev);
667 amdgpu_gart_fini(adev);
668 }
669
670 /*
671 * vm
672 * VMID 0 is the physical GPU addresses as used by the kernel.
673 * VMIDs 1-15 are used for userspace clients and are handled
674 * by the amdgpu vm/hsa code.
675 */
676 /**
677 * gmc_v7_0_vm_init - cik vm init callback
678 *
679 * @adev: amdgpu_device pointer
680 *
681 * Inits cik specific vm parameters (number of VMs, base of vram for
682 * VMIDs 1-15) (CIK).
683 * Returns 0 for success.
684 */
gmc_v7_0_vm_init(struct amdgpu_device * adev)685 static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
686 {
687 /*
688 * number of VMs
689 * VMID 0 is reserved for System
690 * amdgpu graphics/compute will use VMIDs 1-7
691 * amdkfd will use VMIDs 8-15
692 */
693 adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
694
695 /* base offset of vram pages */
696 if (adev->flags & AMD_IS_APU) {
697 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
698 tmp <<= 22;
699 adev->vm_manager.vram_base_offset = tmp;
700 } else
701 adev->vm_manager.vram_base_offset = 0;
702
703 return 0;
704 }
705
706 /**
707 * gmc_v7_0_vm_fini - cik vm fini callback
708 *
709 * @adev: amdgpu_device pointer
710 *
711 * Tear down any asic specific VM setup (CIK).
712 */
gmc_v7_0_vm_fini(struct amdgpu_device * adev)713 static void gmc_v7_0_vm_fini(struct amdgpu_device *adev)
714 {
715 }
716
717 /**
718 * gmc_v7_0_vm_decode_fault - print human readable fault info
719 *
720 * @adev: amdgpu_device pointer
721 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
722 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
723 *
724 * Print human readable fault information (CIK).
725 */
gmc_v7_0_vm_decode_fault(struct amdgpu_device * adev,u32 status,u32 addr,u32 mc_client)726 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
727 u32 status, u32 addr, u32 mc_client)
728 {
729 u32 mc_id;
730 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
731 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
732 PROTECTIONS);
733 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
734 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
735
736 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
737 MEMORY_CLIENT_ID);
738
739 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
740 protections, vmid, addr,
741 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
742 MEMORY_CLIENT_RW) ?
743 "write" : "read", block, mc_client, mc_id);
744 }
745
746
747 static const u32 mc_cg_registers[] = {
748 mmMC_HUB_MISC_HUB_CG,
749 mmMC_HUB_MISC_SIP_CG,
750 mmMC_HUB_MISC_VM_CG,
751 mmMC_XPB_CLK_GAT,
752 mmATC_MISC_CG,
753 mmMC_CITF_MISC_WR_CG,
754 mmMC_CITF_MISC_RD_CG,
755 mmMC_CITF_MISC_VM_CG,
756 mmVM_L2_CG,
757 };
758
759 static const u32 mc_cg_ls_en[] = {
760 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
761 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
762 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
763 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
764 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
765 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
766 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
767 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
768 VM_L2_CG__MEM_LS_ENABLE_MASK,
769 };
770
771 static const u32 mc_cg_en[] = {
772 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
773 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
774 MC_HUB_MISC_VM_CG__ENABLE_MASK,
775 MC_XPB_CLK_GAT__ENABLE_MASK,
776 ATC_MISC_CG__ENABLE_MASK,
777 MC_CITF_MISC_WR_CG__ENABLE_MASK,
778 MC_CITF_MISC_RD_CG__ENABLE_MASK,
779 MC_CITF_MISC_VM_CG__ENABLE_MASK,
780 VM_L2_CG__ENABLE_MASK,
781 };
782
gmc_v7_0_enable_mc_ls(struct amdgpu_device * adev,bool enable)783 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
784 bool enable)
785 {
786 int i;
787 u32 orig, data;
788
789 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
790 orig = data = RREG32(mc_cg_registers[i]);
791 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
792 data |= mc_cg_ls_en[i];
793 else
794 data &= ~mc_cg_ls_en[i];
795 if (data != orig)
796 WREG32(mc_cg_registers[i], data);
797 }
798 }
799
gmc_v7_0_enable_mc_mgcg(struct amdgpu_device * adev,bool enable)800 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
801 bool enable)
802 {
803 int i;
804 u32 orig, data;
805
806 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
807 orig = data = RREG32(mc_cg_registers[i]);
808 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
809 data |= mc_cg_en[i];
810 else
811 data &= ~mc_cg_en[i];
812 if (data != orig)
813 WREG32(mc_cg_registers[i], data);
814 }
815 }
816
gmc_v7_0_enable_bif_mgls(struct amdgpu_device * adev,bool enable)817 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
818 bool enable)
819 {
820 u32 orig, data;
821
822 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
823
824 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
825 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
826 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
827 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
828 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
829 } else {
830 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
831 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
832 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
833 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
834 }
835
836 if (orig != data)
837 WREG32_PCIE(ixPCIE_CNTL2, data);
838 }
839
gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device * adev,bool enable)840 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
841 bool enable)
842 {
843 u32 orig, data;
844
845 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
846
847 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
848 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
849 else
850 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
851
852 if (orig != data)
853 WREG32(mmHDP_HOST_PATH_CNTL, data);
854 }
855
gmc_v7_0_enable_hdp_ls(struct amdgpu_device * adev,bool enable)856 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
857 bool enable)
858 {
859 u32 orig, data;
860
861 orig = data = RREG32(mmHDP_MEM_POWER_LS);
862
863 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
864 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
865 else
866 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
867
868 if (orig != data)
869 WREG32(mmHDP_MEM_POWER_LS, data);
870 }
871
gmc_v7_0_convert_vram_type(int mc_seq_vram_type)872 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
873 {
874 switch (mc_seq_vram_type) {
875 case MC_SEQ_MISC0__MT__GDDR1:
876 return AMDGPU_VRAM_TYPE_GDDR1;
877 case MC_SEQ_MISC0__MT__DDR2:
878 return AMDGPU_VRAM_TYPE_DDR2;
879 case MC_SEQ_MISC0__MT__GDDR3:
880 return AMDGPU_VRAM_TYPE_GDDR3;
881 case MC_SEQ_MISC0__MT__GDDR4:
882 return AMDGPU_VRAM_TYPE_GDDR4;
883 case MC_SEQ_MISC0__MT__GDDR5:
884 return AMDGPU_VRAM_TYPE_GDDR5;
885 case MC_SEQ_MISC0__MT__HBM:
886 return AMDGPU_VRAM_TYPE_HBM;
887 case MC_SEQ_MISC0__MT__DDR3:
888 return AMDGPU_VRAM_TYPE_DDR3;
889 default:
890 return AMDGPU_VRAM_TYPE_UNKNOWN;
891 }
892 }
893
gmc_v7_0_early_init(void * handle)894 static int gmc_v7_0_early_init(void *handle)
895 {
896 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
897
898 gmc_v7_0_set_gart_funcs(adev);
899 gmc_v7_0_set_irq_funcs(adev);
900
901 return 0;
902 }
903
gmc_v7_0_late_init(void * handle)904 static int gmc_v7_0_late_init(void *handle)
905 {
906 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
907
908 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
909 }
910
gmc_v7_0_sw_init(void * handle)911 static int gmc_v7_0_sw_init(void *handle)
912 {
913 int r;
914 int dma_bits;
915 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
916
917 r = amdgpu_gem_init(adev);
918 if (r)
919 return r;
920
921 if (adev->flags & AMD_IS_APU) {
922 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
923 } else {
924 u32 tmp = RREG32(mmMC_SEQ_MISC0);
925 tmp &= MC_SEQ_MISC0__MT__MASK;
926 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
927 }
928
929 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
930 if (r)
931 return r;
932
933 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
934 if (r)
935 return r;
936
937 /* Adjust VM size here.
938 * Currently set to 4GB ((1 << 20) 4k pages).
939 * Max GPUVM size for cayman and SI is 40 bits.
940 */
941 adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
942
943 /* Set the internal MC address mask
944 * This is the max address of the GPU's
945 * internal address space.
946 */
947 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
948
949 /* set DMA mask + need_dma32 flags.
950 * PCIE - can handle 40-bits.
951 * IGP - can handle 40-bits
952 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
953 */
954 adev->need_dma32 = false;
955 dma_bits = adev->need_dma32 ? 32 : 40;
956 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
957 if (r) {
958 adev->need_dma32 = true;
959 dma_bits = 32;
960 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
961 }
962 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
963 if (r) {
964 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
965 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
966 }
967
968 r = gmc_v7_0_init_microcode(adev);
969 if (r) {
970 DRM_ERROR("Failed to load mc firmware!\n");
971 return r;
972 }
973
974 r = gmc_v7_0_mc_init(adev);
975 if (r)
976 return r;
977
978 /* Memory manager */
979 r = amdgpu_bo_init(adev);
980 if (r)
981 return r;
982
983 r = gmc_v7_0_gart_init(adev);
984 if (r)
985 return r;
986
987 if (!adev->vm_manager.enabled) {
988 r = gmc_v7_0_vm_init(adev);
989 if (r) {
990 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
991 return r;
992 }
993 adev->vm_manager.enabled = true;
994 }
995
996 return r;
997 }
998
gmc_v7_0_sw_fini(void * handle)999 static int gmc_v7_0_sw_fini(void *handle)
1000 {
1001 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1002
1003 if (adev->vm_manager.enabled) {
1004 amdgpu_vm_manager_fini(adev);
1005 gmc_v7_0_vm_fini(adev);
1006 adev->vm_manager.enabled = false;
1007 }
1008 gmc_v7_0_gart_fini(adev);
1009 amdgpu_gem_fini(adev);
1010 amdgpu_bo_fini(adev);
1011
1012 return 0;
1013 }
1014
gmc_v7_0_hw_init(void * handle)1015 static int gmc_v7_0_hw_init(void *handle)
1016 {
1017 int r;
1018 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1019
1020 gmc_v7_0_init_golden_registers(adev);
1021
1022 gmc_v7_0_mc_program(adev);
1023
1024 if (!(adev->flags & AMD_IS_APU)) {
1025 r = gmc_v7_0_mc_load_microcode(adev);
1026 if (r) {
1027 DRM_ERROR("Failed to load MC firmware!\n");
1028 return r;
1029 }
1030 }
1031
1032 r = gmc_v7_0_gart_enable(adev);
1033 if (r)
1034 return r;
1035
1036 return r;
1037 }
1038
gmc_v7_0_hw_fini(void * handle)1039 static int gmc_v7_0_hw_fini(void *handle)
1040 {
1041 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1042
1043 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1044 gmc_v7_0_gart_disable(adev);
1045
1046 return 0;
1047 }
1048
gmc_v7_0_suspend(void * handle)1049 static int gmc_v7_0_suspend(void *handle)
1050 {
1051 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1052
1053 if (adev->vm_manager.enabled) {
1054 amdgpu_vm_manager_fini(adev);
1055 gmc_v7_0_vm_fini(adev);
1056 adev->vm_manager.enabled = false;
1057 }
1058 gmc_v7_0_hw_fini(adev);
1059
1060 return 0;
1061 }
1062
gmc_v7_0_resume(void * handle)1063 static int gmc_v7_0_resume(void *handle)
1064 {
1065 int r;
1066 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1067
1068 r = gmc_v7_0_hw_init(adev);
1069 if (r)
1070 return r;
1071
1072 if (!adev->vm_manager.enabled) {
1073 r = gmc_v7_0_vm_init(adev);
1074 if (r) {
1075 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1076 return r;
1077 }
1078 adev->vm_manager.enabled = true;
1079 }
1080
1081 return r;
1082 }
1083
gmc_v7_0_is_idle(void * handle)1084 static bool gmc_v7_0_is_idle(void *handle)
1085 {
1086 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1087 u32 tmp = RREG32(mmSRBM_STATUS);
1088
1089 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1090 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1091 return false;
1092
1093 return true;
1094 }
1095
gmc_v7_0_wait_for_idle(void * handle)1096 static int gmc_v7_0_wait_for_idle(void *handle)
1097 {
1098 unsigned i;
1099 u32 tmp;
1100 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1101
1102 for (i = 0; i < adev->usec_timeout; i++) {
1103 /* read MC_STATUS */
1104 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1105 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1106 SRBM_STATUS__MCC_BUSY_MASK |
1107 SRBM_STATUS__MCD_BUSY_MASK |
1108 SRBM_STATUS__VMC_BUSY_MASK);
1109 if (!tmp)
1110 return 0;
1111 udelay(1);
1112 }
1113 return -ETIMEDOUT;
1114
1115 }
1116
gmc_v7_0_print_status(void * handle)1117 static void gmc_v7_0_print_status(void *handle)
1118 {
1119 int i, j;
1120 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1121
1122 dev_info(adev->dev, "GMC 8.x registers\n");
1123 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
1124 RREG32(mmSRBM_STATUS));
1125 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1126 RREG32(mmSRBM_STATUS2));
1127
1128 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1129 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
1130 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1131 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
1132 dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1133 RREG32(mmMC_VM_MX_L1_TLB_CNTL));
1134 dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n",
1135 RREG32(mmVM_L2_CNTL));
1136 dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n",
1137 RREG32(mmVM_L2_CNTL2));
1138 dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n",
1139 RREG32(mmVM_L2_CNTL3));
1140 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1141 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
1142 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1143 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
1144 dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1145 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
1146 dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n",
1147 RREG32(mmVM_CONTEXT0_CNTL2));
1148 dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n",
1149 RREG32(mmVM_CONTEXT0_CNTL));
1150 dev_info(adev->dev, " 0x15D4=0x%08X\n",
1151 RREG32(0x575));
1152 dev_info(adev->dev, " 0x15D8=0x%08X\n",
1153 RREG32(0x576));
1154 dev_info(adev->dev, " 0x15DC=0x%08X\n",
1155 RREG32(0x577));
1156 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1157 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
1158 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1159 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
1160 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1161 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
1162 dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n",
1163 RREG32(mmVM_CONTEXT1_CNTL2));
1164 dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n",
1165 RREG32(mmVM_CONTEXT1_CNTL));
1166 for (i = 0; i < 16; i++) {
1167 if (i < 8)
1168 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1169 i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
1170 else
1171 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1172 i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
1173 }
1174 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1175 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
1176 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1177 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
1178 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1179 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
1180 dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n",
1181 RREG32(mmMC_VM_FB_LOCATION));
1182 dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n",
1183 RREG32(mmMC_VM_AGP_BASE));
1184 dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n",
1185 RREG32(mmMC_VM_AGP_TOP));
1186 dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n",
1187 RREG32(mmMC_VM_AGP_BOT));
1188
1189 if (adev->asic_type == CHIP_KAVERI) {
1190 dev_info(adev->dev, " CHUB_CONTROL=0x%08X\n",
1191 RREG32(mmCHUB_CONTROL));
1192 }
1193
1194 dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1195 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
1196 dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n",
1197 RREG32(mmHDP_NONSURFACE_BASE));
1198 dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n",
1199 RREG32(mmHDP_NONSURFACE_INFO));
1200 dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n",
1201 RREG32(mmHDP_NONSURFACE_SIZE));
1202 dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n",
1203 RREG32(mmHDP_MISC_CNTL));
1204 dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n",
1205 RREG32(mmHDP_HOST_PATH_CNTL));
1206
1207 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
1208 dev_info(adev->dev, " %d:\n", i);
1209 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1210 0xb05 + j, RREG32(0xb05 + j));
1211 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1212 0xb06 + j, RREG32(0xb06 + j));
1213 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1214 0xb07 + j, RREG32(0xb07 + j));
1215 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1216 0xb08 + j, RREG32(0xb08 + j));
1217 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1218 0xb09 + j, RREG32(0xb09 + j));
1219 }
1220
1221 dev_info(adev->dev, " BIF_FB_EN=0x%08X\n",
1222 RREG32(mmBIF_FB_EN));
1223 }
1224
gmc_v7_0_soft_reset(void * handle)1225 static int gmc_v7_0_soft_reset(void *handle)
1226 {
1227 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1228 struct amdgpu_mode_mc_save save;
1229 u32 srbm_soft_reset = 0;
1230 u32 tmp = RREG32(mmSRBM_STATUS);
1231
1232 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1233 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1234 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1235
1236 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1237 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1238 if (!(adev->flags & AMD_IS_APU))
1239 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1240 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1241 }
1242
1243 if (srbm_soft_reset) {
1244 gmc_v7_0_print_status((void *)adev);
1245
1246 gmc_v7_0_mc_stop(adev, &save);
1247 if (gmc_v7_0_wait_for_idle(adev)) {
1248 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1249 }
1250
1251
1252 tmp = RREG32(mmSRBM_SOFT_RESET);
1253 tmp |= srbm_soft_reset;
1254 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1255 WREG32(mmSRBM_SOFT_RESET, tmp);
1256 tmp = RREG32(mmSRBM_SOFT_RESET);
1257
1258 udelay(50);
1259
1260 tmp &= ~srbm_soft_reset;
1261 WREG32(mmSRBM_SOFT_RESET, tmp);
1262 tmp = RREG32(mmSRBM_SOFT_RESET);
1263
1264 /* Wait a little for things to settle down */
1265 udelay(50);
1266
1267 gmc_v7_0_mc_resume(adev, &save);
1268 udelay(50);
1269
1270 gmc_v7_0_print_status((void *)adev);
1271 }
1272
1273 return 0;
1274 }
1275
gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)1276 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1277 struct amdgpu_irq_src *src,
1278 unsigned type,
1279 enum amdgpu_interrupt_state state)
1280 {
1281 u32 tmp;
1282 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1283 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1284 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1285 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1286 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1287 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1288
1289 switch (state) {
1290 case AMDGPU_IRQ_STATE_DISABLE:
1291 /* system context */
1292 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1293 tmp &= ~bits;
1294 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1295 /* VMs */
1296 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1297 tmp &= ~bits;
1298 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1299 break;
1300 case AMDGPU_IRQ_STATE_ENABLE:
1301 /* system context */
1302 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1303 tmp |= bits;
1304 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1305 /* VMs */
1306 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1307 tmp |= bits;
1308 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1309 break;
1310 default:
1311 break;
1312 }
1313
1314 return 0;
1315 }
1316
gmc_v7_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1317 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1318 struct amdgpu_irq_src *source,
1319 struct amdgpu_iv_entry *entry)
1320 {
1321 u32 addr, status, mc_client;
1322
1323 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1324 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1325 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1326 /* reset addr and status */
1327 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1328
1329 if (!addr && !status)
1330 return 0;
1331
1332 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1333 gmc_v7_0_set_fault_enable_default(adev, false);
1334
1335 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1336 entry->src_id, entry->src_data);
1337 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1338 addr);
1339 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1340 status);
1341 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1342
1343 return 0;
1344 }
1345
gmc_v7_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1346 static int gmc_v7_0_set_clockgating_state(void *handle,
1347 enum amd_clockgating_state state)
1348 {
1349 bool gate = false;
1350 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1351
1352 if (state == AMD_CG_STATE_GATE)
1353 gate = true;
1354
1355 if (!(adev->flags & AMD_IS_APU)) {
1356 gmc_v7_0_enable_mc_mgcg(adev, gate);
1357 gmc_v7_0_enable_mc_ls(adev, gate);
1358 }
1359 gmc_v7_0_enable_bif_mgls(adev, gate);
1360 gmc_v7_0_enable_hdp_mgcg(adev, gate);
1361 gmc_v7_0_enable_hdp_ls(adev, gate);
1362
1363 return 0;
1364 }
1365
gmc_v7_0_set_powergating_state(void * handle,enum amd_powergating_state state)1366 static int gmc_v7_0_set_powergating_state(void *handle,
1367 enum amd_powergating_state state)
1368 {
1369 return 0;
1370 }
1371
1372 const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1373 .early_init = gmc_v7_0_early_init,
1374 .late_init = gmc_v7_0_late_init,
1375 .sw_init = gmc_v7_0_sw_init,
1376 .sw_fini = gmc_v7_0_sw_fini,
1377 .hw_init = gmc_v7_0_hw_init,
1378 .hw_fini = gmc_v7_0_hw_fini,
1379 .suspend = gmc_v7_0_suspend,
1380 .resume = gmc_v7_0_resume,
1381 .is_idle = gmc_v7_0_is_idle,
1382 .wait_for_idle = gmc_v7_0_wait_for_idle,
1383 .soft_reset = gmc_v7_0_soft_reset,
1384 .print_status = gmc_v7_0_print_status,
1385 .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1386 .set_powergating_state = gmc_v7_0_set_powergating_state,
1387 };
1388
1389 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1390 .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1391 .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1392 };
1393
1394 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1395 .set = gmc_v7_0_vm_fault_interrupt_state,
1396 .process = gmc_v7_0_process_interrupt,
1397 };
1398
gmc_v7_0_set_gart_funcs(struct amdgpu_device * adev)1399 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1400 {
1401 if (adev->gart.gart_funcs == NULL)
1402 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1403 }
1404
gmc_v7_0_set_irq_funcs(struct amdgpu_device * adev)1405 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1406 {
1407 adev->mc.vm_fault.num_types = 1;
1408 adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1409 }
1410