1 /*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22 #include "gf100.h"
23 #include "ctxgf100.h"
24
25 #include <subdev/timer.h>
26
27 #include <nvif/class.h>
28
29 static void
gm20b_gr_init_gpc_mmu(struct gf100_gr * gr)30 gm20b_gr_init_gpc_mmu(struct gf100_gr *gr)
31 {
32 struct nvkm_device *device = gr->base.engine.subdev.device;
33 u32 val;
34
35 /* TODO this needs to be removed once secure boot works */
36 if (1) {
37 nvkm_wr32(device, 0x100ce4, 0xffffffff);
38 }
39
40 /* TODO update once secure boot works */
41 val = nvkm_rd32(device, 0x100c80);
42 val &= 0xf000087f;
43 nvkm_wr32(device, 0x418880, val);
44 nvkm_wr32(device, 0x418890, 0);
45 nvkm_wr32(device, 0x418894, 0);
46
47 nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
48 nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
49 nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
50
51 nvkm_wr32(device, 0x4188ac, nvkm_rd32(device, 0x100800));
52 }
53
54 static void
gm20b_gr_set_hww_esr_report_mask(struct gf100_gr * gr)55 gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
56 {
57 struct nvkm_device *device = gr->base.engine.subdev.device;
58 nvkm_wr32(device, 0x419e44, 0xdffffe);
59 nvkm_wr32(device, 0x419e4c, 0x5);
60 }
61
62 static const struct gf100_gr_func
63 gm20b_gr = {
64 .dtor = gk20a_gr_dtor,
65 .init = gk20a_gr_init,
66 .init_gpc_mmu = gm20b_gr_init_gpc_mmu,
67 .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask,
68 .ppc_nr = 1,
69 .grctx = &gm20b_grctx,
70 .sclass = {
71 { -1, -1, FERMI_TWOD_A },
72 { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
73 { -1, -1, MAXWELL_B, &gf100_fermi },
74 { -1, -1, MAXWELL_COMPUTE_B },
75 {}
76 }
77 };
78
79 int
gm20b_gr_new(struct nvkm_device * device,int index,struct nvkm_gr ** pgr)80 gm20b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
81 {
82 return gk20a_gr_new_(&gm20b_gr, device, index, pgr);
83 }
84