1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "nv50.h"
25
26 #include <subdev/bar.h>
27
28 /*******************************************************************************
29 * software object classes
30 ******************************************************************************/
31
32 static int
gf100_sw_mthd_vblsem_offset(struct nvkm_object * object,u32 mthd,void * args,u32 size)33 gf100_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd,
34 void *args, u32 size)
35 {
36 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
37 u64 data = *(u32 *)args;
38 if (mthd == 0x0400) {
39 chan->vblank.offset &= 0x00ffffffffULL;
40 chan->vblank.offset |= data << 32;
41 } else {
42 chan->vblank.offset &= 0xff00000000ULL;
43 chan->vblank.offset |= data;
44 }
45 return 0;
46 }
47
48 static int
gf100_sw_mthd_mp_control(struct nvkm_object * object,u32 mthd,void * args,u32 size)49 gf100_sw_mthd_mp_control(struct nvkm_object *object, u32 mthd,
50 void *args, u32 size)
51 {
52 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
53 struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
54 u32 data = *(u32 *)args;
55
56 switch (mthd) {
57 case 0x600:
58 nv_wr32(priv, 0x419e00, data); /* MP.PM_UNK000 */
59 break;
60 case 0x644:
61 if (data & ~0x1ffffe)
62 return -EINVAL;
63 nv_wr32(priv, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */
64 break;
65 case 0x6ac:
66 nv_wr32(priv, 0x419eac, data); /* MP.PM_UNK0AC */
67 break;
68 default:
69 return -EINVAL;
70 }
71 return 0;
72 }
73
74 static struct nvkm_omthds
75 gf100_sw_omthds[] = {
76 { 0x0400, 0x0400, gf100_sw_mthd_vblsem_offset },
77 { 0x0404, 0x0404, gf100_sw_mthd_vblsem_offset },
78 { 0x0408, 0x0408, nv50_sw_mthd_vblsem_value },
79 { 0x040c, 0x040c, nv50_sw_mthd_vblsem_release },
80 { 0x0500, 0x0500, nv50_sw_mthd_flip },
81 { 0x0600, 0x0600, gf100_sw_mthd_mp_control },
82 { 0x0644, 0x0644, gf100_sw_mthd_mp_control },
83 { 0x06ac, 0x06ac, gf100_sw_mthd_mp_control },
84 {}
85 };
86
87 static struct nvkm_oclass
88 gf100_sw_sclass[] = {
89 { 0x906e, &nvkm_object_ofuncs, gf100_sw_omthds },
90 {}
91 };
92
93 /*******************************************************************************
94 * software context
95 ******************************************************************************/
96
97 static int
gf100_sw_vblsem_release(struct nvkm_notify * notify)98 gf100_sw_vblsem_release(struct nvkm_notify *notify)
99 {
100 struct nv50_sw_chan *chan =
101 container_of(notify, typeof(*chan), vblank.notify[notify->index]);
102 struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
103 struct nvkm_bar *bar = nvkm_bar(priv);
104
105 nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
106 bar->flush(bar);
107 nv_wr32(priv, 0x06000c, upper_32_bits(chan->vblank.offset));
108 nv_wr32(priv, 0x060010, lower_32_bits(chan->vblank.offset));
109 nv_wr32(priv, 0x060014, chan->vblank.value);
110
111 return NVKM_NOTIFY_DROP;
112 }
113
114 static struct nv50_sw_cclass
115 gf100_sw_cclass = {
116 .base.handle = NV_ENGCTX(SW, 0xc0),
117 .base.ofuncs = &(struct nvkm_ofuncs) {
118 .ctor = nv50_sw_context_ctor,
119 .dtor = nv50_sw_context_dtor,
120 .init = _nvkm_sw_context_init,
121 .fini = _nvkm_sw_context_fini,
122 },
123 .vblank = gf100_sw_vblsem_release,
124 };
125
126 /*******************************************************************************
127 * software engine/subdev functions
128 ******************************************************************************/
129
130 struct nvkm_oclass *
131 gf100_sw_oclass = &(struct nv50_sw_oclass) {
132 .base.handle = NV_ENGINE(SW, 0xc0),
133 .base.ofuncs = &(struct nvkm_ofuncs) {
134 .ctor = nv50_sw_ctor,
135 .dtor = _nvkm_sw_dtor,
136 .init = _nvkm_sw_init,
137 .fini = _nvkm_sw_fini,
138 },
139 .cclass = &gf100_sw_cclass.base,
140 .sclass = gf100_sw_sclass,
141 }.base;
142