1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "nv50.h"
25 #include "outpdp.h"
26
27 #include <core/device.h>
28 #include <subdev/timer.h>
29
30 static inline u32
g94_sor_soff(struct nvkm_output_dp * outp)31 g94_sor_soff(struct nvkm_output_dp *outp)
32 {
33 return (ffs(outp->base.info.or) - 1) * 0x800;
34 }
35
36 static inline u32
g94_sor_loff(struct nvkm_output_dp * outp)37 g94_sor_loff(struct nvkm_output_dp *outp)
38 {
39 return g94_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
40 }
41
42 static inline u32
g94_sor_dp_lane_map(struct nv50_disp_priv * priv,u8 lane)43 g94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
44 {
45 static const u8 mcp89[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
46 static const u8 g94[] = { 16, 8, 0, 24 };
47 if (nv_device(priv)->chipset == 0xaf)
48 return mcp89[lane];
49 return g94[lane];
50 }
51
52 static int
g94_sor_dp_pattern(struct nvkm_output_dp * outp,int pattern)53 g94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
54 {
55 struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
56 const u32 loff = g94_sor_loff(outp);
57 nv_mask(priv, 0x61c10c + loff, 0x0f000000, pattern << 24);
58 return 0;
59 }
60
61 int
g94_sor_dp_lnk_pwr(struct nvkm_output_dp * outp,int nr)62 g94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
63 {
64 struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
65 const u32 soff = g94_sor_soff(outp);
66 const u32 loff = g94_sor_loff(outp);
67 u32 mask = 0, i;
68
69 for (i = 0; i < nr; i++)
70 mask |= 1 << (g94_sor_dp_lane_map(priv, i) >> 3);
71
72 nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask);
73 nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000);
74 nv_wait(priv, 0x61c034 + soff, 0x80000000, 0x00000000);
75 return 0;
76 }
77
78 static int
g94_sor_dp_lnk_ctl(struct nvkm_output_dp * outp,int nr,int bw,bool ef)79 g94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
80 {
81 struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
82 const u32 soff = g94_sor_soff(outp);
83 const u32 loff = g94_sor_loff(outp);
84 u32 dpctrl = 0x00000000;
85 u32 clksor = 0x00000000;
86
87 dpctrl |= ((1 << nr) - 1) << 16;
88 if (ef)
89 dpctrl |= 0x00004000;
90 if (bw > 0x06)
91 clksor |= 0x00040000;
92
93 nv_mask(priv, 0x614300 + soff, 0x000c0000, clksor);
94 nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl);
95 return 0;
96 }
97
98 static int
g94_sor_dp_drv_ctl(struct nvkm_output_dp * outp,int ln,int vs,int pe,int pc)99 g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
100 {
101 struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
102 struct nvkm_bios *bios = nvkm_bios(priv);
103 const u32 shift = g94_sor_dp_lane_map(priv, ln);
104 const u32 loff = g94_sor_loff(outp);
105 u32 addr, data[3];
106 u8 ver, hdr, cnt, len;
107 struct nvbios_dpout info;
108 struct nvbios_dpcfg ocfg;
109
110 addr = nvbios_dpout_match(bios, outp->base.info.hasht,
111 outp->base.info.hashm,
112 &ver, &hdr, &cnt, &len, &info);
113 if (!addr)
114 return -ENODEV;
115
116 addr = nvbios_dpcfg_match(bios, addr, 0, vs, pe,
117 &ver, &hdr, &cnt, &len, &ocfg);
118 if (!addr)
119 return -EINVAL;
120
121 data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
122 data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
123 data[2] = nv_rd32(priv, 0x61c130 + loff);
124 if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0)
125 data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
126 nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
127 nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
128 nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8));
129 return 0;
130 }
131
132 struct nvkm_output_dp_impl
133 g94_sor_dp_impl = {
134 .base.base.handle = DCB_OUTPUT_DP,
135 .base.base.ofuncs = &(struct nvkm_ofuncs) {
136 .ctor = _nvkm_output_dp_ctor,
137 .dtor = _nvkm_output_dp_dtor,
138 .init = _nvkm_output_dp_init,
139 .fini = _nvkm_output_dp_fini,
140 },
141 .pattern = g94_sor_dp_pattern,
142 .lnk_pwr = g94_sor_dp_lnk_pwr,
143 .lnk_ctl = g94_sor_dp_lnk_ctl,
144 .drv_ctl = g94_sor_dp_drv_ctl,
145 };
146