1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2012  Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * The full GNU General Public License is included in this distribution in the
15  * file called LICENSE.
16  *
17  * Contact Information:
18  * wlanfae <wlanfae@realtek.com>
19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20  * Hsinchu 300, Taiwan.
21  *
22  * Larry Finger <Larry.Finger@lwfinger.net>
23  *
24  *****************************************************************************/
25 
26 #ifndef __RTL_WIFI_H__
27 #define __RTL_WIFI_H__
28 
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 
31 #include <linux/sched.h>
32 #include <linux/firmware.h>
33 #include <linux/etherdevice.h>
34 #include <linux/vmalloc.h>
35 #include <linux/usb.h>
36 #include <net/mac80211.h>
37 #include <linux/completion.h>
38 #include "debug.h"
39 
40 #define	MASKBYTE0				0xff
41 #define	MASKBYTE1				0xff00
42 #define	MASKBYTE2				0xff0000
43 #define	MASKBYTE3				0xff000000
44 #define	MASKHWORD				0xffff0000
45 #define	MASKLWORD				0x0000ffff
46 #define	MASKDWORD				0xffffffff
47 #define	MASK12BITS				0xfff
48 #define	MASKH4BITS				0xf0000000
49 #define MASKOFDM_D				0xffc00000
50 #define	MASKCCK					0x3f3f3f3f
51 
52 #define	MASK4BITS				0x0f
53 #define	MASK20BITS				0xfffff
54 #define RFREG_OFFSET_MASK			0xfffff
55 
56 #define	MASKBYTE0				0xff
57 #define	MASKBYTE1				0xff00
58 #define	MASKBYTE2				0xff0000
59 #define	MASKBYTE3				0xff000000
60 #define	MASKHWORD				0xffff0000
61 #define	MASKLWORD				0x0000ffff
62 #define	MASKDWORD				0xffffffff
63 #define	MASK12BITS				0xfff
64 #define	MASKH4BITS				0xf0000000
65 #define MASKOFDM_D				0xffc00000
66 #define	MASKCCK					0x3f3f3f3f
67 
68 #define	MASK4BITS				0x0f
69 #define	MASK20BITS				0xfffff
70 #define RFREG_OFFSET_MASK			0xfffff
71 
72 #define RF_CHANGE_BY_INIT			0
73 #define RF_CHANGE_BY_IPS			BIT(28)
74 #define RF_CHANGE_BY_PS				BIT(29)
75 #define RF_CHANGE_BY_HW				BIT(30)
76 #define RF_CHANGE_BY_SW				BIT(31)
77 
78 #define IQK_ADDA_REG_NUM			16
79 #define IQK_MAC_REG_NUM				4
80 #define IQK_THRESHOLD				8
81 
82 #define MAX_KEY_LEN				61
83 #define KEY_BUF_SIZE				5
84 
85 /* QoS related. */
86 /*aci: 0x00	Best Effort*/
87 /*aci: 0x01	Background*/
88 /*aci: 0x10	Video*/
89 /*aci: 0x11	Voice*/
90 /*Max: define total number.*/
91 #define AC0_BE					0
92 #define AC1_BK					1
93 #define AC2_VI					2
94 #define AC3_VO					3
95 #define AC_MAX					4
96 #define QOS_QUEUE_NUM				4
97 #define RTL_MAC80211_NUM_QUEUE			5
98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE		254
99 #define RTL_USB_MAX_RX_COUNT			100
100 #define QBSS_LOAD_SIZE				5
101 #define MAX_WMMELE_LENGTH			64
102 
103 #define TOTAL_CAM_ENTRY				32
104 
105 /*slot time for 11g. */
106 #define RTL_SLOT_TIME_9				9
107 #define RTL_SLOT_TIME_20			20
108 
109 /*related to tcp/ip. */
110 #define SNAP_SIZE		6
111 #define PROTOC_TYPE_SIZE	2
112 
113 /*related with 802.11 frame*/
114 #define MAC80211_3ADDR_LEN			24
115 #define MAC80211_4ADDR_LEN			30
116 
117 #define CHANNEL_MAX_NUMBER	(14 + 24 + 21)	/* 14 is the max channel no */
118 #define CHANNEL_MAX_NUMBER_2G		14
119 #define CHANNEL_MAX_NUMBER_5G		54 /* Please refer to
120 					    *"phy_GetChnlGroup8812A" and
121 					    * "Hal_ReadTxPowerInfo8812A"
122 					    */
123 #define CHANNEL_MAX_NUMBER_5G_80M	7
124 #define CHANNEL_GROUP_MAX	(3 + 9)	/*  ch1~3, 4~9, 10~14 = three groups */
125 #define CHANNEL_MAX_NUMBER_5G		54 /* Please refer to
126 					    *"phy_GetChnlGroup8812A" and
127 					    * "Hal_ReadTxPowerInfo8812A"
128 					    */
129 #define CHANNEL_MAX_NUMBER_5G_80M	7
130 #define MAX_PG_GROUP			13
131 #define	CHANNEL_GROUP_MAX_2G		3
132 #define	CHANNEL_GROUP_IDX_5GL		3
133 #define	CHANNEL_GROUP_IDX_5GM		6
134 #define	CHANNEL_GROUP_IDX_5GH		9
135 #define	CHANNEL_GROUP_MAX_5G		9
136 #define CHANNEL_MAX_NUMBER_2G		14
137 #define AVG_THERMAL_NUM			8
138 #define AVG_THERMAL_NUM_88E		4
139 #define AVG_THERMAL_NUM_8723BE		4
140 #define MAX_TID_COUNT			9
141 
142 /* for early mode */
143 #define FCS_LEN				4
144 #define EM_HDR_LEN			8
145 
146 enum rtl8192c_h2c_cmd {
147 	H2C_AP_OFFLOAD = 0,
148 	H2C_SETPWRMODE = 1,
149 	H2C_JOINBSSRPT = 2,
150 	H2C_RSVDPAGE = 3,
151 	H2C_RSSI_REPORT = 5,
152 	H2C_RA_MASK = 6,
153 	H2C_MACID_PS_MODE = 7,
154 	H2C_P2P_PS_OFFLOAD = 8,
155 	H2C_MAC_MODE_SEL = 9,
156 	H2C_PWRM = 15,
157 	H2C_P2P_PS_CTW_CMD = 24,
158 	MAX_H2CCMD
159 };
160 
161 #define MAX_TX_COUNT			4
162 #define MAX_REGULATION_NUM		4
163 #define MAX_RF_PATH_NUM			4
164 #define MAX_RATE_SECTION_NUM		6
165 #define MAX_2_4G_BANDWITH_NUM		4
166 #define MAX_5G_BANDWITH_NUM		4
167 #define	MAX_RF_PATH			4
168 #define	MAX_CHNL_GROUP_24G		6
169 #define	MAX_CHNL_GROUP_5G		14
170 
171 #define TX_PWR_BY_RATE_NUM_BAND		2
172 #define TX_PWR_BY_RATE_NUM_RF		4
173 #define TX_PWR_BY_RATE_NUM_SECTION	12
174 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G  6
175 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G	5
176 
177 #define RTL8192EE_SEG_NUM		1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
178 
179 #define DEL_SW_IDX_SZ		30
180 #define BAND_NUM			3
181 
182 /* For now, it's just for 8192ee
183  * but not OK yet, keep it 0
184  */
185 #define DMA_IS_64BIT 0
186 #define RTL8192EE_SEG_NUM		1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
187 
188 enum rf_tx_num {
189 	RF_1TX = 0,
190 	RF_2TX,
191 	RF_MAX_TX_NUM,
192 	RF_TX_NUM_NONIMPLEMENT,
193 };
194 
195 #define PACKET_NORMAL			0
196 #define PACKET_DHCP			1
197 #define PACKET_ARP			2
198 #define PACKET_EAPOL			3
199 
200 #define	MAX_SUPPORT_WOL_PATTERN_NUM	16
201 #define	RSVD_WOL_PATTERN_NUM		1
202 #define	WKFMCAM_ADDR_NUM		6
203 #define	WKFMCAM_SIZE			24
204 
205 #define	MAX_WOL_BIT_MASK_SIZE		16
206 /* MIN LEN keeps 13 here */
207 #define	MIN_WOL_PATTERN_SIZE		13
208 #define	MAX_WOL_PATTERN_SIZE		128
209 
210 #define	WAKE_ON_MAGIC_PACKET		BIT(0)
211 #define	WAKE_ON_PATTERN_MATCH		BIT(1)
212 
213 #define	WOL_REASON_PTK_UPDATE		BIT(0)
214 #define	WOL_REASON_GTK_UPDATE		BIT(1)
215 #define	WOL_REASON_DISASSOC		BIT(2)
216 #define	WOL_REASON_DEAUTH		BIT(3)
217 #define	WOL_REASON_AP_LOST		BIT(4)
218 #define	WOL_REASON_MAGIC_PKT		BIT(5)
219 #define	WOL_REASON_UNICAST_PKT		BIT(6)
220 #define	WOL_REASON_PATTERN_PKT		BIT(7)
221 #define	WOL_REASON_RTD3_SSID_MATCH	BIT(8)
222 #define	WOL_REASON_REALWOW_V2_WAKEUPPKT	BIT(9)
223 #define	WOL_REASON_REALWOW_V2_ACKLOST	BIT(10)
224 
225 struct txpower_info_2g {
226 	u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
227 	u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
228 	/*If only one tx, only BW20 and OFDM are used.*/
229 	u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
230 	u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
231 	u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
232 	u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
233 	u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
234 	u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
235 };
236 
237 struct txpower_info_5g {
238 	u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
239 	/*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
240 	u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
241 	u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
242 	u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
243 	u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
244 	u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
245 };
246 
247 enum rate_section {
248 	CCK = 0,
249 	OFDM,
250 	HT_MCS0_MCS7,
251 	HT_MCS8_MCS15,
252 	VHT_1SSMCS0_1SSMCS9,
253 	VHT_2SSMCS0_2SSMCS9,
254 };
255 
256 enum intf_type {
257 	INTF_PCI = 0,
258 	INTF_USB = 1,
259 };
260 
261 enum radio_path {
262 	RF90_PATH_A = 0,
263 	RF90_PATH_B = 1,
264 	RF90_PATH_C = 2,
265 	RF90_PATH_D = 3,
266 };
267 
268 enum regulation_txpwr_lmt {
269 	TXPWR_LMT_FCC = 0,
270 	TXPWR_LMT_MKK = 1,
271 	TXPWR_LMT_ETSI = 2,
272 	TXPWR_LMT_WW = 3,
273 
274 	TXPWR_LMT_MAX_REGULATION_NUM = 4
275 };
276 
277 enum rt_eeprom_type {
278 	EEPROM_93C46,
279 	EEPROM_93C56,
280 	EEPROM_BOOT_EFUSE,
281 };
282 
283 enum ttl_status {
284 	RTL_STATUS_INTERFACE_START = 0,
285 };
286 
287 enum hardware_type {
288 	HARDWARE_TYPE_RTL8192E,
289 	HARDWARE_TYPE_RTL8192U,
290 	HARDWARE_TYPE_RTL8192SE,
291 	HARDWARE_TYPE_RTL8192SU,
292 	HARDWARE_TYPE_RTL8192CE,
293 	HARDWARE_TYPE_RTL8192CU,
294 	HARDWARE_TYPE_RTL8192DE,
295 	HARDWARE_TYPE_RTL8192DU,
296 	HARDWARE_TYPE_RTL8723AE,
297 	HARDWARE_TYPE_RTL8723U,
298 	HARDWARE_TYPE_RTL8188EE,
299 	HARDWARE_TYPE_RTL8723BE,
300 	HARDWARE_TYPE_RTL8192EE,
301 	HARDWARE_TYPE_RTL8821AE,
302 	HARDWARE_TYPE_RTL8812AE,
303 
304 	/* keep it last */
305 	HARDWARE_TYPE_NUM
306 };
307 
308 #define IS_HARDWARE_TYPE_8192SU(rtlhal)			\
309 	(rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
310 #define IS_HARDWARE_TYPE_8192SE(rtlhal)			\
311 	(rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
312 #define IS_HARDWARE_TYPE_8192CE(rtlhal)			\
313 	(rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
314 #define IS_HARDWARE_TYPE_8192CU(rtlhal)			\
315 	(rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
316 #define IS_HARDWARE_TYPE_8192DE(rtlhal)			\
317 	(rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
318 #define IS_HARDWARE_TYPE_8192DU(rtlhal)			\
319 	(rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
320 #define IS_HARDWARE_TYPE_8723E(rtlhal)			\
321 	(rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
322 #define IS_HARDWARE_TYPE_8723U(rtlhal)			\
323 	(rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
324 #define	IS_HARDWARE_TYPE_8192S(rtlhal)			\
325 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
326 #define	IS_HARDWARE_TYPE_8192C(rtlhal)			\
327 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
328 #define	IS_HARDWARE_TYPE_8192D(rtlhal)			\
329 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
330 #define	IS_HARDWARE_TYPE_8723(rtlhal)			\
331 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
332 
333 #define RX_HAL_IS_CCK_RATE(rxmcs)			\
334 	((rxmcs) == DESC_RATE1M ||			\
335 	 (rxmcs) == DESC_RATE2M ||			\
336 	 (rxmcs) == DESC_RATE5_5M ||			\
337 	 (rxmcs) == DESC_RATE11M)
338 
339 enum scan_operation_backup_opt {
340 	SCAN_OPT_BACKUP = 0,
341 	SCAN_OPT_BACKUP_BAND0 = 0,
342 	SCAN_OPT_BACKUP_BAND1,
343 	SCAN_OPT_RESTORE,
344 	SCAN_OPT_MAX
345 };
346 
347 /*RF state.*/
348 enum rf_pwrstate {
349 	ERFON,
350 	ERFSLEEP,
351 	ERFOFF
352 };
353 
354 struct bb_reg_def {
355 	u32 rfintfs;
356 	u32 rfintfi;
357 	u32 rfintfo;
358 	u32 rfintfe;
359 	u32 rf3wire_offset;
360 	u32 rflssi_select;
361 	u32 rftxgain_stage;
362 	u32 rfhssi_para1;
363 	u32 rfhssi_para2;
364 	u32 rfsw_ctrl;
365 	u32 rfagc_control1;
366 	u32 rfagc_control2;
367 	u32 rfrxiq_imbal;
368 	u32 rfrx_afe;
369 	u32 rftxiq_imbal;
370 	u32 rftx_afe;
371 	u32 rf_rb;		/* rflssi_readback */
372 	u32 rf_rbpi;		/* rflssi_readbackpi */
373 };
374 
375 enum io_type {
376 	IO_CMD_PAUSE_DM_BY_SCAN = 0,
377 	IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
378 	IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
379 	IO_CMD_RESUME_DM_BY_SCAN = 2,
380 };
381 
382 enum hw_variables {
383 	HW_VAR_ETHER_ADDR,
384 	HW_VAR_MULTICAST_REG,
385 	HW_VAR_BASIC_RATE,
386 	HW_VAR_BSSID,
387 	HW_VAR_MEDIA_STATUS,
388 	HW_VAR_SECURITY_CONF,
389 	HW_VAR_BEACON_INTERVAL,
390 	HW_VAR_ATIM_WINDOW,
391 	HW_VAR_LISTEN_INTERVAL,
392 	HW_VAR_CS_COUNTER,
393 	HW_VAR_DEFAULTKEY0,
394 	HW_VAR_DEFAULTKEY1,
395 	HW_VAR_DEFAULTKEY2,
396 	HW_VAR_DEFAULTKEY3,
397 	HW_VAR_SIFS,
398 	HW_VAR_R2T_SIFS,
399 	HW_VAR_DIFS,
400 	HW_VAR_EIFS,
401 	HW_VAR_SLOT_TIME,
402 	HW_VAR_ACK_PREAMBLE,
403 	HW_VAR_CW_CONFIG,
404 	HW_VAR_CW_VALUES,
405 	HW_VAR_RATE_FALLBACK_CONTROL,
406 	HW_VAR_CONTENTION_WINDOW,
407 	HW_VAR_RETRY_COUNT,
408 	HW_VAR_TR_SWITCH,
409 	HW_VAR_COMMAND,
410 	HW_VAR_WPA_CONFIG,
411 	HW_VAR_AMPDU_MIN_SPACE,
412 	HW_VAR_SHORTGI_DENSITY,
413 	HW_VAR_AMPDU_FACTOR,
414 	HW_VAR_MCS_RATE_AVAILABLE,
415 	HW_VAR_AC_PARAM,
416 	HW_VAR_ACM_CTRL,
417 	HW_VAR_DIS_Req_Qsize,
418 	HW_VAR_CCX_CHNL_LOAD,
419 	HW_VAR_CCX_NOISE_HISTOGRAM,
420 	HW_VAR_CCX_CLM_NHM,
421 	HW_VAR_TxOPLimit,
422 	HW_VAR_TURBO_MODE,
423 	HW_VAR_RF_STATE,
424 	HW_VAR_RF_OFF_BY_HW,
425 	HW_VAR_BUS_SPEED,
426 	HW_VAR_SET_DEV_POWER,
427 
428 	HW_VAR_RCR,
429 	HW_VAR_RATR_0,
430 	HW_VAR_RRSR,
431 	HW_VAR_CPU_RST,
432 	HW_VAR_CHECK_BSSID,
433 	HW_VAR_LBK_MODE,
434 	HW_VAR_AES_11N_FIX,
435 	HW_VAR_USB_RX_AGGR,
436 	HW_VAR_USER_CONTROL_TURBO_MODE,
437 	HW_VAR_RETRY_LIMIT,
438 	HW_VAR_INIT_TX_RATE,
439 	HW_VAR_TX_RATE_REG,
440 	HW_VAR_EFUSE_USAGE,
441 	HW_VAR_EFUSE_BYTES,
442 	HW_VAR_AUTOLOAD_STATUS,
443 	HW_VAR_RF_2R_DISABLE,
444 	HW_VAR_SET_RPWM,
445 	HW_VAR_H2C_FW_PWRMODE,
446 	HW_VAR_H2C_FW_JOINBSSRPT,
447 	HW_VAR_H2C_FW_MEDIASTATUSRPT,
448 	HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
449 	HW_VAR_FW_PSMODE_STATUS,
450 	HW_VAR_INIT_RTS_RATE,
451 	HW_VAR_RESUME_CLK_ON,
452 	HW_VAR_FW_LPS_ACTION,
453 	HW_VAR_1X1_RECV_COMBINE,
454 	HW_VAR_STOP_SEND_BEACON,
455 	HW_VAR_TSF_TIMER,
456 	HW_VAR_IO_CMD,
457 
458 	HW_VAR_RF_RECOVERY,
459 	HW_VAR_H2C_FW_UPDATE_GTK,
460 	HW_VAR_WF_MASK,
461 	HW_VAR_WF_CRC,
462 	HW_VAR_WF_IS_MAC_ADDR,
463 	HW_VAR_H2C_FW_OFFLOAD,
464 	HW_VAR_RESET_WFCRC,
465 
466 	HW_VAR_HANDLE_FW_C2H,
467 	HW_VAR_DL_FW_RSVD_PAGE,
468 	HW_VAR_AID,
469 	HW_VAR_HW_SEQ_ENABLE,
470 	HW_VAR_CORRECT_TSF,
471 	HW_VAR_BCN_VALID,
472 	HW_VAR_FWLPS_RF_ON,
473 	HW_VAR_DUAL_TSF_RST,
474 	HW_VAR_SWITCH_EPHY_WoWLAN,
475 	HW_VAR_INT_MIGRATION,
476 	HW_VAR_INT_AC,
477 	HW_VAR_RF_TIMING,
478 
479 	HAL_DEF_WOWLAN,
480 	HW_VAR_MRC,
481 	HW_VAR_KEEP_ALIVE,
482 	HW_VAR_NAV_UPPER,
483 
484 	HW_VAR_MGT_FILTER,
485 	HW_VAR_CTRL_FILTER,
486 	HW_VAR_DATA_FILTER,
487 };
488 
489 enum rt_media_status {
490 	RT_MEDIA_DISCONNECT = 0,
491 	RT_MEDIA_CONNECT = 1
492 };
493 
494 enum rt_oem_id {
495 	RT_CID_DEFAULT = 0,
496 	RT_CID_8187_ALPHA0 = 1,
497 	RT_CID_8187_SERCOMM_PS = 2,
498 	RT_CID_8187_HW_LED = 3,
499 	RT_CID_8187_NETGEAR = 4,
500 	RT_CID_WHQL = 5,
501 	RT_CID_819X_CAMEO = 6,
502 	RT_CID_819X_RUNTOP = 7,
503 	RT_CID_819X_SENAO = 8,
504 	RT_CID_TOSHIBA = 9,
505 	RT_CID_819X_NETCORE = 10,
506 	RT_CID_NETTRONIX = 11,
507 	RT_CID_DLINK = 12,
508 	RT_CID_PRONET = 13,
509 	RT_CID_COREGA = 14,
510 	RT_CID_819X_ALPHA = 15,
511 	RT_CID_819X_SITECOM = 16,
512 	RT_CID_CCX = 17,
513 	RT_CID_819X_LENOVO = 18,
514 	RT_CID_819X_QMI = 19,
515 	RT_CID_819X_EDIMAX_BELKIN = 20,
516 	RT_CID_819X_SERCOMM_BELKIN = 21,
517 	RT_CID_819X_CAMEO1 = 22,
518 	RT_CID_819X_MSI = 23,
519 	RT_CID_819X_ACER = 24,
520 	RT_CID_819X_HP = 27,
521 	RT_CID_819X_CLEVO = 28,
522 	RT_CID_819X_ARCADYAN_BELKIN = 29,
523 	RT_CID_819X_SAMSUNG = 30,
524 	RT_CID_819X_WNC_COREGA = 31,
525 	RT_CID_819X_FOXCOON = 32,
526 	RT_CID_819X_DELL = 33,
527 	RT_CID_819X_PRONETS = 34,
528 	RT_CID_819X_EDIMAX_ASUS = 35,
529 	RT_CID_NETGEAR = 36,
530 	RT_CID_PLANEX = 37,
531 	RT_CID_CC_C = 38,
532 };
533 
534 enum hw_descs {
535 	HW_DESC_OWN,
536 	HW_DESC_RXOWN,
537 	HW_DESC_TX_NEXTDESC_ADDR,
538 	HW_DESC_TXBUFF_ADDR,
539 	HW_DESC_RXBUFF_ADDR,
540 	HW_DESC_RXPKT_LEN,
541 	HW_DESC_RXERO,
542 	HW_DESC_RX_PREPARE,
543 };
544 
545 enum prime_sc {
546 	PRIME_CHNL_OFFSET_DONT_CARE = 0,
547 	PRIME_CHNL_OFFSET_LOWER = 1,
548 	PRIME_CHNL_OFFSET_UPPER = 2,
549 };
550 
551 enum rf_type {
552 	RF_1T1R = 0,
553 	RF_1T2R = 1,
554 	RF_2T2R = 2,
555 	RF_2T2R_GREEN = 3,
556 };
557 
558 enum ht_channel_width {
559 	HT_CHANNEL_WIDTH_20 = 0,
560 	HT_CHANNEL_WIDTH_20_40 = 1,
561 	HT_CHANNEL_WIDTH_80 = 2,
562 };
563 
564 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
565 Cipher Suites Encryption Algorithms */
566 enum rt_enc_alg {
567 	NO_ENCRYPTION = 0,
568 	WEP40_ENCRYPTION = 1,
569 	TKIP_ENCRYPTION = 2,
570 	RSERVED_ENCRYPTION = 3,
571 	AESCCMP_ENCRYPTION = 4,
572 	WEP104_ENCRYPTION = 5,
573 	AESCMAC_ENCRYPTION = 6,	/*IEEE802.11w */
574 };
575 
576 enum rtl_hal_state {
577 	_HAL_STATE_STOP = 0,
578 	_HAL_STATE_START = 1,
579 };
580 
581 enum rtl_desc92_rate {
582 	DESC_RATE1M = 0x00,
583 	DESC_RATE2M = 0x01,
584 	DESC_RATE5_5M = 0x02,
585 	DESC_RATE11M = 0x03,
586 
587 	DESC_RATE6M = 0x04,
588 	DESC_RATE9M = 0x05,
589 	DESC_RATE12M = 0x06,
590 	DESC_RATE18M = 0x07,
591 	DESC_RATE24M = 0x08,
592 	DESC_RATE36M = 0x09,
593 	DESC_RATE48M = 0x0a,
594 	DESC_RATE54M = 0x0b,
595 
596 	DESC_RATEMCS0 = 0x0c,
597 	DESC_RATEMCS1 = 0x0d,
598 	DESC_RATEMCS2 = 0x0e,
599 	DESC_RATEMCS3 = 0x0f,
600 	DESC_RATEMCS4 = 0x10,
601 	DESC_RATEMCS5 = 0x11,
602 	DESC_RATEMCS6 = 0x12,
603 	DESC_RATEMCS7 = 0x13,
604 	DESC_RATEMCS8 = 0x14,
605 	DESC_RATEMCS9 = 0x15,
606 	DESC_RATEMCS10 = 0x16,
607 	DESC_RATEMCS11 = 0x17,
608 	DESC_RATEMCS12 = 0x18,
609 	DESC_RATEMCS13 = 0x19,
610 	DESC_RATEMCS14 = 0x1a,
611 	DESC_RATEMCS15 = 0x1b,
612 	DESC_RATEMCS15_SG = 0x1c,
613 	DESC_RATEMCS32 = 0x20,
614 
615 	DESC_RATEVHT1SS_MCS0 = 0x2c,
616 	DESC_RATEVHT1SS_MCS1 = 0x2d,
617 	DESC_RATEVHT1SS_MCS2 = 0x2e,
618 	DESC_RATEVHT1SS_MCS3 = 0x2f,
619 	DESC_RATEVHT1SS_MCS4 = 0x30,
620 	DESC_RATEVHT1SS_MCS5 = 0x31,
621 	DESC_RATEVHT1SS_MCS6 = 0x32,
622 	DESC_RATEVHT1SS_MCS7 = 0x33,
623 	DESC_RATEVHT1SS_MCS8 = 0x34,
624 	DESC_RATEVHT1SS_MCS9 = 0x35,
625 	DESC_RATEVHT2SS_MCS0 = 0x36,
626 	DESC_RATEVHT2SS_MCS1 = 0x37,
627 	DESC_RATEVHT2SS_MCS2 = 0x38,
628 	DESC_RATEVHT2SS_MCS3 = 0x39,
629 	DESC_RATEVHT2SS_MCS4 = 0x3a,
630 	DESC_RATEVHT2SS_MCS5 = 0x3b,
631 	DESC_RATEVHT2SS_MCS6 = 0x3c,
632 	DESC_RATEVHT2SS_MCS7 = 0x3d,
633 	DESC_RATEVHT2SS_MCS8 = 0x3e,
634 	DESC_RATEVHT2SS_MCS9 = 0x3f,
635 };
636 
637 enum rtl_var_map {
638 	/*reg map */
639 	SYS_ISO_CTRL = 0,
640 	SYS_FUNC_EN,
641 	SYS_CLK,
642 	MAC_RCR_AM,
643 	MAC_RCR_AB,
644 	MAC_RCR_ACRC32,
645 	MAC_RCR_ACF,
646 	MAC_RCR_AAP,
647 	MAC_HIMR,
648 	MAC_HIMRE,
649 	MAC_HSISR,
650 
651 	/*efuse map */
652 	EFUSE_TEST,
653 	EFUSE_CTRL,
654 	EFUSE_CLK,
655 	EFUSE_CLK_CTRL,
656 	EFUSE_PWC_EV12V,
657 	EFUSE_FEN_ELDR,
658 	EFUSE_LOADER_CLK_EN,
659 	EFUSE_ANA8M,
660 	EFUSE_HWSET_MAX_SIZE,
661 	EFUSE_MAX_SECTION_MAP,
662 	EFUSE_REAL_CONTENT_SIZE,
663 	EFUSE_OOB_PROTECT_BYTES_LEN,
664 	EFUSE_ACCESS,
665 
666 	/*CAM map */
667 	RWCAM,
668 	WCAMI,
669 	RCAMO,
670 	CAMDBG,
671 	SECR,
672 	SEC_CAM_NONE,
673 	SEC_CAM_WEP40,
674 	SEC_CAM_TKIP,
675 	SEC_CAM_AES,
676 	SEC_CAM_WEP104,
677 
678 	/*IMR map */
679 	RTL_IMR_BCNDMAINT6,	/*Beacon DMA Interrupt 6 */
680 	RTL_IMR_BCNDMAINT5,	/*Beacon DMA Interrupt 5 */
681 	RTL_IMR_BCNDMAINT4,	/*Beacon DMA Interrupt 4 */
682 	RTL_IMR_BCNDMAINT3,	/*Beacon DMA Interrupt 3 */
683 	RTL_IMR_BCNDMAINT2,	/*Beacon DMA Interrupt 2 */
684 	RTL_IMR_BCNDMAINT1,	/*Beacon DMA Interrupt 1 */
685 	RTL_IMR_BCNDOK8,	/*Beacon Queue DMA OK Interrup 8 */
686 	RTL_IMR_BCNDOK7,	/*Beacon Queue DMA OK Interrup 7 */
687 	RTL_IMR_BCNDOK6,	/*Beacon Queue DMA OK Interrup 6 */
688 	RTL_IMR_BCNDOK5,	/*Beacon Queue DMA OK Interrup 5 */
689 	RTL_IMR_BCNDOK4,	/*Beacon Queue DMA OK Interrup 4 */
690 	RTL_IMR_BCNDOK3,	/*Beacon Queue DMA OK Interrup 3 */
691 	RTL_IMR_BCNDOK2,	/*Beacon Queue DMA OK Interrup 2 */
692 	RTL_IMR_BCNDOK1,	/*Beacon Queue DMA OK Interrup 1 */
693 	RTL_IMR_TIMEOUT2,	/*Timeout interrupt 2 */
694 	RTL_IMR_TIMEOUT1,	/*Timeout interrupt 1 */
695 	RTL_IMR_TXFOVW,		/*Transmit FIFO Overflow */
696 	RTL_IMR_PSTIMEOUT,	/*Power save time out interrupt */
697 	RTL_IMR_BCNINT,		/*Beacon DMA Interrupt 0 */
698 	RTL_IMR_RXFOVW,		/*Receive FIFO Overflow */
699 	RTL_IMR_RDU,		/*Receive Descriptor Unavailable */
700 	RTL_IMR_ATIMEND,	/*For 92C,ATIM Window End Interrupt */
701 	RTL_IMR_BDOK,		/*Beacon Queue DMA OK Interrup */
702 	RTL_IMR_HIGHDOK,	/*High Queue DMA OK Interrupt */
703 	RTL_IMR_COMDOK,		/*Command Queue DMA OK Interrupt*/
704 	RTL_IMR_TBDOK,		/*Transmit Beacon OK interrup */
705 	RTL_IMR_MGNTDOK,	/*Management Queue DMA OK Interrupt */
706 	RTL_IMR_TBDER,		/*For 92C,Transmit Beacon Error Interrupt */
707 	RTL_IMR_BKDOK,		/*AC_BK DMA OK Interrupt */
708 	RTL_IMR_BEDOK,		/*AC_BE DMA OK Interrupt */
709 	RTL_IMR_VIDOK,		/*AC_VI DMA OK Interrupt */
710 	RTL_IMR_VODOK,		/*AC_VO DMA Interrupt */
711 	RTL_IMR_ROK,		/*Receive DMA OK Interrupt */
712 	RTL_IMR_HSISR_IND,	/*HSISR Interrupt*/
713 	RTL_IBSS_INT_MASKS,	/*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
714 				 * RTL_IMR_TBDER) */
715 	RTL_IMR_C2HCMD,		/*fw interrupt*/
716 
717 	/*CCK Rates, TxHT = 0 */
718 	RTL_RC_CCK_RATE1M,
719 	RTL_RC_CCK_RATE2M,
720 	RTL_RC_CCK_RATE5_5M,
721 	RTL_RC_CCK_RATE11M,
722 
723 	/*OFDM Rates, TxHT = 0 */
724 	RTL_RC_OFDM_RATE6M,
725 	RTL_RC_OFDM_RATE9M,
726 	RTL_RC_OFDM_RATE12M,
727 	RTL_RC_OFDM_RATE18M,
728 	RTL_RC_OFDM_RATE24M,
729 	RTL_RC_OFDM_RATE36M,
730 	RTL_RC_OFDM_RATE48M,
731 	RTL_RC_OFDM_RATE54M,
732 
733 	RTL_RC_HT_RATEMCS7,
734 	RTL_RC_HT_RATEMCS15,
735 
736 	RTL_RC_VHT_RATE_1SS_MCS7,
737 	RTL_RC_VHT_RATE_1SS_MCS8,
738 	RTL_RC_VHT_RATE_1SS_MCS9,
739 	RTL_RC_VHT_RATE_2SS_MCS7,
740 	RTL_RC_VHT_RATE_2SS_MCS8,
741 	RTL_RC_VHT_RATE_2SS_MCS9,
742 
743 	/*keep it last */
744 	RTL_VAR_MAP_MAX,
745 };
746 
747 /*Firmware PS mode for control LPS.*/
748 enum _fw_ps_mode {
749 	FW_PS_ACTIVE_MODE = 0,
750 	FW_PS_MIN_MODE = 1,
751 	FW_PS_MAX_MODE = 2,
752 	FW_PS_DTIM_MODE = 3,
753 	FW_PS_VOIP_MODE = 4,
754 	FW_PS_UAPSD_WMM_MODE = 5,
755 	FW_PS_UAPSD_MODE = 6,
756 	FW_PS_IBSS_MODE = 7,
757 	FW_PS_WWLAN_MODE = 8,
758 	FW_PS_PM_Radio_Off = 9,
759 	FW_PS_PM_Card_Disable = 10,
760 };
761 
762 enum rt_psmode {
763 	EACTIVE,		/*Active/Continuous access. */
764 	EMAXPS,			/*Max power save mode. */
765 	EFASTPS,		/*Fast power save mode. */
766 	EAUTOPS,		/*Auto power save mode. */
767 };
768 
769 /*LED related.*/
770 enum led_ctl_mode {
771 	LED_CTL_POWER_ON = 1,
772 	LED_CTL_LINK = 2,
773 	LED_CTL_NO_LINK = 3,
774 	LED_CTL_TX = 4,
775 	LED_CTL_RX = 5,
776 	LED_CTL_SITE_SURVEY = 6,
777 	LED_CTL_POWER_OFF = 7,
778 	LED_CTL_START_TO_LINK = 8,
779 	LED_CTL_START_WPS = 9,
780 	LED_CTL_STOP_WPS = 10,
781 };
782 
783 enum rtl_led_pin {
784 	LED_PIN_GPIO0,
785 	LED_PIN_LED0,
786 	LED_PIN_LED1,
787 	LED_PIN_LED2
788 };
789 
790 /*QoS related.*/
791 /*acm implementation method.*/
792 enum acm_method {
793 	eAcmWay0_SwAndHw = 0,
794 	eAcmWay1_HW = 1,
795 	EACMWAY2_SW = 2,
796 };
797 
798 enum macphy_mode {
799 	SINGLEMAC_SINGLEPHY = 0,
800 	DUALMAC_DUALPHY,
801 	DUALMAC_SINGLEPHY,
802 };
803 
804 enum band_type {
805 	BAND_ON_2_4G = 0,
806 	BAND_ON_5G,
807 	BAND_ON_BOTH,
808 	BANDMAX
809 };
810 
811 /*aci/aifsn Field.
812 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
813 union aci_aifsn {
814 	u8 char_data;
815 
816 	struct {
817 		u8 aifsn:4;
818 		u8 acm:1;
819 		u8 aci:2;
820 		u8 reserved:1;
821 	} f;			/* Field */
822 };
823 
824 /*mlme related.*/
825 enum wireless_mode {
826 	WIRELESS_MODE_UNKNOWN = 0x00,
827 	WIRELESS_MODE_A = 0x01,
828 	WIRELESS_MODE_B = 0x02,
829 	WIRELESS_MODE_G = 0x04,
830 	WIRELESS_MODE_AUTO = 0x08,
831 	WIRELESS_MODE_N_24G = 0x10,
832 	WIRELESS_MODE_N_5G = 0x20,
833 	WIRELESS_MODE_AC_5G = 0x40,
834 	WIRELESS_MODE_AC_24G  = 0x80,
835 	WIRELESS_MODE_AC_ONLY = 0x100,
836 	WIRELESS_MODE_MAX = 0x800
837 };
838 
839 #define IS_WIRELESS_MODE_A(wirelessmode)	\
840 	(wirelessmode == WIRELESS_MODE_A)
841 #define IS_WIRELESS_MODE_B(wirelessmode)	\
842 	(wirelessmode == WIRELESS_MODE_B)
843 #define IS_WIRELESS_MODE_G(wirelessmode)	\
844 	(wirelessmode == WIRELESS_MODE_G)
845 #define IS_WIRELESS_MODE_N_24G(wirelessmode)	\
846 	(wirelessmode == WIRELESS_MODE_N_24G)
847 #define IS_WIRELESS_MODE_N_5G(wirelessmode)	\
848 	(wirelessmode == WIRELESS_MODE_N_5G)
849 
850 enum ratr_table_mode {
851 	RATR_INX_WIRELESS_NGB = 0,
852 	RATR_INX_WIRELESS_NG = 1,
853 	RATR_INX_WIRELESS_NB = 2,
854 	RATR_INX_WIRELESS_N = 3,
855 	RATR_INX_WIRELESS_GB = 4,
856 	RATR_INX_WIRELESS_G = 5,
857 	RATR_INX_WIRELESS_B = 6,
858 	RATR_INX_WIRELESS_MC = 7,
859 	RATR_INX_WIRELESS_A = 8,
860 	RATR_INX_WIRELESS_AC_5N = 8,
861 	RATR_INX_WIRELESS_AC_24N = 9,
862 };
863 
864 enum rtl_link_state {
865 	MAC80211_NOLINK = 0,
866 	MAC80211_LINKING = 1,
867 	MAC80211_LINKED = 2,
868 	MAC80211_LINKED_SCANNING = 3,
869 };
870 
871 enum act_category {
872 	ACT_CAT_QOS = 1,
873 	ACT_CAT_DLS = 2,
874 	ACT_CAT_BA = 3,
875 	ACT_CAT_HT = 7,
876 	ACT_CAT_WMM = 17,
877 };
878 
879 enum ba_action {
880 	ACT_ADDBAREQ = 0,
881 	ACT_ADDBARSP = 1,
882 	ACT_DELBA = 2,
883 };
884 
885 enum rt_polarity_ctl {
886 	RT_POLARITY_LOW_ACT = 0,
887 	RT_POLARITY_HIGH_ACT = 1,
888 };
889 
890 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
891 enum fw_wow_reason_v2 {
892 	FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
893 	FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
894 	FW_WOW_V2_DISASSOC_EVENT = 0x04,
895 	FW_WOW_V2_DEAUTH_EVENT = 0x08,
896 	FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
897 	FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
898 	FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
899 	FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
900 	FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
901 	FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
902 	FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
903 	FW_WOW_V2_REASON_MAX = 0xff,
904 };
905 
906 enum wolpattern_type {
907 	UNICAST_PATTERN = 0,
908 	MULTICAST_PATTERN = 1,
909 	BROADCAST_PATTERN = 2,
910 	DONT_CARE_DA = 3,
911 	UNKNOWN_TYPE = 4,
912 };
913 
914 struct octet_string {
915 	u8 *octet;
916 	u16 length;
917 };
918 
919 struct rtl_hdr_3addr {
920 	__le16 frame_ctl;
921 	__le16 duration_id;
922 	u8 addr1[ETH_ALEN];
923 	u8 addr2[ETH_ALEN];
924 	u8 addr3[ETH_ALEN];
925 	__le16 seq_ctl;
926 	u8 payload[0];
927 } __packed;
928 
929 struct rtl_info_element {
930 	u8 id;
931 	u8 len;
932 	u8 data[0];
933 } __packed;
934 
935 struct rtl_probe_rsp {
936 	struct rtl_hdr_3addr header;
937 	u32 time_stamp[2];
938 	__le16 beacon_interval;
939 	__le16 capability;
940 	/*SSID, supported rates, FH params, DS params,
941 	   CF params, IBSS params, TIM (if beacon), RSN */
942 	struct rtl_info_element info_element[0];
943 } __packed;
944 
945 /*LED related.*/
946 /*ledpin Identify how to implement this SW led.*/
947 struct rtl_led {
948 	void *hw;
949 	enum rtl_led_pin ledpin;
950 	bool ledon;
951 };
952 
953 struct rtl_led_ctl {
954 	bool led_opendrain;
955 	struct rtl_led sw_led0;
956 	struct rtl_led sw_led1;
957 };
958 
959 struct rtl_qos_parameters {
960 	__le16 cw_min;
961 	__le16 cw_max;
962 	u8 aifs;
963 	u8 flag;
964 	__le16 tx_op;
965 } __packed;
966 
967 struct rt_smooth_data {
968 	u32 elements[100];	/*array to store values */
969 	u32 index;		/*index to current array to store */
970 	u32 total_num;		/*num of valid elements */
971 	u32 total_val;		/*sum of valid elements */
972 };
973 
974 struct false_alarm_statistics {
975 	u32 cnt_parity_fail;
976 	u32 cnt_rate_illegal;
977 	u32 cnt_crc8_fail;
978 	u32 cnt_mcs_fail;
979 	u32 cnt_fast_fsync_fail;
980 	u32 cnt_sb_search_fail;
981 	u32 cnt_ofdm_fail;
982 	u32 cnt_cck_fail;
983 	u32 cnt_all;
984 	u32 cnt_ofdm_cca;
985 	u32 cnt_cck_cca;
986 	u32 cnt_cca_all;
987 	u32 cnt_bw_usc;
988 	u32 cnt_bw_lsc;
989 };
990 
991 struct init_gain {
992 	u8 xaagccore1;
993 	u8 xbagccore1;
994 	u8 xcagccore1;
995 	u8 xdagccore1;
996 	u8 cca;
997 
998 };
999 
1000 struct wireless_stats {
1001 	unsigned long txbytesunicast;
1002 	unsigned long txbytesmulticast;
1003 	unsigned long txbytesbroadcast;
1004 	unsigned long rxbytesunicast;
1005 
1006 	long rx_snr_db[4];
1007 	/*Correct smoothed ss in Dbm, only used
1008 	   in driver to report real power now. */
1009 	long recv_signal_power;
1010 	long signal_quality;
1011 	long last_sigstrength_inpercent;
1012 
1013 	u32 rssi_calculate_cnt;
1014 	u32 pwdb_all_cnt;
1015 
1016 	/*Transformed, in dbm. Beautified signal
1017 	   strength for UI, not correct. */
1018 	long signal_strength;
1019 
1020 	u8 rx_rssi_percentage[4];
1021 	u8 rx_evm_dbm[4];
1022 	u8 rx_evm_percentage[2];
1023 
1024 	u16 rx_cfo_short[4];
1025 	u16 rx_cfo_tail[4];
1026 
1027 	struct rt_smooth_data ui_rssi;
1028 	struct rt_smooth_data ui_link_quality;
1029 };
1030 
1031 struct rate_adaptive {
1032 	u8 rate_adaptive_disabled;
1033 	u8 ratr_state;
1034 	u16 reserve;
1035 
1036 	u32 high_rssi_thresh_for_ra;
1037 	u32 high2low_rssi_thresh_for_ra;
1038 	u8 low2high_rssi_thresh_for_ra40m;
1039 	u32 low_rssi_thresh_for_ra40m;
1040 	u8 low2high_rssi_thresh_for_ra20m;
1041 	u32 low_rssi_thresh_for_ra20m;
1042 	u32 upper_rssi_threshold_ratr;
1043 	u32 middleupper_rssi_threshold_ratr;
1044 	u32 middle_rssi_threshold_ratr;
1045 	u32 middlelow_rssi_threshold_ratr;
1046 	u32 low_rssi_threshold_ratr;
1047 	u32 ultralow_rssi_threshold_ratr;
1048 	u32 low_rssi_threshold_ratr_40m;
1049 	u32 low_rssi_threshold_ratr_20m;
1050 	u8 ping_rssi_enable;
1051 	u32 ping_rssi_ratr;
1052 	u32 ping_rssi_thresh_for_ra;
1053 	u32 last_ratr;
1054 	u8 pre_ratr_state;
1055 	u8 ldpc_thres;
1056 	bool use_ldpc;
1057 	bool lower_rts_rate;
1058 	bool is_special_data;
1059 };
1060 
1061 struct regd_pair_mapping {
1062 	u16 reg_dmnenum;
1063 	u16 reg_5ghz_ctl;
1064 	u16 reg_2ghz_ctl;
1065 };
1066 
1067 struct dynamic_primary_cca {
1068 	u8 pricca_flag;
1069 	u8 intf_flag;
1070 	u8 intf_type;
1071 	u8 dup_rts_flag;
1072 	u8 monitor_flag;
1073 	u8 ch_offset;
1074 	u8 mf_state;
1075 };
1076 
1077 struct rtl_regulatory {
1078 	char alpha2[2];
1079 	u16 country_code;
1080 	u16 max_power_level;
1081 	u32 tp_scale;
1082 	u16 current_rd;
1083 	u16 current_rd_ext;
1084 	int16_t power_limit;
1085 	struct regd_pair_mapping *regpair;
1086 };
1087 
1088 struct rtl_rfkill {
1089 	bool rfkill_state;	/*0 is off, 1 is on */
1090 };
1091 
1092 /*for P2P PS**/
1093 #define	P2P_MAX_NOA_NUM		2
1094 
1095 enum p2p_role {
1096 	P2P_ROLE_DISABLE = 0,
1097 	P2P_ROLE_DEVICE = 1,
1098 	P2P_ROLE_CLIENT = 2,
1099 	P2P_ROLE_GO = 3
1100 };
1101 
1102 enum p2p_ps_state {
1103 	P2P_PS_DISABLE = 0,
1104 	P2P_PS_ENABLE = 1,
1105 	P2P_PS_SCAN = 2,
1106 	P2P_PS_SCAN_DONE = 3,
1107 	P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1108 };
1109 
1110 enum p2p_ps_mode {
1111 	P2P_PS_NONE = 0,
1112 	P2P_PS_CTWINDOW = 1,
1113 	P2P_PS_NOA	 = 2,
1114 	P2P_PS_MIX = 3, /* CTWindow and NoA */
1115 };
1116 
1117 struct rtl_p2p_ps_info {
1118 	enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1119 	enum p2p_ps_state p2p_ps_state; /*  indicate p2p ps state */
1120 	u8 noa_index; /*  Identifies instance of Notice of Absence timing. */
1121 	/*  Client traffic window. A period of time in TU after TBTT. */
1122 	u8 ctwindow;
1123 	u8 opp_ps; /*  opportunistic power save. */
1124 	u8 noa_num; /*  number of NoA descriptor in P2P IE. */
1125 	/*  Count for owner, Type of client. */
1126 	u8 noa_count_type[P2P_MAX_NOA_NUM];
1127 	/*  Max duration for owner, preferred or min acceptable duration
1128 	 * for client.
1129 	 */
1130 	u32 noa_duration[P2P_MAX_NOA_NUM];
1131 	/*  Length of interval for owner, preferred or max acceptable intervali
1132 	 * of client.
1133 	 */
1134 	u32 noa_interval[P2P_MAX_NOA_NUM];
1135 	/*  schedule in terms of the lower 4 bytes of the TSF timer. */
1136 	u32 noa_start_time[P2P_MAX_NOA_NUM];
1137 };
1138 
1139 struct p2p_ps_offload_t {
1140 	u8 offload_en:1;
1141 	u8 role:1; /* 1: Owner, 0: Client */
1142 	u8 ctwindow_en:1;
1143 	u8 noa0_en:1;
1144 	u8 noa1_en:1;
1145 	u8 allstasleep:1;
1146 	u8 discovery:1;
1147 	u8 reserved:1;
1148 };
1149 
1150 #define IQK_MATRIX_REG_NUM	8
1151 #define IQK_MATRIX_SETTINGS_NUM	(1 + 24 + 21)
1152 
1153 struct iqk_matrix_regs {
1154 	bool iqk_done;
1155 	long value[1][IQK_MATRIX_REG_NUM];
1156 };
1157 
1158 struct phy_parameters {
1159 	u16 length;
1160 	u32 *pdata;
1161 };
1162 
1163 enum hw_param_tab_index {
1164 	PHY_REG_2T,
1165 	PHY_REG_1T,
1166 	PHY_REG_PG,
1167 	RADIOA_2T,
1168 	RADIOB_2T,
1169 	RADIOA_1T,
1170 	RADIOB_1T,
1171 	MAC_REG,
1172 	AGCTAB_2T,
1173 	AGCTAB_1T,
1174 	MAX_TAB
1175 };
1176 
1177 struct rtl_phy {
1178 	struct bb_reg_def phyreg_def[4];	/*Radio A/B/C/D */
1179 	struct init_gain initgain_backup;
1180 	enum io_type current_io_type;
1181 
1182 	u8 rf_mode;
1183 	u8 rf_type;
1184 	u8 current_chan_bw;
1185 	u8 set_bwmode_inprogress;
1186 	u8 sw_chnl_inprogress;
1187 	u8 sw_chnl_stage;
1188 	u8 sw_chnl_step;
1189 	u8 current_channel;
1190 	u8 h2c_box_num;
1191 	u8 set_io_inprogress;
1192 	u8 lck_inprogress;
1193 
1194 	/* record for power tracking */
1195 	s32 reg_e94;
1196 	s32 reg_e9c;
1197 	s32 reg_ea4;
1198 	s32 reg_eac;
1199 	s32 reg_eb4;
1200 	s32 reg_ebc;
1201 	s32 reg_ec4;
1202 	s32 reg_ecc;
1203 	u8 rfpienable;
1204 	u8 reserve_0;
1205 	u16 reserve_1;
1206 	u32 reg_c04, reg_c08, reg_874;
1207 	u32 adda_backup[16];
1208 	u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1209 	u32 iqk_bb_backup[10];
1210 	bool iqk_initialized;
1211 
1212 	bool rfpath_rx_enable[MAX_RF_PATH];
1213 	u8 reg_837;
1214 	/* Dual mac */
1215 	bool need_iqk;
1216 	struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1217 
1218 	bool rfpi_enable;
1219 	bool iqk_in_progress;
1220 
1221 	u8 pwrgroup_cnt;
1222 	u8 cck_high_power;
1223 	/* this is for 88E & 8723A */
1224 	u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1225 	/* MAX_PG_GROUP groups of pwr diff by rates */
1226 	u32 mcs_offset[MAX_PG_GROUP][16];
1227 	u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1228 				   [TX_PWR_BY_RATE_NUM_RF]
1229 				   [TX_PWR_BY_RATE_NUM_RF]
1230 				   [TX_PWR_BY_RATE_NUM_SECTION];
1231 	u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1232 				 [TX_PWR_BY_RATE_NUM_RF]
1233 				 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1234 	u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1235 				[TX_PWR_BY_RATE_NUM_RF]
1236 				[MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1237 	u8 default_initialgain[4];
1238 
1239 	/* the current Tx power level */
1240 	u8 cur_cck_txpwridx;
1241 	u8 cur_ofdm24g_txpwridx;
1242 	u8 cur_bw20_txpwridx;
1243 	u8 cur_bw40_txpwridx;
1244 
1245 	char txpwr_limit_2_4g[MAX_REGULATION_NUM]
1246 			     [MAX_2_4G_BANDWITH_NUM]
1247 			     [MAX_RATE_SECTION_NUM]
1248 			     [CHANNEL_MAX_NUMBER_2G]
1249 			     [MAX_RF_PATH_NUM];
1250 	char txpwr_limit_5g[MAX_REGULATION_NUM]
1251 			   [MAX_5G_BANDWITH_NUM]
1252 			   [MAX_RATE_SECTION_NUM]
1253 			   [CHANNEL_MAX_NUMBER_5G]
1254 			   [MAX_RF_PATH_NUM];
1255 
1256 	u32 rfreg_chnlval[2];
1257 	bool apk_done;
1258 	u32 reg_rf3c[2];	/* pathA / pathB  */
1259 
1260 	u32 backup_rf_0x1a;/*92ee*/
1261 	/* bfsync */
1262 	u8 framesync;
1263 	u32 framesync_c34;
1264 
1265 	u8 num_total_rfpath;
1266 	struct phy_parameters hwparam_tables[MAX_TAB];
1267 	u16 rf_pathmap;
1268 
1269 	u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1270 	enum rt_polarity_ctl polarity_ctl;
1271 };
1272 
1273 #define MAX_TID_COUNT				9
1274 #define RTL_AGG_STOP				0
1275 #define RTL_AGG_PROGRESS			1
1276 #define RTL_AGG_START				2
1277 #define RTL_AGG_OPERATIONAL			3
1278 #define RTL_AGG_OFF				0
1279 #define RTL_AGG_ON				1
1280 #define RTL_RX_AGG_START			1
1281 #define RTL_RX_AGG_STOP				0
1282 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA		2
1283 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA		3
1284 
1285 struct rtl_ht_agg {
1286 	u16 txq_id;
1287 	u16 wait_for_ba;
1288 	u16 start_idx;
1289 	u64 bitmap;
1290 	u32 rate_n_flags;
1291 	u8 agg_state;
1292 	u8 rx_agg_state;
1293 };
1294 
1295 struct rssi_sta {
1296 	long undec_sm_pwdb;
1297 	long undec_sm_cck;
1298 };
1299 
1300 struct rtl_tid_data {
1301 	u16 seq_number;
1302 	struct rtl_ht_agg agg;
1303 };
1304 
1305 struct rtl_sta_info {
1306 	struct list_head list;
1307 	u8 ratr_index;
1308 	u8 wireless_mode;
1309 	u8 mimo_ps;
1310 	u8 mac_addr[ETH_ALEN];
1311 	struct rtl_tid_data tids[MAX_TID_COUNT];
1312 
1313 	/* just used for ap adhoc or mesh*/
1314 	struct rssi_sta rssi_stat;
1315 } __packed;
1316 
1317 struct rtl_priv;
1318 struct rtl_io {
1319 	struct device *dev;
1320 	struct mutex bb_mutex;
1321 
1322 	/*PCI MEM map */
1323 	unsigned long pci_mem_end;	/*shared mem end        */
1324 	unsigned long pci_mem_start;	/*shared mem start */
1325 
1326 	/*PCI IO map */
1327 	unsigned long pci_base_addr;	/*device I/O address */
1328 
1329 	void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1330 	void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1331 	void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1332 	void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1333 			     u16 len);
1334 
1335 	u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1336 	u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1337 	u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1338 
1339 };
1340 
1341 struct rtl_mac {
1342 	u8 mac_addr[ETH_ALEN];
1343 	u8 mac80211_registered;
1344 	u8 beacon_enabled;
1345 
1346 	u32 tx_ss_num;
1347 	u32 rx_ss_num;
1348 
1349 	struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1350 	struct ieee80211_hw *hw;
1351 	struct ieee80211_vif *vif;
1352 	enum nl80211_iftype opmode;
1353 
1354 	/*Probe Beacon management */
1355 	struct rtl_tid_data tids[MAX_TID_COUNT];
1356 	enum rtl_link_state link_state;
1357 
1358 	int n_channels;
1359 	int n_bitrates;
1360 
1361 	bool offchan_delay;
1362 	u8 p2p;	/*using p2p role*/
1363 	bool p2p_in_use;
1364 
1365 	/*filters */
1366 	u32 rx_conf;
1367 	u16 rx_mgt_filter;
1368 	u16 rx_ctrl_filter;
1369 	u16 rx_data_filter;
1370 
1371 	bool act_scanning;
1372 	u8 cnt_after_linked;
1373 	bool skip_scan;
1374 
1375 	/* early mode */
1376 	/* skb wait queue */
1377 	struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1378 
1379 	u8 ht_stbc_cap;
1380 	u8 ht_cur_stbc;
1381 
1382 	/*vht support*/
1383 	u8 vht_enable;
1384 	u8 bw_80;
1385 	u8 vht_cur_ldpc;
1386 	u8 vht_cur_stbc;
1387 	u8 vht_stbc_cap;
1388 	u8 vht_ldpc_cap;
1389 
1390 	/*RDG*/
1391 	bool rdg_en;
1392 
1393 	/*AP*/
1394 	u8 bssid[ETH_ALEN] __aligned(2);
1395 	u32 vendor;
1396 	u8 mcs[16];	/* 16 bytes mcs for HT rates. */
1397 	u32 basic_rates; /* b/g rates */
1398 	u8 ht_enable;
1399 	u8 sgi_40;
1400 	u8 sgi_20;
1401 	u8 bw_40;
1402 	u16 mode;		/* wireless mode */
1403 	u8 slot_time;
1404 	u8 short_preamble;
1405 	u8 use_cts_protect;
1406 	u8 cur_40_prime_sc;
1407 	u8 cur_40_prime_sc_bk;
1408 	u8 cur_80_prime_sc;
1409 	u64 tsf;
1410 	u8 retry_short;
1411 	u8 retry_long;
1412 	u16 assoc_id;
1413 	bool hiddenssid;
1414 
1415 	/*IBSS*/
1416 	int beacon_interval;
1417 
1418 	/*AMPDU*/
1419 	u8 min_space_cfg;	/*For Min spacing configurations */
1420 	u8 max_mss_density;
1421 	u8 current_ampdu_factor;
1422 	u8 current_ampdu_density;
1423 
1424 	/*QOS & EDCA */
1425 	struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1426 	struct rtl_qos_parameters ac[AC_MAX];
1427 
1428 	/* counters */
1429 	u64 last_txok_cnt;
1430 	u64 last_rxok_cnt;
1431 	u32 last_bt_edca_ul;
1432 	u32 last_bt_edca_dl;
1433 };
1434 
1435 struct btdm_8723 {
1436 	bool all_off;
1437 	bool agc_table_en;
1438 	bool adc_back_off_on;
1439 	bool b2_ant_hid_en;
1440 	bool low_penalty_rate_adaptive;
1441 	bool rf_rx_lpf_shrink;
1442 	bool reject_aggre_pkt;
1443 	bool tra_tdma_on;
1444 	u8 tra_tdma_nav;
1445 	u8 tra_tdma_ant;
1446 	bool tdma_on;
1447 	u8 tdma_ant;
1448 	u8 tdma_nav;
1449 	u8 tdma_dac_swing;
1450 	u8 fw_dac_swing_lvl;
1451 	bool ps_tdma_on;
1452 	u8 ps_tdma_byte[5];
1453 	bool pta_on;
1454 	u32 val_0x6c0;
1455 	u32 val_0x6c8;
1456 	u32 val_0x6cc;
1457 	bool sw_dac_swing_on;
1458 	u32 sw_dac_swing_lvl;
1459 	u32 wlan_act_hi;
1460 	u32 wlan_act_lo;
1461 	u32 bt_retry_index;
1462 	bool dec_bt_pwr;
1463 	bool ignore_wlan_act;
1464 };
1465 
1466 struct bt_coexist_8723 {
1467 	u32 high_priority_tx;
1468 	u32 high_priority_rx;
1469 	u32 low_priority_tx;
1470 	u32 low_priority_rx;
1471 	u8 c2h_bt_info;
1472 	bool c2h_bt_info_req_sent;
1473 	bool c2h_bt_inquiry_page;
1474 	u32 bt_inq_page_start_time;
1475 	u8 bt_retry_cnt;
1476 	u8 c2h_bt_info_original;
1477 	u8 bt_inquiry_page_cnt;
1478 	struct btdm_8723 btdm;
1479 };
1480 
1481 struct rtl_hal {
1482 	struct ieee80211_hw *hw;
1483 	bool driver_is_goingto_unload;
1484 	bool up_first_time;
1485 	bool first_init;
1486 	bool being_init_adapter;
1487 	bool bbrf_ready;
1488 	bool mac_func_enable;
1489 	bool pre_edcca_enable;
1490 	struct bt_coexist_8723 hal_coex_8723;
1491 
1492 	enum intf_type interface;
1493 	u16 hw_type;		/*92c or 92d or 92s and so on */
1494 	u8 ic_class;
1495 	u8 oem_id;
1496 	u32 version;		/*version of chip */
1497 	u8 state;		/*stop 0, start 1 */
1498 	u8 board_type;
1499 	u8 external_pa;
1500 
1501 	u8 pa_mode;
1502 	u8 pa_type_2g;
1503 	u8 pa_type_5g;
1504 	u8 lna_type_2g;
1505 	u8 lna_type_5g;
1506 	u8 external_pa_2g;
1507 	u8 external_lna_2g;
1508 	u8 external_pa_5g;
1509 	u8 external_lna_5g;
1510 	u8 rfe_type;
1511 
1512 	/*firmware */
1513 	u32 fwsize;
1514 	u8 *pfirmware;
1515 	u16 fw_version;
1516 	u16 fw_subversion;
1517 	bool h2c_setinprogress;
1518 	u8 last_hmeboxnum;
1519 	bool fw_ready;
1520 	/*Reserve page start offset except beacon in TxQ. */
1521 	u8 fw_rsvdpage_startoffset;
1522 	u8 h2c_txcmd_seq;
1523 	u8 current_ra_rate;
1524 
1525 	/* FW Cmd IO related */
1526 	u16 fwcmd_iomap;
1527 	u32 fwcmd_ioparam;
1528 	bool set_fwcmd_inprogress;
1529 	u8 current_fwcmd_io;
1530 
1531 	struct p2p_ps_offload_t p2p_ps_offload;
1532 	bool fw_clk_change_in_progress;
1533 	bool allow_sw_to_change_hwclc;
1534 	u8 fw_ps_state;
1535 	/**/
1536 	bool driver_going2unload;
1537 
1538 	/*AMPDU init min space*/
1539 	u8 minspace_cfg;	/*For Min spacing configurations */
1540 
1541 	/* Dual mac */
1542 	enum macphy_mode macphymode;
1543 	enum band_type current_bandtype;	/* 0:2.4G, 1:5G */
1544 	enum band_type current_bandtypebackup;
1545 	enum band_type bandset;
1546 	/* dual MAC 0--Mac0 1--Mac1 */
1547 	u32 interfaceindex;
1548 	/* just for DualMac S3S4 */
1549 	u8 macphyctl_reg;
1550 	bool earlymode_enable;
1551 	u8 max_earlymode_num;
1552 	/* Dual mac*/
1553 	bool during_mac0init_radiob;
1554 	bool during_mac1init_radioa;
1555 	bool reloadtxpowerindex;
1556 	/* True if IMR or IQK  have done
1557 	for 2.4G in scan progress */
1558 	bool load_imrandiqk_setting_for2g;
1559 
1560 	bool disable_amsdu_8k;
1561 	bool master_of_dmsp;
1562 	bool slave_of_dmsp;
1563 
1564 	u16 rx_tag;/*for 92ee*/
1565 	u8 rts_en;
1566 
1567 	/*for wowlan*/
1568 	bool wow_enable;
1569 	bool enter_pnp_sleep;
1570 	bool wake_from_pnp_sleep;
1571 	bool wow_enabled;
1572 	__kernel_time_t last_suspend_sec;
1573 	u32 wowlan_fwsize;
1574 	u8 *wowlan_firmware;
1575 
1576 	u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1577 
1578 	bool real_wow_v2_enable;
1579 	bool re_init_llt_table;
1580 };
1581 
1582 struct rtl_security {
1583 	/*default 0 */
1584 	bool use_sw_sec;
1585 
1586 	bool being_setkey;
1587 	bool use_defaultkey;
1588 	/*Encryption Algorithm for Unicast Packet */
1589 	enum rt_enc_alg pairwise_enc_algorithm;
1590 	/*Encryption Algorithm for Brocast/Multicast */
1591 	enum rt_enc_alg group_enc_algorithm;
1592 	/*Cam Entry Bitmap */
1593 	u32 hwsec_cam_bitmap;
1594 	u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1595 	/*local Key buffer, indx 0 is for
1596 	   pairwise key 1-4 is for agoup key. */
1597 	u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1598 	u8 key_len[KEY_BUF_SIZE];
1599 
1600 	/*The pointer of Pairwise Key,
1601 	   it always points to KeyBuf[4] */
1602 	u8 *pairwise_key;
1603 };
1604 
1605 #define ASSOCIATE_ENTRY_NUM	33
1606 
1607 struct fast_ant_training {
1608 	u8	bssid[6];
1609 	u8	antsel_rx_keep_0;
1610 	u8	antsel_rx_keep_1;
1611 	u8	antsel_rx_keep_2;
1612 	u32	ant_sum[7];
1613 	u32	ant_cnt[7];
1614 	u32	ant_ave[7];
1615 	u8	fat_state;
1616 	u32	train_idx;
1617 	u8	antsel_a[ASSOCIATE_ENTRY_NUM];
1618 	u8	antsel_b[ASSOCIATE_ENTRY_NUM];
1619 	u8	antsel_c[ASSOCIATE_ENTRY_NUM];
1620 	u32	main_ant_sum[ASSOCIATE_ENTRY_NUM];
1621 	u32	aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1622 	u32	main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1623 	u32	aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1624 	u8	rx_idle_ant;
1625 	bool	becomelinked;
1626 };
1627 
1628 struct dm_phy_dbg_info {
1629 	char rx_snrdb[4];
1630 	u64 num_qry_phy_status;
1631 	u64 num_qry_phy_status_cck;
1632 	u64 num_qry_phy_status_ofdm;
1633 	u16 num_qry_beacon_pkt;
1634 	u16 num_non_be_pkt;
1635 	s32 rx_evm[4];
1636 };
1637 
1638 struct rtl_dm {
1639 	/*PHY status for Dynamic Management */
1640 	long entry_min_undec_sm_pwdb;
1641 	long undec_sm_cck;
1642 	long undec_sm_pwdb;	/*out dm */
1643 	long entry_max_undec_sm_pwdb;
1644 	s32 ofdm_pkt_cnt;
1645 	bool dm_initialgain_enable;
1646 	bool dynamic_txpower_enable;
1647 	bool current_turbo_edca;
1648 	bool is_any_nonbepkts;	/*out dm */
1649 	bool is_cur_rdlstate;
1650 	bool txpower_trackinginit;
1651 	bool disable_framebursting;
1652 	bool cck_inch14;
1653 	bool txpower_tracking;
1654 	bool useramask;
1655 	bool rfpath_rxenable[4];
1656 	bool inform_fw_driverctrldm;
1657 	bool current_mrc_switch;
1658 	u8 txpowercount;
1659 	u8 powerindex_backup[6];
1660 
1661 	u8 thermalvalue_rxgain;
1662 	u8 thermalvalue_iqk;
1663 	u8 thermalvalue_lck;
1664 	u8 thermalvalue;
1665 	u8 last_dtp_lvl;
1666 	u8 thermalvalue_avg[AVG_THERMAL_NUM];
1667 	u8 thermalvalue_avg_index;
1668 	bool done_txpower;
1669 	u8 dynamic_txhighpower_lvl;	/*Tx high power level */
1670 	u8 dm_flag;		/*Indicate each dynamic mechanism's status. */
1671 	u8 dm_flag_tmp;
1672 	u8 dm_type;
1673 	u8 dm_rssi_sel;
1674 	u8 txpower_track_control;
1675 	bool interrupt_migration;
1676 	bool disable_tx_int;
1677 	char ofdm_index[MAX_RF_PATH];
1678 	u8 default_ofdm_index;
1679 	u8 default_cck_index;
1680 	char cck_index;
1681 	char delta_power_index[MAX_RF_PATH];
1682 	char delta_power_index_last[MAX_RF_PATH];
1683 	char power_index_offset[MAX_RF_PATH];
1684 	char absolute_ofdm_swing_idx[MAX_RF_PATH];
1685 	char remnant_ofdm_swing_idx[MAX_RF_PATH];
1686 	char remnant_cck_idx;
1687 	bool modify_txagc_flag_path_a;
1688 	bool modify_txagc_flag_path_b;
1689 
1690 	bool one_entry_only;
1691 	struct dm_phy_dbg_info dbginfo;
1692 
1693 	/* Dynamic ATC switch */
1694 	bool atc_status;
1695 	bool large_cfo_hit;
1696 	bool is_freeze;
1697 	int cfo_tail[2];
1698 	int cfo_ave_pre;
1699 	int crystal_cap;
1700 	u8 cfo_threshold;
1701 	u32 packet_count;
1702 	u32 packet_count_pre;
1703 	u8 tx_rate;
1704 
1705 	/*88e tx power tracking*/
1706 	u8	swing_idx_ofdm[MAX_RF_PATH];
1707 	u8	swing_idx_ofdm_cur;
1708 	u8	swing_idx_ofdm_base[MAX_RF_PATH];
1709 	bool	swing_flag_ofdm;
1710 	u8	swing_idx_cck;
1711 	u8	swing_idx_cck_cur;
1712 	u8	swing_idx_cck_base;
1713 	bool	swing_flag_cck;
1714 
1715 	char	swing_diff_2g;
1716 	char	swing_diff_5g;
1717 
1718 	u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ];
1719 	u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ];
1720 	u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ];
1721 	u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ];
1722 	u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ];
1723 	u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ];
1724 	u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ];
1725 	u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ];
1726 	u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ];
1727 	u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ];
1728 	u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ];
1729 	u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ];
1730 	u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ];
1731 	u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ];
1732 
1733 	/* DMSP */
1734 	bool supp_phymode_switch;
1735 
1736 	/* DulMac */
1737 	struct fast_ant_training fat_table;
1738 
1739 	u8	resp_tx_path;
1740 	u8	path_sel;
1741 	u32	patha_sum;
1742 	u32	pathb_sum;
1743 	u32	patha_cnt;
1744 	u32	pathb_cnt;
1745 
1746 	u8 pre_channel;
1747 	u8 *p_channel;
1748 	u8 linked_interval;
1749 
1750 	u64 last_tx_ok_cnt;
1751 	u64 last_rx_ok_cnt;
1752 };
1753 
1754 #define	EFUSE_MAX_LOGICAL_SIZE			512
1755 
1756 struct rtl_efuse {
1757 	bool autoLoad_ok;
1758 	bool bootfromefuse;
1759 	u16 max_physical_size;
1760 
1761 	u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1762 	u16 efuse_usedbytes;
1763 	u8 efuse_usedpercentage;
1764 #ifdef EFUSE_REPG_WORKAROUND
1765 	bool efuse_re_pg_sec1flag;
1766 	u8 efuse_re_pg_data[8];
1767 #endif
1768 
1769 	u8 autoload_failflag;
1770 	u8 autoload_status;
1771 
1772 	short epromtype;
1773 	u16 eeprom_vid;
1774 	u16 eeprom_did;
1775 	u16 eeprom_svid;
1776 	u16 eeprom_smid;
1777 	u8 eeprom_oemid;
1778 	u16 eeprom_channelplan;
1779 	u8 eeprom_version;
1780 	u8 board_type;
1781 	u8 external_pa;
1782 
1783 	u8 dev_addr[6];
1784 	u8 wowlan_enable;
1785 	u8 antenna_div_cfg;
1786 	u8 antenna_div_type;
1787 
1788 	bool txpwr_fromeprom;
1789 	u8 eeprom_crystalcap;
1790 	u8 eeprom_tssi[2];
1791 	u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1792 	u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1793 	u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1794 	u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1795 	u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1796 	u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1797 
1798 	u8 internal_pa_5g[2];	/* pathA / pathB */
1799 	u8 eeprom_c9;
1800 	u8 eeprom_cc;
1801 
1802 	/*For power group */
1803 	u8 eeprom_pwrgroup[2][3];
1804 	u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1805 	u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1806 
1807 	u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1808 	/*For HT 40MHZ pwr */
1809 	u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1810 	/*For HT 40MHZ pwr */
1811 	u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1812 
1813 	/*--------------------------------------------------------*
1814 	 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1815 	 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1816 	 * define new arrays in Windows code.
1817 	 * BUT, in linux code, we use the same array for all ICs.
1818 	 *
1819 	 * The Correspondance relation between two arrays is:
1820 	 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1821 	 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1822 	 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1823 	 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1824 	 *
1825 	 * Sizes of these arrays are decided by the larger ones.
1826 	 */
1827 	char txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1828 	char txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1829 	char txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1830 	char txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1831 
1832 	u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1833 	u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1834 	char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1835 	char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1836 	char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1837 	char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1838 
1839 	u8 txpwr_safetyflag;			/* Band edge enable flag */
1840 	u16 eeprom_txpowerdiff;
1841 	u8 legacy_httxpowerdiff;	/* Legacy to HT rate power diff */
1842 	u8 antenna_txpwdiff[3];
1843 
1844 	u8 eeprom_regulatory;
1845 	u8 eeprom_thermalmeter;
1846 	u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1847 	u16 tssi_13dbm;
1848 	u8 crystalcap;		/* CrystalCap. */
1849 	u8 delta_iqk;
1850 	u8 delta_lck;
1851 
1852 	u8 legacy_ht_txpowerdiff;	/*Legacy to HT rate power diff */
1853 	bool apk_thermalmeterignore;
1854 
1855 	bool b1x1_recvcombine;
1856 	bool b1ss_support;
1857 
1858 	/*channel plan */
1859 	u8 channel_plan;
1860 };
1861 
1862 struct rtl_ps_ctl {
1863 	bool pwrdomain_protect;
1864 	bool in_powersavemode;
1865 	bool rfchange_inprogress;
1866 	bool swrf_processing;
1867 	bool hwradiooff;
1868 	/*
1869 	 * just for PCIE ASPM
1870 	 * If it supports ASPM, Offset[560h] = 0x40,
1871 	 * otherwise Offset[560h] = 0x00.
1872 	 * */
1873 	bool support_aspm;
1874 	bool support_backdoor;
1875 
1876 	/*for LPS */
1877 	enum rt_psmode dot11_psmode;	/*Power save mode configured. */
1878 	bool swctrl_lps;
1879 	bool leisure_ps;
1880 	bool fwctrl_lps;
1881 	u8 fwctrl_psmode;
1882 	/*For Fw control LPS mode */
1883 	u8 reg_fwctrl_lps;
1884 	/*Record Fw PS mode status. */
1885 	bool fw_current_inpsmode;
1886 	u8 reg_max_lps_awakeintvl;
1887 	bool report_linked;
1888 	bool low_power_enable;/*for 32k*/
1889 
1890 	/*for IPS */
1891 	bool inactiveps;
1892 
1893 	u32 rfoff_reason;
1894 
1895 	/*RF OFF Level */
1896 	u32 cur_ps_level;
1897 	u32 reg_rfps_level;
1898 
1899 	/*just for PCIE ASPM */
1900 	u8 const_amdpci_aspm;
1901 	bool pwrdown_mode;
1902 
1903 	enum rf_pwrstate inactive_pwrstate;
1904 	enum rf_pwrstate rfpwr_state;	/*cur power state */
1905 
1906 	/* for SW LPS*/
1907 	bool sw_ps_enabled;
1908 	bool state;
1909 	bool state_inap;
1910 	bool multi_buffered;
1911 	u16 nullfunc_seq;
1912 	unsigned int dtim_counter;
1913 	unsigned int sleep_ms;
1914 	unsigned long last_sleep_jiffies;
1915 	unsigned long last_awake_jiffies;
1916 	unsigned long last_delaylps_stamp_jiffies;
1917 	unsigned long last_dtim;
1918 	unsigned long last_beacon;
1919 	unsigned long last_action;
1920 	unsigned long last_slept;
1921 
1922 	/*For P2P PS */
1923 	struct rtl_p2p_ps_info p2p_ps_info;
1924 	u8 pwr_mode;
1925 	u8 smart_ps;
1926 
1927 	/* wake up on line */
1928 	u8 wo_wlan_mode;
1929 	u8 arp_offload_enable;
1930 	u8 gtk_offload_enable;
1931 	/* Used for WOL, indicates the reason for waking event.*/
1932 	u32 wakeup_reason;
1933 	/* Record the last waking time for comparison with setting key. */
1934 	u64 last_wakeup_time;
1935 };
1936 
1937 struct rtl_stats {
1938 	u8 psaddr[ETH_ALEN];
1939 	u32 mac_time[2];
1940 	s8 rssi;
1941 	u8 signal;
1942 	u8 noise;
1943 	u8 rate;		/* hw desc rate */
1944 	u8 received_channel;
1945 	u8 control;
1946 	u8 mask;
1947 	u8 freq;
1948 	u16 len;
1949 	u64 tsf;
1950 	u32 beacon_time;
1951 	u8 nic_type;
1952 	u16 length;
1953 	u8 signalquality;	/*in 0-100 index. */
1954 	/*
1955 	 * Real power in dBm for this packet,
1956 	 * no beautification and aggregation.
1957 	 * */
1958 	s32 recvsignalpower;
1959 	s8 rxpower;		/*in dBm Translate from PWdB */
1960 	u8 signalstrength;	/*in 0-100 index. */
1961 	u16 hwerror:1;
1962 	u16 crc:1;
1963 	u16 icv:1;
1964 	u16 shortpreamble:1;
1965 	u16 antenna:1;
1966 	u16 decrypted:1;
1967 	u16 wakeup:1;
1968 	u32 timestamp_low;
1969 	u32 timestamp_high;
1970 	bool shift;
1971 
1972 	u8 rx_drvinfo_size;
1973 	u8 rx_bufshift;
1974 	bool isampdu;
1975 	bool isfirst_ampdu;
1976 	bool rx_is40Mhzpacket;
1977 	u8 rx_packet_bw;
1978 	u32 rx_pwdb_all;
1979 	u8 rx_mimo_signalstrength[4];	/*in 0~100 index */
1980 	s8 rx_mimo_signalquality[4];
1981 	u8 rx_mimo_evm_dbm[4];
1982 	u16 cfo_short[4];		/* per-path's Cfo_short */
1983 	u16 cfo_tail[4];
1984 
1985 	s8 rx_mimo_sig_qual[4];
1986 	u8 rx_pwr[4]; /* per-path's pwdb */
1987 	u8 rx_snr[4]; /* per-path's SNR */
1988 	u8 bandwidth;
1989 	u8 bt_coex_pwr_adjust;
1990 	bool packet_matchbssid;
1991 	bool is_cck;
1992 	bool is_ht;
1993 	bool packet_toself;
1994 	bool packet_beacon;	/*for rssi */
1995 	char cck_adc_pwdb[4];	/*for rx path selection */
1996 
1997 	bool is_vht;
1998 	bool is_short_gi;
1999 	u8 vht_nss;
2000 
2001 	u8 packet_report_type;
2002 
2003 	u32 macid;
2004 	u8 wake_match;
2005 	u32 bt_rx_rssi_percentage;
2006 	u32 macid_valid_entry[2];
2007 };
2008 
2009 
2010 struct rt_link_detect {
2011 	/* count for roaming */
2012 	u32 bcn_rx_inperiod;
2013 	u32 roam_times;
2014 
2015 	u32 num_tx_in4period[4];
2016 	u32 num_rx_in4period[4];
2017 
2018 	u32 num_tx_inperiod;
2019 	u32 num_rx_inperiod;
2020 
2021 	bool busytraffic;
2022 	bool tx_busy_traffic;
2023 	bool rx_busy_traffic;
2024 	bool higher_busytraffic;
2025 	bool higher_busyrxtraffic;
2026 
2027 	u32 tidtx_in4period[MAX_TID_COUNT][4];
2028 	u32 tidtx_inperiod[MAX_TID_COUNT];
2029 	bool higher_busytxtraffic[MAX_TID_COUNT];
2030 };
2031 
2032 struct rtl_tcb_desc {
2033 	u8 packet_bw:2;
2034 	u8 multicast:1;
2035 	u8 broadcast:1;
2036 
2037 	u8 rts_stbc:1;
2038 	u8 rts_enable:1;
2039 	u8 cts_enable:1;
2040 	u8 rts_use_shortpreamble:1;
2041 	u8 rts_use_shortgi:1;
2042 	u8 rts_sc:1;
2043 	u8 rts_bw:1;
2044 	u8 rts_rate;
2045 
2046 	u8 use_shortgi:1;
2047 	u8 use_shortpreamble:1;
2048 	u8 use_driver_rate:1;
2049 	u8 disable_ratefallback:1;
2050 
2051 	u8 ratr_index;
2052 	u8 mac_id;
2053 	u8 hw_rate;
2054 
2055 	u8 last_inipkt:1;
2056 	u8 cmd_or_init:1;
2057 	u8 queue_index;
2058 
2059 	/* early mode */
2060 	u8 empkt_num;
2061 	/* The max value by HW */
2062 	u32 empkt_len[10];
2063 	bool tx_enable_sw_calc_duration;
2064 };
2065 
2066 struct rtl92c_firmware_header;
2067 
2068 struct rtl_wow_pattern {
2069 	u8 type;
2070 	u16 crc;
2071 	u32 mask[4];
2072 };
2073 
2074 struct rtl8723e_firmware_header;
2075 
2076 struct rtl_hal_ops {
2077 	int (*init_sw_vars) (struct ieee80211_hw *hw);
2078 	void (*deinit_sw_vars) (struct ieee80211_hw *hw);
2079 	void (*read_chip_version)(struct ieee80211_hw *hw);
2080 	void (*read_eeprom_info) (struct ieee80211_hw *hw);
2081 	void (*interrupt_recognized) (struct ieee80211_hw *hw,
2082 				      u32 *p_inta, u32 *p_intb);
2083 	int (*hw_init) (struct ieee80211_hw *hw);
2084 	void (*hw_disable) (struct ieee80211_hw *hw);
2085 	void (*hw_suspend) (struct ieee80211_hw *hw);
2086 	void (*hw_resume) (struct ieee80211_hw *hw);
2087 	void (*enable_interrupt) (struct ieee80211_hw *hw);
2088 	void (*disable_interrupt) (struct ieee80211_hw *hw);
2089 	int (*set_network_type) (struct ieee80211_hw *hw,
2090 				 enum nl80211_iftype type);
2091 	void (*set_chk_bssid)(struct ieee80211_hw *hw,
2092 				bool check_bssid);
2093 	void (*set_bw_mode) (struct ieee80211_hw *hw,
2094 			     enum nl80211_channel_type ch_type);
2095 	 u8(*switch_channel) (struct ieee80211_hw *hw);
2096 	void (*set_qos) (struct ieee80211_hw *hw, int aci);
2097 	void (*set_bcn_reg) (struct ieee80211_hw *hw);
2098 	void (*set_bcn_intv) (struct ieee80211_hw *hw);
2099 	void (*update_interrupt_mask) (struct ieee80211_hw *hw,
2100 				       u32 add_msr, u32 rm_msr);
2101 	void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2102 	void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2103 	void (*update_rate_tbl) (struct ieee80211_hw *hw,
2104 			      struct ieee80211_sta *sta, u8 rssi_level);
2105 	void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2106 				    u8 *desc, u8 queue_index,
2107 				    struct sk_buff *skb, dma_addr_t addr);
2108 	void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
2109 	u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2110 					 u8 queue_index);
2111 	void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2112 				u8 queue_index);
2113 	void (*fill_tx_desc) (struct ieee80211_hw *hw,
2114 			      struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2115 			      u8 *pbd_desc_tx,
2116 			      struct ieee80211_tx_info *info,
2117 			      struct ieee80211_sta *sta,
2118 			      struct sk_buff *skb, u8 hw_queue,
2119 			      struct rtl_tcb_desc *ptcb_desc);
2120 	void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
2121 				  u32 buffer_len, bool bIsPsPoll);
2122 	void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
2123 				 bool firstseg, bool lastseg,
2124 				 struct sk_buff *skb);
2125 	bool (*query_rx_desc) (struct ieee80211_hw *hw,
2126 			       struct rtl_stats *stats,
2127 			       struct ieee80211_rx_status *rx_status,
2128 			       u8 *pdesc, struct sk_buff *skb);
2129 	void (*set_channel_access) (struct ieee80211_hw *hw);
2130 	bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
2131 	void (*dm_watchdog) (struct ieee80211_hw *hw);
2132 	void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
2133 	bool (*set_rf_power_state) (struct ieee80211_hw *hw,
2134 				    enum rf_pwrstate rfpwr_state);
2135 	void (*led_control) (struct ieee80211_hw *hw,
2136 			     enum led_ctl_mode ledaction);
2137 	void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2138 			 u8 desc_name, u8 *val);
2139 	u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
2140 	bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
2141 				   u8 hw_queue, u16 index);
2142 	void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
2143 	void (*enable_hw_sec) (struct ieee80211_hw *hw);
2144 	void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
2145 			 u8 *macaddr, bool is_group, u8 enc_algo,
2146 			 bool is_wepkey, bool clear_all);
2147 	void (*init_sw_leds) (struct ieee80211_hw *hw);
2148 	void (*deinit_sw_leds) (struct ieee80211_hw *hw);
2149 	u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2150 	void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2151 			   u32 data);
2152 	u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2153 			  u32 regaddr, u32 bitmask);
2154 	void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2155 			   u32 regaddr, u32 bitmask, u32 data);
2156 	void (*linked_set_reg) (struct ieee80211_hw *hw);
2157 	void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
2158 	void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
2159 	void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
2160 	bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
2161 	void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
2162 					    u8 *powerlevel);
2163 	void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
2164 					     u8 *ppowerlevel, u8 channel);
2165 	bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
2166 					   u8 configtype);
2167 	bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
2168 					     u8 configtype);
2169 	void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
2170 	void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
2171 	void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
2172 	void (*c2h_command_handle) (struct ieee80211_hw *hw);
2173 	void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
2174 					     bool mstate);
2175 	void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
2176 	void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
2177 			      u32 cmd_len, u8 *p_cmdbuffer);
2178 	bool (*get_btc_status) (void);
2179 	bool (*is_fw_header)(struct rtl8723e_firmware_header *hdr);
2180 	u32 (*rx_command_packet)(struct ieee80211_hw *hw,
2181 				 struct rtl_stats status, struct sk_buff *skb);
2182 	void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2183 				   struct rtl_wow_pattern *rtl_pattern,
2184 				   u8 index);
2185 	u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2186 };
2187 
2188 struct rtl_intf_ops {
2189 	/*com */
2190 	void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2191 	int (*adapter_start) (struct ieee80211_hw *hw);
2192 	void (*adapter_stop) (struct ieee80211_hw *hw);
2193 	bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2194 				 struct rtl_priv **buddy_priv);
2195 
2196 	int (*adapter_tx) (struct ieee80211_hw *hw,
2197 			   struct ieee80211_sta *sta,
2198 			   struct sk_buff *skb,
2199 			   struct rtl_tcb_desc *ptcb_desc);
2200 	void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2201 	int (*reset_trx_ring) (struct ieee80211_hw *hw);
2202 	bool (*waitq_insert) (struct ieee80211_hw *hw,
2203 			      struct ieee80211_sta *sta,
2204 			      struct sk_buff *skb);
2205 
2206 	/*pci */
2207 	void (*disable_aspm) (struct ieee80211_hw *hw);
2208 	void (*enable_aspm) (struct ieee80211_hw *hw);
2209 
2210 	/*usb */
2211 };
2212 
2213 struct rtl_mod_params {
2214 	/* default: 0 = using hardware encryption */
2215 	bool sw_crypto;
2216 
2217 	/* default: 0 = DBG_EMERG (0)*/
2218 	int debug;
2219 
2220 	/* default: 1 = using no linked power save */
2221 	bool inactiveps;
2222 
2223 	/* default: 1 = using linked sw power save */
2224 	bool swctrl_lps;
2225 
2226 	/* default: 1 = using linked fw power save */
2227 	bool fwctrl_lps;
2228 
2229 	/* default: 0 = not using MSI interrupts mode
2230 	 * submodules should set their own default value
2231 	 */
2232 	bool msi_support;
2233 
2234 	/* default 0: 1 means disable */
2235 	bool disable_watchdog;
2236 
2237 	/* default 0: 1 means do not disable interrupts */
2238 	bool int_clear;
2239 
2240 	/* select antenna */
2241 	int ant_sel;
2242 };
2243 
2244 struct rtl_hal_usbint_cfg {
2245 	/* data - rx */
2246 	u32 in_ep_num;
2247 	u32 rx_urb_num;
2248 	u32 rx_max_size;
2249 
2250 	/* op - rx */
2251 	void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2252 	void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2253 				     struct sk_buff_head *);
2254 
2255 	/* tx */
2256 	void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2257 	int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2258 			       struct sk_buff *);
2259 	struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2260 						struct sk_buff_head *);
2261 
2262 	/* endpoint mapping */
2263 	int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2264 	u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2265 };
2266 
2267 struct rtl_hal_cfg {
2268 	u8 bar_id;
2269 	bool write_readback;
2270 	char *name;
2271 	char *fw_name;
2272 	char *alt_fw_name;
2273 	char *wowlan_fw_name;
2274 	struct rtl_hal_ops *ops;
2275 	struct rtl_mod_params *mod_params;
2276 	struct rtl_hal_usbint_cfg *usb_interface_cfg;
2277 
2278 	/*this map used for some registers or vars
2279 	   defined int HAL but used in MAIN */
2280 	u32 maps[RTL_VAR_MAP_MAX];
2281 
2282 };
2283 
2284 struct rtl_locks {
2285 	/* mutex */
2286 	struct mutex conf_mutex;
2287 	struct mutex ps_mutex;
2288 
2289 	/*spin lock */
2290 	spinlock_t ips_lock;
2291 	spinlock_t irq_th_lock;
2292 	spinlock_t irq_pci_lock;
2293 	spinlock_t tx_lock;
2294 	spinlock_t h2c_lock;
2295 	spinlock_t rf_ps_lock;
2296 	spinlock_t rf_lock;
2297 	spinlock_t lps_lock;
2298 	spinlock_t waitq_lock;
2299 	spinlock_t entry_list_lock;
2300 	spinlock_t usb_lock;
2301 
2302 	/*FW clock change */
2303 	spinlock_t fw_ps_lock;
2304 
2305 	/*Dual mac*/
2306 	spinlock_t cck_and_rw_pagea_lock;
2307 
2308 	/*Easy concurrent*/
2309 	spinlock_t check_sendpkt_lock;
2310 
2311 	spinlock_t iqk_lock;
2312 };
2313 
2314 struct rtl_works {
2315 	struct ieee80211_hw *hw;
2316 
2317 	/*timer */
2318 	struct timer_list watchdog_timer;
2319 	struct timer_list dualmac_easyconcurrent_retrytimer;
2320 	struct timer_list fw_clockoff_timer;
2321 	struct timer_list fast_antenna_training_timer;
2322 	/*task */
2323 	struct tasklet_struct irq_tasklet;
2324 	struct tasklet_struct irq_prepare_bcn_tasklet;
2325 
2326 	/*work queue */
2327 	struct workqueue_struct *rtl_wq;
2328 	struct delayed_work watchdog_wq;
2329 	struct delayed_work ips_nic_off_wq;
2330 
2331 	/* For SW LPS */
2332 	struct delayed_work ps_work;
2333 	struct delayed_work ps_rfon_wq;
2334 	struct delayed_work fwevt_wq;
2335 
2336 	struct work_struct lps_change_work;
2337 	struct work_struct fill_h2c_cmd;
2338 };
2339 
2340 struct rtl_debug {
2341 	u32 dbgp_type[DBGP_TYPE_MAX];
2342 	int global_debuglevel;
2343 	u64 global_debugcomponents;
2344 
2345 	/* add for proc debug */
2346 	struct proc_dir_entry *proc_dir;
2347 	char proc_name[20];
2348 };
2349 
2350 #define MIMO_PS_STATIC			0
2351 #define MIMO_PS_DYNAMIC			1
2352 #define MIMO_PS_NOLIMIT			3
2353 
2354 struct rtl_dualmac_easy_concurrent_ctl {
2355 	enum band_type currentbandtype_backfordmdp;
2356 	bool close_bbandrf_for_dmsp;
2357 	bool change_to_dmdp;
2358 	bool change_to_dmsp;
2359 	bool switch_in_process;
2360 };
2361 
2362 struct rtl_dmsp_ctl {
2363 	bool activescan_for_slaveofdmsp;
2364 	bool scan_for_anothermac_fordmsp;
2365 	bool scan_for_itself_fordmsp;
2366 	bool writedig_for_anothermacofdmsp;
2367 	u32 curdigvalue_for_anothermacofdmsp;
2368 	bool changecckpdstate_for_anothermacofdmsp;
2369 	u8 curcckpdstate_for_anothermacofdmsp;
2370 	bool changetxhighpowerlvl_for_anothermacofdmsp;
2371 	u8 curtxhighlvl_for_anothermacofdmsp;
2372 	long rssivalmin_for_anothermacofdmsp;
2373 };
2374 
2375 struct ps_t {
2376 	u8 pre_ccastate;
2377 	u8 cur_ccasate;
2378 	u8 pre_rfstate;
2379 	u8 cur_rfstate;
2380 	u8 initialize;
2381 	long rssi_val_min;
2382 };
2383 
2384 struct dig_t {
2385 	u32 rssi_lowthresh;
2386 	u32 rssi_highthresh;
2387 	u32 fa_lowthresh;
2388 	u32 fa_highthresh;
2389 	long last_min_undec_pwdb_for_dm;
2390 	long rssi_highpower_lowthresh;
2391 	long rssi_highpower_highthresh;
2392 	u32 recover_cnt;
2393 	u32 pre_igvalue;
2394 	u32 cur_igvalue;
2395 	long rssi_val;
2396 	u8 dig_enable_flag;
2397 	u8 dig_ext_port_stage;
2398 	u8 dig_algorithm;
2399 	u8 dig_twoport_algorithm;
2400 	u8 dig_dbgmode;
2401 	u8 dig_slgorithm_switch;
2402 	u8 cursta_cstate;
2403 	u8 presta_cstate;
2404 	u8 curmultista_cstate;
2405 	u8 stop_dig;
2406 	char back_val;
2407 	char back_range_max;
2408 	char back_range_min;
2409 	u8 rx_gain_max;
2410 	u8 rx_gain_min;
2411 	u8 min_undec_pwdb_for_dm;
2412 	u8 rssi_val_min;
2413 	u8 pre_cck_cca_thres;
2414 	u8 cur_cck_cca_thres;
2415 	u8 pre_cck_pd_state;
2416 	u8 cur_cck_pd_state;
2417 	u8 pre_cck_fa_state;
2418 	u8 cur_cck_fa_state;
2419 	u8 pre_ccastate;
2420 	u8 cur_ccasate;
2421 	u8 large_fa_hit;
2422 	u8 forbidden_igi;
2423 	u8 dig_state;
2424 	u8 dig_highpwrstate;
2425 	u8 cur_sta_cstate;
2426 	u8 pre_sta_cstate;
2427 	u8 cur_ap_cstate;
2428 	u8 pre_ap_cstate;
2429 	u8 cur_pd_thstate;
2430 	u8 pre_pd_thstate;
2431 	u8 cur_cs_ratiostate;
2432 	u8 pre_cs_ratiostate;
2433 	u8 backoff_enable_flag;
2434 	char backoffval_range_max;
2435 	char backoffval_range_min;
2436 	u8 dig_min_0;
2437 	u8 dig_min_1;
2438 	u8 bt30_cur_igi;
2439 	bool media_connect_0;
2440 	bool media_connect_1;
2441 
2442 	u32 antdiv_rssi_max;
2443 	u32 rssi_max;
2444 };
2445 
2446 struct rtl_global_var {
2447 	/* from this list we can get
2448 	 * other adapter's rtl_priv */
2449 	struct list_head glb_priv_list;
2450 	spinlock_t glb_list_lock;
2451 };
2452 
2453 struct rtl_btc_info {
2454 	u8 bt_type;
2455 	u8 btcoexist;
2456 	u8 ant_num;
2457 };
2458 
2459 struct bt_coexist_info {
2460 	struct rtl_btc_ops *btc_ops;
2461 	struct rtl_btc_info btc_info;
2462 	/* EEPROM BT info. */
2463 	u8 eeprom_bt_coexist;
2464 	u8 eeprom_bt_type;
2465 	u8 eeprom_bt_ant_num;
2466 	u8 eeprom_bt_ant_isol;
2467 	u8 eeprom_bt_radio_shared;
2468 
2469 	u8 bt_coexistence;
2470 	u8 bt_ant_num;
2471 	u8 bt_coexist_type;
2472 	u8 bt_state;
2473 	u8 bt_cur_state;	/* 0:on, 1:off */
2474 	u8 bt_ant_isolation;	/* 0:good, 1:bad */
2475 	u8 bt_pape_ctrl;	/* 0:SW, 1:SW/HW dynamic */
2476 	u8 bt_service;
2477 	u8 bt_radio_shared_type;
2478 	u8 bt_rfreg_origin_1e;
2479 	u8 bt_rfreg_origin_1f;
2480 	u8 bt_rssi_state;
2481 	u32 ratio_tx;
2482 	u32 ratio_pri;
2483 	u32 bt_edca_ul;
2484 	u32 bt_edca_dl;
2485 
2486 	bool init_set;
2487 	bool bt_busy_traffic;
2488 	bool bt_traffic_mode_set;
2489 	bool bt_non_traffic_mode_set;
2490 
2491 	bool fw_coexist_all_off;
2492 	bool sw_coexist_all_off;
2493 	bool hw_coexist_all_off;
2494 	u32 cstate;
2495 	u32 previous_state;
2496 	u32 cstate_h;
2497 	u32 previous_state_h;
2498 
2499 	u8 bt_pre_rssi_state;
2500 	u8 bt_pre_rssi_state1;
2501 
2502 	u8 reg_bt_iso;
2503 	u8 reg_bt_sco;
2504 	bool balance_on;
2505 	u8 bt_active_zero_cnt;
2506 	bool cur_bt_disabled;
2507 	bool pre_bt_disabled;
2508 
2509 	u8 bt_profile_case;
2510 	u8 bt_profile_action;
2511 	bool bt_busy;
2512 	bool hold_for_bt_operation;
2513 	u8 lps_counter;
2514 };
2515 
2516 struct rtl_btc_ops {
2517 	void (*btc_init_variables) (struct rtl_priv *rtlpriv);
2518 	void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv);
2519 	void (*btc_init_hw_config) (struct rtl_priv *rtlpriv);
2520 	void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type);
2521 	void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2522 	void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype);
2523 	void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action);
2524 	void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv,
2525 					enum rt_media_status mstatus);
2526 	void (*btc_periodical) (struct rtl_priv *rtlpriv);
2527 	void (*btc_halt_notify) (void);
2528 	void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv,
2529 				   u8 *tmp_buf, u8 length);
2530 	bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv);
2531 	bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv);
2532 	bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv);
2533 	void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2534 					  u8 pkt_type);
2535 };
2536 
2537 struct proxim {
2538 	bool proxim_on;
2539 
2540 	void *proximity_priv;
2541 	int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2542 			 struct sk_buff *skb);
2543 	u8  (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2544 };
2545 
2546 struct rtl_priv {
2547 	struct ieee80211_hw *hw;
2548 	struct completion firmware_loading_complete;
2549 	struct list_head list;
2550 	struct rtl_priv *buddy_priv;
2551 	struct rtl_global_var *glb_var;
2552 	struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2553 	struct rtl_dmsp_ctl dmsp_ctl;
2554 	struct rtl_locks locks;
2555 	struct rtl_works works;
2556 	struct rtl_mac mac80211;
2557 	struct rtl_hal rtlhal;
2558 	struct rtl_regulatory regd;
2559 	struct rtl_rfkill rfkill;
2560 	struct rtl_io io;
2561 	struct rtl_phy phy;
2562 	struct rtl_dm dm;
2563 	struct rtl_security sec;
2564 	struct rtl_efuse efuse;
2565 
2566 	struct rtl_ps_ctl psc;
2567 	struct rate_adaptive ra;
2568 	struct dynamic_primary_cca primarycca;
2569 	struct wireless_stats stats;
2570 	struct rt_link_detect link_info;
2571 	struct false_alarm_statistics falsealm_cnt;
2572 
2573 	struct rtl_rate_priv *rate_priv;
2574 
2575 	/* sta entry list for ap adhoc or mesh */
2576 	struct list_head entry_list;
2577 
2578 	struct rtl_debug dbg;
2579 	int max_fw_size;
2580 
2581 	/*
2582 	 *hal_cfg : for diff cards
2583 	 *intf_ops : for diff interrface usb/pcie
2584 	 */
2585 	struct rtl_hal_cfg *cfg;
2586 	struct rtl_intf_ops *intf_ops;
2587 
2588 	/*this var will be set by set_bit,
2589 	   and was used to indicate status of
2590 	   interface or hardware */
2591 	unsigned long status;
2592 
2593 	/* tables for dm */
2594 	struct dig_t dm_digtable;
2595 	struct ps_t dm_pstable;
2596 
2597 	u32 reg_874;
2598 	u32 reg_c70;
2599 	u32 reg_85c;
2600 	u32 reg_a74;
2601 	bool reg_init;	/* true if regs saved */
2602 	bool bt_operation_on;
2603 	__le32 *usb_data;
2604 	int usb_data_index;
2605 	bool initialized;
2606 	bool enter_ps;	/* true when entering PS */
2607 	u8 rate_mask[5];
2608 
2609 	/* intel Proximity, should be alloc mem
2610 	 * in intel Proximity module and can only
2611 	 * be used in intel Proximity mode
2612 	 */
2613 	struct proxim proximity;
2614 
2615 	/*for bt coexist use*/
2616 	struct bt_coexist_info btcoexist;
2617 
2618 	/* separate 92ee from other ICs,
2619 	 * 92ee use new trx flow.
2620 	 */
2621 	bool use_new_trx_flow;
2622 
2623 #ifdef CONFIG_PM
2624 	struct wiphy_wowlan_support wowlan;
2625 #endif
2626 	/*This must be the last item so
2627 	   that it points to the data allocated
2628 	   beyond  this structure like:
2629 	   rtl_pci_priv or rtl_usb_priv */
2630 	u8 priv[0] __aligned(sizeof(void *));
2631 };
2632 
2633 #define rtl_priv(hw)		(((struct rtl_priv *)(hw)->priv))
2634 #define rtl_mac(rtlpriv)	(&((rtlpriv)->mac80211))
2635 #define rtl_hal(rtlpriv)	(&((rtlpriv)->rtlhal))
2636 #define rtl_efuse(rtlpriv)	(&((rtlpriv)->efuse))
2637 #define rtl_psc(rtlpriv)	(&((rtlpriv)->psc))
2638 
2639 
2640 /***************************************
2641     Bluetooth Co-existence Related
2642 ****************************************/
2643 
2644 enum bt_ant_num {
2645 	ANT_X2 = 0,
2646 	ANT_X1 = 1,
2647 };
2648 
2649 enum bt_co_type {
2650 	BT_2WIRE = 0,
2651 	BT_ISSC_3WIRE = 1,
2652 	BT_ACCEL = 2,
2653 	BT_CSR_BC4 = 3,
2654 	BT_CSR_BC8 = 4,
2655 	BT_RTL8756 = 5,
2656 	BT_RTL8723A = 6,
2657 	BT_RTL8821A = 7,
2658 	BT_RTL8723B = 8,
2659 	BT_RTL8192E = 9,
2660 	BT_RTL8812A = 11,
2661 };
2662 
2663 enum bt_total_ant_num {
2664 	ANT_TOTAL_X2 = 0,
2665 	ANT_TOTAL_X1 = 1
2666 };
2667 
2668 enum bt_cur_state {
2669 	BT_OFF = 0,
2670 	BT_ON = 1,
2671 };
2672 
2673 enum bt_service_type {
2674 	BT_SCO = 0,
2675 	BT_A2DP = 1,
2676 	BT_HID = 2,
2677 	BT_HID_IDLE = 3,
2678 	BT_SCAN = 4,
2679 	BT_IDLE = 5,
2680 	BT_OTHER_ACTION = 6,
2681 	BT_BUSY = 7,
2682 	BT_OTHERBUSY = 8,
2683 	BT_PAN = 9,
2684 };
2685 
2686 enum bt_radio_shared {
2687 	BT_RADIO_SHARED = 0,
2688 	BT_RADIO_INDIVIDUAL = 1,
2689 };
2690 
2691 
2692 /****************************************
2693 	mem access macro define start
2694 	Call endian free function when
2695 	1. Read/write packet content.
2696 	2. Before write integer to IO.
2697 	3. After read integer from IO.
2698 ****************************************/
2699 /* Convert little data endian to host ordering */
2700 #define EF1BYTE(_val)		\
2701 	((u8)(_val))
2702 #define EF2BYTE(_val)		\
2703 	(le16_to_cpu(_val))
2704 #define EF4BYTE(_val)		\
2705 	(le32_to_cpu(_val))
2706 
2707 /* Read data from memory */
2708 #define READEF1BYTE(_ptr)	\
2709 	EF1BYTE(*((u8 *)(_ptr)))
2710 /* Read le16 data from memory and convert to host ordering */
2711 #define READEF2BYTE(_ptr)	\
2712 	EF2BYTE(*(_ptr))
2713 #define READEF4BYTE(_ptr)	\
2714 	EF4BYTE(*(_ptr))
2715 
2716 /* Write data to memory */
2717 #define WRITEEF1BYTE(_ptr, _val)	\
2718 	(*((u8 *)(_ptr))) = EF1BYTE(_val)
2719 /* Write le16 data to memory in host ordering */
2720 #define WRITEEF2BYTE(_ptr, _val)	\
2721 	(*((u16 *)(_ptr))) = EF2BYTE(_val)
2722 #define WRITEEF4BYTE(_ptr, _val)	\
2723 	(*((u32 *)(_ptr))) = EF2BYTE(_val)
2724 
2725 /* Create a bit mask
2726  * Examples:
2727  * BIT_LEN_MASK_32(0) => 0x00000000
2728  * BIT_LEN_MASK_32(1) => 0x00000001
2729  * BIT_LEN_MASK_32(2) => 0x00000003
2730  * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2731  */
2732 #define BIT_LEN_MASK_32(__bitlen)	 \
2733 	(0xFFFFFFFF >> (32 - (__bitlen)))
2734 #define BIT_LEN_MASK_16(__bitlen)	 \
2735 	(0xFFFF >> (16 - (__bitlen)))
2736 #define BIT_LEN_MASK_8(__bitlen) \
2737 	(0xFF >> (8 - (__bitlen)))
2738 
2739 /* Create an offset bit mask
2740  * Examples:
2741  * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2742  * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2743  */
2744 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2745 	(BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2746 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2747 	(BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2748 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2749 	(BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2750 
2751 /*Description:
2752  * Return 4-byte value in host byte ordering from
2753  * 4-byte pointer in little-endian system.
2754  */
2755 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2756 	(EF4BYTE(*((__le32 *)(__pstart))))
2757 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2758 	(EF2BYTE(*((__le16 *)(__pstart))))
2759 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2760 	(EF1BYTE(*((u8 *)(__pstart))))
2761 
2762 /*Description:
2763 Translate subfield (continuous bits in little-endian) of 4-byte
2764 value to host byte ordering.*/
2765 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2766 	( \
2767 		(LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset))  & \
2768 		BIT_LEN_MASK_32(__bitlen) \
2769 	)
2770 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2771 	( \
2772 		(LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2773 		BIT_LEN_MASK_16(__bitlen) \
2774 	)
2775 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2776 	( \
2777 		(LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2778 		BIT_LEN_MASK_8(__bitlen) \
2779 	)
2780 
2781 /* Description:
2782  * Mask subfield (continuous bits in little-endian) of 4-byte value
2783  * and return the result in 4-byte value in host byte ordering.
2784  */
2785 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2786 	( \
2787 		LE_P4BYTE_TO_HOST_4BYTE(__pstart)  & \
2788 		(~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2789 	)
2790 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2791 	( \
2792 		LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2793 		(~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2794 	)
2795 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2796 	( \
2797 		LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2798 		(~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2799 	)
2800 
2801 /* Description:
2802  * Set subfield of little-endian 4-byte value to specified value.
2803  */
2804 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2805 	*((u32 *)(__pstart)) = \
2806 	( \
2807 		LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2808 		((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2809 	);
2810 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2811 	*((u16 *)(__pstart)) = \
2812 	( \
2813 		LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2814 		((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2815 	);
2816 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2817 	*((u8 *)(__pstart)) = EF1BYTE \
2818 	( \
2819 		LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2820 		((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2821 	);
2822 
2823 #define	N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2824 	(__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2825 
2826 /****************************************
2827 	mem access macro define end
2828 ****************************************/
2829 
2830 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2831 
2832 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2833 #define RTL_WATCH_DOG_TIME	2000
2834 #define MSECS(t)		msecs_to_jiffies(t)
2835 #define WLAN_FC_GET_VERS(fc)	(le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2836 #define WLAN_FC_GET_TYPE(fc)	(le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2837 #define WLAN_FC_GET_STYPE(fc)	(le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2838 #define WLAN_FC_MORE_DATA(fc)	(le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2839 #define rtl_dm(rtlpriv)		(&((rtlpriv)->dm))
2840 
2841 #define	RT_RF_OFF_LEVL_ASPM		BIT(0)	/*PCI ASPM */
2842 #define	RT_RF_OFF_LEVL_CLK_REQ		BIT(1)	/*PCI clock request */
2843 #define	RT_RF_OFF_LEVL_PCI_D3		BIT(2)	/*PCI D3 mode */
2844 /*NIC halt, re-initialize hw parameters*/
2845 #define	RT_RF_OFF_LEVL_HALT_NIC		BIT(3)
2846 #define	RT_RF_OFF_LEVL_FREE_FW		BIT(4)	/*FW free, re-download the FW */
2847 #define	RT_RF_OFF_LEVL_FW_32K		BIT(5)	/*FW in 32k */
2848 /*Always enable ASPM and Clock Req in initialization.*/
2849 #define	RT_RF_PS_LEVEL_ALWAYS_ASPM	BIT(6)
2850 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2851 #define	RT_PS_LEVEL_ASPM		BIT(7)
2852 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2853 #define	RT_RF_LPS_DISALBE_2R		BIT(30)
2854 #define	RT_RF_LPS_LEVEL_ASPM		BIT(31)	/*LPS with ASPM */
2855 #define	RT_IN_PS_LEVEL(ppsc, _ps_flg)		\
2856 	((ppsc->cur_ps_level & _ps_flg) ? true : false)
2857 #define	RT_CLEAR_PS_LEVEL(ppsc, _ps_flg)	\
2858 	(ppsc->cur_ps_level &= (~(_ps_flg)))
2859 #define	RT_SET_PS_LEVEL(ppsc, _ps_flg)		\
2860 	(ppsc->cur_ps_level |= _ps_flg)
2861 
2862 #define container_of_dwork_rtl(x, y, z) \
2863 	container_of(container_of(x, struct delayed_work, work), y, z)
2864 
2865 #define FILL_OCTET_STRING(_os, _octet, _len)	\
2866 		(_os).octet = (u8 *)(_octet);		\
2867 		(_os).length = (_len);
2868 
2869 #define CP_MACADDR(des, src)	\
2870 	((des)[0] = (src)[0], (des)[1] = (src)[1],\
2871 	(des)[2] = (src)[2], (des)[3] = (src)[3],\
2872 	(des)[4] = (src)[4], (des)[5] = (src)[5])
2873 
2874 #define	LDPC_HT_ENABLE_RX			BIT(0)
2875 #define	LDPC_HT_ENABLE_TX			BIT(1)
2876 #define	LDPC_HT_TEST_TX_ENABLE			BIT(2)
2877 #define	LDPC_HT_CAP_TX				BIT(3)
2878 
2879 #define	STBC_HT_ENABLE_RX			BIT(0)
2880 #define	STBC_HT_ENABLE_TX			BIT(1)
2881 #define	STBC_HT_TEST_TX_ENABLE			BIT(2)
2882 #define	STBC_HT_CAP_TX				BIT(3)
2883 
2884 #define	LDPC_VHT_ENABLE_RX			BIT(0)
2885 #define	LDPC_VHT_ENABLE_TX			BIT(1)
2886 #define	LDPC_VHT_TEST_TX_ENABLE			BIT(2)
2887 #define	LDPC_VHT_CAP_TX				BIT(3)
2888 
2889 #define	STBC_VHT_ENABLE_RX			BIT(0)
2890 #define	STBC_VHT_ENABLE_TX			BIT(1)
2891 #define	STBC_VHT_TEST_TX_ENABLE			BIT(2)
2892 #define	STBC_VHT_CAP_TX				BIT(3)
2893 
rtl_read_byte(struct rtl_priv * rtlpriv,u32 addr)2894 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2895 {
2896 	return rtlpriv->io.read8_sync(rtlpriv, addr);
2897 }
2898 
rtl_read_word(struct rtl_priv * rtlpriv,u32 addr)2899 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2900 {
2901 	return rtlpriv->io.read16_sync(rtlpriv, addr);
2902 }
2903 
rtl_read_dword(struct rtl_priv * rtlpriv,u32 addr)2904 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2905 {
2906 	return rtlpriv->io.read32_sync(rtlpriv, addr);
2907 }
2908 
rtl_write_byte(struct rtl_priv * rtlpriv,u32 addr,u8 val8)2909 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2910 {
2911 	rtlpriv->io.write8_async(rtlpriv, addr, val8);
2912 
2913 	if (rtlpriv->cfg->write_readback)
2914 		rtlpriv->io.read8_sync(rtlpriv, addr);
2915 }
2916 
rtl_write_word(struct rtl_priv * rtlpriv,u32 addr,u16 val16)2917 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2918 {
2919 	rtlpriv->io.write16_async(rtlpriv, addr, val16);
2920 
2921 	if (rtlpriv->cfg->write_readback)
2922 		rtlpriv->io.read16_sync(rtlpriv, addr);
2923 }
2924 
rtl_write_dword(struct rtl_priv * rtlpriv,u32 addr,u32 val32)2925 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2926 				   u32 addr, u32 val32)
2927 {
2928 	rtlpriv->io.write32_async(rtlpriv, addr, val32);
2929 
2930 	if (rtlpriv->cfg->write_readback)
2931 		rtlpriv->io.read32_sync(rtlpriv, addr);
2932 }
2933 
rtl_get_bbreg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask)2934 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2935 				u32 regaddr, u32 bitmask)
2936 {
2937 	struct rtl_priv *rtlpriv = hw->priv;
2938 
2939 	return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2940 }
2941 
rtl_set_bbreg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask,u32 data)2942 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2943 				 u32 bitmask, u32 data)
2944 {
2945 	struct rtl_priv *rtlpriv = hw->priv;
2946 
2947 	rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2948 }
2949 
rtl_get_rfreg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask)2950 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2951 				enum radio_path rfpath, u32 regaddr,
2952 				u32 bitmask)
2953 {
2954 	struct rtl_priv *rtlpriv = hw->priv;
2955 
2956 	return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2957 }
2958 
rtl_set_rfreg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask,u32 data)2959 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2960 				 enum radio_path rfpath, u32 regaddr,
2961 				 u32 bitmask, u32 data)
2962 {
2963 	struct rtl_priv *rtlpriv = hw->priv;
2964 
2965 	rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2966 }
2967 
is_hal_stop(struct rtl_hal * rtlhal)2968 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2969 {
2970 	return (_HAL_STATE_STOP == rtlhal->state);
2971 }
2972 
set_hal_start(struct rtl_hal * rtlhal)2973 static inline void set_hal_start(struct rtl_hal *rtlhal)
2974 {
2975 	rtlhal->state = _HAL_STATE_START;
2976 }
2977 
set_hal_stop(struct rtl_hal * rtlhal)2978 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2979 {
2980 	rtlhal->state = _HAL_STATE_STOP;
2981 }
2982 
get_rf_type(struct rtl_phy * rtlphy)2983 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2984 {
2985 	return rtlphy->rf_type;
2986 }
2987 
rtl_get_hdr(struct sk_buff * skb)2988 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2989 {
2990 	return (struct ieee80211_hdr *)(skb->data);
2991 }
2992 
rtl_get_fc(struct sk_buff * skb)2993 static inline __le16 rtl_get_fc(struct sk_buff *skb)
2994 {
2995 	return rtl_get_hdr(skb)->frame_control;
2996 }
2997 
rtl_get_tid_h(struct ieee80211_hdr * hdr)2998 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2999 {
3000 	return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
3001 }
3002 
rtl_get_tid(struct sk_buff * skb)3003 static inline u16 rtl_get_tid(struct sk_buff *skb)
3004 {
3005 	return rtl_get_tid_h(rtl_get_hdr(skb));
3006 }
3007 
get_sta(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * bssid)3008 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3009 					    struct ieee80211_vif *vif,
3010 					    const u8 *bssid)
3011 {
3012 	return ieee80211_find_sta(vif, bssid);
3013 }
3014 
rtl_find_sta(struct ieee80211_hw * hw,u8 * mac_addr)3015 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3016 		u8 *mac_addr)
3017 {
3018 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3019 	return ieee80211_find_sta(mac->vif, mac_addr);
3020 }
3021 
3022 #endif
3023