1 /*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
35 */
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
41
42 #include <asm/branch.h>
43 #include <asm/inst.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
47
48 #include <asm/cpu-info.h>
49 #include <asm/processor.h>
50 #include <asm/fpu_emulator.h>
51 #include <asm/fpu.h>
52 #include <asm/mips-r2-to-r6-emul.h>
53
54 #include "ieee754.h"
55
56 /* Function which emulates a floating point instruction. */
57
58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
59 mips_instruction);
60
61 static int fpux_emu(struct pt_regs *,
62 struct mips_fpu_struct *, mips_instruction, void *__user *);
63
64 /* Control registers */
65
66 #define FPCREG_RID 0 /* $0 = revision id */
67 #define FPCREG_FCCR 25 /* $25 = fccr */
68 #define FPCREG_FEXR 26 /* $26 = fexr */
69 #define FPCREG_FENR 28 /* $28 = fenr */
70 #define FPCREG_CSR 31 /* $31 = csr */
71
72 /* convert condition code register number to csr bit */
73 const unsigned int fpucondbit[8] = {
74 FPU_CSR_COND,
75 FPU_CSR_COND1,
76 FPU_CSR_COND2,
77 FPU_CSR_COND3,
78 FPU_CSR_COND4,
79 FPU_CSR_COND5,
80 FPU_CSR_COND6,
81 FPU_CSR_COND7
82 };
83
84 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
85 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
86 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
87 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
88 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
89
90 /*
91 * This functions translates a 32-bit microMIPS instruction
92 * into a 32-bit MIPS32 instruction. Returns 0 on success
93 * and SIGILL otherwise.
94 */
microMIPS32_to_MIPS32(union mips_instruction * insn_ptr)95 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
96 {
97 union mips_instruction insn = *insn_ptr;
98 union mips_instruction mips32_insn = insn;
99 int func, fmt, op;
100
101 switch (insn.mm_i_format.opcode) {
102 case mm_ldc132_op:
103 mips32_insn.mm_i_format.opcode = ldc1_op;
104 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
105 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
106 break;
107 case mm_lwc132_op:
108 mips32_insn.mm_i_format.opcode = lwc1_op;
109 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
110 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
111 break;
112 case mm_sdc132_op:
113 mips32_insn.mm_i_format.opcode = sdc1_op;
114 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
115 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
116 break;
117 case mm_swc132_op:
118 mips32_insn.mm_i_format.opcode = swc1_op;
119 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
120 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
121 break;
122 case mm_pool32i_op:
123 /* NOTE: offset is << by 1 if in microMIPS mode. */
124 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
125 (insn.mm_i_format.rt == mm_bc1t_op)) {
126 mips32_insn.fb_format.opcode = cop1_op;
127 mips32_insn.fb_format.bc = bc_op;
128 mips32_insn.fb_format.flag =
129 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
130 } else
131 return SIGILL;
132 break;
133 case mm_pool32f_op:
134 switch (insn.mm_fp0_format.func) {
135 case mm_32f_01_op:
136 case mm_32f_11_op:
137 case mm_32f_02_op:
138 case mm_32f_12_op:
139 case mm_32f_41_op:
140 case mm_32f_51_op:
141 case mm_32f_42_op:
142 case mm_32f_52_op:
143 op = insn.mm_fp0_format.func;
144 if (op == mm_32f_01_op)
145 func = madd_s_op;
146 else if (op == mm_32f_11_op)
147 func = madd_d_op;
148 else if (op == mm_32f_02_op)
149 func = nmadd_s_op;
150 else if (op == mm_32f_12_op)
151 func = nmadd_d_op;
152 else if (op == mm_32f_41_op)
153 func = msub_s_op;
154 else if (op == mm_32f_51_op)
155 func = msub_d_op;
156 else if (op == mm_32f_42_op)
157 func = nmsub_s_op;
158 else
159 func = nmsub_d_op;
160 mips32_insn.fp6_format.opcode = cop1x_op;
161 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
162 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
163 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
164 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
165 mips32_insn.fp6_format.func = func;
166 break;
167 case mm_32f_10_op:
168 func = -1; /* Invalid */
169 op = insn.mm_fp5_format.op & 0x7;
170 if (op == mm_ldxc1_op)
171 func = ldxc1_op;
172 else if (op == mm_sdxc1_op)
173 func = sdxc1_op;
174 else if (op == mm_lwxc1_op)
175 func = lwxc1_op;
176 else if (op == mm_swxc1_op)
177 func = swxc1_op;
178
179 if (func != -1) {
180 mips32_insn.r_format.opcode = cop1x_op;
181 mips32_insn.r_format.rs =
182 insn.mm_fp5_format.base;
183 mips32_insn.r_format.rt =
184 insn.mm_fp5_format.index;
185 mips32_insn.r_format.rd = 0;
186 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
187 mips32_insn.r_format.func = func;
188 } else
189 return SIGILL;
190 break;
191 case mm_32f_40_op:
192 op = -1; /* Invalid */
193 if (insn.mm_fp2_format.op == mm_fmovt_op)
194 op = 1;
195 else if (insn.mm_fp2_format.op == mm_fmovf_op)
196 op = 0;
197 if (op != -1) {
198 mips32_insn.fp0_format.opcode = cop1_op;
199 mips32_insn.fp0_format.fmt =
200 sdps_format[insn.mm_fp2_format.fmt];
201 mips32_insn.fp0_format.ft =
202 (insn.mm_fp2_format.cc<<2) + op;
203 mips32_insn.fp0_format.fs =
204 insn.mm_fp2_format.fs;
205 mips32_insn.fp0_format.fd =
206 insn.mm_fp2_format.fd;
207 mips32_insn.fp0_format.func = fmovc_op;
208 } else
209 return SIGILL;
210 break;
211 case mm_32f_60_op:
212 func = -1; /* Invalid */
213 if (insn.mm_fp0_format.op == mm_fadd_op)
214 func = fadd_op;
215 else if (insn.mm_fp0_format.op == mm_fsub_op)
216 func = fsub_op;
217 else if (insn.mm_fp0_format.op == mm_fmul_op)
218 func = fmul_op;
219 else if (insn.mm_fp0_format.op == mm_fdiv_op)
220 func = fdiv_op;
221 if (func != -1) {
222 mips32_insn.fp0_format.opcode = cop1_op;
223 mips32_insn.fp0_format.fmt =
224 sdps_format[insn.mm_fp0_format.fmt];
225 mips32_insn.fp0_format.ft =
226 insn.mm_fp0_format.ft;
227 mips32_insn.fp0_format.fs =
228 insn.mm_fp0_format.fs;
229 mips32_insn.fp0_format.fd =
230 insn.mm_fp0_format.fd;
231 mips32_insn.fp0_format.func = func;
232 } else
233 return SIGILL;
234 break;
235 case mm_32f_70_op:
236 func = -1; /* Invalid */
237 if (insn.mm_fp0_format.op == mm_fmovn_op)
238 func = fmovn_op;
239 else if (insn.mm_fp0_format.op == mm_fmovz_op)
240 func = fmovz_op;
241 if (func != -1) {
242 mips32_insn.fp0_format.opcode = cop1_op;
243 mips32_insn.fp0_format.fmt =
244 sdps_format[insn.mm_fp0_format.fmt];
245 mips32_insn.fp0_format.ft =
246 insn.mm_fp0_format.ft;
247 mips32_insn.fp0_format.fs =
248 insn.mm_fp0_format.fs;
249 mips32_insn.fp0_format.fd =
250 insn.mm_fp0_format.fd;
251 mips32_insn.fp0_format.func = func;
252 } else
253 return SIGILL;
254 break;
255 case mm_32f_73_op: /* POOL32FXF */
256 switch (insn.mm_fp1_format.op) {
257 case mm_movf0_op:
258 case mm_movf1_op:
259 case mm_movt0_op:
260 case mm_movt1_op:
261 if ((insn.mm_fp1_format.op & 0x7f) ==
262 mm_movf0_op)
263 op = 0;
264 else
265 op = 1;
266 mips32_insn.r_format.opcode = spec_op;
267 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
268 mips32_insn.r_format.rt =
269 (insn.mm_fp4_format.cc << 2) + op;
270 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
271 mips32_insn.r_format.re = 0;
272 mips32_insn.r_format.func = movc_op;
273 break;
274 case mm_fcvtd0_op:
275 case mm_fcvtd1_op:
276 case mm_fcvts0_op:
277 case mm_fcvts1_op:
278 if ((insn.mm_fp1_format.op & 0x7f) ==
279 mm_fcvtd0_op) {
280 func = fcvtd_op;
281 fmt = swl_format[insn.mm_fp3_format.fmt];
282 } else {
283 func = fcvts_op;
284 fmt = dwl_format[insn.mm_fp3_format.fmt];
285 }
286 mips32_insn.fp0_format.opcode = cop1_op;
287 mips32_insn.fp0_format.fmt = fmt;
288 mips32_insn.fp0_format.ft = 0;
289 mips32_insn.fp0_format.fs =
290 insn.mm_fp3_format.fs;
291 mips32_insn.fp0_format.fd =
292 insn.mm_fp3_format.rt;
293 mips32_insn.fp0_format.func = func;
294 break;
295 case mm_fmov0_op:
296 case mm_fmov1_op:
297 case mm_fabs0_op:
298 case mm_fabs1_op:
299 case mm_fneg0_op:
300 case mm_fneg1_op:
301 if ((insn.mm_fp1_format.op & 0x7f) ==
302 mm_fmov0_op)
303 func = fmov_op;
304 else if ((insn.mm_fp1_format.op & 0x7f) ==
305 mm_fabs0_op)
306 func = fabs_op;
307 else
308 func = fneg_op;
309 mips32_insn.fp0_format.opcode = cop1_op;
310 mips32_insn.fp0_format.fmt =
311 sdps_format[insn.mm_fp3_format.fmt];
312 mips32_insn.fp0_format.ft = 0;
313 mips32_insn.fp0_format.fs =
314 insn.mm_fp3_format.fs;
315 mips32_insn.fp0_format.fd =
316 insn.mm_fp3_format.rt;
317 mips32_insn.fp0_format.func = func;
318 break;
319 case mm_ffloorl_op:
320 case mm_ffloorw_op:
321 case mm_fceill_op:
322 case mm_fceilw_op:
323 case mm_ftruncl_op:
324 case mm_ftruncw_op:
325 case mm_froundl_op:
326 case mm_froundw_op:
327 case mm_fcvtl_op:
328 case mm_fcvtw_op:
329 if (insn.mm_fp1_format.op == mm_ffloorl_op)
330 func = ffloorl_op;
331 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
332 func = ffloor_op;
333 else if (insn.mm_fp1_format.op == mm_fceill_op)
334 func = fceill_op;
335 else if (insn.mm_fp1_format.op == mm_fceilw_op)
336 func = fceil_op;
337 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
338 func = ftruncl_op;
339 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
340 func = ftrunc_op;
341 else if (insn.mm_fp1_format.op == mm_froundl_op)
342 func = froundl_op;
343 else if (insn.mm_fp1_format.op == mm_froundw_op)
344 func = fround_op;
345 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
346 func = fcvtl_op;
347 else
348 func = fcvtw_op;
349 mips32_insn.fp0_format.opcode = cop1_op;
350 mips32_insn.fp0_format.fmt =
351 sd_format[insn.mm_fp1_format.fmt];
352 mips32_insn.fp0_format.ft = 0;
353 mips32_insn.fp0_format.fs =
354 insn.mm_fp1_format.fs;
355 mips32_insn.fp0_format.fd =
356 insn.mm_fp1_format.rt;
357 mips32_insn.fp0_format.func = func;
358 break;
359 case mm_frsqrt_op:
360 case mm_fsqrt_op:
361 case mm_frecip_op:
362 if (insn.mm_fp1_format.op == mm_frsqrt_op)
363 func = frsqrt_op;
364 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
365 func = fsqrt_op;
366 else
367 func = frecip_op;
368 mips32_insn.fp0_format.opcode = cop1_op;
369 mips32_insn.fp0_format.fmt =
370 sdps_format[insn.mm_fp1_format.fmt];
371 mips32_insn.fp0_format.ft = 0;
372 mips32_insn.fp0_format.fs =
373 insn.mm_fp1_format.fs;
374 mips32_insn.fp0_format.fd =
375 insn.mm_fp1_format.rt;
376 mips32_insn.fp0_format.func = func;
377 break;
378 case mm_mfc1_op:
379 case mm_mtc1_op:
380 case mm_cfc1_op:
381 case mm_ctc1_op:
382 case mm_mfhc1_op:
383 case mm_mthc1_op:
384 if (insn.mm_fp1_format.op == mm_mfc1_op)
385 op = mfc_op;
386 else if (insn.mm_fp1_format.op == mm_mtc1_op)
387 op = mtc_op;
388 else if (insn.mm_fp1_format.op == mm_cfc1_op)
389 op = cfc_op;
390 else if (insn.mm_fp1_format.op == mm_ctc1_op)
391 op = ctc_op;
392 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
393 op = mfhc_op;
394 else
395 op = mthc_op;
396 mips32_insn.fp1_format.opcode = cop1_op;
397 mips32_insn.fp1_format.op = op;
398 mips32_insn.fp1_format.rt =
399 insn.mm_fp1_format.rt;
400 mips32_insn.fp1_format.fs =
401 insn.mm_fp1_format.fs;
402 mips32_insn.fp1_format.fd = 0;
403 mips32_insn.fp1_format.func = 0;
404 break;
405 default:
406 return SIGILL;
407 }
408 break;
409 case mm_32f_74_op: /* c.cond.fmt */
410 mips32_insn.fp0_format.opcode = cop1_op;
411 mips32_insn.fp0_format.fmt =
412 sdps_format[insn.mm_fp4_format.fmt];
413 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
414 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
415 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
416 mips32_insn.fp0_format.func =
417 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
418 break;
419 default:
420 return SIGILL;
421 }
422 break;
423 default:
424 return SIGILL;
425 }
426
427 *insn_ptr = mips32_insn;
428 return 0;
429 }
430
431 /*
432 * Redundant with logic already in kernel/branch.c,
433 * embedded in compute_return_epc. At some point,
434 * a single subroutine should be used across both
435 * modules.
436 */
isBranchInstr(struct pt_regs * regs,struct mm_decoded_insn dec_insn,unsigned long * contpc)437 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
438 unsigned long *contpc)
439 {
440 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
441 unsigned int fcr31;
442 unsigned int bit = 0;
443
444 switch (insn.i_format.opcode) {
445 case spec_op:
446 switch (insn.r_format.func) {
447 case jalr_op:
448 if (insn.r_format.rd != 0) {
449 regs->regs[insn.r_format.rd] =
450 regs->cp0_epc + dec_insn.pc_inc +
451 dec_insn.next_pc_inc;
452 }
453 /* Fall through */
454 case jr_op:
455 /* For R6, JR already emulated in jalr_op */
456 if (NO_R6EMU && insn.r_format.func == jr_op)
457 break;
458 *contpc = regs->regs[insn.r_format.rs];
459 return 1;
460 }
461 break;
462 case bcond_op:
463 switch (insn.i_format.rt) {
464 case bltzal_op:
465 case bltzall_op:
466 if (NO_R6EMU && (insn.i_format.rs ||
467 insn.i_format.rt == bltzall_op))
468 break;
469
470 regs->regs[31] = regs->cp0_epc +
471 dec_insn.pc_inc +
472 dec_insn.next_pc_inc;
473 /* Fall through */
474 case bltzl_op:
475 if (NO_R6EMU)
476 break;
477 case bltz_op:
478 if ((long)regs->regs[insn.i_format.rs] < 0)
479 *contpc = regs->cp0_epc +
480 dec_insn.pc_inc +
481 (insn.i_format.simmediate << 2);
482 else
483 *contpc = regs->cp0_epc +
484 dec_insn.pc_inc +
485 dec_insn.next_pc_inc;
486 return 1;
487 case bgezal_op:
488 case bgezall_op:
489 if (NO_R6EMU && (insn.i_format.rs ||
490 insn.i_format.rt == bgezall_op))
491 break;
492
493 regs->regs[31] = regs->cp0_epc +
494 dec_insn.pc_inc +
495 dec_insn.next_pc_inc;
496 /* Fall through */
497 case bgezl_op:
498 if (NO_R6EMU)
499 break;
500 case bgez_op:
501 if ((long)regs->regs[insn.i_format.rs] >= 0)
502 *contpc = regs->cp0_epc +
503 dec_insn.pc_inc +
504 (insn.i_format.simmediate << 2);
505 else
506 *contpc = regs->cp0_epc +
507 dec_insn.pc_inc +
508 dec_insn.next_pc_inc;
509 return 1;
510 }
511 break;
512 case jalx_op:
513 set_isa16_mode(bit);
514 case jal_op:
515 regs->regs[31] = regs->cp0_epc +
516 dec_insn.pc_inc +
517 dec_insn.next_pc_inc;
518 /* Fall through */
519 case j_op:
520 *contpc = regs->cp0_epc + dec_insn.pc_inc;
521 *contpc >>= 28;
522 *contpc <<= 28;
523 *contpc |= (insn.j_format.target << 2);
524 /* Set microMIPS mode bit: XOR for jalx. */
525 *contpc ^= bit;
526 return 1;
527 case beql_op:
528 if (NO_R6EMU)
529 break;
530 case beq_op:
531 if (regs->regs[insn.i_format.rs] ==
532 regs->regs[insn.i_format.rt])
533 *contpc = regs->cp0_epc +
534 dec_insn.pc_inc +
535 (insn.i_format.simmediate << 2);
536 else
537 *contpc = regs->cp0_epc +
538 dec_insn.pc_inc +
539 dec_insn.next_pc_inc;
540 return 1;
541 case bnel_op:
542 if (NO_R6EMU)
543 break;
544 case bne_op:
545 if (regs->regs[insn.i_format.rs] !=
546 regs->regs[insn.i_format.rt])
547 *contpc = regs->cp0_epc +
548 dec_insn.pc_inc +
549 (insn.i_format.simmediate << 2);
550 else
551 *contpc = regs->cp0_epc +
552 dec_insn.pc_inc +
553 dec_insn.next_pc_inc;
554 return 1;
555 case blezl_op:
556 if (!insn.i_format.rt && NO_R6EMU)
557 break;
558 case blez_op:
559
560 /*
561 * Compact branches for R6 for the
562 * blez and blezl opcodes.
563 * BLEZ | rs = 0 | rt != 0 == BLEZALC
564 * BLEZ | rs = rt != 0 == BGEZALC
565 * BLEZ | rs != 0 | rt != 0 == BGEUC
566 * BLEZL | rs = 0 | rt != 0 == BLEZC
567 * BLEZL | rs = rt != 0 == BGEZC
568 * BLEZL | rs != 0 | rt != 0 == BGEC
569 *
570 * For real BLEZ{,L}, rt is always 0.
571 */
572 if (cpu_has_mips_r6 && insn.i_format.rt) {
573 if ((insn.i_format.opcode == blez_op) &&
574 ((!insn.i_format.rs && insn.i_format.rt) ||
575 (insn.i_format.rs == insn.i_format.rt)))
576 regs->regs[31] = regs->cp0_epc +
577 dec_insn.pc_inc;
578 *contpc = regs->cp0_epc + dec_insn.pc_inc +
579 dec_insn.next_pc_inc;
580
581 return 1;
582 }
583 if ((long)regs->regs[insn.i_format.rs] <= 0)
584 *contpc = regs->cp0_epc +
585 dec_insn.pc_inc +
586 (insn.i_format.simmediate << 2);
587 else
588 *contpc = regs->cp0_epc +
589 dec_insn.pc_inc +
590 dec_insn.next_pc_inc;
591 return 1;
592 case bgtzl_op:
593 if (!insn.i_format.rt && NO_R6EMU)
594 break;
595 case bgtz_op:
596 /*
597 * Compact branches for R6 for the
598 * bgtz and bgtzl opcodes.
599 * BGTZ | rs = 0 | rt != 0 == BGTZALC
600 * BGTZ | rs = rt != 0 == BLTZALC
601 * BGTZ | rs != 0 | rt != 0 == BLTUC
602 * BGTZL | rs = 0 | rt != 0 == BGTZC
603 * BGTZL | rs = rt != 0 == BLTZC
604 * BGTZL | rs != 0 | rt != 0 == BLTC
605 *
606 * *ZALC varint for BGTZ &&& rt != 0
607 * For real GTZ{,L}, rt is always 0.
608 */
609 if (cpu_has_mips_r6 && insn.i_format.rt) {
610 if ((insn.i_format.opcode == blez_op) &&
611 ((!insn.i_format.rs && insn.i_format.rt) ||
612 (insn.i_format.rs == insn.i_format.rt)))
613 regs->regs[31] = regs->cp0_epc +
614 dec_insn.pc_inc;
615 *contpc = regs->cp0_epc + dec_insn.pc_inc +
616 dec_insn.next_pc_inc;
617
618 return 1;
619 }
620
621 if ((long)regs->regs[insn.i_format.rs] > 0)
622 *contpc = regs->cp0_epc +
623 dec_insn.pc_inc +
624 (insn.i_format.simmediate << 2);
625 else
626 *contpc = regs->cp0_epc +
627 dec_insn.pc_inc +
628 dec_insn.next_pc_inc;
629 return 1;
630 case cbcond0_op:
631 case cbcond1_op:
632 if (!cpu_has_mips_r6)
633 break;
634 if (insn.i_format.rt && !insn.i_format.rs)
635 regs->regs[31] = regs->cp0_epc + 4;
636 *contpc = regs->cp0_epc + dec_insn.pc_inc +
637 dec_insn.next_pc_inc;
638
639 return 1;
640 #ifdef CONFIG_CPU_CAVIUM_OCTEON
641 case lwc2_op: /* This is bbit0 on Octeon */
642 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
643 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
644 else
645 *contpc = regs->cp0_epc + 8;
646 return 1;
647 case ldc2_op: /* This is bbit032 on Octeon */
648 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
649 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
650 else
651 *contpc = regs->cp0_epc + 8;
652 return 1;
653 case swc2_op: /* This is bbit1 on Octeon */
654 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
655 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
656 else
657 *contpc = regs->cp0_epc + 8;
658 return 1;
659 case sdc2_op: /* This is bbit132 on Octeon */
660 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
661 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
662 else
663 *contpc = regs->cp0_epc + 8;
664 return 1;
665 #else
666 case bc6_op:
667 /*
668 * Only valid for MIPS R6 but we can still end up
669 * here from a broken userland so just tell emulator
670 * this is not a branch and let it break later on.
671 */
672 if (!cpu_has_mips_r6)
673 break;
674 *contpc = regs->cp0_epc + dec_insn.pc_inc +
675 dec_insn.next_pc_inc;
676
677 return 1;
678 case balc6_op:
679 if (!cpu_has_mips_r6)
680 break;
681 regs->regs[31] = regs->cp0_epc + 4;
682 *contpc = regs->cp0_epc + dec_insn.pc_inc +
683 dec_insn.next_pc_inc;
684
685 return 1;
686 case beqzcjic_op:
687 if (!cpu_has_mips_r6)
688 break;
689 *contpc = regs->cp0_epc + dec_insn.pc_inc +
690 dec_insn.next_pc_inc;
691
692 return 1;
693 case bnezcjialc_op:
694 if (!cpu_has_mips_r6)
695 break;
696 if (!insn.i_format.rs)
697 regs->regs[31] = regs->cp0_epc + 4;
698 *contpc = regs->cp0_epc + dec_insn.pc_inc +
699 dec_insn.next_pc_inc;
700
701 return 1;
702 #endif
703 case cop0_op:
704 case cop1_op:
705 /* Need to check for R6 bc1nez and bc1eqz branches */
706 if (cpu_has_mips_r6 &&
707 ((insn.i_format.rs == bc1eqz_op) ||
708 (insn.i_format.rs == bc1nez_op))) {
709 bit = 0;
710 switch (insn.i_format.rs) {
711 case bc1eqz_op:
712 if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
713 bit = 1;
714 break;
715 case bc1nez_op:
716 if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
717 bit = 1;
718 break;
719 }
720 if (bit)
721 *contpc = regs->cp0_epc +
722 dec_insn.pc_inc +
723 (insn.i_format.simmediate << 2);
724 else
725 *contpc = regs->cp0_epc +
726 dec_insn.pc_inc +
727 dec_insn.next_pc_inc;
728
729 return 1;
730 }
731 /* R2/R6 compatible cop1 instruction. Fall through */
732 case cop2_op:
733 case cop1x_op:
734 if (insn.i_format.rs == bc_op) {
735 preempt_disable();
736 if (is_fpu_owner())
737 fcr31 = read_32bit_cp1_register(CP1_STATUS);
738 else
739 fcr31 = current->thread.fpu.fcr31;
740 preempt_enable();
741
742 bit = (insn.i_format.rt >> 2);
743 bit += (bit != 0);
744 bit += 23;
745 switch (insn.i_format.rt & 3) {
746 case 0: /* bc1f */
747 case 2: /* bc1fl */
748 if (~fcr31 & (1 << bit))
749 *contpc = regs->cp0_epc +
750 dec_insn.pc_inc +
751 (insn.i_format.simmediate << 2);
752 else
753 *contpc = regs->cp0_epc +
754 dec_insn.pc_inc +
755 dec_insn.next_pc_inc;
756 return 1;
757 case 1: /* bc1t */
758 case 3: /* bc1tl */
759 if (fcr31 & (1 << bit))
760 *contpc = regs->cp0_epc +
761 dec_insn.pc_inc +
762 (insn.i_format.simmediate << 2);
763 else
764 *contpc = regs->cp0_epc +
765 dec_insn.pc_inc +
766 dec_insn.next_pc_inc;
767 return 1;
768 }
769 }
770 break;
771 }
772 return 0;
773 }
774
775 /*
776 * In the Linux kernel, we support selection of FPR format on the
777 * basis of the Status.FR bit. If an FPU is not present, the FR bit
778 * is hardwired to zero, which would imply a 32-bit FPU even for
779 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
780 * FPU emu is slow and bulky and optimizing this function offers fairly
781 * sizeable benefits so we try to be clever and make this function return
782 * a constant whenever possible, that is on 64-bit kernels without O32
783 * compatibility enabled and on 32-bit without 64-bit FPU support.
784 */
cop1_64bit(struct pt_regs * xcp)785 static inline int cop1_64bit(struct pt_regs *xcp)
786 {
787 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
788 return 1;
789 else if (config_enabled(CONFIG_32BIT) &&
790 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
791 return 0;
792
793 return !test_thread_flag(TIF_32BIT_FPREGS);
794 }
795
hybrid_fprs(void)796 static inline bool hybrid_fprs(void)
797 {
798 return test_thread_flag(TIF_HYBRID_FPREGS);
799 }
800
801 #define SIFROMREG(si, x) \
802 do { \
803 if (cop1_64bit(xcp) && !hybrid_fprs()) \
804 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
805 else \
806 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
807 } while (0)
808
809 #define SITOREG(si, x) \
810 do { \
811 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
812 unsigned i; \
813 set_fpr32(&ctx->fpr[x], 0, si); \
814 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
815 set_fpr32(&ctx->fpr[x], i, 0); \
816 } else { \
817 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
818 } \
819 } while (0)
820
821 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
822
823 #define SITOHREG(si, x) \
824 do { \
825 unsigned i; \
826 set_fpr32(&ctx->fpr[x], 1, si); \
827 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
828 set_fpr32(&ctx->fpr[x], i, 0); \
829 } while (0)
830
831 #define DIFROMREG(di, x) \
832 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
833
834 #define DITOREG(di, x) \
835 do { \
836 unsigned fpr, i; \
837 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
838 set_fpr64(&ctx->fpr[fpr], 0, di); \
839 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
840 set_fpr64(&ctx->fpr[fpr], i, 0); \
841 } while (0)
842
843 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
844 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
845 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
846 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
847
848 /*
849 * Emulate a CFC1 instruction.
850 */
cop1_cfc(struct pt_regs * xcp,struct mips_fpu_struct * ctx,mips_instruction ir)851 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
852 mips_instruction ir)
853 {
854 u32 fcr31 = ctx->fcr31;
855 u32 value = 0;
856
857 switch (MIPSInst_RD(ir)) {
858 case FPCREG_CSR:
859 value = fcr31;
860 pr_debug("%p gpr[%d]<-csr=%08x\n",
861 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
862 break;
863
864 case FPCREG_FENR:
865 if (!cpu_has_mips_r)
866 break;
867 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
868 MIPS_FENR_FS;
869 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
870 pr_debug("%p gpr[%d]<-enr=%08x\n",
871 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
872 break;
873
874 case FPCREG_FEXR:
875 if (!cpu_has_mips_r)
876 break;
877 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
878 pr_debug("%p gpr[%d]<-exr=%08x\n",
879 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
880 break;
881
882 case FPCREG_FCCR:
883 if (!cpu_has_mips_r)
884 break;
885 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
886 MIPS_FCCR_COND0;
887 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
888 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
889 pr_debug("%p gpr[%d]<-ccr=%08x\n",
890 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
891 break;
892
893 case FPCREG_RID:
894 value = boot_cpu_data.fpu_id;
895 break;
896
897 default:
898 break;
899 }
900
901 if (MIPSInst_RT(ir))
902 xcp->regs[MIPSInst_RT(ir)] = value;
903 }
904
905 /*
906 * Emulate a CTC1 instruction.
907 */
cop1_ctc(struct pt_regs * xcp,struct mips_fpu_struct * ctx,mips_instruction ir)908 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
909 mips_instruction ir)
910 {
911 u32 fcr31 = ctx->fcr31;
912 u32 value;
913 u32 mask;
914
915 if (MIPSInst_RT(ir) == 0)
916 value = 0;
917 else
918 value = xcp->regs[MIPSInst_RT(ir)];
919
920 switch (MIPSInst_RD(ir)) {
921 case FPCREG_CSR:
922 pr_debug("%p gpr[%d]->csr=%08x\n",
923 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
924
925 /* Preserve read-only bits. */
926 mask = boot_cpu_data.fpu_msk31;
927 fcr31 = (value & ~mask) | (fcr31 & mask);
928 break;
929
930 case FPCREG_FENR:
931 if (!cpu_has_mips_r)
932 break;
933 pr_debug("%p gpr[%d]->enr=%08x\n",
934 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
935 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
936 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
937 FPU_CSR_FS;
938 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
939 break;
940
941 case FPCREG_FEXR:
942 if (!cpu_has_mips_r)
943 break;
944 pr_debug("%p gpr[%d]->exr=%08x\n",
945 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
946 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
947 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
948 break;
949
950 case FPCREG_FCCR:
951 if (!cpu_has_mips_r)
952 break;
953 pr_debug("%p gpr[%d]->ccr=%08x\n",
954 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
955 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
956 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
957 FPU_CSR_COND;
958 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
959 FPU_CSR_CONDX;
960 break;
961
962 default:
963 break;
964 }
965
966 ctx->fcr31 = fcr31;
967 }
968
969 /*
970 * Emulate the single floating point instruction pointed at by EPC.
971 * Two instructions if the instruction is in a branch delay slot.
972 */
973
cop1Emulate(struct pt_regs * xcp,struct mips_fpu_struct * ctx,struct mm_decoded_insn dec_insn,void * __user * fault_addr)974 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
975 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
976 {
977 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
978 unsigned int cond, cbit;
979 mips_instruction ir;
980 int likely, pc_inc;
981 u32 __user *wva;
982 u64 __user *dva;
983 u32 wval;
984 u64 dval;
985 int sig;
986
987 /*
988 * These are giving gcc a gentle hint about what to expect in
989 * dec_inst in order to do better optimization.
990 */
991 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
992 unreachable();
993
994 /* XXX NEC Vr54xx bug workaround */
995 if (delay_slot(xcp)) {
996 if (dec_insn.micro_mips_mode) {
997 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
998 clear_delay_slot(xcp);
999 } else {
1000 if (!isBranchInstr(xcp, dec_insn, &contpc))
1001 clear_delay_slot(xcp);
1002 }
1003 }
1004
1005 if (delay_slot(xcp)) {
1006 /*
1007 * The instruction to be emulated is in a branch delay slot
1008 * which means that we have to emulate the branch instruction
1009 * BEFORE we do the cop1 instruction.
1010 *
1011 * This branch could be a COP1 branch, but in that case we
1012 * would have had a trap for that instruction, and would not
1013 * come through this route.
1014 *
1015 * Linux MIPS branch emulator operates on context, updating the
1016 * cp0_epc.
1017 */
1018 ir = dec_insn.next_insn; /* process delay slot instr */
1019 pc_inc = dec_insn.next_pc_inc;
1020 } else {
1021 ir = dec_insn.insn; /* process current instr */
1022 pc_inc = dec_insn.pc_inc;
1023 }
1024
1025 /*
1026 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1027 * instructions, we want to convert microMIPS FPU instructions
1028 * into MIPS32 instructions so that we could reuse all of the
1029 * FPU emulation code.
1030 *
1031 * NOTE: We cannot do this for branch instructions since they
1032 * are not a subset. Example: Cannot emulate a 16-bit
1033 * aligned target address with a MIPS32 instruction.
1034 */
1035 if (dec_insn.micro_mips_mode) {
1036 /*
1037 * If next instruction is a 16-bit instruction, then it
1038 * it cannot be a FPU instruction. This could happen
1039 * since we can be called for non-FPU instructions.
1040 */
1041 if ((pc_inc == 2) ||
1042 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1043 == SIGILL))
1044 return SIGILL;
1045 }
1046
1047 emul:
1048 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1049 MIPS_FPU_EMU_INC_STATS(emulated);
1050 switch (MIPSInst_OPCODE(ir)) {
1051 case ldc1_op:
1052 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1053 MIPSInst_SIMM(ir));
1054 MIPS_FPU_EMU_INC_STATS(loads);
1055
1056 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1057 MIPS_FPU_EMU_INC_STATS(errors);
1058 *fault_addr = dva;
1059 return SIGBUS;
1060 }
1061 if (__get_user(dval, dva)) {
1062 MIPS_FPU_EMU_INC_STATS(errors);
1063 *fault_addr = dva;
1064 return SIGSEGV;
1065 }
1066 DITOREG(dval, MIPSInst_RT(ir));
1067 break;
1068
1069 case sdc1_op:
1070 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1071 MIPSInst_SIMM(ir));
1072 MIPS_FPU_EMU_INC_STATS(stores);
1073 DIFROMREG(dval, MIPSInst_RT(ir));
1074 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1075 MIPS_FPU_EMU_INC_STATS(errors);
1076 *fault_addr = dva;
1077 return SIGBUS;
1078 }
1079 if (__put_user(dval, dva)) {
1080 MIPS_FPU_EMU_INC_STATS(errors);
1081 *fault_addr = dva;
1082 return SIGSEGV;
1083 }
1084 break;
1085
1086 case lwc1_op:
1087 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1088 MIPSInst_SIMM(ir));
1089 MIPS_FPU_EMU_INC_STATS(loads);
1090 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1091 MIPS_FPU_EMU_INC_STATS(errors);
1092 *fault_addr = wva;
1093 return SIGBUS;
1094 }
1095 if (__get_user(wval, wva)) {
1096 MIPS_FPU_EMU_INC_STATS(errors);
1097 *fault_addr = wva;
1098 return SIGSEGV;
1099 }
1100 SITOREG(wval, MIPSInst_RT(ir));
1101 break;
1102
1103 case swc1_op:
1104 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1105 MIPSInst_SIMM(ir));
1106 MIPS_FPU_EMU_INC_STATS(stores);
1107 SIFROMREG(wval, MIPSInst_RT(ir));
1108 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1109 MIPS_FPU_EMU_INC_STATS(errors);
1110 *fault_addr = wva;
1111 return SIGBUS;
1112 }
1113 if (__put_user(wval, wva)) {
1114 MIPS_FPU_EMU_INC_STATS(errors);
1115 *fault_addr = wva;
1116 return SIGSEGV;
1117 }
1118 break;
1119
1120 case cop1_op:
1121 switch (MIPSInst_RS(ir)) {
1122 case dmfc_op:
1123 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1124 return SIGILL;
1125
1126 /* copregister fs -> gpr[rt] */
1127 if (MIPSInst_RT(ir) != 0) {
1128 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1129 MIPSInst_RD(ir));
1130 }
1131 break;
1132
1133 case dmtc_op:
1134 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1135 return SIGILL;
1136
1137 /* copregister fs <- rt */
1138 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1139 break;
1140
1141 case mfhc_op:
1142 if (!cpu_has_mips_r2_r6)
1143 goto sigill;
1144
1145 /* copregister rd -> gpr[rt] */
1146 if (MIPSInst_RT(ir) != 0) {
1147 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1148 MIPSInst_RD(ir));
1149 }
1150 break;
1151
1152 case mthc_op:
1153 if (!cpu_has_mips_r2_r6)
1154 goto sigill;
1155
1156 /* copregister rd <- gpr[rt] */
1157 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1158 break;
1159
1160 case mfc_op:
1161 /* copregister rd -> gpr[rt] */
1162 if (MIPSInst_RT(ir) != 0) {
1163 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1164 MIPSInst_RD(ir));
1165 }
1166 break;
1167
1168 case mtc_op:
1169 /* copregister rd <- rt */
1170 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1171 break;
1172
1173 case cfc_op:
1174 /* cop control register rd -> gpr[rt] */
1175 cop1_cfc(xcp, ctx, ir);
1176 break;
1177
1178 case ctc_op:
1179 /* copregister rd <- rt */
1180 cop1_ctc(xcp, ctx, ir);
1181 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1182 return SIGFPE;
1183 }
1184 break;
1185
1186 case bc1eqz_op:
1187 case bc1nez_op:
1188 if (!cpu_has_mips_r6 || delay_slot(xcp))
1189 return SIGILL;
1190
1191 cond = likely = 0;
1192 switch (MIPSInst_RS(ir)) {
1193 case bc1eqz_op:
1194 if (get_fpr32(¤t->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)
1195 cond = 1;
1196 break;
1197 case bc1nez_op:
1198 if (!(get_fpr32(¤t->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1))
1199 cond = 1;
1200 break;
1201 }
1202 goto branch_common;
1203
1204 case bc_op:
1205 if (delay_slot(xcp))
1206 return SIGILL;
1207
1208 if (cpu_has_mips_4_5_r)
1209 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1210 else
1211 cbit = FPU_CSR_COND;
1212 cond = ctx->fcr31 & cbit;
1213
1214 likely = 0;
1215 switch (MIPSInst_RT(ir) & 3) {
1216 case bcfl_op:
1217 if (cpu_has_mips_2_3_4_5_r)
1218 likely = 1;
1219 /* Fall through */
1220 case bcf_op:
1221 cond = !cond;
1222 break;
1223 case bctl_op:
1224 if (cpu_has_mips_2_3_4_5_r)
1225 likely = 1;
1226 /* Fall through */
1227 case bct_op:
1228 break;
1229 }
1230 branch_common:
1231 set_delay_slot(xcp);
1232 if (cond) {
1233 /*
1234 * Branch taken: emulate dslot instruction
1235 */
1236 unsigned long bcpc;
1237
1238 /*
1239 * Remember EPC at the branch to point back
1240 * at so that any delay-slot instruction
1241 * signal is not silently ignored.
1242 */
1243 bcpc = xcp->cp0_epc;
1244 xcp->cp0_epc += dec_insn.pc_inc;
1245
1246 contpc = MIPSInst_SIMM(ir);
1247 ir = dec_insn.next_insn;
1248 if (dec_insn.micro_mips_mode) {
1249 contpc = (xcp->cp0_epc + (contpc << 1));
1250
1251 /* If 16-bit instruction, not FPU. */
1252 if ((dec_insn.next_pc_inc == 2) ||
1253 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1254
1255 /*
1256 * Since this instruction will
1257 * be put on the stack with
1258 * 32-bit words, get around
1259 * this problem by putting a
1260 * NOP16 as the second one.
1261 */
1262 if (dec_insn.next_pc_inc == 2)
1263 ir = (ir & (~0xffff)) | MM_NOP16;
1264
1265 /*
1266 * Single step the non-CP1
1267 * instruction in the dslot.
1268 */
1269 sig = mips_dsemul(xcp, ir,
1270 contpc);
1271 if (sig)
1272 xcp->cp0_epc = bcpc;
1273 /*
1274 * SIGILL forces out of
1275 * the emulation loop.
1276 */
1277 return sig ? sig : SIGILL;
1278 }
1279 } else
1280 contpc = (xcp->cp0_epc + (contpc << 2));
1281
1282 switch (MIPSInst_OPCODE(ir)) {
1283 case lwc1_op:
1284 case swc1_op:
1285 goto emul;
1286
1287 case ldc1_op:
1288 case sdc1_op:
1289 if (cpu_has_mips_2_3_4_5_r)
1290 goto emul;
1291
1292 goto bc_sigill;
1293
1294 case cop1_op:
1295 goto emul;
1296
1297 case cop1x_op:
1298 if (cpu_has_mips_4_5_64_r2_r6)
1299 /* its one of ours */
1300 goto emul;
1301
1302 goto bc_sigill;
1303
1304 case spec_op:
1305 switch (MIPSInst_FUNC(ir)) {
1306 case movc_op:
1307 if (cpu_has_mips_4_5_r)
1308 goto emul;
1309
1310 goto bc_sigill;
1311 }
1312 break;
1313
1314 bc_sigill:
1315 xcp->cp0_epc = bcpc;
1316 return SIGILL;
1317 }
1318
1319 /*
1320 * Single step the non-cp1
1321 * instruction in the dslot
1322 */
1323 sig = mips_dsemul(xcp, ir, contpc);
1324 if (sig)
1325 xcp->cp0_epc = bcpc;
1326 /* SIGILL forces out of the emulation loop. */
1327 return sig ? sig : SIGILL;
1328 } else if (likely) { /* branch not taken */
1329 /*
1330 * branch likely nullifies
1331 * dslot if not taken
1332 */
1333 xcp->cp0_epc += dec_insn.pc_inc;
1334 contpc += dec_insn.pc_inc;
1335 /*
1336 * else continue & execute
1337 * dslot as normal insn
1338 */
1339 }
1340 break;
1341
1342 default:
1343 if (!(MIPSInst_RS(ir) & 0x10))
1344 return SIGILL;
1345
1346 /* a real fpu computation instruction */
1347 if ((sig = fpu_emu(xcp, ctx, ir)))
1348 return sig;
1349 }
1350 break;
1351
1352 case cop1x_op:
1353 if (!cpu_has_mips_4_5_64_r2_r6)
1354 return SIGILL;
1355
1356 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1357 if (sig)
1358 return sig;
1359 break;
1360
1361 case spec_op:
1362 if (!cpu_has_mips_4_5_r)
1363 return SIGILL;
1364
1365 if (MIPSInst_FUNC(ir) != movc_op)
1366 return SIGILL;
1367 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1368 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1369 xcp->regs[MIPSInst_RD(ir)] =
1370 xcp->regs[MIPSInst_RS(ir)];
1371 break;
1372 default:
1373 sigill:
1374 return SIGILL;
1375 }
1376
1377 /* we did it !! */
1378 xcp->cp0_epc = contpc;
1379 clear_delay_slot(xcp);
1380
1381 return 0;
1382 }
1383
1384 /*
1385 * Conversion table from MIPS compare ops 48-63
1386 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1387 */
1388 static const unsigned char cmptab[8] = {
1389 0, /* cmp_0 (sig) cmp_sf */
1390 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1391 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1392 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1393 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1394 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1395 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1396 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1397 };
1398
1399 static const unsigned char negative_cmptab[8] = {
1400 0, /* Reserved */
1401 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1402 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1403 IEEE754_CLT | IEEE754_CGT,
1404 /* Reserved */
1405 };
1406
1407
1408 /*
1409 * Additional MIPS4 instructions
1410 */
1411
1412 #define DEF3OP(name, p, f1, f2, f3) \
1413 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1414 union ieee754##p s, union ieee754##p t) \
1415 { \
1416 struct _ieee754_csr ieee754_csr_save; \
1417 s = f1(s, t); \
1418 ieee754_csr_save = ieee754_csr; \
1419 s = f2(s, r); \
1420 ieee754_csr_save.cx |= ieee754_csr.cx; \
1421 ieee754_csr_save.sx |= ieee754_csr.sx; \
1422 s = f3(s); \
1423 ieee754_csr.cx |= ieee754_csr_save.cx; \
1424 ieee754_csr.sx |= ieee754_csr_save.sx; \
1425 return s; \
1426 }
1427
fpemu_dp_recip(union ieee754dp d)1428 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1429 {
1430 return ieee754dp_div(ieee754dp_one(0), d);
1431 }
1432
fpemu_dp_rsqrt(union ieee754dp d)1433 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1434 {
1435 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1436 }
1437
fpemu_sp_recip(union ieee754sp s)1438 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1439 {
1440 return ieee754sp_div(ieee754sp_one(0), s);
1441 }
1442
fpemu_sp_rsqrt(union ieee754sp s)1443 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1444 {
1445 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1446 }
1447
1448 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1449 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1450 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1451 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1452 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1453 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1454 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1455 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1456
fpux_emu(struct pt_regs * xcp,struct mips_fpu_struct * ctx,mips_instruction ir,void * __user * fault_addr)1457 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1458 mips_instruction ir, void *__user *fault_addr)
1459 {
1460 unsigned rcsr = 0; /* resulting csr */
1461
1462 MIPS_FPU_EMU_INC_STATS(cp1xops);
1463
1464 switch (MIPSInst_FMA_FFMT(ir)) {
1465 case s_fmt:{ /* 0 */
1466
1467 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1468 union ieee754sp fd, fr, fs, ft;
1469 u32 __user *va;
1470 u32 val;
1471
1472 switch (MIPSInst_FUNC(ir)) {
1473 case lwxc1_op:
1474 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1475 xcp->regs[MIPSInst_FT(ir)]);
1476
1477 MIPS_FPU_EMU_INC_STATS(loads);
1478 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1479 MIPS_FPU_EMU_INC_STATS(errors);
1480 *fault_addr = va;
1481 return SIGBUS;
1482 }
1483 if (__get_user(val, va)) {
1484 MIPS_FPU_EMU_INC_STATS(errors);
1485 *fault_addr = va;
1486 return SIGSEGV;
1487 }
1488 SITOREG(val, MIPSInst_FD(ir));
1489 break;
1490
1491 case swxc1_op:
1492 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1493 xcp->regs[MIPSInst_FT(ir)]);
1494
1495 MIPS_FPU_EMU_INC_STATS(stores);
1496
1497 SIFROMREG(val, MIPSInst_FS(ir));
1498 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1499 MIPS_FPU_EMU_INC_STATS(errors);
1500 *fault_addr = va;
1501 return SIGBUS;
1502 }
1503 if (put_user(val, va)) {
1504 MIPS_FPU_EMU_INC_STATS(errors);
1505 *fault_addr = va;
1506 return SIGSEGV;
1507 }
1508 break;
1509
1510 case madd_s_op:
1511 handler = fpemu_sp_madd;
1512 goto scoptop;
1513 case msub_s_op:
1514 handler = fpemu_sp_msub;
1515 goto scoptop;
1516 case nmadd_s_op:
1517 handler = fpemu_sp_nmadd;
1518 goto scoptop;
1519 case nmsub_s_op:
1520 handler = fpemu_sp_nmsub;
1521 goto scoptop;
1522
1523 scoptop:
1524 SPFROMREG(fr, MIPSInst_FR(ir));
1525 SPFROMREG(fs, MIPSInst_FS(ir));
1526 SPFROMREG(ft, MIPSInst_FT(ir));
1527 fd = (*handler) (fr, fs, ft);
1528 SPTOREG(fd, MIPSInst_FD(ir));
1529
1530 copcsr:
1531 if (ieee754_cxtest(IEEE754_INEXACT)) {
1532 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1533 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1534 }
1535 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1536 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1537 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1538 }
1539 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1540 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1541 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1542 }
1543 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1544 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1545 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1546 }
1547
1548 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1549 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1550 /*printk ("SIGFPE: FPU csr = %08x\n",
1551 ctx->fcr31); */
1552 return SIGFPE;
1553 }
1554
1555 break;
1556
1557 default:
1558 return SIGILL;
1559 }
1560 break;
1561 }
1562
1563 case d_fmt:{ /* 1 */
1564 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1565 union ieee754dp fd, fr, fs, ft;
1566 u64 __user *va;
1567 u64 val;
1568
1569 switch (MIPSInst_FUNC(ir)) {
1570 case ldxc1_op:
1571 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1572 xcp->regs[MIPSInst_FT(ir)]);
1573
1574 MIPS_FPU_EMU_INC_STATS(loads);
1575 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1576 MIPS_FPU_EMU_INC_STATS(errors);
1577 *fault_addr = va;
1578 return SIGBUS;
1579 }
1580 if (__get_user(val, va)) {
1581 MIPS_FPU_EMU_INC_STATS(errors);
1582 *fault_addr = va;
1583 return SIGSEGV;
1584 }
1585 DITOREG(val, MIPSInst_FD(ir));
1586 break;
1587
1588 case sdxc1_op:
1589 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1590 xcp->regs[MIPSInst_FT(ir)]);
1591
1592 MIPS_FPU_EMU_INC_STATS(stores);
1593 DIFROMREG(val, MIPSInst_FS(ir));
1594 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1595 MIPS_FPU_EMU_INC_STATS(errors);
1596 *fault_addr = va;
1597 return SIGBUS;
1598 }
1599 if (__put_user(val, va)) {
1600 MIPS_FPU_EMU_INC_STATS(errors);
1601 *fault_addr = va;
1602 return SIGSEGV;
1603 }
1604 break;
1605
1606 case madd_d_op:
1607 handler = fpemu_dp_madd;
1608 goto dcoptop;
1609 case msub_d_op:
1610 handler = fpemu_dp_msub;
1611 goto dcoptop;
1612 case nmadd_d_op:
1613 handler = fpemu_dp_nmadd;
1614 goto dcoptop;
1615 case nmsub_d_op:
1616 handler = fpemu_dp_nmsub;
1617 goto dcoptop;
1618
1619 dcoptop:
1620 DPFROMREG(fr, MIPSInst_FR(ir));
1621 DPFROMREG(fs, MIPSInst_FS(ir));
1622 DPFROMREG(ft, MIPSInst_FT(ir));
1623 fd = (*handler) (fr, fs, ft);
1624 DPTOREG(fd, MIPSInst_FD(ir));
1625 goto copcsr;
1626
1627 default:
1628 return SIGILL;
1629 }
1630 break;
1631 }
1632
1633 case 0x3:
1634 if (MIPSInst_FUNC(ir) != pfetch_op)
1635 return SIGILL;
1636
1637 /* ignore prefx operation */
1638 break;
1639
1640 default:
1641 return SIGILL;
1642 }
1643
1644 return 0;
1645 }
1646
1647
1648
1649 /*
1650 * Emulate a single COP1 arithmetic instruction.
1651 */
fpu_emu(struct pt_regs * xcp,struct mips_fpu_struct * ctx,mips_instruction ir)1652 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1653 mips_instruction ir)
1654 {
1655 int rfmt; /* resulting format */
1656 unsigned rcsr = 0; /* resulting csr */
1657 unsigned int oldrm;
1658 unsigned int cbit;
1659 unsigned cond;
1660 union {
1661 union ieee754dp d;
1662 union ieee754sp s;
1663 int w;
1664 s64 l;
1665 } rv; /* resulting value */
1666 u64 bits;
1667
1668 MIPS_FPU_EMU_INC_STATS(cp1ops);
1669 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1670 case s_fmt: { /* 0 */
1671 union {
1672 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1673 union ieee754sp(*u) (union ieee754sp);
1674 } handler;
1675 union ieee754sp fs, ft;
1676
1677 switch (MIPSInst_FUNC(ir)) {
1678 /* binary ops */
1679 case fadd_op:
1680 handler.b = ieee754sp_add;
1681 goto scopbop;
1682 case fsub_op:
1683 handler.b = ieee754sp_sub;
1684 goto scopbop;
1685 case fmul_op:
1686 handler.b = ieee754sp_mul;
1687 goto scopbop;
1688 case fdiv_op:
1689 handler.b = ieee754sp_div;
1690 goto scopbop;
1691
1692 /* unary ops */
1693 case fsqrt_op:
1694 if (!cpu_has_mips_2_3_4_5_r)
1695 return SIGILL;
1696
1697 handler.u = ieee754sp_sqrt;
1698 goto scopuop;
1699
1700 /*
1701 * Note that on some MIPS IV implementations such as the
1702 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1703 * achieve full IEEE-754 accuracy - however this emulator does.
1704 */
1705 case frsqrt_op:
1706 if (!cpu_has_mips_4_5_64_r2_r6)
1707 return SIGILL;
1708
1709 handler.u = fpemu_sp_rsqrt;
1710 goto scopuop;
1711
1712 case frecip_op:
1713 if (!cpu_has_mips_4_5_64_r2_r6)
1714 return SIGILL;
1715
1716 handler.u = fpemu_sp_recip;
1717 goto scopuop;
1718
1719 case fmovc_op:
1720 if (!cpu_has_mips_4_5_r)
1721 return SIGILL;
1722
1723 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1724 if (((ctx->fcr31 & cond) != 0) !=
1725 ((MIPSInst_FT(ir) & 1) != 0))
1726 return 0;
1727 SPFROMREG(rv.s, MIPSInst_FS(ir));
1728 break;
1729
1730 case fmovz_op:
1731 if (!cpu_has_mips_4_5_r)
1732 return SIGILL;
1733
1734 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1735 return 0;
1736 SPFROMREG(rv.s, MIPSInst_FS(ir));
1737 break;
1738
1739 case fmovn_op:
1740 if (!cpu_has_mips_4_5_r)
1741 return SIGILL;
1742
1743 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1744 return 0;
1745 SPFROMREG(rv.s, MIPSInst_FS(ir));
1746 break;
1747
1748 case fseleqz_op:
1749 if (!cpu_has_mips_r6)
1750 return SIGILL;
1751
1752 SPFROMREG(rv.s, MIPSInst_FT(ir));
1753 if (rv.w & 0x1)
1754 rv.w = 0;
1755 else
1756 SPFROMREG(rv.s, MIPSInst_FS(ir));
1757 break;
1758
1759 case fselnez_op:
1760 if (!cpu_has_mips_r6)
1761 return SIGILL;
1762
1763 SPFROMREG(rv.s, MIPSInst_FT(ir));
1764 if (rv.w & 0x1)
1765 SPFROMREG(rv.s, MIPSInst_FS(ir));
1766 else
1767 rv.w = 0;
1768 break;
1769
1770 case fmaddf_op: {
1771 union ieee754sp ft, fs, fd;
1772
1773 if (!cpu_has_mips_r6)
1774 return SIGILL;
1775
1776 SPFROMREG(ft, MIPSInst_FT(ir));
1777 SPFROMREG(fs, MIPSInst_FS(ir));
1778 SPFROMREG(fd, MIPSInst_FD(ir));
1779 rv.s = ieee754sp_maddf(fd, fs, ft);
1780 break;
1781 }
1782
1783 case fmsubf_op: {
1784 union ieee754sp ft, fs, fd;
1785
1786 if (!cpu_has_mips_r6)
1787 return SIGILL;
1788
1789 SPFROMREG(ft, MIPSInst_FT(ir));
1790 SPFROMREG(fs, MIPSInst_FS(ir));
1791 SPFROMREG(fd, MIPSInst_FD(ir));
1792 rv.s = ieee754sp_msubf(fd, fs, ft);
1793 break;
1794 }
1795
1796 case frint_op: {
1797 union ieee754sp fs;
1798
1799 if (!cpu_has_mips_r6)
1800 return SIGILL;
1801
1802 SPFROMREG(fs, MIPSInst_FS(ir));
1803 rv.l = ieee754sp_tlong(fs);
1804 rv.s = ieee754sp_flong(rv.l);
1805 goto copcsr;
1806 }
1807
1808 case fclass_op: {
1809 union ieee754sp fs;
1810
1811 if (!cpu_has_mips_r6)
1812 return SIGILL;
1813
1814 SPFROMREG(fs, MIPSInst_FS(ir));
1815 rv.w = ieee754sp_2008class(fs);
1816 rfmt = w_fmt;
1817 break;
1818 }
1819
1820 case fmin_op: {
1821 union ieee754sp fs, ft;
1822
1823 if (!cpu_has_mips_r6)
1824 return SIGILL;
1825
1826 SPFROMREG(ft, MIPSInst_FT(ir));
1827 SPFROMREG(fs, MIPSInst_FS(ir));
1828 rv.s = ieee754sp_fmin(fs, ft);
1829 break;
1830 }
1831
1832 case fmina_op: {
1833 union ieee754sp fs, ft;
1834
1835 if (!cpu_has_mips_r6)
1836 return SIGILL;
1837
1838 SPFROMREG(ft, MIPSInst_FT(ir));
1839 SPFROMREG(fs, MIPSInst_FS(ir));
1840 rv.s = ieee754sp_fmina(fs, ft);
1841 break;
1842 }
1843
1844 case fmax_op: {
1845 union ieee754sp fs, ft;
1846
1847 if (!cpu_has_mips_r6)
1848 return SIGILL;
1849
1850 SPFROMREG(ft, MIPSInst_FT(ir));
1851 SPFROMREG(fs, MIPSInst_FS(ir));
1852 rv.s = ieee754sp_fmax(fs, ft);
1853 break;
1854 }
1855
1856 case fmaxa_op: {
1857 union ieee754sp fs, ft;
1858
1859 if (!cpu_has_mips_r6)
1860 return SIGILL;
1861
1862 SPFROMREG(ft, MIPSInst_FT(ir));
1863 SPFROMREG(fs, MIPSInst_FS(ir));
1864 rv.s = ieee754sp_fmaxa(fs, ft);
1865 break;
1866 }
1867
1868 case fabs_op:
1869 handler.u = ieee754sp_abs;
1870 goto scopuop;
1871
1872 case fneg_op:
1873 handler.u = ieee754sp_neg;
1874 goto scopuop;
1875
1876 case fmov_op:
1877 /* an easy one */
1878 SPFROMREG(rv.s, MIPSInst_FS(ir));
1879 goto copcsr;
1880
1881 /* binary op on handler */
1882 scopbop:
1883 SPFROMREG(fs, MIPSInst_FS(ir));
1884 SPFROMREG(ft, MIPSInst_FT(ir));
1885
1886 rv.s = (*handler.b) (fs, ft);
1887 goto copcsr;
1888 scopuop:
1889 SPFROMREG(fs, MIPSInst_FS(ir));
1890 rv.s = (*handler.u) (fs);
1891 goto copcsr;
1892 copcsr:
1893 if (ieee754_cxtest(IEEE754_INEXACT)) {
1894 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1895 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1896 }
1897 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1898 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1899 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1900 }
1901 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1902 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1903 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1904 }
1905 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1906 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1907 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1908 }
1909 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1910 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1911 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1912 }
1913 break;
1914
1915 /* unary conv ops */
1916 case fcvts_op:
1917 return SIGILL; /* not defined */
1918
1919 case fcvtd_op:
1920 SPFROMREG(fs, MIPSInst_FS(ir));
1921 rv.d = ieee754dp_fsp(fs);
1922 rfmt = d_fmt;
1923 goto copcsr;
1924
1925 case fcvtw_op:
1926 SPFROMREG(fs, MIPSInst_FS(ir));
1927 rv.w = ieee754sp_tint(fs);
1928 rfmt = w_fmt;
1929 goto copcsr;
1930
1931 case fround_op:
1932 case ftrunc_op:
1933 case fceil_op:
1934 case ffloor_op:
1935 if (!cpu_has_mips_2_3_4_5_r)
1936 return SIGILL;
1937
1938 oldrm = ieee754_csr.rm;
1939 SPFROMREG(fs, MIPSInst_FS(ir));
1940 ieee754_csr.rm = MIPSInst_FUNC(ir);
1941 rv.w = ieee754sp_tint(fs);
1942 ieee754_csr.rm = oldrm;
1943 rfmt = w_fmt;
1944 goto copcsr;
1945
1946 case fcvtl_op:
1947 if (!cpu_has_mips_3_4_5_64_r2_r6)
1948 return SIGILL;
1949
1950 SPFROMREG(fs, MIPSInst_FS(ir));
1951 rv.l = ieee754sp_tlong(fs);
1952 rfmt = l_fmt;
1953 goto copcsr;
1954
1955 case froundl_op:
1956 case ftruncl_op:
1957 case fceill_op:
1958 case ffloorl_op:
1959 if (!cpu_has_mips_3_4_5_64_r2_r6)
1960 return SIGILL;
1961
1962 oldrm = ieee754_csr.rm;
1963 SPFROMREG(fs, MIPSInst_FS(ir));
1964 ieee754_csr.rm = MIPSInst_FUNC(ir);
1965 rv.l = ieee754sp_tlong(fs);
1966 ieee754_csr.rm = oldrm;
1967 rfmt = l_fmt;
1968 goto copcsr;
1969
1970 default:
1971 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1972 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1973 union ieee754sp fs, ft;
1974
1975 SPFROMREG(fs, MIPSInst_FS(ir));
1976 SPFROMREG(ft, MIPSInst_FT(ir));
1977 rv.w = ieee754sp_cmp(fs, ft,
1978 cmptab[cmpop & 0x7], cmpop & 0x8);
1979 rfmt = -1;
1980 if ((cmpop & 0x8) && ieee754_cxtest
1981 (IEEE754_INVALID_OPERATION))
1982 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1983 else
1984 goto copcsr;
1985
1986 } else
1987 return SIGILL;
1988 break;
1989 }
1990 break;
1991 }
1992
1993 case d_fmt: {
1994 union ieee754dp fs, ft;
1995 union {
1996 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1997 union ieee754dp(*u) (union ieee754dp);
1998 } handler;
1999
2000 switch (MIPSInst_FUNC(ir)) {
2001 /* binary ops */
2002 case fadd_op:
2003 handler.b = ieee754dp_add;
2004 goto dcopbop;
2005 case fsub_op:
2006 handler.b = ieee754dp_sub;
2007 goto dcopbop;
2008 case fmul_op:
2009 handler.b = ieee754dp_mul;
2010 goto dcopbop;
2011 case fdiv_op:
2012 handler.b = ieee754dp_div;
2013 goto dcopbop;
2014
2015 /* unary ops */
2016 case fsqrt_op:
2017 if (!cpu_has_mips_2_3_4_5_r)
2018 return SIGILL;
2019
2020 handler.u = ieee754dp_sqrt;
2021 goto dcopuop;
2022 /*
2023 * Note that on some MIPS IV implementations such as the
2024 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2025 * achieve full IEEE-754 accuracy - however this emulator does.
2026 */
2027 case frsqrt_op:
2028 if (!cpu_has_mips_4_5_64_r2_r6)
2029 return SIGILL;
2030
2031 handler.u = fpemu_dp_rsqrt;
2032 goto dcopuop;
2033 case frecip_op:
2034 if (!cpu_has_mips_4_5_64_r2_r6)
2035 return SIGILL;
2036
2037 handler.u = fpemu_dp_recip;
2038 goto dcopuop;
2039 case fmovc_op:
2040 if (!cpu_has_mips_4_5_r)
2041 return SIGILL;
2042
2043 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2044 if (((ctx->fcr31 & cond) != 0) !=
2045 ((MIPSInst_FT(ir) & 1) != 0))
2046 return 0;
2047 DPFROMREG(rv.d, MIPSInst_FS(ir));
2048 break;
2049 case fmovz_op:
2050 if (!cpu_has_mips_4_5_r)
2051 return SIGILL;
2052
2053 if (xcp->regs[MIPSInst_FT(ir)] != 0)
2054 return 0;
2055 DPFROMREG(rv.d, MIPSInst_FS(ir));
2056 break;
2057 case fmovn_op:
2058 if (!cpu_has_mips_4_5_r)
2059 return SIGILL;
2060
2061 if (xcp->regs[MIPSInst_FT(ir)] == 0)
2062 return 0;
2063 DPFROMREG(rv.d, MIPSInst_FS(ir));
2064 break;
2065
2066 case fseleqz_op:
2067 if (!cpu_has_mips_r6)
2068 return SIGILL;
2069
2070 DPFROMREG(rv.d, MIPSInst_FT(ir));
2071 if (rv.l & 0x1)
2072 rv.l = 0;
2073 else
2074 DPFROMREG(rv.d, MIPSInst_FS(ir));
2075 break;
2076
2077 case fselnez_op:
2078 if (!cpu_has_mips_r6)
2079 return SIGILL;
2080
2081 DPFROMREG(rv.d, MIPSInst_FT(ir));
2082 if (rv.l & 0x1)
2083 DPFROMREG(rv.d, MIPSInst_FS(ir));
2084 else
2085 rv.l = 0;
2086 break;
2087
2088 case fmaddf_op: {
2089 union ieee754dp ft, fs, fd;
2090
2091 if (!cpu_has_mips_r6)
2092 return SIGILL;
2093
2094 DPFROMREG(ft, MIPSInst_FT(ir));
2095 DPFROMREG(fs, MIPSInst_FS(ir));
2096 DPFROMREG(fd, MIPSInst_FD(ir));
2097 rv.d = ieee754dp_maddf(fd, fs, ft);
2098 break;
2099 }
2100
2101 case fmsubf_op: {
2102 union ieee754dp ft, fs, fd;
2103
2104 if (!cpu_has_mips_r6)
2105 return SIGILL;
2106
2107 DPFROMREG(ft, MIPSInst_FT(ir));
2108 DPFROMREG(fs, MIPSInst_FS(ir));
2109 DPFROMREG(fd, MIPSInst_FD(ir));
2110 rv.d = ieee754dp_msubf(fd, fs, ft);
2111 break;
2112 }
2113
2114 case frint_op: {
2115 union ieee754dp fs;
2116
2117 if (!cpu_has_mips_r6)
2118 return SIGILL;
2119
2120 DPFROMREG(fs, MIPSInst_FS(ir));
2121 rv.l = ieee754dp_tlong(fs);
2122 rv.d = ieee754dp_flong(rv.l);
2123 goto copcsr;
2124 }
2125
2126 case fclass_op: {
2127 union ieee754dp fs;
2128
2129 if (!cpu_has_mips_r6)
2130 return SIGILL;
2131
2132 DPFROMREG(fs, MIPSInst_FS(ir));
2133 rv.w = ieee754dp_2008class(fs);
2134 rfmt = w_fmt;
2135 break;
2136 }
2137
2138 case fmin_op: {
2139 union ieee754dp fs, ft;
2140
2141 if (!cpu_has_mips_r6)
2142 return SIGILL;
2143
2144 DPFROMREG(ft, MIPSInst_FT(ir));
2145 DPFROMREG(fs, MIPSInst_FS(ir));
2146 rv.d = ieee754dp_fmin(fs, ft);
2147 break;
2148 }
2149
2150 case fmina_op: {
2151 union ieee754dp fs, ft;
2152
2153 if (!cpu_has_mips_r6)
2154 return SIGILL;
2155
2156 DPFROMREG(ft, MIPSInst_FT(ir));
2157 DPFROMREG(fs, MIPSInst_FS(ir));
2158 rv.d = ieee754dp_fmina(fs, ft);
2159 break;
2160 }
2161
2162 case fmax_op: {
2163 union ieee754dp fs, ft;
2164
2165 if (!cpu_has_mips_r6)
2166 return SIGILL;
2167
2168 DPFROMREG(ft, MIPSInst_FT(ir));
2169 DPFROMREG(fs, MIPSInst_FS(ir));
2170 rv.d = ieee754dp_fmax(fs, ft);
2171 break;
2172 }
2173
2174 case fmaxa_op: {
2175 union ieee754dp fs, ft;
2176
2177 if (!cpu_has_mips_r6)
2178 return SIGILL;
2179
2180 DPFROMREG(ft, MIPSInst_FT(ir));
2181 DPFROMREG(fs, MIPSInst_FS(ir));
2182 rv.d = ieee754dp_fmaxa(fs, ft);
2183 break;
2184 }
2185
2186 case fabs_op:
2187 handler.u = ieee754dp_abs;
2188 goto dcopuop;
2189
2190 case fneg_op:
2191 handler.u = ieee754dp_neg;
2192 goto dcopuop;
2193
2194 case fmov_op:
2195 /* an easy one */
2196 DPFROMREG(rv.d, MIPSInst_FS(ir));
2197 goto copcsr;
2198
2199 /* binary op on handler */
2200 dcopbop:
2201 DPFROMREG(fs, MIPSInst_FS(ir));
2202 DPFROMREG(ft, MIPSInst_FT(ir));
2203
2204 rv.d = (*handler.b) (fs, ft);
2205 goto copcsr;
2206 dcopuop:
2207 DPFROMREG(fs, MIPSInst_FS(ir));
2208 rv.d = (*handler.u) (fs);
2209 goto copcsr;
2210
2211 /*
2212 * unary conv ops
2213 */
2214 case fcvts_op:
2215 DPFROMREG(fs, MIPSInst_FS(ir));
2216 rv.s = ieee754sp_fdp(fs);
2217 rfmt = s_fmt;
2218 goto copcsr;
2219
2220 case fcvtd_op:
2221 return SIGILL; /* not defined */
2222
2223 case fcvtw_op:
2224 DPFROMREG(fs, MIPSInst_FS(ir));
2225 rv.w = ieee754dp_tint(fs); /* wrong */
2226 rfmt = w_fmt;
2227 goto copcsr;
2228
2229 case fround_op:
2230 case ftrunc_op:
2231 case fceil_op:
2232 case ffloor_op:
2233 if (!cpu_has_mips_2_3_4_5_r)
2234 return SIGILL;
2235
2236 oldrm = ieee754_csr.rm;
2237 DPFROMREG(fs, MIPSInst_FS(ir));
2238 ieee754_csr.rm = MIPSInst_FUNC(ir);
2239 rv.w = ieee754dp_tint(fs);
2240 ieee754_csr.rm = oldrm;
2241 rfmt = w_fmt;
2242 goto copcsr;
2243
2244 case fcvtl_op:
2245 if (!cpu_has_mips_3_4_5_64_r2_r6)
2246 return SIGILL;
2247
2248 DPFROMREG(fs, MIPSInst_FS(ir));
2249 rv.l = ieee754dp_tlong(fs);
2250 rfmt = l_fmt;
2251 goto copcsr;
2252
2253 case froundl_op:
2254 case ftruncl_op:
2255 case fceill_op:
2256 case ffloorl_op:
2257 if (!cpu_has_mips_3_4_5_64_r2_r6)
2258 return SIGILL;
2259
2260 oldrm = ieee754_csr.rm;
2261 DPFROMREG(fs, MIPSInst_FS(ir));
2262 ieee754_csr.rm = MIPSInst_FUNC(ir);
2263 rv.l = ieee754dp_tlong(fs);
2264 ieee754_csr.rm = oldrm;
2265 rfmt = l_fmt;
2266 goto copcsr;
2267
2268 default:
2269 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2270 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2271 union ieee754dp fs, ft;
2272
2273 DPFROMREG(fs, MIPSInst_FS(ir));
2274 DPFROMREG(ft, MIPSInst_FT(ir));
2275 rv.w = ieee754dp_cmp(fs, ft,
2276 cmptab[cmpop & 0x7], cmpop & 0x8);
2277 rfmt = -1;
2278 if ((cmpop & 0x8)
2279 &&
2280 ieee754_cxtest
2281 (IEEE754_INVALID_OPERATION))
2282 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2283 else
2284 goto copcsr;
2285
2286 }
2287 else {
2288 return SIGILL;
2289 }
2290 break;
2291 }
2292 break;
2293 }
2294
2295 case w_fmt: {
2296 union ieee754dp fs;
2297
2298 switch (MIPSInst_FUNC(ir)) {
2299 case fcvts_op:
2300 /* convert word to single precision real */
2301 SPFROMREG(fs, MIPSInst_FS(ir));
2302 rv.s = ieee754sp_fint(fs.bits);
2303 rfmt = s_fmt;
2304 goto copcsr;
2305 case fcvtd_op:
2306 /* convert word to double precision real */
2307 SPFROMREG(fs, MIPSInst_FS(ir));
2308 rv.d = ieee754dp_fint(fs.bits);
2309 rfmt = d_fmt;
2310 goto copcsr;
2311 default: {
2312 /* Emulating the new CMP.condn.fmt R6 instruction */
2313 #define CMPOP_MASK 0x7
2314 #define SIGN_BIT (0x1 << 3)
2315 #define PREDICATE_BIT (0x1 << 4)
2316
2317 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2318 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2319 union ieee754sp fs, ft;
2320
2321 /* This is an R6 only instruction */
2322 if (!cpu_has_mips_r6 ||
2323 (MIPSInst_FUNC(ir) & 0x20))
2324 return SIGILL;
2325
2326 /* fmt is w_fmt for single precision so fix it */
2327 rfmt = s_fmt;
2328 /* default to false */
2329 rv.w = 0;
2330
2331 /* CMP.condn.S */
2332 SPFROMREG(fs, MIPSInst_FS(ir));
2333 SPFROMREG(ft, MIPSInst_FT(ir));
2334
2335 /* positive predicates */
2336 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2337 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2338 sig))
2339 rv.w = -1; /* true, all 1s */
2340 if ((sig) &&
2341 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2342 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2343 else
2344 goto copcsr;
2345 } else {
2346 /* negative predicates */
2347 switch (cmpop) {
2348 case 1:
2349 case 2:
2350 case 3:
2351 if (ieee754sp_cmp(fs, ft,
2352 negative_cmptab[cmpop],
2353 sig))
2354 rv.w = -1; /* true, all 1s */
2355 if (sig &&
2356 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2357 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2358 else
2359 goto copcsr;
2360 break;
2361 default:
2362 /* Reserved R6 ops */
2363 pr_err("Reserved MIPS R6 CMP.condn.S operation\n");
2364 return SIGILL;
2365 }
2366 }
2367 break;
2368 }
2369 }
2370 }
2371
2372 case l_fmt:
2373
2374 if (!cpu_has_mips_3_4_5_64_r2_r6)
2375 return SIGILL;
2376
2377 DIFROMREG(bits, MIPSInst_FS(ir));
2378
2379 switch (MIPSInst_FUNC(ir)) {
2380 case fcvts_op:
2381 /* convert long to single precision real */
2382 rv.s = ieee754sp_flong(bits);
2383 rfmt = s_fmt;
2384 goto copcsr;
2385 case fcvtd_op:
2386 /* convert long to double precision real */
2387 rv.d = ieee754dp_flong(bits);
2388 rfmt = d_fmt;
2389 goto copcsr;
2390 default: {
2391 /* Emulating the new CMP.condn.fmt R6 instruction */
2392 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2393 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2394 union ieee754dp fs, ft;
2395
2396 if (!cpu_has_mips_r6 ||
2397 (MIPSInst_FUNC(ir) & 0x20))
2398 return SIGILL;
2399
2400 /* fmt is l_fmt for double precision so fix it */
2401 rfmt = d_fmt;
2402 /* default to false */
2403 rv.l = 0;
2404
2405 /* CMP.condn.D */
2406 DPFROMREG(fs, MIPSInst_FS(ir));
2407 DPFROMREG(ft, MIPSInst_FT(ir));
2408
2409 /* positive predicates */
2410 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2411 if (ieee754dp_cmp(fs, ft,
2412 cmptab[cmpop], sig))
2413 rv.l = -1LL; /* true, all 1s */
2414 if (sig &&
2415 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2416 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2417 else
2418 goto copcsr;
2419 } else {
2420 /* negative predicates */
2421 switch (cmpop) {
2422 case 1:
2423 case 2:
2424 case 3:
2425 if (ieee754dp_cmp(fs, ft,
2426 negative_cmptab[cmpop],
2427 sig))
2428 rv.l = -1LL; /* true, all 1s */
2429 if (sig &&
2430 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2431 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2432 else
2433 goto copcsr;
2434 break;
2435 default:
2436 /* Reserved R6 ops */
2437 pr_err("Reserved MIPS R6 CMP.condn.D operation\n");
2438 return SIGILL;
2439 }
2440 }
2441 break;
2442 }
2443 }
2444 default:
2445 return SIGILL;
2446 }
2447
2448 /*
2449 * Update the fpu CSR register for this operation.
2450 * If an exception is required, generate a tidy SIGFPE exception,
2451 * without updating the result register.
2452 * Note: cause exception bits do not accumulate, they are rewritten
2453 * for each op; only the flag/sticky bits accumulate.
2454 */
2455 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2456 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2457 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2458 return SIGFPE;
2459 }
2460
2461 /*
2462 * Now we can safely write the result back to the register file.
2463 */
2464 switch (rfmt) {
2465 case -1:
2466
2467 if (cpu_has_mips_4_5_r)
2468 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2469 else
2470 cbit = FPU_CSR_COND;
2471 if (rv.w)
2472 ctx->fcr31 |= cbit;
2473 else
2474 ctx->fcr31 &= ~cbit;
2475 break;
2476
2477 case d_fmt:
2478 DPTOREG(rv.d, MIPSInst_FD(ir));
2479 break;
2480 case s_fmt:
2481 SPTOREG(rv.s, MIPSInst_FD(ir));
2482 break;
2483 case w_fmt:
2484 SITOREG(rv.w, MIPSInst_FD(ir));
2485 break;
2486 case l_fmt:
2487 if (!cpu_has_mips_3_4_5_64_r2_r6)
2488 return SIGILL;
2489
2490 DITOREG(rv.l, MIPSInst_FD(ir));
2491 break;
2492 default:
2493 return SIGILL;
2494 }
2495
2496 return 0;
2497 }
2498
fpu_emulator_cop1Handler(struct pt_regs * xcp,struct mips_fpu_struct * ctx,int has_fpu,void * __user * fault_addr)2499 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2500 int has_fpu, void *__user *fault_addr)
2501 {
2502 unsigned long oldepc, prevepc;
2503 struct mm_decoded_insn dec_insn;
2504 u16 instr[4];
2505 u16 *instr_ptr;
2506 int sig = 0;
2507
2508 oldepc = xcp->cp0_epc;
2509 do {
2510 prevepc = xcp->cp0_epc;
2511
2512 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2513 /*
2514 * Get next 2 microMIPS instructions and convert them
2515 * into 32-bit instructions.
2516 */
2517 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2518 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2519 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2520 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2521 MIPS_FPU_EMU_INC_STATS(errors);
2522 return SIGBUS;
2523 }
2524 instr_ptr = instr;
2525
2526 /* Get first instruction. */
2527 if (mm_insn_16bit(*instr_ptr)) {
2528 /* Duplicate the half-word. */
2529 dec_insn.insn = (*instr_ptr << 16) |
2530 (*instr_ptr);
2531 /* 16-bit instruction. */
2532 dec_insn.pc_inc = 2;
2533 instr_ptr += 1;
2534 } else {
2535 dec_insn.insn = (*instr_ptr << 16) |
2536 *(instr_ptr+1);
2537 /* 32-bit instruction. */
2538 dec_insn.pc_inc = 4;
2539 instr_ptr += 2;
2540 }
2541 /* Get second instruction. */
2542 if (mm_insn_16bit(*instr_ptr)) {
2543 /* Duplicate the half-word. */
2544 dec_insn.next_insn = (*instr_ptr << 16) |
2545 (*instr_ptr);
2546 /* 16-bit instruction. */
2547 dec_insn.next_pc_inc = 2;
2548 } else {
2549 dec_insn.next_insn = (*instr_ptr << 16) |
2550 *(instr_ptr+1);
2551 /* 32-bit instruction. */
2552 dec_insn.next_pc_inc = 4;
2553 }
2554 dec_insn.micro_mips_mode = 1;
2555 } else {
2556 if ((get_user(dec_insn.insn,
2557 (mips_instruction __user *) xcp->cp0_epc)) ||
2558 (get_user(dec_insn.next_insn,
2559 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2560 MIPS_FPU_EMU_INC_STATS(errors);
2561 return SIGBUS;
2562 }
2563 dec_insn.pc_inc = 4;
2564 dec_insn.next_pc_inc = 4;
2565 dec_insn.micro_mips_mode = 0;
2566 }
2567
2568 if ((dec_insn.insn == 0) ||
2569 ((dec_insn.pc_inc == 2) &&
2570 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2571 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2572 else {
2573 /*
2574 * The 'ieee754_csr' is an alias of ctx->fcr31.
2575 * No need to copy ctx->fcr31 to ieee754_csr.
2576 */
2577 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2578 }
2579
2580 if (has_fpu)
2581 break;
2582 if (sig)
2583 break;
2584
2585 cond_resched();
2586 } while (xcp->cp0_epc > prevepc);
2587
2588 /* SIGILL indicates a non-fpu instruction */
2589 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2590 /* but if EPC has advanced, then ignore it */
2591 sig = 0;
2592
2593 return sig;
2594 }
2595