1 /*
2 * Copyright © 2006-2015, Intel Corporation.
3 *
4 * Authors: Ashok Raj <ashok.raj@intel.com>
5 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
6 * David Woodhouse <David.Woodhouse@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19 * Place - Suite 330, Boston, MA 02111-1307 USA.
20 */
21
22 #ifndef _INTEL_IOMMU_H_
23 #define _INTEL_IOMMU_H_
24
25 #include <linux/types.h>
26 #include <linux/iova.h>
27 #include <linux/io.h>
28 #include <linux/idr.h>
29 #include <linux/dma_remapping.h>
30 #include <linux/mmu_notifier.h>
31 #include <linux/list.h>
32 #include <asm/cacheflush.h>
33 #include <asm/iommu.h>
34
35 /*
36 * Intel IOMMU register specification per version 1.0 public spec.
37 */
38
39 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
40 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
41 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
42 #define DMAR_GCMD_REG 0x18 /* Global command register */
43 #define DMAR_GSTS_REG 0x1c /* Global status register */
44 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
45 #define DMAR_CCMD_REG 0x28 /* Context command reg */
46 #define DMAR_FSTS_REG 0x34 /* Fault Status register */
47 #define DMAR_FECTL_REG 0x38 /* Fault control register */
48 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
49 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
50 #define DMAR_FEUADDR_REG 0x44 /* Upper address register */
51 #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
52 #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
53 #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
54 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
55 #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
56 #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
57 #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
58 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
59 #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
60 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
61 #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
62 #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
63 #define DMAR_PQH_REG 0xc0 /* Page request queue head register */
64 #define DMAR_PQT_REG 0xc8 /* Page request queue tail register */
65 #define DMAR_PQA_REG 0xd0 /* Page request queue address register */
66 #define DMAR_PRS_REG 0xdc /* Page request status register */
67 #define DMAR_PECTL_REG 0xe0 /* Page request event control register */
68 #define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */
69 #define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
70 #define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */
71
72 #define OFFSET_STRIDE (9)
73
74 #ifdef CONFIG_64BIT
75 #define dmar_readq(a) readq(a)
76 #define dmar_writeq(a,v) writeq(v,a)
77 #else
dmar_readq(void __iomem * addr)78 static inline u64 dmar_readq(void __iomem *addr)
79 {
80 u32 lo, hi;
81 lo = readl(addr);
82 hi = readl(addr + 4);
83 return (((u64) hi) << 32) + lo;
84 }
85
dmar_writeq(void __iomem * addr,u64 val)86 static inline void dmar_writeq(void __iomem *addr, u64 val)
87 {
88 writel((u32)val, addr);
89 writel((u32)(val >> 32), addr + 4);
90 }
91 #endif
92
93 #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
94 #define DMAR_VER_MINOR(v) ((v) & 0x0f)
95
96 /*
97 * Decoding Capability Register
98 */
99 #define cap_pi_support(c) (((c) >> 59) & 1)
100 #define cap_read_drain(c) (((c) >> 55) & 1)
101 #define cap_write_drain(c) (((c) >> 54) & 1)
102 #define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
103 #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
104 #define cap_pgsel_inv(c) (((c) >> 39) & 1)
105
106 #define cap_super_page_val(c) (((c) >> 34) & 0xf)
107 #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
108 * OFFSET_STRIDE) + 21)
109
110 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
111 #define cap_max_fault_reg_offset(c) \
112 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
113
114 #define cap_zlr(c) (((c) >> 22) & 1)
115 #define cap_isoch(c) (((c) >> 23) & 1)
116 #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
117 #define cap_sagaw(c) (((c) >> 8) & 0x1f)
118 #define cap_caching_mode(c) (((c) >> 7) & 1)
119 #define cap_phmr(c) (((c) >> 6) & 1)
120 #define cap_plmr(c) (((c) >> 5) & 1)
121 #define cap_rwbf(c) (((c) >> 4) & 1)
122 #define cap_afl(c) (((c) >> 3) & 1)
123 #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
124 /*
125 * Extended Capability Register
126 */
127
128 #define ecap_pasid(e) ((e >> 40) & 0x1)
129 #define ecap_pss(e) ((e >> 35) & 0x1f)
130 #define ecap_eafs(e) ((e >> 34) & 0x1)
131 #define ecap_nwfs(e) ((e >> 33) & 0x1)
132 #define ecap_srs(e) ((e >> 31) & 0x1)
133 #define ecap_ers(e) ((e >> 30) & 0x1)
134 #define ecap_prs(e) ((e >> 29) & 0x1)
135 #define ecap_broken_pasid(e) ((e >> 28) & 0x1)
136 #define ecap_dis(e) ((e >> 27) & 0x1)
137 #define ecap_nest(e) ((e >> 26) & 0x1)
138 #define ecap_mts(e) ((e >> 25) & 0x1)
139 #define ecap_ecs(e) ((e >> 24) & 0x1)
140 #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
141 #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
142 #define ecap_coherent(e) ((e) & 0x1)
143 #define ecap_qis(e) ((e) & 0x2)
144 #define ecap_pass_through(e) ((e >> 6) & 0x1)
145 #define ecap_eim_support(e) ((e >> 4) & 0x1)
146 #define ecap_ir_support(e) ((e >> 3) & 0x1)
147 #define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)
148 #define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
149 #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */
150
151 /* IOTLB_REG */
152 #define DMA_TLB_FLUSH_GRANU_OFFSET 60
153 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
154 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
155 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
156 #define DMA_TLB_IIRG(type) ((type >> 60) & 7)
157 #define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
158 #define DMA_TLB_READ_DRAIN (((u64)1) << 49)
159 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
160 #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
161 #define DMA_TLB_IVT (((u64)1) << 63)
162 #define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
163 #define DMA_TLB_MAX_SIZE (0x3f)
164
165 /* INVALID_DESC */
166 #define DMA_CCMD_INVL_GRANU_OFFSET 61
167 #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3)
168 #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3)
169 #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3)
170 #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
171 #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
172 #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
173 #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
174 #define DMA_ID_TLB_ADDR(addr) (addr)
175 #define DMA_ID_TLB_ADDR_MASK(mask) (mask)
176
177 /* PMEN_REG */
178 #define DMA_PMEN_EPM (((u32)1)<<31)
179 #define DMA_PMEN_PRS (((u32)1)<<0)
180
181 /* GCMD_REG */
182 #define DMA_GCMD_TE (((u32)1) << 31)
183 #define DMA_GCMD_SRTP (((u32)1) << 30)
184 #define DMA_GCMD_SFL (((u32)1) << 29)
185 #define DMA_GCMD_EAFL (((u32)1) << 28)
186 #define DMA_GCMD_WBF (((u32)1) << 27)
187 #define DMA_GCMD_QIE (((u32)1) << 26)
188 #define DMA_GCMD_SIRTP (((u32)1) << 24)
189 #define DMA_GCMD_IRE (((u32) 1) << 25)
190 #define DMA_GCMD_CFI (((u32) 1) << 23)
191
192 /* GSTS_REG */
193 #define DMA_GSTS_TES (((u32)1) << 31)
194 #define DMA_GSTS_RTPS (((u32)1) << 30)
195 #define DMA_GSTS_FLS (((u32)1) << 29)
196 #define DMA_GSTS_AFLS (((u32)1) << 28)
197 #define DMA_GSTS_WBFS (((u32)1) << 27)
198 #define DMA_GSTS_QIES (((u32)1) << 26)
199 #define DMA_GSTS_IRTPS (((u32)1) << 24)
200 #define DMA_GSTS_IRES (((u32)1) << 25)
201 #define DMA_GSTS_CFIS (((u32)1) << 23)
202
203 /* DMA_RTADDR_REG */
204 #define DMA_RTADDR_RTT (((u64)1) << 11)
205
206 /* CCMD_REG */
207 #define DMA_CCMD_ICC (((u64)1) << 63)
208 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
209 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
210 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
211 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
212 #define DMA_CCMD_MASK_NOBIT 0
213 #define DMA_CCMD_MASK_1BIT 1
214 #define DMA_CCMD_MASK_2BIT 2
215 #define DMA_CCMD_MASK_3BIT 3
216 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
217 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
218
219 /* FECTL_REG */
220 #define DMA_FECTL_IM (((u32)1) << 31)
221
222 /* FSTS_REG */
223 #define DMA_FSTS_PPF ((u32)2)
224 #define DMA_FSTS_PFO ((u32)1)
225 #define DMA_FSTS_IQE (1 << 4)
226 #define DMA_FSTS_ICE (1 << 5)
227 #define DMA_FSTS_ITE (1 << 6)
228 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
229
230 /* FRCD_REG, 32 bits access */
231 #define DMA_FRCD_F (((u32)1) << 31)
232 #define dma_frcd_type(d) ((d >> 30) & 1)
233 #define dma_frcd_fault_reason(c) (c & 0xff)
234 #define dma_frcd_source_id(c) (c & 0xffff)
235 /* low 64 bit */
236 #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
237
238 /* PRS_REG */
239 #define DMA_PRS_PPR ((u32)1)
240
241 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
242 do { \
243 cycles_t start_time = get_cycles(); \
244 while (1) { \
245 sts = op(iommu->reg + offset); \
246 if (cond) \
247 break; \
248 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
249 panic("DMAR hardware is malfunctioning\n"); \
250 cpu_relax(); \
251 } \
252 } while (0)
253
254 #define QI_LENGTH 256 /* queue length */
255
256 enum {
257 QI_FREE,
258 QI_IN_USE,
259 QI_DONE,
260 QI_ABORT
261 };
262
263 #define QI_CC_TYPE 0x1
264 #define QI_IOTLB_TYPE 0x2
265 #define QI_DIOTLB_TYPE 0x3
266 #define QI_IEC_TYPE 0x4
267 #define QI_IWD_TYPE 0x5
268 #define QI_EIOTLB_TYPE 0x6
269 #define QI_PC_TYPE 0x7
270 #define QI_DEIOTLB_TYPE 0x8
271 #define QI_PGRP_RESP_TYPE 0x9
272 #define QI_PSTRM_RESP_TYPE 0xa
273
274 #define QI_IEC_SELECTIVE (((u64)1) << 4)
275 #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
276 #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
277
278 #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
279 #define QI_IWD_STATUS_WRITE (((u64)1) << 5)
280
281 #define QI_IOTLB_DID(did) (((u64)did) << 16)
282 #define QI_IOTLB_DR(dr) (((u64)dr) << 7)
283 #define QI_IOTLB_DW(dw) (((u64)dw) << 6)
284 #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
285 #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
286 #define QI_IOTLB_IH(ih) (((u64)ih) << 6)
287 #define QI_IOTLB_AM(am) (((u8)am))
288
289 #define QI_CC_FM(fm) (((u64)fm) << 48)
290 #define QI_CC_SID(sid) (((u64)sid) << 32)
291 #define QI_CC_DID(did) (((u64)did) << 16)
292 #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
293
294 #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
295 #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
296 #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
297 #define QI_DEV_IOTLB_SIZE 1
298 #define QI_DEV_IOTLB_MAX_INVS 32
299
300 #define QI_PC_PASID(pasid) (((u64)pasid) << 32)
301 #define QI_PC_DID(did) (((u64)did) << 16)
302 #define QI_PC_GRAN(gran) (((u64)gran) << 4)
303
304 #define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0))
305 #define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1))
306
307 #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
308 #define QI_EIOTLB_GL(gl) (((u64)gl) << 7)
309 #define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
310 #define QI_EIOTLB_AM(am) (((u64)am))
311 #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
312 #define QI_EIOTLB_DID(did) (((u64)did) << 16)
313 #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
314
315 #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
316 #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
317 #define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
318 #define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
319 #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
320 #define QI_DEV_EIOTLB_QDEP(qd) (((qd) & 0x1f) << 16)
321 #define QI_DEV_EIOTLB_MAX_INVS 32
322
323 #define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)
324 #define QI_PGRP_PRIV(priv) (((u64)(priv)) << 32)
325 #define QI_PGRP_RESP_CODE(res) ((u64)(res))
326 #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
327 #define QI_PGRP_DID(did) (((u64)(did)) << 16)
328 #define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
329
330 #define QI_PSTRM_ADDR(addr) (((u64)(addr)) & VTD_PAGE_MASK)
331 #define QI_PSTRM_DEVFN(devfn) (((u64)(devfn)) << 4)
332 #define QI_PSTRM_RESP_CODE(res) ((u64)(res))
333 #define QI_PSTRM_IDX(idx) (((u64)(idx)) << 55)
334 #define QI_PSTRM_PRIV(priv) (((u64)(priv)) << 32)
335 #define QI_PSTRM_BUS(bus) (((u64)(bus)) << 24)
336 #define QI_PSTRM_PASID(pasid) (((u64)(pasid)) << 4)
337
338 #define QI_RESP_SUCCESS 0x0
339 #define QI_RESP_INVALID 0x1
340 #define QI_RESP_FAILURE 0xf
341
342 #define QI_GRAN_ALL_ALL 0
343 #define QI_GRAN_NONG_ALL 1
344 #define QI_GRAN_NONG_PASID 2
345 #define QI_GRAN_PSI_PASID 3
346
347 struct qi_desc {
348 u64 low, high;
349 };
350
351 struct q_inval {
352 raw_spinlock_t q_lock;
353 struct qi_desc *desc; /* invalidation queue */
354 int *desc_status; /* desc status */
355 int free_head; /* first free entry */
356 int free_tail; /* last free entry */
357 int free_cnt;
358 };
359
360 #ifdef CONFIG_IRQ_REMAP
361 /* 1MB - maximum possible interrupt remapping table size */
362 #define INTR_REMAP_PAGE_ORDER 8
363 #define INTR_REMAP_TABLE_REG_SIZE 0xf
364 #define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf
365
366 #define INTR_REMAP_TABLE_ENTRIES 65536
367
368 struct irq_domain;
369
370 struct ir_table {
371 struct irte *base;
372 unsigned long *bitmap;
373 };
374 #endif
375
376 struct iommu_flush {
377 void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
378 u8 fm, u64 type);
379 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
380 unsigned int size_order, u64 type);
381 };
382
383 enum {
384 SR_DMAR_FECTL_REG,
385 SR_DMAR_FEDATA_REG,
386 SR_DMAR_FEADDR_REG,
387 SR_DMAR_FEUADDR_REG,
388 MAX_SR_DMAR_REGS
389 };
390
391 #define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
392 #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
393
394 struct pasid_entry;
395 struct pasid_state_entry;
396 struct page_req_dsc;
397
398 struct intel_iommu {
399 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
400 u64 reg_phys; /* physical address of hw register set */
401 u64 reg_size; /* size of hw register set */
402 u64 cap;
403 u64 ecap;
404 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
405 raw_spinlock_t register_lock; /* protect register handling */
406 int seq_id; /* sequence id of the iommu */
407 int agaw; /* agaw of this iommu */
408 int msagaw; /* max sagaw of this iommu */
409 unsigned int irq, pr_irq;
410 u16 segment; /* PCI segment# */
411 unsigned char name[13]; /* Device Name */
412
413 #ifdef CONFIG_INTEL_IOMMU
414 unsigned long *domain_ids; /* bitmap of domains */
415 struct dmar_domain ***domains; /* ptr to domains */
416 spinlock_t lock; /* protect context, domain ids */
417 struct root_entry *root_entry; /* virtual address */
418
419 struct iommu_flush flush;
420 #endif
421 #ifdef CONFIG_INTEL_IOMMU_SVM
422 /* These are large and need to be contiguous, so we allocate just
423 * one for now. We'll maybe want to rethink that if we truly give
424 * devices away to userspace processes (e.g. for DPDK) and don't
425 * want to trust that userspace will use *only* the PASID it was
426 * told to. But while it's all driver-arbitrated, we're fine. */
427 struct pasid_entry *pasid_table;
428 struct pasid_state_entry *pasid_state_table;
429 struct page_req_dsc *prq;
430 unsigned char prq_name[16]; /* Name for PRQ interrupt */
431 struct idr pasid_idr;
432 #endif
433 struct q_inval *qi; /* Queued invalidation info */
434 u32 *iommu_state; /* Store iommu states between suspend and resume.*/
435
436 #ifdef CONFIG_IRQ_REMAP
437 struct ir_table *ir_table; /* Interrupt remapping info */
438 struct irq_domain *ir_domain;
439 struct irq_domain *ir_msi_domain;
440 #endif
441 struct device *iommu_dev; /* IOMMU-sysfs device */
442 int node;
443 u32 flags; /* Software defined flags */
444 };
445
__iommu_flush_cache(struct intel_iommu * iommu,void * addr,int size)446 static inline void __iommu_flush_cache(
447 struct intel_iommu *iommu, void *addr, int size)
448 {
449 if (!ecap_coherent(iommu->ecap))
450 clflush_cache_range(addr, size);
451 }
452
453 extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
454 extern int dmar_find_matched_atsr_unit(struct pci_dev *dev);
455
456 extern int dmar_enable_qi(struct intel_iommu *iommu);
457 extern void dmar_disable_qi(struct intel_iommu *iommu);
458 extern int dmar_reenable_qi(struct intel_iommu *iommu);
459 extern void qi_global_iec(struct intel_iommu *iommu);
460
461 extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
462 u8 fm, u64 type);
463 extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
464 unsigned int size_order, u64 type);
465 extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
466 u64 addr, unsigned mask);
467
468 extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
469
470 extern int dmar_ir_support(void);
471
472 #ifdef CONFIG_INTEL_IOMMU_SVM
473 extern int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu);
474 extern int intel_svm_free_pasid_tables(struct intel_iommu *iommu);
475 extern int intel_svm_enable_prq(struct intel_iommu *iommu);
476 extern int intel_svm_finish_prq(struct intel_iommu *iommu);
477
478 struct svm_dev_ops;
479
480 struct intel_svm_dev {
481 struct list_head list;
482 struct rcu_head rcu;
483 struct device *dev;
484 struct svm_dev_ops *ops;
485 int users;
486 u16 did;
487 u16 dev_iotlb:1;
488 u16 sid, qdep;
489 };
490
491 struct intel_svm {
492 struct mmu_notifier notifier;
493 struct mm_struct *mm;
494 struct intel_iommu *iommu;
495 int flags;
496 int pasid;
497 struct list_head devs;
498 };
499
500 extern int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev);
501 extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev);
502 #endif
503
504 extern const struct attribute_group *intel_iommu_groups[];
505
506 #endif
507