1 /*
2 * linux/drivers/video/omap2/dss/dss.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #define DSS_SUBSYS_NAME "DSS"
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/io.h>
28 #include <linux/export.h>
29 #include <linux/err.h>
30 #include <linux/delay.h>
31 #include <linux/seq_file.h>
32 #include <linux/clk.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/gfp.h>
36 #include <linux/sizes.h>
37 #include <linux/mfd/syscon.h>
38 #include <linux/regmap.h>
39 #include <linux/of.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/suspend.h>
42
43 #include <video/omapdss.h>
44
45 #include "dss.h"
46 #include "dss_features.h"
47
48 #define DSS_SZ_REGS SZ_512
49
50 struct dss_reg {
51 u16 idx;
52 };
53
54 #define DSS_REG(idx) ((const struct dss_reg) { idx })
55
56 #define DSS_REVISION DSS_REG(0x0000)
57 #define DSS_SYSCONFIG DSS_REG(0x0010)
58 #define DSS_SYSSTATUS DSS_REG(0x0014)
59 #define DSS_CONTROL DSS_REG(0x0040)
60 #define DSS_SDI_CONTROL DSS_REG(0x0044)
61 #define DSS_PLL_CONTROL DSS_REG(0x0048)
62 #define DSS_SDI_STATUS DSS_REG(0x005C)
63
64 #define REG_GET(idx, start, end) \
65 FLD_GET(dss_read_reg(idx), start, end)
66
67 #define REG_FLD_MOD(idx, val, start, end) \
68 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
69
70 struct dss_features {
71 u8 fck_div_max;
72 u8 dss_fck_multiplier;
73 const char *parent_clk_name;
74 const enum omap_display_type *ports;
75 int num_ports;
76 int (*dpi_select_source)(int port, enum omap_channel channel);
77 };
78
79 static struct {
80 struct platform_device *pdev;
81 void __iomem *base;
82 struct regmap *syscon_pll_ctrl;
83 u32 syscon_pll_ctrl_offset;
84
85 struct clk *parent_clk;
86 struct clk *dss_clk;
87 unsigned long dss_clk_rate;
88
89 unsigned long cache_req_pck;
90 unsigned long cache_prate;
91 struct dispc_clock_info cache_dispc_cinfo;
92
93 enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
94 enum omap_dss_clk_source dispc_clk_source;
95 enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
96
97 bool ctx_valid;
98 u32 ctx[DSS_SZ_REGS / sizeof(u32)];
99
100 const struct dss_features *feat;
101
102 struct dss_pll *video1_pll;
103 struct dss_pll *video2_pll;
104 } dss;
105
106 static const char * const dss_generic_clk_source_names[] = {
107 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC",
108 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI",
109 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK",
110 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DSI_PLL2_HSDIV_DISPC",
111 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DSI_PLL2_HSDIV_DSI",
112 };
113
dss_write_reg(const struct dss_reg idx,u32 val)114 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
115 {
116 __raw_writel(val, dss.base + idx.idx);
117 }
118
dss_read_reg(const struct dss_reg idx)119 static inline u32 dss_read_reg(const struct dss_reg idx)
120 {
121 return __raw_readl(dss.base + idx.idx);
122 }
123
124 #define SR(reg) \
125 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
126 #define RR(reg) \
127 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
128
dss_save_context(void)129 static void dss_save_context(void)
130 {
131 DSSDBG("dss_save_context\n");
132
133 SR(CONTROL);
134
135 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
136 OMAP_DISPLAY_TYPE_SDI) {
137 SR(SDI_CONTROL);
138 SR(PLL_CONTROL);
139 }
140
141 dss.ctx_valid = true;
142
143 DSSDBG("context saved\n");
144 }
145
dss_restore_context(void)146 static void dss_restore_context(void)
147 {
148 DSSDBG("dss_restore_context\n");
149
150 if (!dss.ctx_valid)
151 return;
152
153 RR(CONTROL);
154
155 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
156 OMAP_DISPLAY_TYPE_SDI) {
157 RR(SDI_CONTROL);
158 RR(PLL_CONTROL);
159 }
160
161 DSSDBG("context restored\n");
162 }
163
164 #undef SR
165 #undef RR
166
dss_ctrl_pll_enable(enum dss_pll_id pll_id,bool enable)167 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable)
168 {
169 unsigned shift;
170 unsigned val;
171
172 if (!dss.syscon_pll_ctrl)
173 return;
174
175 val = !enable;
176
177 switch (pll_id) {
178 case DSS_PLL_VIDEO1:
179 shift = 0;
180 break;
181 case DSS_PLL_VIDEO2:
182 shift = 1;
183 break;
184 case DSS_PLL_HDMI:
185 shift = 2;
186 break;
187 default:
188 DSSERR("illegal DSS PLL ID %d\n", pll_id);
189 return;
190 }
191
192 regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
193 1 << shift, val << shift);
194 }
195
dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,enum omap_channel channel)196 void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
197 enum omap_channel channel)
198 {
199 unsigned shift, val;
200
201 if (!dss.syscon_pll_ctrl)
202 return;
203
204 switch (channel) {
205 case OMAP_DSS_CHANNEL_LCD:
206 shift = 3;
207
208 switch (pll_id) {
209 case DSS_PLL_VIDEO1:
210 val = 0; break;
211 case DSS_PLL_HDMI:
212 val = 1; break;
213 default:
214 DSSERR("error in PLL mux config for LCD\n");
215 return;
216 }
217
218 break;
219 case OMAP_DSS_CHANNEL_LCD2:
220 shift = 5;
221
222 switch (pll_id) {
223 case DSS_PLL_VIDEO1:
224 val = 0; break;
225 case DSS_PLL_VIDEO2:
226 val = 1; break;
227 case DSS_PLL_HDMI:
228 val = 2; break;
229 default:
230 DSSERR("error in PLL mux config for LCD2\n");
231 return;
232 }
233
234 break;
235 case OMAP_DSS_CHANNEL_LCD3:
236 shift = 7;
237
238 switch (pll_id) {
239 case DSS_PLL_VIDEO1:
240 val = 1; break;
241 case DSS_PLL_VIDEO2:
242 val = 0; break;
243 case DSS_PLL_HDMI:
244 val = 2; break;
245 default:
246 DSSERR("error in PLL mux config for LCD3\n");
247 return;
248 }
249
250 break;
251 default:
252 DSSERR("error in PLL mux config\n");
253 return;
254 }
255
256 regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
257 0x3 << shift, val << shift);
258 }
259
dss_sdi_init(int datapairs)260 void dss_sdi_init(int datapairs)
261 {
262 u32 l;
263
264 BUG_ON(datapairs > 3 || datapairs < 1);
265
266 l = dss_read_reg(DSS_SDI_CONTROL);
267 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
268 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
269 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
270 dss_write_reg(DSS_SDI_CONTROL, l);
271
272 l = dss_read_reg(DSS_PLL_CONTROL);
273 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
274 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
275 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
276 dss_write_reg(DSS_PLL_CONTROL, l);
277 }
278
dss_sdi_enable(void)279 int dss_sdi_enable(void)
280 {
281 unsigned long timeout;
282
283 dispc_pck_free_enable(1);
284
285 /* Reset SDI PLL */
286 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
287 udelay(1); /* wait 2x PCLK */
288
289 /* Lock SDI PLL */
290 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
291
292 /* Waiting for PLL lock request to complete */
293 timeout = jiffies + msecs_to_jiffies(500);
294 while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
295 if (time_after_eq(jiffies, timeout)) {
296 DSSERR("PLL lock request timed out\n");
297 goto err1;
298 }
299 }
300
301 /* Clearing PLL_GO bit */
302 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
303
304 /* Waiting for PLL to lock */
305 timeout = jiffies + msecs_to_jiffies(500);
306 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
307 if (time_after_eq(jiffies, timeout)) {
308 DSSERR("PLL lock timed out\n");
309 goto err1;
310 }
311 }
312
313 dispc_lcd_enable_signal(1);
314
315 /* Waiting for SDI reset to complete */
316 timeout = jiffies + msecs_to_jiffies(500);
317 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
318 if (time_after_eq(jiffies, timeout)) {
319 DSSERR("SDI reset timed out\n");
320 goto err2;
321 }
322 }
323
324 return 0;
325
326 err2:
327 dispc_lcd_enable_signal(0);
328 err1:
329 /* Reset SDI PLL */
330 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
331
332 dispc_pck_free_enable(0);
333
334 return -ETIMEDOUT;
335 }
336
dss_sdi_disable(void)337 void dss_sdi_disable(void)
338 {
339 dispc_lcd_enable_signal(0);
340
341 dispc_pck_free_enable(0);
342
343 /* Reset SDI PLL */
344 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
345 }
346
dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)347 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
348 {
349 return dss_generic_clk_source_names[clk_src];
350 }
351
dss_dump_clocks(struct seq_file * s)352 void dss_dump_clocks(struct seq_file *s)
353 {
354 const char *fclk_name, *fclk_real_name;
355 unsigned long fclk_rate;
356
357 if (dss_runtime_get())
358 return;
359
360 seq_printf(s, "- DSS -\n");
361
362 fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
363 fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
364 fclk_rate = clk_get_rate(dss.dss_clk);
365
366 seq_printf(s, "%s (%s) = %lu\n",
367 fclk_name, fclk_real_name,
368 fclk_rate);
369
370 dss_runtime_put();
371 }
372
dss_dump_regs(struct seq_file * s)373 static void dss_dump_regs(struct seq_file *s)
374 {
375 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
376
377 if (dss_runtime_get())
378 return;
379
380 DUMPREG(DSS_REVISION);
381 DUMPREG(DSS_SYSCONFIG);
382 DUMPREG(DSS_SYSSTATUS);
383 DUMPREG(DSS_CONTROL);
384
385 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
386 OMAP_DISPLAY_TYPE_SDI) {
387 DUMPREG(DSS_SDI_CONTROL);
388 DUMPREG(DSS_PLL_CONTROL);
389 DUMPREG(DSS_SDI_STATUS);
390 }
391
392 dss_runtime_put();
393 #undef DUMPREG
394 }
395
dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)396 static void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
397 {
398 int b;
399 u8 start, end;
400
401 switch (clk_src) {
402 case OMAP_DSS_CLK_SRC_FCK:
403 b = 0;
404 break;
405 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
406 b = 1;
407 break;
408 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
409 b = 2;
410 break;
411 default:
412 BUG();
413 return;
414 }
415
416 dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
417
418 REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */
419
420 dss.dispc_clk_source = clk_src;
421 }
422
dss_select_dsi_clk_source(int dsi_module,enum omap_dss_clk_source clk_src)423 void dss_select_dsi_clk_source(int dsi_module,
424 enum omap_dss_clk_source clk_src)
425 {
426 int b, pos;
427
428 switch (clk_src) {
429 case OMAP_DSS_CLK_SRC_FCK:
430 b = 0;
431 break;
432 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
433 BUG_ON(dsi_module != 0);
434 b = 1;
435 break;
436 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
437 BUG_ON(dsi_module != 1);
438 b = 1;
439 break;
440 default:
441 BUG();
442 return;
443 }
444
445 pos = dsi_module == 0 ? 1 : 10;
446 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */
447
448 dss.dsi_clk_source[dsi_module] = clk_src;
449 }
450
dss_select_lcd_clk_source(enum omap_channel channel,enum omap_dss_clk_source clk_src)451 void dss_select_lcd_clk_source(enum omap_channel channel,
452 enum omap_dss_clk_source clk_src)
453 {
454 int b, ix, pos;
455
456 if (!dss_has_feature(FEAT_LCD_CLK_SRC)) {
457 dss_select_dispc_clk_source(clk_src);
458 return;
459 }
460
461 switch (clk_src) {
462 case OMAP_DSS_CLK_SRC_FCK:
463 b = 0;
464 break;
465 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
466 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
467 b = 1;
468 break;
469 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
470 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 &&
471 channel != OMAP_DSS_CHANNEL_LCD3);
472 b = 1;
473 break;
474 default:
475 BUG();
476 return;
477 }
478
479 pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
480 (channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19);
481 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */
482
483 ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
484 (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
485 dss.lcd_clk_source[ix] = clk_src;
486 }
487
dss_get_dispc_clk_source(void)488 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
489 {
490 return dss.dispc_clk_source;
491 }
492
dss_get_dsi_clk_source(int dsi_module)493 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
494 {
495 return dss.dsi_clk_source[dsi_module];
496 }
497
dss_get_lcd_clk_source(enum omap_channel channel)498 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
499 {
500 if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
501 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
502 (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
503 return dss.lcd_clk_source[ix];
504 } else {
505 /* LCD_CLK source is the same as DISPC_FCLK source for
506 * OMAP2 and OMAP3 */
507 return dss.dispc_clk_source;
508 }
509 }
510
dss_div_calc(unsigned long pck,unsigned long fck_min,dss_div_calc_func func,void * data)511 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
512 dss_div_calc_func func, void *data)
513 {
514 int fckd, fckd_start, fckd_stop;
515 unsigned long fck;
516 unsigned long fck_hw_max;
517 unsigned long fckd_hw_max;
518 unsigned long prate;
519 unsigned m;
520
521 fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
522
523 if (dss.parent_clk == NULL) {
524 unsigned pckd;
525
526 pckd = fck_hw_max / pck;
527
528 fck = pck * pckd;
529
530 fck = clk_round_rate(dss.dss_clk, fck);
531
532 return func(fck, data);
533 }
534
535 fckd_hw_max = dss.feat->fck_div_max;
536
537 m = dss.feat->dss_fck_multiplier;
538 prate = clk_get_rate(dss.parent_clk);
539
540 fck_min = fck_min ? fck_min : 1;
541
542 fckd_start = min(prate * m / fck_min, fckd_hw_max);
543 fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
544
545 for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
546 fck = DIV_ROUND_UP(prate, fckd) * m;
547
548 if (func(fck, data))
549 return true;
550 }
551
552 return false;
553 }
554
dss_set_fck_rate(unsigned long rate)555 int dss_set_fck_rate(unsigned long rate)
556 {
557 int r;
558
559 DSSDBG("set fck to %lu\n", rate);
560
561 r = clk_set_rate(dss.dss_clk, rate);
562 if (r)
563 return r;
564
565 dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
566
567 WARN_ONCE(dss.dss_clk_rate != rate,
568 "clk rate mismatch: %lu != %lu", dss.dss_clk_rate,
569 rate);
570
571 return 0;
572 }
573
dss_get_dispc_clk_rate(void)574 unsigned long dss_get_dispc_clk_rate(void)
575 {
576 return dss.dss_clk_rate;
577 }
578
dss_setup_default_clock(void)579 static int dss_setup_default_clock(void)
580 {
581 unsigned long max_dss_fck, prate;
582 unsigned long fck;
583 unsigned fck_div;
584 int r;
585
586 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
587
588 if (dss.parent_clk == NULL) {
589 fck = clk_round_rate(dss.dss_clk, max_dss_fck);
590 } else {
591 prate = clk_get_rate(dss.parent_clk);
592
593 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
594 max_dss_fck);
595 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier;
596 }
597
598 r = dss_set_fck_rate(fck);
599 if (r)
600 return r;
601
602 return 0;
603 }
604
dss_set_venc_output(enum omap_dss_venc_type type)605 void dss_set_venc_output(enum omap_dss_venc_type type)
606 {
607 int l = 0;
608
609 if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
610 l = 0;
611 else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
612 l = 1;
613 else
614 BUG();
615
616 /* venc out selection. 0 = comp, 1 = svideo */
617 REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
618 }
619
dss_set_dac_pwrdn_bgz(bool enable)620 void dss_set_dac_pwrdn_bgz(bool enable)
621 {
622 REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
623 }
624
dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)625 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)
626 {
627 enum omap_display_type dp;
628 dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
629
630 /* Complain about invalid selections */
631 WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC));
632 WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI));
633
634 /* Select only if we have options */
635 if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI))
636 REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */
637 }
638
dss_get_hdmi_venc_clk_source(void)639 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
640 {
641 enum omap_display_type displays;
642
643 displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
644 if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
645 return DSS_VENC_TV_CLK;
646
647 if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0)
648 return DSS_HDMI_M_PCLK;
649
650 return REG_GET(DSS_CONTROL, 15, 15);
651 }
652
dss_dpi_select_source_omap2_omap3(int port,enum omap_channel channel)653 static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel)
654 {
655 if (channel != OMAP_DSS_CHANNEL_LCD)
656 return -EINVAL;
657
658 return 0;
659 }
660
dss_dpi_select_source_omap4(int port,enum omap_channel channel)661 static int dss_dpi_select_source_omap4(int port, enum omap_channel channel)
662 {
663 int val;
664
665 switch (channel) {
666 case OMAP_DSS_CHANNEL_LCD2:
667 val = 0;
668 break;
669 case OMAP_DSS_CHANNEL_DIGIT:
670 val = 1;
671 break;
672 default:
673 return -EINVAL;
674 }
675
676 REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
677
678 return 0;
679 }
680
dss_dpi_select_source_omap5(int port,enum omap_channel channel)681 static int dss_dpi_select_source_omap5(int port, enum omap_channel channel)
682 {
683 int val;
684
685 switch (channel) {
686 case OMAP_DSS_CHANNEL_LCD:
687 val = 1;
688 break;
689 case OMAP_DSS_CHANNEL_LCD2:
690 val = 2;
691 break;
692 case OMAP_DSS_CHANNEL_LCD3:
693 val = 3;
694 break;
695 case OMAP_DSS_CHANNEL_DIGIT:
696 val = 0;
697 break;
698 default:
699 return -EINVAL;
700 }
701
702 REG_FLD_MOD(DSS_CONTROL, val, 17, 16);
703
704 return 0;
705 }
706
dss_dpi_select_source_dra7xx(int port,enum omap_channel channel)707 static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel)
708 {
709 switch (port) {
710 case 0:
711 return dss_dpi_select_source_omap5(port, channel);
712 case 1:
713 if (channel != OMAP_DSS_CHANNEL_LCD2)
714 return -EINVAL;
715 break;
716 case 2:
717 if (channel != OMAP_DSS_CHANNEL_LCD3)
718 return -EINVAL;
719 break;
720 default:
721 return -EINVAL;
722 }
723
724 return 0;
725 }
726
dss_dpi_select_source(int port,enum omap_channel channel)727 int dss_dpi_select_source(int port, enum omap_channel channel)
728 {
729 return dss.feat->dpi_select_source(port, channel);
730 }
731
dss_get_clocks(void)732 static int dss_get_clocks(void)
733 {
734 struct clk *clk;
735
736 clk = devm_clk_get(&dss.pdev->dev, "fck");
737 if (IS_ERR(clk)) {
738 DSSERR("can't get clock fck\n");
739 return PTR_ERR(clk);
740 }
741
742 dss.dss_clk = clk;
743
744 if (dss.feat->parent_clk_name) {
745 clk = clk_get(NULL, dss.feat->parent_clk_name);
746 if (IS_ERR(clk)) {
747 DSSERR("Failed to get %s\n", dss.feat->parent_clk_name);
748 return PTR_ERR(clk);
749 }
750 } else {
751 clk = NULL;
752 }
753
754 dss.parent_clk = clk;
755
756 return 0;
757 }
758
dss_put_clocks(void)759 static void dss_put_clocks(void)
760 {
761 if (dss.parent_clk)
762 clk_put(dss.parent_clk);
763 }
764
dss_runtime_get(void)765 int dss_runtime_get(void)
766 {
767 int r;
768
769 DSSDBG("dss_runtime_get\n");
770
771 r = pm_runtime_get_sync(&dss.pdev->dev);
772 WARN_ON(r < 0);
773 return r < 0 ? r : 0;
774 }
775
dss_runtime_put(void)776 void dss_runtime_put(void)
777 {
778 int r;
779
780 DSSDBG("dss_runtime_put\n");
781
782 r = pm_runtime_put_sync(&dss.pdev->dev);
783 WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
784 }
785
786 /* DEBUGFS */
787 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
dss_debug_dump_clocks(struct seq_file * s)788 void dss_debug_dump_clocks(struct seq_file *s)
789 {
790 dss_dump_clocks(s);
791 dispc_dump_clocks(s);
792 #ifdef CONFIG_OMAP2_DSS_DSI
793 dsi_dump_clocks(s);
794 #endif
795 }
796 #endif
797
798
799 static const enum omap_display_type omap2plus_ports[] = {
800 OMAP_DISPLAY_TYPE_DPI,
801 };
802
803 static const enum omap_display_type omap34xx_ports[] = {
804 OMAP_DISPLAY_TYPE_DPI,
805 OMAP_DISPLAY_TYPE_SDI,
806 };
807
808 static const enum omap_display_type dra7xx_ports[] = {
809 OMAP_DISPLAY_TYPE_DPI,
810 OMAP_DISPLAY_TYPE_DPI,
811 OMAP_DISPLAY_TYPE_DPI,
812 };
813
814 static const struct dss_features omap24xx_dss_feats __initconst = {
815 /*
816 * fck div max is really 16, but the divider range has gaps. The range
817 * from 1 to 6 has no gaps, so let's use that as a max.
818 */
819 .fck_div_max = 6,
820 .dss_fck_multiplier = 2,
821 .parent_clk_name = "core_ck",
822 .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
823 .ports = omap2plus_ports,
824 .num_ports = ARRAY_SIZE(omap2plus_ports),
825 };
826
827 static const struct dss_features omap34xx_dss_feats __initconst = {
828 .fck_div_max = 16,
829 .dss_fck_multiplier = 2,
830 .parent_clk_name = "dpll4_ck",
831 .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
832 .ports = omap34xx_ports,
833 .num_ports = ARRAY_SIZE(omap34xx_ports),
834 };
835
836 static const struct dss_features omap3630_dss_feats __initconst = {
837 .fck_div_max = 32,
838 .dss_fck_multiplier = 1,
839 .parent_clk_name = "dpll4_ck",
840 .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
841 .ports = omap2plus_ports,
842 .num_ports = ARRAY_SIZE(omap2plus_ports),
843 };
844
845 static const struct dss_features omap44xx_dss_feats __initconst = {
846 .fck_div_max = 32,
847 .dss_fck_multiplier = 1,
848 .parent_clk_name = "dpll_per_x2_ck",
849 .dpi_select_source = &dss_dpi_select_source_omap4,
850 .ports = omap2plus_ports,
851 .num_ports = ARRAY_SIZE(omap2plus_ports),
852 };
853
854 static const struct dss_features omap54xx_dss_feats __initconst = {
855 .fck_div_max = 64,
856 .dss_fck_multiplier = 1,
857 .parent_clk_name = "dpll_per_x2_ck",
858 .dpi_select_source = &dss_dpi_select_source_omap5,
859 .ports = omap2plus_ports,
860 .num_ports = ARRAY_SIZE(omap2plus_ports),
861 };
862
863 static const struct dss_features am43xx_dss_feats __initconst = {
864 .fck_div_max = 0,
865 .dss_fck_multiplier = 0,
866 .parent_clk_name = NULL,
867 .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
868 .ports = omap2plus_ports,
869 .num_ports = ARRAY_SIZE(omap2plus_ports),
870 };
871
872 static const struct dss_features dra7xx_dss_feats __initconst = {
873 .fck_div_max = 64,
874 .dss_fck_multiplier = 1,
875 .parent_clk_name = "dpll_per_x2_ck",
876 .dpi_select_source = &dss_dpi_select_source_dra7xx,
877 .ports = dra7xx_ports,
878 .num_ports = ARRAY_SIZE(dra7xx_ports),
879 };
880
dss_init_features(struct platform_device * pdev)881 static int __init dss_init_features(struct platform_device *pdev)
882 {
883 const struct dss_features *src;
884 struct dss_features *dst;
885
886 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
887 if (!dst) {
888 dev_err(&pdev->dev, "Failed to allocate local DSS Features\n");
889 return -ENOMEM;
890 }
891
892 switch (omapdss_get_version()) {
893 case OMAPDSS_VER_OMAP24xx:
894 src = &omap24xx_dss_feats;
895 break;
896
897 case OMAPDSS_VER_OMAP34xx_ES1:
898 case OMAPDSS_VER_OMAP34xx_ES3:
899 case OMAPDSS_VER_AM35xx:
900 src = &omap34xx_dss_feats;
901 break;
902
903 case OMAPDSS_VER_OMAP3630:
904 src = &omap3630_dss_feats;
905 break;
906
907 case OMAPDSS_VER_OMAP4430_ES1:
908 case OMAPDSS_VER_OMAP4430_ES2:
909 case OMAPDSS_VER_OMAP4:
910 src = &omap44xx_dss_feats;
911 break;
912
913 case OMAPDSS_VER_OMAP5:
914 src = &omap54xx_dss_feats;
915 break;
916
917 case OMAPDSS_VER_AM43xx:
918 src = &am43xx_dss_feats;
919 break;
920
921 case OMAPDSS_VER_DRA7xx:
922 src = &dra7xx_dss_feats;
923 break;
924
925 default:
926 return -ENODEV;
927 }
928
929 memcpy(dst, src, sizeof(*dst));
930 dss.feat = dst;
931
932 return 0;
933 }
934
dss_init_ports(struct platform_device * pdev)935 static int __init dss_init_ports(struct platform_device *pdev)
936 {
937 struct device_node *parent = pdev->dev.of_node;
938 struct device_node *port;
939 int r;
940
941 if (parent == NULL)
942 return 0;
943
944 port = omapdss_of_get_next_port(parent, NULL);
945 if (!port)
946 return 0;
947
948 if (dss.feat->num_ports == 0)
949 return 0;
950
951 do {
952 enum omap_display_type port_type;
953 u32 reg;
954
955 r = of_property_read_u32(port, "reg", ®);
956 if (r)
957 reg = 0;
958
959 if (reg >= dss.feat->num_ports)
960 continue;
961
962 port_type = dss.feat->ports[reg];
963
964 switch (port_type) {
965 case OMAP_DISPLAY_TYPE_DPI:
966 dpi_init_port(pdev, port);
967 break;
968 case OMAP_DISPLAY_TYPE_SDI:
969 sdi_init_port(pdev, port);
970 break;
971 default:
972 break;
973 }
974 } while ((port = omapdss_of_get_next_port(parent, port)) != NULL);
975
976 return 0;
977 }
978
dss_uninit_ports(struct platform_device * pdev)979 static void __exit dss_uninit_ports(struct platform_device *pdev)
980 {
981 struct device_node *parent = pdev->dev.of_node;
982 struct device_node *port;
983
984 if (parent == NULL)
985 return;
986
987 port = omapdss_of_get_next_port(parent, NULL);
988 if (!port)
989 return;
990
991 if (dss.feat->num_ports == 0)
992 return;
993
994 do {
995 enum omap_display_type port_type;
996 u32 reg;
997 int r;
998
999 r = of_property_read_u32(port, "reg", ®);
1000 if (r)
1001 reg = 0;
1002
1003 if (reg >= dss.feat->num_ports)
1004 continue;
1005
1006 port_type = dss.feat->ports[reg];
1007
1008 switch (port_type) {
1009 case OMAP_DISPLAY_TYPE_DPI:
1010 dpi_uninit_port(port);
1011 break;
1012 case OMAP_DISPLAY_TYPE_SDI:
1013 sdi_uninit_port(port);
1014 break;
1015 default:
1016 break;
1017 }
1018 } while ((port = omapdss_of_get_next_port(parent, port)) != NULL);
1019 }
1020
1021 /* DSS HW IP initialisation */
omap_dsshw_probe(struct platform_device * pdev)1022 static int __init omap_dsshw_probe(struct platform_device *pdev)
1023 {
1024 struct resource *dss_mem;
1025 struct device_node *np = pdev->dev.of_node;
1026 u32 rev;
1027 int r;
1028 struct regulator *pll_regulator;
1029
1030 dss.pdev = pdev;
1031
1032 r = dss_init_features(dss.pdev);
1033 if (r)
1034 return r;
1035
1036 dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
1037 if (!dss_mem) {
1038 DSSERR("can't get IORESOURCE_MEM DSS\n");
1039 return -EINVAL;
1040 }
1041
1042 dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
1043 resource_size(dss_mem));
1044 if (!dss.base) {
1045 DSSERR("can't ioremap DSS\n");
1046 return -ENOMEM;
1047 }
1048
1049 r = dss_get_clocks();
1050 if (r)
1051 return r;
1052
1053 r = dss_setup_default_clock();
1054 if (r)
1055 goto err_setup_clocks;
1056
1057 pm_runtime_enable(&pdev->dev);
1058
1059 r = dss_runtime_get();
1060 if (r)
1061 goto err_runtime_get;
1062
1063 dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
1064
1065 /* Select DPLL */
1066 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
1067
1068 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
1069
1070 #ifdef CONFIG_OMAP2_DSS_VENC
1071 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
1072 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
1073 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
1074 #endif
1075 dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
1076 dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
1077 dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
1078 dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
1079 dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
1080
1081 dss_init_ports(pdev);
1082
1083 if (np && of_property_read_bool(np, "syscon-pll-ctrl")) {
1084 dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np,
1085 "syscon-pll-ctrl");
1086 if (IS_ERR(dss.syscon_pll_ctrl)) {
1087 dev_err(&pdev->dev,
1088 "failed to get syscon-pll-ctrl regmap\n");
1089 return PTR_ERR(dss.syscon_pll_ctrl);
1090 }
1091
1092 if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1,
1093 &dss.syscon_pll_ctrl_offset)) {
1094 dev_err(&pdev->dev,
1095 "failed to get syscon-pll-ctrl offset\n");
1096 return -EINVAL;
1097 }
1098 }
1099
1100 pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video");
1101 if (IS_ERR(pll_regulator)) {
1102 r = PTR_ERR(pll_regulator);
1103
1104 switch (r) {
1105 case -ENOENT:
1106 pll_regulator = NULL;
1107 break;
1108
1109 case -EPROBE_DEFER:
1110 return -EPROBE_DEFER;
1111
1112 default:
1113 DSSERR("can't get DPLL VDDA regulator\n");
1114 return r;
1115 }
1116 }
1117
1118 if (of_property_match_string(np, "reg-names", "pll1") >= 0) {
1119 dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator);
1120 if (IS_ERR(dss.video1_pll)) {
1121 r = PTR_ERR(dss.video1_pll);
1122 goto err_pll_init;
1123 }
1124 }
1125
1126 if (of_property_match_string(np, "reg-names", "pll2") >= 0) {
1127 dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator);
1128 if (IS_ERR(dss.video2_pll)) {
1129 r = PTR_ERR(dss.video2_pll);
1130 goto err_pll_init;
1131 }
1132 }
1133
1134 rev = dss_read_reg(DSS_REVISION);
1135 printk(KERN_INFO "OMAP DSS rev %d.%d\n",
1136 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1137
1138 dss_runtime_put();
1139
1140 dss_debugfs_create_file("dss", dss_dump_regs);
1141
1142 pm_set_vt_switch(0);
1143
1144 return 0;
1145
1146 err_pll_init:
1147 if (dss.video1_pll)
1148 dss_video_pll_uninit(dss.video1_pll);
1149
1150 if (dss.video2_pll)
1151 dss_video_pll_uninit(dss.video2_pll);
1152 err_runtime_get:
1153 pm_runtime_disable(&pdev->dev);
1154 err_setup_clocks:
1155 dss_put_clocks();
1156 return r;
1157 }
1158
omap_dsshw_remove(struct platform_device * pdev)1159 static int __exit omap_dsshw_remove(struct platform_device *pdev)
1160 {
1161 if (dss.video1_pll)
1162 dss_video_pll_uninit(dss.video1_pll);
1163
1164 if (dss.video2_pll)
1165 dss_video_pll_uninit(dss.video2_pll);
1166
1167 dss_uninit_ports(pdev);
1168
1169 pm_runtime_disable(&pdev->dev);
1170
1171 dss_put_clocks();
1172
1173 return 0;
1174 }
1175
dss_runtime_suspend(struct device * dev)1176 static int dss_runtime_suspend(struct device *dev)
1177 {
1178 dss_save_context();
1179 dss_set_min_bus_tput(dev, 0);
1180 return 0;
1181 }
1182
dss_runtime_resume(struct device * dev)1183 static int dss_runtime_resume(struct device *dev)
1184 {
1185 int r;
1186 /*
1187 * Set an arbitrarily high tput request to ensure OPP100.
1188 * What we should really do is to make a request to stay in OPP100,
1189 * without any tput requirements, but that is not currently possible
1190 * via the PM layer.
1191 */
1192
1193 r = dss_set_min_bus_tput(dev, 1000000000);
1194 if (r)
1195 return r;
1196
1197 dss_restore_context();
1198 return 0;
1199 }
1200
1201 static const struct dev_pm_ops dss_pm_ops = {
1202 .runtime_suspend = dss_runtime_suspend,
1203 .runtime_resume = dss_runtime_resume,
1204 };
1205
1206 static const struct of_device_id dss_of_match[] = {
1207 { .compatible = "ti,omap2-dss", },
1208 { .compatible = "ti,omap3-dss", },
1209 { .compatible = "ti,omap4-dss", },
1210 { .compatible = "ti,omap5-dss", },
1211 { .compatible = "ti,dra7-dss", },
1212 {},
1213 };
1214
1215 MODULE_DEVICE_TABLE(of, dss_of_match);
1216
1217 static struct platform_driver omap_dsshw_driver = {
1218 .remove = __exit_p(omap_dsshw_remove),
1219 .driver = {
1220 .name = "omapdss_dss",
1221 .pm = &dss_pm_ops,
1222 .of_match_table = dss_of_match,
1223 .suppress_bind_attrs = true,
1224 },
1225 };
1226
dss_init_platform_driver(void)1227 int __init dss_init_platform_driver(void)
1228 {
1229 return platform_driver_probe(&omap_dsshw_driver, omap_dsshw_probe);
1230 }
1231
dss_uninit_platform_driver(void)1232 void dss_uninit_platform_driver(void)
1233 {
1234 platform_driver_unregister(&omap_dsshw_driver);
1235 }
1236