1 /*
2 * Copyright (c) 2009,2010 One Laptop per Child
3 *
4 * This program is free software. You can redistribute it and/or
5 * modify it under the terms of version 2 of the GNU General Public
6 * License as published by the Free Software Foundation.
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/acpi.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <asm/olpc.h>
15
16 /* TODO: this eventually belongs in linux/vx855.h */
17 #define NR_VX855_GPI 14
18 #define NR_VX855_GPO 13
19 #define NR_VX855_GPIO 15
20
21 #define VX855_GPI(n) (n)
22 #define VX855_GPO(n) (NR_VX855_GPI + (n))
23 #define VX855_GPIO(n) (NR_VX855_GPI + NR_VX855_GPO + (n))
24
25 #include "olpc_dcon.h"
26
27 /* Hardware setup on the XO 1.5:
28 * DCONLOAD connects to VX855_GPIO1 (not SMBCK2)
29 * DCONBLANK connects to VX855_GPIO8 (not SSPICLK) unused in driver
30 * DCONSTAT0 connects to VX855_GPI10 (not SSPISDI)
31 * DCONSTAT1 connects to VX855_GPI11 (not nSSPISS)
32 * DCONIRQ connects to VX855_GPIO12
33 * DCONSMBDATA connects to VX855 graphics CRTSPD
34 * DCONSMBCLK connects to VX855 graphics CRTSPCLK
35 */
36
37 #define VX855_GENL_PURPOSE_OUTPUT 0x44c /* PMIO_Rx4c-4f */
38 #define VX855_GPI_STATUS_CHG 0x450 /* PMIO_Rx50 */
39 #define VX855_GPI_SCI_SMI 0x452 /* PMIO_Rx52 */
40 #define BIT_GPIO12 0x40
41
42 #define PREFIX "OLPC DCON:"
43
dcon_clear_irq(void)44 static void dcon_clear_irq(void)
45 {
46 /* irq status will appear in PMIO_Rx50[6] (RW1C) on gpio12 */
47 outb(BIT_GPIO12, VX855_GPI_STATUS_CHG);
48 }
49
dcon_was_irq(void)50 static int dcon_was_irq(void)
51 {
52 u_int8_t tmp;
53
54 /* irq status will appear in PMIO_Rx50[6] on gpio12 */
55 tmp = inb(VX855_GPI_STATUS_CHG);
56 return !!(tmp & BIT_GPIO12);
57
58 return 0;
59 }
60
dcon_init_xo_1_5(struct dcon_priv * dcon)61 static int dcon_init_xo_1_5(struct dcon_priv *dcon)
62 {
63 unsigned int irq;
64
65 dcon_clear_irq();
66
67 /* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
68 outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
69
70 /* Determine the current state of DCONLOAD, likely set by firmware */
71 /* GPIO1 */
72 dcon->curr_src = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x1000) ?
73 DCON_SOURCE_CPU : DCON_SOURCE_DCON;
74 dcon->pending_src = dcon->curr_src;
75
76 /* we're sharing the IRQ with ACPI */
77 irq = acpi_gbl_FADT.sci_interrupt;
78 if (request_irq(irq, &dcon_interrupt, IRQF_SHARED, "DCON", dcon)) {
79 pr_err("DCON (IRQ%d) allocation failed\n", irq);
80 return 1;
81 }
82
83 return 0;
84 }
85
set_i2c_line(int sda,int scl)86 static void set_i2c_line(int sda, int scl)
87 {
88 unsigned char tmp;
89 unsigned int port = 0x26;
90
91 /* FIXME: This directly accesses the CRT GPIO controller !!! */
92 outb(port, 0x3c4);
93 tmp = inb(0x3c5);
94
95 if (scl)
96 tmp |= 0x20;
97 else
98 tmp &= ~0x20;
99
100 if (sda)
101 tmp |= 0x10;
102 else
103 tmp &= ~0x10;
104
105 tmp |= 0x01;
106
107 outb(port, 0x3c4);
108 outb(tmp, 0x3c5);
109 }
110
111
dcon_wiggle_xo_1_5(void)112 static void dcon_wiggle_xo_1_5(void)
113 {
114 int x;
115
116 /*
117 * According to HiMax, when powering the DCON up we should hold
118 * SMB_DATA high for 8 SMB_CLK cycles. This will force the DCON
119 * state machine to reset to a (sane) initial state. Mitch Bradley
120 * did some testing and discovered that holding for 16 SMB_CLK cycles
121 * worked a lot more reliably, so that's what we do here.
122 */
123 set_i2c_line(1, 1);
124
125 for (x = 0; x < 16; x++) {
126 udelay(5);
127 set_i2c_line(1, 0);
128 udelay(5);
129 set_i2c_line(1, 1);
130 }
131 udelay(5);
132
133 /* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
134 outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
135 }
136
dcon_set_dconload_xo_1_5(int val)137 static void dcon_set_dconload_xo_1_5(int val)
138 {
139 gpio_set_value(VX855_GPIO(1), val);
140 }
141
dcon_read_status_xo_1_5(u8 * status)142 static int dcon_read_status_xo_1_5(u8 *status)
143 {
144 if (!dcon_was_irq())
145 return -1;
146
147 /* i believe this is the same as "inb(0x44b) & 3" */
148 *status = gpio_get_value(VX855_GPI(10));
149 *status |= gpio_get_value(VX855_GPI(11)) << 1;
150
151 dcon_clear_irq();
152
153 return 0;
154 }
155
156 struct dcon_platform_data dcon_pdata_xo_1_5 = {
157 .init = dcon_init_xo_1_5,
158 .bus_stabilize_wiggle = dcon_wiggle_xo_1_5,
159 .set_dconload = dcon_set_dconload_xo_1_5,
160 .read_status = dcon_read_status_xo_1_5,
161 };
162