1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 39 #if defined(__LITTLE_ENDIAN) 40 #define MLX5_SET_HOST_ENDIANNESS 0 41 #elif defined(__BIG_ENDIAN) 42 #define MLX5_SET_HOST_ENDIANNESS 0x80 43 #else 44 #error Host endianness not defined 45 #endif 46 47 /* helper macros */ 48 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 49 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 50 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld))) 51 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 52 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 53 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 54 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 55 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 56 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 57 58 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 59 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 60 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 61 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 62 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 63 64 /* insert a value to a struct */ 65 #define MLX5_SET(typ, p, fld, v) do { \ 66 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 67 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 68 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 69 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 70 << __mlx5_dw_bit_off(typ, fld))); \ 71 } while (0) 72 73 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 74 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 75 __mlx5_mask(typ, fld)) 76 77 #define MLX5_GET_PR(typ, p, fld) ({ \ 78 u32 ___t = MLX5_GET(typ, p, fld); \ 79 pr_debug(#fld " = 0x%x\n", ___t); \ 80 ___t; \ 81 }) 82 83 #define MLX5_SET64(typ, p, fld, v) do { \ 84 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 85 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 86 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 87 } while (0) 88 89 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 90 91 enum { 92 MLX5_MAX_COMMANDS = 32, 93 MLX5_CMD_DATA_BLOCK_SIZE = 512, 94 MLX5_PCI_CMD_XPORT = 7, 95 MLX5_MKEY_BSF_OCTO_SIZE = 4, 96 MLX5_MAX_PSVS = 4, 97 }; 98 99 enum { 100 MLX5_EXTENDED_UD_AV = 0x80000000, 101 }; 102 103 enum { 104 MLX5_CQ_STATE_ARMED = 9, 105 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 106 MLX5_CQ_STATE_FIRED = 0xa, 107 }; 108 109 enum { 110 MLX5_STAT_RATE_OFFSET = 5, 111 }; 112 113 enum { 114 MLX5_INLINE_SEG = 0x80000000, 115 }; 116 117 enum { 118 MLX5_MIN_PKEY_TABLE_SIZE = 128, 119 MLX5_MAX_LOG_PKEY_TABLE = 5, 120 }; 121 122 enum { 123 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 124 }; 125 126 enum { 127 MLX5_PFAULT_SUBTYPE_WQE = 0, 128 MLX5_PFAULT_SUBTYPE_RDMA = 1, 129 }; 130 131 enum { 132 MLX5_PERM_LOCAL_READ = 1 << 2, 133 MLX5_PERM_LOCAL_WRITE = 1 << 3, 134 MLX5_PERM_REMOTE_READ = 1 << 4, 135 MLX5_PERM_REMOTE_WRITE = 1 << 5, 136 MLX5_PERM_ATOMIC = 1 << 6, 137 MLX5_PERM_UMR_EN = 1 << 7, 138 }; 139 140 enum { 141 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 142 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 143 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 144 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 145 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 146 }; 147 148 enum { 149 MLX5_ACCESS_MODE_PA = 0, 150 MLX5_ACCESS_MODE_MTT = 1, 151 MLX5_ACCESS_MODE_KLM = 2 152 }; 153 154 enum { 155 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 156 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 157 MLX5_MKEY_BSF_EN = 1 << 30, 158 MLX5_MKEY_LEN64 = 1 << 31, 159 }; 160 161 enum { 162 MLX5_EN_RD = (u64)1, 163 MLX5_EN_WR = (u64)2 164 }; 165 166 enum { 167 MLX5_BF_REGS_PER_PAGE = 4, 168 MLX5_MAX_UAR_PAGES = 1 << 8, 169 MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 170 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 171 }; 172 173 enum { 174 MLX5_MKEY_MASK_LEN = 1ull << 0, 175 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 176 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 177 MLX5_MKEY_MASK_PD = 1ull << 7, 178 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 179 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 180 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 181 MLX5_MKEY_MASK_KEY = 1ull << 13, 182 MLX5_MKEY_MASK_QPN = 1ull << 14, 183 MLX5_MKEY_MASK_LR = 1ull << 17, 184 MLX5_MKEY_MASK_LW = 1ull << 18, 185 MLX5_MKEY_MASK_RR = 1ull << 19, 186 MLX5_MKEY_MASK_RW = 1ull << 20, 187 MLX5_MKEY_MASK_A = 1ull << 21, 188 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 189 MLX5_MKEY_MASK_FREE = 1ull << 29, 190 }; 191 192 enum { 193 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 194 195 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 196 MLX5_UMR_CHECK_FREE = (2 << 5), 197 198 MLX5_UMR_INLINE = (1 << 7), 199 }; 200 201 #define MLX5_UMR_MTT_ALIGNMENT 0x40 202 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 203 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 204 205 enum mlx5_event { 206 MLX5_EVENT_TYPE_COMP = 0x0, 207 208 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 209 MLX5_EVENT_TYPE_COMM_EST = 0x02, 210 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 211 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 212 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 213 214 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 215 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 216 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 217 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 218 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 219 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 220 221 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 222 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 223 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 224 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 225 226 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 227 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 228 229 MLX5_EVENT_TYPE_CMD = 0x0a, 230 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 231 232 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 233 }; 234 235 enum { 236 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 237 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 238 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 239 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 240 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 241 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 242 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 243 }; 244 245 enum { 246 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 247 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 248 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 249 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 250 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 251 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 252 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, 253 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 254 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 255 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 256 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 257 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 258 }; 259 260 enum { 261 MLX5_OPCODE_NOP = 0x00, 262 MLX5_OPCODE_SEND_INVAL = 0x01, 263 MLX5_OPCODE_RDMA_WRITE = 0x08, 264 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 265 MLX5_OPCODE_SEND = 0x0a, 266 MLX5_OPCODE_SEND_IMM = 0x0b, 267 MLX5_OPCODE_RDMA_READ = 0x10, 268 MLX5_OPCODE_ATOMIC_CS = 0x11, 269 MLX5_OPCODE_ATOMIC_FA = 0x12, 270 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 271 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 272 MLX5_OPCODE_BIND_MW = 0x18, 273 MLX5_OPCODE_CONFIG_CMD = 0x1f, 274 275 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 276 MLX5_RECV_OPCODE_SEND = 0x01, 277 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 278 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 279 280 MLX5_CQE_OPCODE_ERROR = 0x1e, 281 MLX5_CQE_OPCODE_RESIZE = 0x16, 282 283 MLX5_OPCODE_SET_PSV = 0x20, 284 MLX5_OPCODE_GET_PSV = 0x21, 285 MLX5_OPCODE_CHECK_PSV = 0x22, 286 MLX5_OPCODE_RGET_PSV = 0x26, 287 MLX5_OPCODE_RCHECK_PSV = 0x27, 288 289 MLX5_OPCODE_UMR = 0x25, 290 291 }; 292 293 enum { 294 MLX5_SET_PORT_RESET_QKEY = 0, 295 MLX5_SET_PORT_GUID0 = 16, 296 MLX5_SET_PORT_NODE_GUID = 17, 297 MLX5_SET_PORT_SYS_GUID = 18, 298 MLX5_SET_PORT_GID_TABLE = 19, 299 MLX5_SET_PORT_PKEY_TABLE = 20, 300 }; 301 302 enum { 303 MLX5_MAX_PAGE_SHIFT = 31 304 }; 305 306 enum { 307 MLX5_ADAPTER_PAGE_SHIFT = 12, 308 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 309 }; 310 311 enum { 312 MLX5_CAP_OFF_CMDIF_CSUM = 46, 313 }; 314 315 enum { 316 HCA_CAP_OPMOD_GET_MAX = 0, 317 HCA_CAP_OPMOD_GET_CUR = 1, 318 HCA_CAP_OPMOD_GET_ODP_MAX = 4, 319 HCA_CAP_OPMOD_GET_ODP_CUR = 5 320 }; 321 322 struct mlx5_inbox_hdr { 323 __be16 opcode; 324 u8 rsvd[4]; 325 __be16 opmod; 326 }; 327 328 struct mlx5_outbox_hdr { 329 u8 status; 330 u8 rsvd[3]; 331 __be32 syndrome; 332 }; 333 334 struct mlx5_cmd_query_adapter_mbox_in { 335 struct mlx5_inbox_hdr hdr; 336 u8 rsvd[8]; 337 }; 338 339 struct mlx5_cmd_query_adapter_mbox_out { 340 struct mlx5_outbox_hdr hdr; 341 u8 rsvd0[24]; 342 u8 intapin; 343 u8 rsvd1[13]; 344 __be16 vsd_vendor_id; 345 u8 vsd[208]; 346 u8 vsd_psid[16]; 347 }; 348 349 enum mlx5_odp_transport_cap_bits { 350 MLX5_ODP_SUPPORT_SEND = 1 << 31, 351 MLX5_ODP_SUPPORT_RECV = 1 << 30, 352 MLX5_ODP_SUPPORT_WRITE = 1 << 29, 353 MLX5_ODP_SUPPORT_READ = 1 << 28, 354 }; 355 356 struct mlx5_odp_caps { 357 char reserved[0x10]; 358 struct { 359 __be32 rc_odp_caps; 360 __be32 uc_odp_caps; 361 __be32 ud_odp_caps; 362 } per_transport_caps; 363 char reserved2[0xe4]; 364 }; 365 366 struct mlx5_cmd_init_hca_mbox_in { 367 struct mlx5_inbox_hdr hdr; 368 u8 rsvd0[2]; 369 __be16 profile; 370 u8 rsvd1[4]; 371 }; 372 373 struct mlx5_cmd_init_hca_mbox_out { 374 struct mlx5_outbox_hdr hdr; 375 u8 rsvd[8]; 376 }; 377 378 struct mlx5_cmd_teardown_hca_mbox_in { 379 struct mlx5_inbox_hdr hdr; 380 u8 rsvd0[2]; 381 __be16 profile; 382 u8 rsvd1[4]; 383 }; 384 385 struct mlx5_cmd_teardown_hca_mbox_out { 386 struct mlx5_outbox_hdr hdr; 387 u8 rsvd[8]; 388 }; 389 390 struct mlx5_cmd_layout { 391 u8 type; 392 u8 rsvd0[3]; 393 __be32 inlen; 394 __be64 in_ptr; 395 __be32 in[4]; 396 __be32 out[4]; 397 __be64 out_ptr; 398 __be32 outlen; 399 u8 token; 400 u8 sig; 401 u8 rsvd1; 402 u8 status_own; 403 }; 404 405 406 struct health_buffer { 407 __be32 assert_var[5]; 408 __be32 rsvd0[3]; 409 __be32 assert_exit_ptr; 410 __be32 assert_callra; 411 __be32 rsvd1[2]; 412 __be32 fw_ver; 413 __be32 hw_id; 414 __be32 rsvd2; 415 u8 irisc_index; 416 u8 synd; 417 __be16 ext_sync; 418 }; 419 420 struct mlx5_init_seg { 421 __be32 fw_rev; 422 __be32 cmdif_rev_fw_sub; 423 __be32 rsvd0[2]; 424 __be32 cmdq_addr_h; 425 __be32 cmdq_addr_l_sz; 426 __be32 cmd_dbell; 427 __be32 rsvd1[121]; 428 struct health_buffer health; 429 __be32 rsvd2[884]; 430 __be32 health_counter; 431 __be32 rsvd3[1019]; 432 __be64 ieee1588_clk; 433 __be32 ieee1588_clk_type; 434 __be32 clr_intx; 435 }; 436 437 struct mlx5_eqe_comp { 438 __be32 reserved[6]; 439 __be32 cqn; 440 }; 441 442 struct mlx5_eqe_qp_srq { 443 __be32 reserved[6]; 444 __be32 qp_srq_n; 445 }; 446 447 struct mlx5_eqe_cq_err { 448 __be32 cqn; 449 u8 reserved1[7]; 450 u8 syndrome; 451 }; 452 453 struct mlx5_eqe_port_state { 454 u8 reserved0[8]; 455 u8 port; 456 }; 457 458 struct mlx5_eqe_gpio { 459 __be32 reserved0[2]; 460 __be64 gpio_event; 461 }; 462 463 struct mlx5_eqe_congestion { 464 u8 type; 465 u8 rsvd0; 466 u8 congestion_level; 467 }; 468 469 struct mlx5_eqe_stall_vl { 470 u8 rsvd0[3]; 471 u8 port_vl; 472 }; 473 474 struct mlx5_eqe_cmd { 475 __be32 vector; 476 __be32 rsvd[6]; 477 }; 478 479 struct mlx5_eqe_page_req { 480 u8 rsvd0[2]; 481 __be16 func_id; 482 __be32 num_pages; 483 __be32 rsvd1[5]; 484 }; 485 486 struct mlx5_eqe_page_fault { 487 __be32 bytes_committed; 488 union { 489 struct { 490 u16 reserved1; 491 __be16 wqe_index; 492 u16 reserved2; 493 __be16 packet_length; 494 u8 reserved3[12]; 495 } __packed wqe; 496 struct { 497 __be32 r_key; 498 u16 reserved1; 499 __be16 packet_length; 500 __be32 rdma_op_len; 501 __be64 rdma_va; 502 } __packed rdma; 503 } __packed; 504 __be32 flags_qpn; 505 } __packed; 506 507 union ev_data { 508 __be32 raw[7]; 509 struct mlx5_eqe_cmd cmd; 510 struct mlx5_eqe_comp comp; 511 struct mlx5_eqe_qp_srq qp_srq; 512 struct mlx5_eqe_cq_err cq_err; 513 struct mlx5_eqe_port_state port; 514 struct mlx5_eqe_gpio gpio; 515 struct mlx5_eqe_congestion cong; 516 struct mlx5_eqe_stall_vl stall_vl; 517 struct mlx5_eqe_page_req req_pages; 518 struct mlx5_eqe_page_fault page_fault; 519 } __packed; 520 521 struct mlx5_eqe { 522 u8 rsvd0; 523 u8 type; 524 u8 rsvd1; 525 u8 sub_type; 526 __be32 rsvd2[7]; 527 union ev_data data; 528 __be16 rsvd3; 529 u8 signature; 530 u8 owner; 531 } __packed; 532 533 struct mlx5_cmd_prot_block { 534 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 535 u8 rsvd0[48]; 536 __be64 next; 537 __be32 block_num; 538 u8 rsvd1; 539 u8 token; 540 u8 ctrl_sig; 541 u8 sig; 542 }; 543 544 struct mlx5_err_cqe { 545 u8 rsvd0[32]; 546 __be32 srqn; 547 u8 rsvd1[18]; 548 u8 vendor_err_synd; 549 u8 syndrome; 550 __be32 s_wqe_opcode_qpn; 551 __be16 wqe_counter; 552 u8 signature; 553 u8 op_own; 554 }; 555 556 struct mlx5_cqe64 { 557 u8 rsvd0[17]; 558 u8 ml_path; 559 u8 rsvd20[4]; 560 __be16 slid; 561 __be32 flags_rqpn; 562 u8 rsvd28[4]; 563 __be32 srqn; 564 __be32 imm_inval_pkey; 565 u8 rsvd40[4]; 566 __be32 byte_cnt; 567 __be64 timestamp; 568 __be32 sop_drop_qpn; 569 __be16 wqe_counter; 570 u8 signature; 571 u8 op_own; 572 }; 573 574 struct mlx5_sig_err_cqe { 575 u8 rsvd0[16]; 576 __be32 expected_trans_sig; 577 __be32 actual_trans_sig; 578 __be32 expected_reftag; 579 __be32 actual_reftag; 580 __be16 syndrome; 581 u8 rsvd22[2]; 582 __be32 mkey; 583 __be64 err_offset; 584 u8 rsvd30[8]; 585 __be32 qpn; 586 u8 rsvd38[2]; 587 u8 signature; 588 u8 op_own; 589 }; 590 591 struct mlx5_wqe_srq_next_seg { 592 u8 rsvd0[2]; 593 __be16 next_wqe_index; 594 u8 signature; 595 u8 rsvd1[11]; 596 }; 597 598 union mlx5_ext_cqe { 599 struct ib_grh grh; 600 u8 inl[64]; 601 }; 602 603 struct mlx5_cqe128 { 604 union mlx5_ext_cqe inl_grh; 605 struct mlx5_cqe64 cqe64; 606 }; 607 608 struct mlx5_srq_ctx { 609 u8 state_log_sz; 610 u8 rsvd0[3]; 611 __be32 flags_xrcd; 612 __be32 pgoff_cqn; 613 u8 rsvd1[4]; 614 u8 log_pg_sz; 615 u8 rsvd2[7]; 616 __be32 pd; 617 __be16 lwm; 618 __be16 wqe_cnt; 619 u8 rsvd3[8]; 620 __be64 db_record; 621 }; 622 623 struct mlx5_create_srq_mbox_in { 624 struct mlx5_inbox_hdr hdr; 625 __be32 input_srqn; 626 u8 rsvd0[4]; 627 struct mlx5_srq_ctx ctx; 628 u8 rsvd1[208]; 629 __be64 pas[0]; 630 }; 631 632 struct mlx5_create_srq_mbox_out { 633 struct mlx5_outbox_hdr hdr; 634 __be32 srqn; 635 u8 rsvd[4]; 636 }; 637 638 struct mlx5_destroy_srq_mbox_in { 639 struct mlx5_inbox_hdr hdr; 640 __be32 srqn; 641 u8 rsvd[4]; 642 }; 643 644 struct mlx5_destroy_srq_mbox_out { 645 struct mlx5_outbox_hdr hdr; 646 u8 rsvd[8]; 647 }; 648 649 struct mlx5_query_srq_mbox_in { 650 struct mlx5_inbox_hdr hdr; 651 __be32 srqn; 652 u8 rsvd0[4]; 653 }; 654 655 struct mlx5_query_srq_mbox_out { 656 struct mlx5_outbox_hdr hdr; 657 u8 rsvd0[8]; 658 struct mlx5_srq_ctx ctx; 659 u8 rsvd1[32]; 660 __be64 pas[0]; 661 }; 662 663 struct mlx5_arm_srq_mbox_in { 664 struct mlx5_inbox_hdr hdr; 665 __be32 srqn; 666 __be16 rsvd; 667 __be16 lwm; 668 }; 669 670 struct mlx5_arm_srq_mbox_out { 671 struct mlx5_outbox_hdr hdr; 672 u8 rsvd[8]; 673 }; 674 675 struct mlx5_cq_context { 676 u8 status; 677 u8 cqe_sz_flags; 678 u8 st; 679 u8 rsvd3; 680 u8 rsvd4[6]; 681 __be16 page_offset; 682 __be32 log_sz_usr_page; 683 __be16 cq_period; 684 __be16 cq_max_count; 685 __be16 rsvd20; 686 __be16 c_eqn; 687 u8 log_pg_sz; 688 u8 rsvd25[7]; 689 __be32 last_notified_index; 690 __be32 solicit_producer_index; 691 __be32 consumer_counter; 692 __be32 producer_counter; 693 u8 rsvd48[8]; 694 __be64 db_record_addr; 695 }; 696 697 struct mlx5_create_cq_mbox_in { 698 struct mlx5_inbox_hdr hdr; 699 __be32 input_cqn; 700 u8 rsvdx[4]; 701 struct mlx5_cq_context ctx; 702 u8 rsvd6[192]; 703 __be64 pas[0]; 704 }; 705 706 struct mlx5_create_cq_mbox_out { 707 struct mlx5_outbox_hdr hdr; 708 __be32 cqn; 709 u8 rsvd0[4]; 710 }; 711 712 struct mlx5_destroy_cq_mbox_in { 713 struct mlx5_inbox_hdr hdr; 714 __be32 cqn; 715 u8 rsvd0[4]; 716 }; 717 718 struct mlx5_destroy_cq_mbox_out { 719 struct mlx5_outbox_hdr hdr; 720 u8 rsvd0[8]; 721 }; 722 723 struct mlx5_query_cq_mbox_in { 724 struct mlx5_inbox_hdr hdr; 725 __be32 cqn; 726 u8 rsvd0[4]; 727 }; 728 729 struct mlx5_query_cq_mbox_out { 730 struct mlx5_outbox_hdr hdr; 731 u8 rsvd0[8]; 732 struct mlx5_cq_context ctx; 733 u8 rsvd6[16]; 734 __be64 pas[0]; 735 }; 736 737 struct mlx5_modify_cq_mbox_in { 738 struct mlx5_inbox_hdr hdr; 739 __be32 cqn; 740 __be32 field_select; 741 struct mlx5_cq_context ctx; 742 u8 rsvd[192]; 743 __be64 pas[0]; 744 }; 745 746 struct mlx5_modify_cq_mbox_out { 747 struct mlx5_outbox_hdr hdr; 748 u8 rsvd[8]; 749 }; 750 751 struct mlx5_enable_hca_mbox_in { 752 struct mlx5_inbox_hdr hdr; 753 u8 rsvd[8]; 754 }; 755 756 struct mlx5_enable_hca_mbox_out { 757 struct mlx5_outbox_hdr hdr; 758 u8 rsvd[8]; 759 }; 760 761 struct mlx5_disable_hca_mbox_in { 762 struct mlx5_inbox_hdr hdr; 763 u8 rsvd[8]; 764 }; 765 766 struct mlx5_disable_hca_mbox_out { 767 struct mlx5_outbox_hdr hdr; 768 u8 rsvd[8]; 769 }; 770 771 struct mlx5_eq_context { 772 u8 status; 773 u8 ec_oi; 774 u8 st; 775 u8 rsvd2[7]; 776 __be16 page_pffset; 777 __be32 log_sz_usr_page; 778 u8 rsvd3[7]; 779 u8 intr; 780 u8 log_page_size; 781 u8 rsvd4[15]; 782 __be32 consumer_counter; 783 __be32 produser_counter; 784 u8 rsvd5[16]; 785 }; 786 787 struct mlx5_create_eq_mbox_in { 788 struct mlx5_inbox_hdr hdr; 789 u8 rsvd0[3]; 790 u8 input_eqn; 791 u8 rsvd1[4]; 792 struct mlx5_eq_context ctx; 793 u8 rsvd2[8]; 794 __be64 events_mask; 795 u8 rsvd3[176]; 796 __be64 pas[0]; 797 }; 798 799 struct mlx5_create_eq_mbox_out { 800 struct mlx5_outbox_hdr hdr; 801 u8 rsvd0[3]; 802 u8 eq_number; 803 u8 rsvd1[4]; 804 }; 805 806 struct mlx5_destroy_eq_mbox_in { 807 struct mlx5_inbox_hdr hdr; 808 u8 rsvd0[3]; 809 u8 eqn; 810 u8 rsvd1[4]; 811 }; 812 813 struct mlx5_destroy_eq_mbox_out { 814 struct mlx5_outbox_hdr hdr; 815 u8 rsvd[8]; 816 }; 817 818 struct mlx5_map_eq_mbox_in { 819 struct mlx5_inbox_hdr hdr; 820 __be64 mask; 821 u8 mu; 822 u8 rsvd0[2]; 823 u8 eqn; 824 u8 rsvd1[24]; 825 }; 826 827 struct mlx5_map_eq_mbox_out { 828 struct mlx5_outbox_hdr hdr; 829 u8 rsvd[8]; 830 }; 831 832 struct mlx5_query_eq_mbox_in { 833 struct mlx5_inbox_hdr hdr; 834 u8 rsvd0[3]; 835 u8 eqn; 836 u8 rsvd1[4]; 837 }; 838 839 struct mlx5_query_eq_mbox_out { 840 struct mlx5_outbox_hdr hdr; 841 u8 rsvd[8]; 842 struct mlx5_eq_context ctx; 843 }; 844 845 enum { 846 MLX5_MKEY_STATUS_FREE = 1 << 6, 847 }; 848 849 struct mlx5_mkey_seg { 850 /* This is a two bit field occupying bits 31-30. 851 * bit 31 is always 0, 852 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 853 */ 854 u8 status; 855 u8 pcie_control; 856 u8 flags; 857 u8 version; 858 __be32 qpn_mkey7_0; 859 u8 rsvd1[4]; 860 __be32 flags_pd; 861 __be64 start_addr; 862 __be64 len; 863 __be32 bsfs_octo_size; 864 u8 rsvd2[16]; 865 __be32 xlt_oct_size; 866 u8 rsvd3[3]; 867 u8 log2_page_size; 868 u8 rsvd4[4]; 869 }; 870 871 struct mlx5_query_special_ctxs_mbox_in { 872 struct mlx5_inbox_hdr hdr; 873 u8 rsvd[8]; 874 }; 875 876 struct mlx5_query_special_ctxs_mbox_out { 877 struct mlx5_outbox_hdr hdr; 878 __be32 dump_fill_mkey; 879 __be32 reserved_lkey; 880 }; 881 882 struct mlx5_create_mkey_mbox_in { 883 struct mlx5_inbox_hdr hdr; 884 __be32 input_mkey_index; 885 __be32 flags; 886 struct mlx5_mkey_seg seg; 887 u8 rsvd1[16]; 888 __be32 xlat_oct_act_size; 889 __be32 rsvd2; 890 u8 rsvd3[168]; 891 __be64 pas[0]; 892 }; 893 894 struct mlx5_create_mkey_mbox_out { 895 struct mlx5_outbox_hdr hdr; 896 __be32 mkey; 897 u8 rsvd[4]; 898 }; 899 900 struct mlx5_destroy_mkey_mbox_in { 901 struct mlx5_inbox_hdr hdr; 902 __be32 mkey; 903 u8 rsvd[4]; 904 }; 905 906 struct mlx5_destroy_mkey_mbox_out { 907 struct mlx5_outbox_hdr hdr; 908 u8 rsvd[8]; 909 }; 910 911 struct mlx5_query_mkey_mbox_in { 912 struct mlx5_inbox_hdr hdr; 913 __be32 mkey; 914 }; 915 916 struct mlx5_query_mkey_mbox_out { 917 struct mlx5_outbox_hdr hdr; 918 __be64 pas[0]; 919 }; 920 921 struct mlx5_modify_mkey_mbox_in { 922 struct mlx5_inbox_hdr hdr; 923 __be32 mkey; 924 __be64 pas[0]; 925 }; 926 927 struct mlx5_modify_mkey_mbox_out { 928 struct mlx5_outbox_hdr hdr; 929 u8 rsvd[8]; 930 }; 931 932 struct mlx5_dump_mkey_mbox_in { 933 struct mlx5_inbox_hdr hdr; 934 }; 935 936 struct mlx5_dump_mkey_mbox_out { 937 struct mlx5_outbox_hdr hdr; 938 __be32 mkey; 939 }; 940 941 struct mlx5_mad_ifc_mbox_in { 942 struct mlx5_inbox_hdr hdr; 943 __be16 remote_lid; 944 u8 rsvd0; 945 u8 port; 946 u8 rsvd1[4]; 947 u8 data[256]; 948 }; 949 950 struct mlx5_mad_ifc_mbox_out { 951 struct mlx5_outbox_hdr hdr; 952 u8 rsvd[8]; 953 u8 data[256]; 954 }; 955 956 struct mlx5_access_reg_mbox_in { 957 struct mlx5_inbox_hdr hdr; 958 u8 rsvd0[2]; 959 __be16 register_id; 960 __be32 arg; 961 __be32 data[0]; 962 }; 963 964 struct mlx5_access_reg_mbox_out { 965 struct mlx5_outbox_hdr hdr; 966 u8 rsvd[8]; 967 __be32 data[0]; 968 }; 969 970 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 971 972 enum { 973 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 974 }; 975 976 struct mlx5_allocate_psv_in { 977 struct mlx5_inbox_hdr hdr; 978 __be32 npsv_pd; 979 __be32 rsvd_psv0; 980 }; 981 982 struct mlx5_allocate_psv_out { 983 struct mlx5_outbox_hdr hdr; 984 u8 rsvd[8]; 985 __be32 psv_idx[4]; 986 }; 987 988 struct mlx5_destroy_psv_in { 989 struct mlx5_inbox_hdr hdr; 990 __be32 psv_number; 991 u8 rsvd[4]; 992 }; 993 994 struct mlx5_destroy_psv_out { 995 struct mlx5_outbox_hdr hdr; 996 u8 rsvd[8]; 997 }; 998 999 #endif /* MLX5_DEVICE_H */ 1000