1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34
35 #include "iw_cxgb4.h"
36
37 static int db_delay_usecs = 1;
38 module_param(db_delay_usecs, int, 0644);
39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
40
41 static int ocqp_support = 1;
42 module_param(ocqp_support, int, 0644);
43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
44
45 int db_fc_threshold = 1000;
46 module_param(db_fc_threshold, int, 0644);
47 MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
50
51 int db_coalescing_threshold;
52 module_param(db_coalescing_threshold, int, 0644);
53 MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
56
57 static int max_fr_immd = T4_MAX_FR_IMMD;
58 module_param(max_fr_immd, int, 0644);
59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
60
alloc_ird(struct c4iw_dev * dev,u32 ird)61 static int alloc_ird(struct c4iw_dev *dev, u32 ird)
62 {
63 int ret = 0;
64
65 spin_lock_irq(&dev->lock);
66 if (ird <= dev->avail_ird)
67 dev->avail_ird -= ird;
68 else
69 ret = -ENOMEM;
70 spin_unlock_irq(&dev->lock);
71
72 if (ret)
73 dev_warn(&dev->rdev.lldi.pdev->dev,
74 "device IRD resources exhausted\n");
75
76 return ret;
77 }
78
free_ird(struct c4iw_dev * dev,int ird)79 static void free_ird(struct c4iw_dev *dev, int ird)
80 {
81 spin_lock_irq(&dev->lock);
82 dev->avail_ird += ird;
83 spin_unlock_irq(&dev->lock);
84 }
85
set_state(struct c4iw_qp * qhp,enum c4iw_qp_state state)86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
87 {
88 unsigned long flag;
89 spin_lock_irqsave(&qhp->lock, flag);
90 qhp->attr.state = state;
91 spin_unlock_irqrestore(&qhp->lock, flag);
92 }
93
dealloc_oc_sq(struct c4iw_rdev * rdev,struct t4_sq * sq)94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
95 {
96 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
97 }
98
dealloc_host_sq(struct c4iw_rdev * rdev,struct t4_sq * sq)99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
100 {
101 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
102 pci_unmap_addr(sq, mapping));
103 }
104
dealloc_sq(struct c4iw_rdev * rdev,struct t4_sq * sq)105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
106 {
107 if (t4_sq_onchip(sq))
108 dealloc_oc_sq(rdev, sq);
109 else
110 dealloc_host_sq(rdev, sq);
111 }
112
alloc_oc_sq(struct c4iw_rdev * rdev,struct t4_sq * sq)113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
114 {
115 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
116 return -ENOSYS;
117 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
118 if (!sq->dma_addr)
119 return -ENOMEM;
120 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
121 rdev->lldi.vr->ocq.start;
122 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
123 rdev->lldi.vr->ocq.start);
124 sq->flags |= T4_SQ_ONCHIP;
125 return 0;
126 }
127
alloc_host_sq(struct c4iw_rdev * rdev,struct t4_sq * sq)128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
129 {
130 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
131 &(sq->dma_addr), GFP_KERNEL);
132 if (!sq->queue)
133 return -ENOMEM;
134 sq->phys_addr = virt_to_phys(sq->queue);
135 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
136 return 0;
137 }
138
alloc_sq(struct c4iw_rdev * rdev,struct t4_sq * sq,int user)139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
140 {
141 int ret = -ENOSYS;
142 if (user)
143 ret = alloc_oc_sq(rdev, sq);
144 if (ret)
145 ret = alloc_host_sq(rdev, sq);
146 return ret;
147 }
148
destroy_qp(struct c4iw_rdev * rdev,struct t4_wq * wq,struct c4iw_dev_ucontext * uctx)149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
150 struct c4iw_dev_ucontext *uctx)
151 {
152 /*
153 * uP clears EQ contexts when the connection exits rdma mode,
154 * so no need to post a RESET WR for these EQs.
155 */
156 dma_free_coherent(&(rdev->lldi.pdev->dev),
157 wq->rq.memsize, wq->rq.queue,
158 dma_unmap_addr(&wq->rq, mapping));
159 dealloc_sq(rdev, &wq->sq);
160 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
161 kfree(wq->rq.sw_rq);
162 kfree(wq->sq.sw_sq);
163 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
164 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
165 return 0;
166 }
167
168 /*
169 * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL,
170 * then this is a user mapping so compute the page-aligned physical address
171 * for mapping.
172 */
c4iw_bar2_addrs(struct c4iw_rdev * rdev,unsigned int qid,enum cxgb4_bar2_qtype qtype,unsigned int * pbar2_qid,u64 * pbar2_pa)173 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
174 enum cxgb4_bar2_qtype qtype,
175 unsigned int *pbar2_qid, u64 *pbar2_pa)
176 {
177 u64 bar2_qoffset;
178 int ret;
179
180 ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype,
181 pbar2_pa ? 1 : 0,
182 &bar2_qoffset, pbar2_qid);
183 if (ret)
184 return NULL;
185
186 if (pbar2_pa)
187 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK;
188
189 if (is_t4(rdev->lldi.adapter_type))
190 return NULL;
191
192 return rdev->bar2_kva + bar2_qoffset;
193 }
194
create_qp(struct c4iw_rdev * rdev,struct t4_wq * wq,struct t4_cq * rcq,struct t4_cq * scq,struct c4iw_dev_ucontext * uctx)195 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
196 struct t4_cq *rcq, struct t4_cq *scq,
197 struct c4iw_dev_ucontext *uctx)
198 {
199 int user = (uctx != &rdev->uctx);
200 struct fw_ri_res_wr *res_wr;
201 struct fw_ri_res *res;
202 int wr_len;
203 struct c4iw_wr_wait wr_wait;
204 struct sk_buff *skb;
205 int ret = 0;
206 int eqsize;
207
208 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
209 if (!wq->sq.qid)
210 return -ENOMEM;
211
212 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
213 if (!wq->rq.qid) {
214 ret = -ENOMEM;
215 goto free_sq_qid;
216 }
217
218 if (!user) {
219 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
220 GFP_KERNEL);
221 if (!wq->sq.sw_sq) {
222 ret = -ENOMEM;
223 goto free_rq_qid;
224 }
225
226 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
227 GFP_KERNEL);
228 if (!wq->rq.sw_rq) {
229 ret = -ENOMEM;
230 goto free_sw_sq;
231 }
232 }
233
234 /*
235 * RQT must be a power of 2 and at least 16 deep.
236 */
237 wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16));
238 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
239 if (!wq->rq.rqt_hwaddr) {
240 ret = -ENOMEM;
241 goto free_sw_rq;
242 }
243
244 ret = alloc_sq(rdev, &wq->sq, user);
245 if (ret)
246 goto free_hwaddr;
247 memset(wq->sq.queue, 0, wq->sq.memsize);
248 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
249
250 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
251 wq->rq.memsize, &(wq->rq.dma_addr),
252 GFP_KERNEL);
253 if (!wq->rq.queue) {
254 ret = -ENOMEM;
255 goto free_sq;
256 }
257 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
258 __func__, wq->sq.queue,
259 (unsigned long long)virt_to_phys(wq->sq.queue),
260 wq->rq.queue,
261 (unsigned long long)virt_to_phys(wq->rq.queue));
262 memset(wq->rq.queue, 0, wq->rq.memsize);
263 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
264
265 wq->db = rdev->lldi.db_reg;
266
267 wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid, T4_BAR2_QTYPE_EGRESS,
268 &wq->sq.bar2_qid,
269 user ? &wq->sq.bar2_pa : NULL);
270 wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid, T4_BAR2_QTYPE_EGRESS,
271 &wq->rq.bar2_qid,
272 user ? &wq->rq.bar2_pa : NULL);
273
274 /*
275 * User mode must have bar2 access.
276 */
277 if (user && (!wq->sq.bar2_pa || !wq->rq.bar2_pa)) {
278 pr_warn(MOD "%s: sqid %u or rqid %u not in BAR2 range.\n",
279 pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid);
280 goto free_dma;
281 }
282
283 wq->rdev = rdev;
284 wq->rq.msn = 1;
285
286 /* build fw_ri_res_wr */
287 wr_len = sizeof *res_wr + 2 * sizeof *res;
288
289 skb = alloc_skb(wr_len, GFP_KERNEL);
290 if (!skb) {
291 ret = -ENOMEM;
292 goto free_dma;
293 }
294 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
295
296 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
297 memset(res_wr, 0, wr_len);
298 res_wr->op_nres = cpu_to_be32(
299 FW_WR_OP_V(FW_RI_RES_WR) |
300 FW_RI_RES_WR_NRES_V(2) |
301 FW_WR_COMPL_F);
302 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
303 res_wr->cookie = (uintptr_t)&wr_wait;
304 res = res_wr->res;
305 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
306 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
307
308 /*
309 * eqsize is the number of 64B entries plus the status page size.
310 */
311 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
312 rdev->hw_queue.t4_eq_status_entries;
313
314 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
315 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
316 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
317 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
318 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) |
319 FW_RI_RES_WR_IQID_V(scq->cqid));
320 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
321 FW_RI_RES_WR_DCAEN_V(0) |
322 FW_RI_RES_WR_DCACPU_V(0) |
323 FW_RI_RES_WR_FBMIN_V(2) |
324 FW_RI_RES_WR_FBMAX_V(2) |
325 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
326 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
327 FW_RI_RES_WR_EQSIZE_V(eqsize));
328 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
329 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
330 res++;
331 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
332 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
333
334 /*
335 * eqsize is the number of 64B entries plus the status page size.
336 */
337 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
338 rdev->hw_queue.t4_eq_status_entries;
339 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
340 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
341 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
342 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
343 FW_RI_RES_WR_IQID_V(rcq->cqid));
344 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
345 FW_RI_RES_WR_DCAEN_V(0) |
346 FW_RI_RES_WR_DCACPU_V(0) |
347 FW_RI_RES_WR_FBMIN_V(2) |
348 FW_RI_RES_WR_FBMAX_V(2) |
349 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
350 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
351 FW_RI_RES_WR_EQSIZE_V(eqsize));
352 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
353 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
354
355 c4iw_init_wr_wait(&wr_wait);
356
357 ret = c4iw_ofld_send(rdev, skb);
358 if (ret)
359 goto free_dma;
360 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
361 if (ret)
362 goto free_dma;
363
364 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n",
365 __func__, wq->sq.qid, wq->rq.qid, wq->db,
366 wq->sq.bar2_va, wq->rq.bar2_va);
367
368 return 0;
369 free_dma:
370 dma_free_coherent(&(rdev->lldi.pdev->dev),
371 wq->rq.memsize, wq->rq.queue,
372 dma_unmap_addr(&wq->rq, mapping));
373 free_sq:
374 dealloc_sq(rdev, &wq->sq);
375 free_hwaddr:
376 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
377 free_sw_rq:
378 kfree(wq->rq.sw_rq);
379 free_sw_sq:
380 kfree(wq->sq.sw_sq);
381 free_rq_qid:
382 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
383 free_sq_qid:
384 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
385 return ret;
386 }
387
build_immd(struct t4_sq * sq,struct fw_ri_immd * immdp,struct ib_send_wr * wr,int max,u32 * plenp)388 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
389 struct ib_send_wr *wr, int max, u32 *plenp)
390 {
391 u8 *dstp, *srcp;
392 u32 plen = 0;
393 int i;
394 int rem, len;
395
396 dstp = (u8 *)immdp->data;
397 for (i = 0; i < wr->num_sge; i++) {
398 if ((plen + wr->sg_list[i].length) > max)
399 return -EMSGSIZE;
400 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
401 plen += wr->sg_list[i].length;
402 rem = wr->sg_list[i].length;
403 while (rem) {
404 if (dstp == (u8 *)&sq->queue[sq->size])
405 dstp = (u8 *)sq->queue;
406 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
407 len = rem;
408 else
409 len = (u8 *)&sq->queue[sq->size] - dstp;
410 memcpy(dstp, srcp, len);
411 dstp += len;
412 srcp += len;
413 rem -= len;
414 }
415 }
416 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
417 if (len)
418 memset(dstp, 0, len);
419 immdp->op = FW_RI_DATA_IMMD;
420 immdp->r1 = 0;
421 immdp->r2 = 0;
422 immdp->immdlen = cpu_to_be32(plen);
423 *plenp = plen;
424 return 0;
425 }
426
build_isgl(__be64 * queue_start,__be64 * queue_end,struct fw_ri_isgl * isglp,struct ib_sge * sg_list,int num_sge,u32 * plenp)427 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
428 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
429 int num_sge, u32 *plenp)
430
431 {
432 int i;
433 u32 plen = 0;
434 __be64 *flitp = (__be64 *)isglp->sge;
435
436 for (i = 0; i < num_sge; i++) {
437 if ((plen + sg_list[i].length) < plen)
438 return -EMSGSIZE;
439 plen += sg_list[i].length;
440 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
441 sg_list[i].length);
442 if (++flitp == queue_end)
443 flitp = queue_start;
444 *flitp = cpu_to_be64(sg_list[i].addr);
445 if (++flitp == queue_end)
446 flitp = queue_start;
447 }
448 *flitp = (__force __be64)0;
449 isglp->op = FW_RI_DATA_ISGL;
450 isglp->r1 = 0;
451 isglp->nsge = cpu_to_be16(num_sge);
452 isglp->r2 = 0;
453 if (plenp)
454 *plenp = plen;
455 return 0;
456 }
457
build_rdma_send(struct t4_sq * sq,union t4_wr * wqe,struct ib_send_wr * wr,u8 * len16)458 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
459 struct ib_send_wr *wr, u8 *len16)
460 {
461 u32 plen;
462 int size;
463 int ret;
464
465 if (wr->num_sge > T4_MAX_SEND_SGE)
466 return -EINVAL;
467 switch (wr->opcode) {
468 case IB_WR_SEND:
469 if (wr->send_flags & IB_SEND_SOLICITED)
470 wqe->send.sendop_pkd = cpu_to_be32(
471 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE));
472 else
473 wqe->send.sendop_pkd = cpu_to_be32(
474 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND));
475 wqe->send.stag_inv = 0;
476 break;
477 case IB_WR_SEND_WITH_INV:
478 if (wr->send_flags & IB_SEND_SOLICITED)
479 wqe->send.sendop_pkd = cpu_to_be32(
480 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV));
481 else
482 wqe->send.sendop_pkd = cpu_to_be32(
483 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV));
484 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
485 break;
486
487 default:
488 return -EINVAL;
489 }
490 wqe->send.r3 = 0;
491 wqe->send.r4 = 0;
492
493 plen = 0;
494 if (wr->num_sge) {
495 if (wr->send_flags & IB_SEND_INLINE) {
496 ret = build_immd(sq, wqe->send.u.immd_src, wr,
497 T4_MAX_SEND_INLINE, &plen);
498 if (ret)
499 return ret;
500 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
501 plen;
502 } else {
503 ret = build_isgl((__be64 *)sq->queue,
504 (__be64 *)&sq->queue[sq->size],
505 wqe->send.u.isgl_src,
506 wr->sg_list, wr->num_sge, &plen);
507 if (ret)
508 return ret;
509 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
510 wr->num_sge * sizeof(struct fw_ri_sge);
511 }
512 } else {
513 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
514 wqe->send.u.immd_src[0].r1 = 0;
515 wqe->send.u.immd_src[0].r2 = 0;
516 wqe->send.u.immd_src[0].immdlen = 0;
517 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
518 plen = 0;
519 }
520 *len16 = DIV_ROUND_UP(size, 16);
521 wqe->send.plen = cpu_to_be32(plen);
522 return 0;
523 }
524
build_rdma_write(struct t4_sq * sq,union t4_wr * wqe,struct ib_send_wr * wr,u8 * len16)525 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
526 struct ib_send_wr *wr, u8 *len16)
527 {
528 u32 plen;
529 int size;
530 int ret;
531
532 if (wr->num_sge > T4_MAX_SEND_SGE)
533 return -EINVAL;
534 wqe->write.r2 = 0;
535 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
536 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
537 if (wr->num_sge) {
538 if (wr->send_flags & IB_SEND_INLINE) {
539 ret = build_immd(sq, wqe->write.u.immd_src, wr,
540 T4_MAX_WRITE_INLINE, &plen);
541 if (ret)
542 return ret;
543 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
544 plen;
545 } else {
546 ret = build_isgl((__be64 *)sq->queue,
547 (__be64 *)&sq->queue[sq->size],
548 wqe->write.u.isgl_src,
549 wr->sg_list, wr->num_sge, &plen);
550 if (ret)
551 return ret;
552 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
553 wr->num_sge * sizeof(struct fw_ri_sge);
554 }
555 } else {
556 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
557 wqe->write.u.immd_src[0].r1 = 0;
558 wqe->write.u.immd_src[0].r2 = 0;
559 wqe->write.u.immd_src[0].immdlen = 0;
560 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
561 plen = 0;
562 }
563 *len16 = DIV_ROUND_UP(size, 16);
564 wqe->write.plen = cpu_to_be32(plen);
565 return 0;
566 }
567
build_rdma_read(union t4_wr * wqe,struct ib_send_wr * wr,u8 * len16)568 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
569 {
570 if (wr->num_sge > 1)
571 return -EINVAL;
572 if (wr->num_sge) {
573 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey);
574 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr
575 >> 32));
576 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr);
577 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
578 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
579 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
580 >> 32));
581 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
582 } else {
583 wqe->read.stag_src = cpu_to_be32(2);
584 wqe->read.to_src_hi = 0;
585 wqe->read.to_src_lo = 0;
586 wqe->read.stag_sink = cpu_to_be32(2);
587 wqe->read.plen = 0;
588 wqe->read.to_sink_hi = 0;
589 wqe->read.to_sink_lo = 0;
590 }
591 wqe->read.r2 = 0;
592 wqe->read.r5 = 0;
593 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
594 return 0;
595 }
596
build_rdma_recv(struct c4iw_qp * qhp,union t4_recv_wr * wqe,struct ib_recv_wr * wr,u8 * len16)597 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
598 struct ib_recv_wr *wr, u8 *len16)
599 {
600 int ret;
601
602 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
603 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
604 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
605 if (ret)
606 return ret;
607 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
608 wr->num_sge * sizeof(struct fw_ri_sge), 16);
609 return 0;
610 }
611
build_memreg(struct t4_sq * sq,union t4_wr * wqe,struct ib_reg_wr * wr,u8 * len16,u8 t5dev)612 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
613 struct ib_reg_wr *wr, u8 *len16, u8 t5dev)
614 {
615 struct c4iw_mr *mhp = to_c4iw_mr(wr->mr);
616 struct fw_ri_immd *imdp;
617 __be64 *p;
618 int i;
619 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
620 int rem;
621
622 if (mhp->mpl_len > t4_max_fr_depth(use_dsgl))
623 return -EINVAL;
624
625 wqe->fr.qpbinde_to_dcacpu = 0;
626 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12;
627 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
628 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access);
629 wqe->fr.len_hi = 0;
630 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length);
631 wqe->fr.stag = cpu_to_be32(wr->key);
632 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
633 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova &
634 0xffffffff);
635
636 if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
637 struct fw_ri_dsgl *sglp;
638
639 for (i = 0; i < mhp->mpl_len; i++)
640 mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]);
641
642 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
643 sglp->op = FW_RI_DATA_DSGL;
644 sglp->r1 = 0;
645 sglp->nsge = cpu_to_be16(1);
646 sglp->addr0 = cpu_to_be64(mhp->mpl_addr);
647 sglp->len0 = cpu_to_be32(pbllen);
648
649 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
650 } else {
651 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
652 imdp->op = FW_RI_DATA_IMMD;
653 imdp->r1 = 0;
654 imdp->r2 = 0;
655 imdp->immdlen = cpu_to_be32(pbllen);
656 p = (__be64 *)(imdp + 1);
657 rem = pbllen;
658 for (i = 0; i < mhp->mpl_len; i++) {
659 *p = cpu_to_be64((u64)mhp->mpl[i]);
660 rem -= sizeof(*p);
661 if (++p == (__be64 *)&sq->queue[sq->size])
662 p = (__be64 *)sq->queue;
663 }
664 BUG_ON(rem < 0);
665 while (rem) {
666 *p = 0;
667 rem -= sizeof(*p);
668 if (++p == (__be64 *)&sq->queue[sq->size])
669 p = (__be64 *)sq->queue;
670 }
671 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
672 + pbllen, 16);
673 }
674 return 0;
675 }
676
build_inv_stag(union t4_wr * wqe,struct ib_send_wr * wr,u8 * len16)677 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
678 u8 *len16)
679 {
680 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
681 wqe->inv.r2 = 0;
682 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
683 return 0;
684 }
685
c4iw_qp_add_ref(struct ib_qp * qp)686 void c4iw_qp_add_ref(struct ib_qp *qp)
687 {
688 PDBG("%s ib_qp %p\n", __func__, qp);
689 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
690 }
691
c4iw_qp_rem_ref(struct ib_qp * qp)692 void c4iw_qp_rem_ref(struct ib_qp *qp)
693 {
694 PDBG("%s ib_qp %p\n", __func__, qp);
695 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
696 wake_up(&(to_c4iw_qp(qp)->wait));
697 }
698
add_to_fc_list(struct list_head * head,struct list_head * entry)699 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
700 {
701 if (list_empty(entry))
702 list_add_tail(entry, head);
703 }
704
ring_kernel_sq_db(struct c4iw_qp * qhp,u16 inc)705 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
706 {
707 unsigned long flags;
708
709 spin_lock_irqsave(&qhp->rhp->lock, flags);
710 spin_lock(&qhp->lock);
711 if (qhp->rhp->db_state == NORMAL)
712 t4_ring_sq_db(&qhp->wq, inc, NULL);
713 else {
714 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
715 qhp->wq.sq.wq_pidx_inc += inc;
716 }
717 spin_unlock(&qhp->lock);
718 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
719 return 0;
720 }
721
ring_kernel_rq_db(struct c4iw_qp * qhp,u16 inc)722 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
723 {
724 unsigned long flags;
725
726 spin_lock_irqsave(&qhp->rhp->lock, flags);
727 spin_lock(&qhp->lock);
728 if (qhp->rhp->db_state == NORMAL)
729 t4_ring_rq_db(&qhp->wq, inc, NULL);
730 else {
731 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
732 qhp->wq.rq.wq_pidx_inc += inc;
733 }
734 spin_unlock(&qhp->lock);
735 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
736 return 0;
737 }
738
c4iw_post_send(struct ib_qp * ibqp,struct ib_send_wr * wr,struct ib_send_wr ** bad_wr)739 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
740 struct ib_send_wr **bad_wr)
741 {
742 int err = 0;
743 u8 len16 = 0;
744 enum fw_wr_opcodes fw_opcode = 0;
745 enum fw_ri_wr_flags fw_flags;
746 struct c4iw_qp *qhp;
747 union t4_wr *wqe = NULL;
748 u32 num_wrs;
749 struct t4_swsqe *swsqe;
750 unsigned long flag;
751 u16 idx = 0;
752
753 qhp = to_c4iw_qp(ibqp);
754 spin_lock_irqsave(&qhp->lock, flag);
755 if (t4_wq_in_error(&qhp->wq)) {
756 spin_unlock_irqrestore(&qhp->lock, flag);
757 return -EINVAL;
758 }
759 num_wrs = t4_sq_avail(&qhp->wq);
760 if (num_wrs == 0) {
761 spin_unlock_irqrestore(&qhp->lock, flag);
762 return -ENOMEM;
763 }
764 while (wr) {
765 if (num_wrs == 0) {
766 err = -ENOMEM;
767 *bad_wr = wr;
768 break;
769 }
770 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
771 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
772
773 fw_flags = 0;
774 if (wr->send_flags & IB_SEND_SOLICITED)
775 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
776 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
777 fw_flags |= FW_RI_COMPLETION_FLAG;
778 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
779 switch (wr->opcode) {
780 case IB_WR_SEND_WITH_INV:
781 case IB_WR_SEND:
782 if (wr->send_flags & IB_SEND_FENCE)
783 fw_flags |= FW_RI_READ_FENCE_FLAG;
784 fw_opcode = FW_RI_SEND_WR;
785 if (wr->opcode == IB_WR_SEND)
786 swsqe->opcode = FW_RI_SEND;
787 else
788 swsqe->opcode = FW_RI_SEND_WITH_INV;
789 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
790 break;
791 case IB_WR_RDMA_WRITE:
792 fw_opcode = FW_RI_RDMA_WRITE_WR;
793 swsqe->opcode = FW_RI_RDMA_WRITE;
794 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
795 break;
796 case IB_WR_RDMA_READ:
797 case IB_WR_RDMA_READ_WITH_INV:
798 fw_opcode = FW_RI_RDMA_READ_WR;
799 swsqe->opcode = FW_RI_READ_REQ;
800 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
801 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
802 else
803 fw_flags = 0;
804 err = build_rdma_read(wqe, wr, &len16);
805 if (err)
806 break;
807 swsqe->read_len = wr->sg_list[0].length;
808 if (!qhp->wq.sq.oldest_read)
809 qhp->wq.sq.oldest_read = swsqe;
810 break;
811 case IB_WR_REG_MR:
812 fw_opcode = FW_RI_FR_NSMR_WR;
813 swsqe->opcode = FW_RI_FAST_REGISTER;
814 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr), &len16,
815 is_t5(
816 qhp->rhp->rdev.lldi.adapter_type) ?
817 1 : 0);
818 break;
819 case IB_WR_LOCAL_INV:
820 if (wr->send_flags & IB_SEND_FENCE)
821 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
822 fw_opcode = FW_RI_INV_LSTAG_WR;
823 swsqe->opcode = FW_RI_LOCAL_INV;
824 err = build_inv_stag(wqe, wr, &len16);
825 break;
826 default:
827 PDBG("%s post of type=%d TBD!\n", __func__,
828 wr->opcode);
829 err = -EINVAL;
830 }
831 if (err) {
832 *bad_wr = wr;
833 break;
834 }
835 swsqe->idx = qhp->wq.sq.pidx;
836 swsqe->complete = 0;
837 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
838 qhp->sq_sig_all;
839 swsqe->flushed = 0;
840 swsqe->wr_id = wr->wr_id;
841 if (c4iw_wr_log) {
842 swsqe->sge_ts = cxgb4_read_sge_timestamp(
843 qhp->rhp->rdev.lldi.ports[0]);
844 getnstimeofday(&swsqe->host_ts);
845 }
846
847 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
848
849 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
850 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
851 swsqe->opcode, swsqe->read_len);
852 wr = wr->next;
853 num_wrs--;
854 t4_sq_produce(&qhp->wq, len16);
855 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
856 }
857 if (!qhp->rhp->rdev.status_page->db_off) {
858 t4_ring_sq_db(&qhp->wq, idx, wqe);
859 spin_unlock_irqrestore(&qhp->lock, flag);
860 } else {
861 spin_unlock_irqrestore(&qhp->lock, flag);
862 ring_kernel_sq_db(qhp, idx);
863 }
864 return err;
865 }
866
c4iw_post_receive(struct ib_qp * ibqp,struct ib_recv_wr * wr,struct ib_recv_wr ** bad_wr)867 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
868 struct ib_recv_wr **bad_wr)
869 {
870 int err = 0;
871 struct c4iw_qp *qhp;
872 union t4_recv_wr *wqe = NULL;
873 u32 num_wrs;
874 u8 len16 = 0;
875 unsigned long flag;
876 u16 idx = 0;
877
878 qhp = to_c4iw_qp(ibqp);
879 spin_lock_irqsave(&qhp->lock, flag);
880 if (t4_wq_in_error(&qhp->wq)) {
881 spin_unlock_irqrestore(&qhp->lock, flag);
882 return -EINVAL;
883 }
884 num_wrs = t4_rq_avail(&qhp->wq);
885 if (num_wrs == 0) {
886 spin_unlock_irqrestore(&qhp->lock, flag);
887 return -ENOMEM;
888 }
889 while (wr) {
890 if (wr->num_sge > T4_MAX_RECV_SGE) {
891 err = -EINVAL;
892 *bad_wr = wr;
893 break;
894 }
895 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
896 qhp->wq.rq.wq_pidx *
897 T4_EQ_ENTRY_SIZE);
898 if (num_wrs)
899 err = build_rdma_recv(qhp, wqe, wr, &len16);
900 else
901 err = -ENOMEM;
902 if (err) {
903 *bad_wr = wr;
904 break;
905 }
906
907 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
908 if (c4iw_wr_log) {
909 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts =
910 cxgb4_read_sge_timestamp(
911 qhp->rhp->rdev.lldi.ports[0]);
912 getnstimeofday(
913 &qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_ts);
914 }
915
916 wqe->recv.opcode = FW_RI_RECV_WR;
917 wqe->recv.r1 = 0;
918 wqe->recv.wrid = qhp->wq.rq.pidx;
919 wqe->recv.r2[0] = 0;
920 wqe->recv.r2[1] = 0;
921 wqe->recv.r2[2] = 0;
922 wqe->recv.len16 = len16;
923 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
924 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
925 t4_rq_produce(&qhp->wq, len16);
926 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
927 wr = wr->next;
928 num_wrs--;
929 }
930 if (!qhp->rhp->rdev.status_page->db_off) {
931 t4_ring_rq_db(&qhp->wq, idx, wqe);
932 spin_unlock_irqrestore(&qhp->lock, flag);
933 } else {
934 spin_unlock_irqrestore(&qhp->lock, flag);
935 ring_kernel_rq_db(qhp, idx);
936 }
937 return err;
938 }
939
c4iw_bind_mw(struct ib_qp * qp,struct ib_mw * mw,struct ib_mw_bind * mw_bind)940 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
941 {
942 return -ENOSYS;
943 }
944
build_term_codes(struct t4_cqe * err_cqe,u8 * layer_type,u8 * ecode)945 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
946 u8 *ecode)
947 {
948 int status;
949 int tagged;
950 int opcode;
951 int rqtype;
952 int send_inv;
953
954 if (!err_cqe) {
955 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
956 *ecode = 0;
957 return;
958 }
959
960 status = CQE_STATUS(err_cqe);
961 opcode = CQE_OPCODE(err_cqe);
962 rqtype = RQ_TYPE(err_cqe);
963 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
964 (opcode == FW_RI_SEND_WITH_SE_INV);
965 tagged = (opcode == FW_RI_RDMA_WRITE) ||
966 (rqtype && (opcode == FW_RI_READ_RESP));
967
968 switch (status) {
969 case T4_ERR_STAG:
970 if (send_inv) {
971 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
972 *ecode = RDMAP_CANT_INV_STAG;
973 } else {
974 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
975 *ecode = RDMAP_INV_STAG;
976 }
977 break;
978 case T4_ERR_PDID:
979 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
980 if ((opcode == FW_RI_SEND_WITH_INV) ||
981 (opcode == FW_RI_SEND_WITH_SE_INV))
982 *ecode = RDMAP_CANT_INV_STAG;
983 else
984 *ecode = RDMAP_STAG_NOT_ASSOC;
985 break;
986 case T4_ERR_QPID:
987 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
988 *ecode = RDMAP_STAG_NOT_ASSOC;
989 break;
990 case T4_ERR_ACCESS:
991 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
992 *ecode = RDMAP_ACC_VIOL;
993 break;
994 case T4_ERR_WRAP:
995 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
996 *ecode = RDMAP_TO_WRAP;
997 break;
998 case T4_ERR_BOUND:
999 if (tagged) {
1000 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1001 *ecode = DDPT_BASE_BOUNDS;
1002 } else {
1003 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1004 *ecode = RDMAP_BASE_BOUNDS;
1005 }
1006 break;
1007 case T4_ERR_INVALIDATE_SHARED_MR:
1008 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
1009 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1010 *ecode = RDMAP_CANT_INV_STAG;
1011 break;
1012 case T4_ERR_ECC:
1013 case T4_ERR_ECC_PSTAG:
1014 case T4_ERR_INTERNAL_ERR:
1015 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
1016 *ecode = 0;
1017 break;
1018 case T4_ERR_OUT_OF_RQE:
1019 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1020 *ecode = DDPU_INV_MSN_NOBUF;
1021 break;
1022 case T4_ERR_PBL_ADDR_BOUND:
1023 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1024 *ecode = DDPT_BASE_BOUNDS;
1025 break;
1026 case T4_ERR_CRC:
1027 *layer_type = LAYER_MPA|DDP_LLP;
1028 *ecode = MPA_CRC_ERR;
1029 break;
1030 case T4_ERR_MARKER:
1031 *layer_type = LAYER_MPA|DDP_LLP;
1032 *ecode = MPA_MARKER_ERR;
1033 break;
1034 case T4_ERR_PDU_LEN_ERR:
1035 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1036 *ecode = DDPU_MSG_TOOBIG;
1037 break;
1038 case T4_ERR_DDP_VERSION:
1039 if (tagged) {
1040 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1041 *ecode = DDPT_INV_VERS;
1042 } else {
1043 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1044 *ecode = DDPU_INV_VERS;
1045 }
1046 break;
1047 case T4_ERR_RDMA_VERSION:
1048 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1049 *ecode = RDMAP_INV_VERS;
1050 break;
1051 case T4_ERR_OPCODE:
1052 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1053 *ecode = RDMAP_INV_OPCODE;
1054 break;
1055 case T4_ERR_DDP_QUEUE_NUM:
1056 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1057 *ecode = DDPU_INV_QN;
1058 break;
1059 case T4_ERR_MSN:
1060 case T4_ERR_MSN_GAP:
1061 case T4_ERR_MSN_RANGE:
1062 case T4_ERR_IRD_OVERFLOW:
1063 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1064 *ecode = DDPU_INV_MSN_RANGE;
1065 break;
1066 case T4_ERR_TBIT:
1067 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1068 *ecode = 0;
1069 break;
1070 case T4_ERR_MO:
1071 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1072 *ecode = DDPU_INV_MO;
1073 break;
1074 default:
1075 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1076 *ecode = 0;
1077 break;
1078 }
1079 }
1080
post_terminate(struct c4iw_qp * qhp,struct t4_cqe * err_cqe,gfp_t gfp)1081 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1082 gfp_t gfp)
1083 {
1084 struct fw_ri_wr *wqe;
1085 struct sk_buff *skb;
1086 struct terminate_message *term;
1087
1088 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1089 qhp->ep->hwtid);
1090
1091 skb = alloc_skb(sizeof *wqe, gfp);
1092 if (!skb)
1093 return;
1094 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1095
1096 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1097 memset(wqe, 0, sizeof *wqe);
1098 wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR));
1099 wqe->flowid_len16 = cpu_to_be32(
1100 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1101 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1102
1103 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1104 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1105 term = (struct terminate_message *)wqe->u.terminate.termmsg;
1106 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1107 term->layer_etype = qhp->attr.layer_etype;
1108 term->ecode = qhp->attr.ecode;
1109 } else
1110 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1111 c4iw_ofld_send(&qhp->rhp->rdev, skb);
1112 }
1113
1114 /*
1115 * Assumes qhp lock is held.
1116 */
__flush_qp(struct c4iw_qp * qhp,struct c4iw_cq * rchp,struct c4iw_cq * schp)1117 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1118 struct c4iw_cq *schp)
1119 {
1120 int count;
1121 int rq_flushed, sq_flushed;
1122 unsigned long flag;
1123
1124 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
1125
1126 /* locking hierarchy: cq lock first, then qp lock. */
1127 spin_lock_irqsave(&rchp->lock, flag);
1128 spin_lock(&qhp->lock);
1129
1130 if (qhp->wq.flushed) {
1131 spin_unlock(&qhp->lock);
1132 spin_unlock_irqrestore(&rchp->lock, flag);
1133 return;
1134 }
1135 qhp->wq.flushed = 1;
1136
1137 c4iw_flush_hw_cq(rchp);
1138 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1139 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1140 spin_unlock(&qhp->lock);
1141 spin_unlock_irqrestore(&rchp->lock, flag);
1142
1143 /* locking hierarchy: cq lock first, then qp lock. */
1144 spin_lock_irqsave(&schp->lock, flag);
1145 spin_lock(&qhp->lock);
1146 if (schp != rchp)
1147 c4iw_flush_hw_cq(schp);
1148 sq_flushed = c4iw_flush_sq(qhp);
1149 spin_unlock(&qhp->lock);
1150 spin_unlock_irqrestore(&schp->lock, flag);
1151
1152 if (schp == rchp) {
1153 if (t4_clear_cq_armed(&rchp->cq) &&
1154 (rq_flushed || sq_flushed)) {
1155 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1156 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1157 rchp->ibcq.cq_context);
1158 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1159 }
1160 } else {
1161 if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) {
1162 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1163 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1164 rchp->ibcq.cq_context);
1165 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1166 }
1167 if (t4_clear_cq_armed(&schp->cq) && sq_flushed) {
1168 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1169 (*schp->ibcq.comp_handler)(&schp->ibcq,
1170 schp->ibcq.cq_context);
1171 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1172 }
1173 }
1174 }
1175
flush_qp(struct c4iw_qp * qhp)1176 static void flush_qp(struct c4iw_qp *qhp)
1177 {
1178 struct c4iw_cq *rchp, *schp;
1179 unsigned long flag;
1180
1181 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1182 schp = to_c4iw_cq(qhp->ibqp.send_cq);
1183
1184 t4_set_wq_in_error(&qhp->wq);
1185 if (qhp->ibqp.uobject) {
1186 t4_set_cq_in_error(&rchp->cq);
1187 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1188 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1189 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1190 if (schp != rchp) {
1191 t4_set_cq_in_error(&schp->cq);
1192 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1193 (*schp->ibcq.comp_handler)(&schp->ibcq,
1194 schp->ibcq.cq_context);
1195 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1196 }
1197 return;
1198 }
1199 __flush_qp(qhp, rchp, schp);
1200 }
1201
rdma_fini(struct c4iw_dev * rhp,struct c4iw_qp * qhp,struct c4iw_ep * ep)1202 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1203 struct c4iw_ep *ep)
1204 {
1205 struct fw_ri_wr *wqe;
1206 int ret;
1207 struct sk_buff *skb;
1208
1209 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1210 ep->hwtid);
1211
1212 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1213 if (!skb)
1214 return -ENOMEM;
1215 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1216
1217 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1218 memset(wqe, 0, sizeof *wqe);
1219 wqe->op_compl = cpu_to_be32(
1220 FW_WR_OP_V(FW_RI_INIT_WR) |
1221 FW_WR_COMPL_F);
1222 wqe->flowid_len16 = cpu_to_be32(
1223 FW_WR_FLOWID_V(ep->hwtid) |
1224 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1225 wqe->cookie = (uintptr_t)&ep->com.wr_wait;
1226
1227 wqe->u.fini.type = FW_RI_TYPE_FINI;
1228 ret = c4iw_ofld_send(&rhp->rdev, skb);
1229 if (ret)
1230 goto out;
1231
1232 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1233 qhp->wq.sq.qid, __func__);
1234 out:
1235 PDBG("%s ret %d\n", __func__, ret);
1236 return ret;
1237 }
1238
build_rtr_msg(u8 p2p_type,struct fw_ri_init * init)1239 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1240 {
1241 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1242 memset(&init->u, 0, sizeof init->u);
1243 switch (p2p_type) {
1244 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1245 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1246 init->u.write.stag_sink = cpu_to_be32(1);
1247 init->u.write.to_sink = cpu_to_be64(1);
1248 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1249 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1250 sizeof(struct fw_ri_immd),
1251 16);
1252 break;
1253 case FW_RI_INIT_P2PTYPE_READ_REQ:
1254 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1255 init->u.read.stag_src = cpu_to_be32(1);
1256 init->u.read.to_src_lo = cpu_to_be32(1);
1257 init->u.read.stag_sink = cpu_to_be32(1);
1258 init->u.read.to_sink_lo = cpu_to_be32(1);
1259 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1260 break;
1261 }
1262 }
1263
rdma_init(struct c4iw_dev * rhp,struct c4iw_qp * qhp)1264 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1265 {
1266 struct fw_ri_wr *wqe;
1267 int ret;
1268 struct sk_buff *skb;
1269
1270 PDBG("%s qhp %p qid 0x%x tid %u ird %u ord %u\n", __func__, qhp,
1271 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord);
1272
1273 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1274 if (!skb) {
1275 ret = -ENOMEM;
1276 goto out;
1277 }
1278 ret = alloc_ird(rhp, qhp->attr.max_ird);
1279 if (ret) {
1280 qhp->attr.max_ird = 0;
1281 kfree_skb(skb);
1282 goto out;
1283 }
1284 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1285
1286 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1287 memset(wqe, 0, sizeof *wqe);
1288 wqe->op_compl = cpu_to_be32(
1289 FW_WR_OP_V(FW_RI_INIT_WR) |
1290 FW_WR_COMPL_F);
1291 wqe->flowid_len16 = cpu_to_be32(
1292 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1293 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1294
1295 wqe->cookie = (uintptr_t)&qhp->ep->com.wr_wait;
1296
1297 wqe->u.init.type = FW_RI_TYPE_INIT;
1298 wqe->u.init.mpareqbit_p2ptype =
1299 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) |
1300 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type);
1301 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1302 if (qhp->attr.mpa_attr.recv_marker_enabled)
1303 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1304 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1305 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1306 if (qhp->attr.mpa_attr.crc_enabled)
1307 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1308
1309 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1310 FW_RI_QP_RDMA_WRITE_ENABLE |
1311 FW_RI_QP_BIND_ENABLE;
1312 if (!qhp->ibqp.uobject)
1313 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1314 FW_RI_QP_STAG0_ENABLE;
1315 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1316 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1317 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1318 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1319 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1320 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1321 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1322 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1323 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1324 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1325 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1326 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1327 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1328 rhp->rdev.lldi.vr->rq.start);
1329 if (qhp->attr.mpa_attr.initiator)
1330 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1331
1332 ret = c4iw_ofld_send(&rhp->rdev, skb);
1333 if (ret)
1334 goto err1;
1335
1336 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1337 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1338 if (!ret)
1339 goto out;
1340 err1:
1341 free_ird(rhp, qhp->attr.max_ird);
1342 out:
1343 PDBG("%s ret %d\n", __func__, ret);
1344 return ret;
1345 }
1346
c4iw_modify_qp(struct c4iw_dev * rhp,struct c4iw_qp * qhp,enum c4iw_qp_attr_mask mask,struct c4iw_qp_attributes * attrs,int internal)1347 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1348 enum c4iw_qp_attr_mask mask,
1349 struct c4iw_qp_attributes *attrs,
1350 int internal)
1351 {
1352 int ret = 0;
1353 struct c4iw_qp_attributes newattr = qhp->attr;
1354 int disconnect = 0;
1355 int terminate = 0;
1356 int abort = 0;
1357 int free = 0;
1358 struct c4iw_ep *ep = NULL;
1359
1360 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1361 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1362 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1363
1364 mutex_lock(&qhp->mutex);
1365
1366 /* Process attr changes if in IDLE */
1367 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1368 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1369 ret = -EIO;
1370 goto out;
1371 }
1372 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1373 newattr.enable_rdma_read = attrs->enable_rdma_read;
1374 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1375 newattr.enable_rdma_write = attrs->enable_rdma_write;
1376 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1377 newattr.enable_bind = attrs->enable_bind;
1378 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1379 if (attrs->max_ord > c4iw_max_read_depth) {
1380 ret = -EINVAL;
1381 goto out;
1382 }
1383 newattr.max_ord = attrs->max_ord;
1384 }
1385 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1386 if (attrs->max_ird > cur_max_read_depth(rhp)) {
1387 ret = -EINVAL;
1388 goto out;
1389 }
1390 newattr.max_ird = attrs->max_ird;
1391 }
1392 qhp->attr = newattr;
1393 }
1394
1395 if (mask & C4IW_QP_ATTR_SQ_DB) {
1396 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1397 goto out;
1398 }
1399 if (mask & C4IW_QP_ATTR_RQ_DB) {
1400 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1401 goto out;
1402 }
1403
1404 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1405 goto out;
1406 if (qhp->attr.state == attrs->next_state)
1407 goto out;
1408
1409 switch (qhp->attr.state) {
1410 case C4IW_QP_STATE_IDLE:
1411 switch (attrs->next_state) {
1412 case C4IW_QP_STATE_RTS:
1413 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1414 ret = -EINVAL;
1415 goto out;
1416 }
1417 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1418 ret = -EINVAL;
1419 goto out;
1420 }
1421 qhp->attr.mpa_attr = attrs->mpa_attr;
1422 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1423 qhp->ep = qhp->attr.llp_stream_handle;
1424 set_state(qhp, C4IW_QP_STATE_RTS);
1425
1426 /*
1427 * Ref the endpoint here and deref when we
1428 * disassociate the endpoint from the QP. This
1429 * happens in CLOSING->IDLE transition or *->ERROR
1430 * transition.
1431 */
1432 c4iw_get_ep(&qhp->ep->com);
1433 ret = rdma_init(rhp, qhp);
1434 if (ret)
1435 goto err;
1436 break;
1437 case C4IW_QP_STATE_ERROR:
1438 set_state(qhp, C4IW_QP_STATE_ERROR);
1439 flush_qp(qhp);
1440 break;
1441 default:
1442 ret = -EINVAL;
1443 goto out;
1444 }
1445 break;
1446 case C4IW_QP_STATE_RTS:
1447 switch (attrs->next_state) {
1448 case C4IW_QP_STATE_CLOSING:
1449 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1450 t4_set_wq_in_error(&qhp->wq);
1451 set_state(qhp, C4IW_QP_STATE_CLOSING);
1452 ep = qhp->ep;
1453 if (!internal) {
1454 abort = 0;
1455 disconnect = 1;
1456 c4iw_get_ep(&qhp->ep->com);
1457 }
1458 ret = rdma_fini(rhp, qhp, ep);
1459 if (ret)
1460 goto err;
1461 break;
1462 case C4IW_QP_STATE_TERMINATE:
1463 t4_set_wq_in_error(&qhp->wq);
1464 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1465 qhp->attr.layer_etype = attrs->layer_etype;
1466 qhp->attr.ecode = attrs->ecode;
1467 ep = qhp->ep;
1468 if (!internal) {
1469 c4iw_get_ep(&qhp->ep->com);
1470 terminate = 1;
1471 disconnect = 1;
1472 } else {
1473 terminate = qhp->attr.send_term;
1474 ret = rdma_fini(rhp, qhp, ep);
1475 if (ret)
1476 goto err;
1477 }
1478 break;
1479 case C4IW_QP_STATE_ERROR:
1480 t4_set_wq_in_error(&qhp->wq);
1481 set_state(qhp, C4IW_QP_STATE_ERROR);
1482 if (!internal) {
1483 abort = 1;
1484 disconnect = 1;
1485 ep = qhp->ep;
1486 c4iw_get_ep(&qhp->ep->com);
1487 }
1488 goto err;
1489 break;
1490 default:
1491 ret = -EINVAL;
1492 goto out;
1493 }
1494 break;
1495 case C4IW_QP_STATE_CLOSING:
1496 if (!internal) {
1497 ret = -EINVAL;
1498 goto out;
1499 }
1500 switch (attrs->next_state) {
1501 case C4IW_QP_STATE_IDLE:
1502 flush_qp(qhp);
1503 set_state(qhp, C4IW_QP_STATE_IDLE);
1504 qhp->attr.llp_stream_handle = NULL;
1505 c4iw_put_ep(&qhp->ep->com);
1506 qhp->ep = NULL;
1507 wake_up(&qhp->wait);
1508 break;
1509 case C4IW_QP_STATE_ERROR:
1510 goto err;
1511 default:
1512 ret = -EINVAL;
1513 goto err;
1514 }
1515 break;
1516 case C4IW_QP_STATE_ERROR:
1517 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1518 ret = -EINVAL;
1519 goto out;
1520 }
1521 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1522 ret = -EINVAL;
1523 goto out;
1524 }
1525 set_state(qhp, C4IW_QP_STATE_IDLE);
1526 break;
1527 case C4IW_QP_STATE_TERMINATE:
1528 if (!internal) {
1529 ret = -EINVAL;
1530 goto out;
1531 }
1532 goto err;
1533 break;
1534 default:
1535 printk(KERN_ERR "%s in a bad state %d\n",
1536 __func__, qhp->attr.state);
1537 ret = -EINVAL;
1538 goto err;
1539 break;
1540 }
1541 goto out;
1542 err:
1543 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1544 qhp->wq.sq.qid);
1545
1546 /* disassociate the LLP connection */
1547 qhp->attr.llp_stream_handle = NULL;
1548 if (!ep)
1549 ep = qhp->ep;
1550 qhp->ep = NULL;
1551 set_state(qhp, C4IW_QP_STATE_ERROR);
1552 free = 1;
1553 abort = 1;
1554 BUG_ON(!ep);
1555 flush_qp(qhp);
1556 wake_up(&qhp->wait);
1557 out:
1558 mutex_unlock(&qhp->mutex);
1559
1560 if (terminate)
1561 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1562
1563 /*
1564 * If disconnect is 1, then we need to initiate a disconnect
1565 * on the EP. This can be a normal close (RTS->CLOSING) or
1566 * an abnormal close (RTS/CLOSING->ERROR).
1567 */
1568 if (disconnect) {
1569 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1570 GFP_KERNEL);
1571 c4iw_put_ep(&ep->com);
1572 }
1573
1574 /*
1575 * If free is 1, then we've disassociated the EP from the QP
1576 * and we need to dereference the EP.
1577 */
1578 if (free)
1579 c4iw_put_ep(&ep->com);
1580 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1581 return ret;
1582 }
1583
c4iw_destroy_qp(struct ib_qp * ib_qp)1584 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1585 {
1586 struct c4iw_dev *rhp;
1587 struct c4iw_qp *qhp;
1588 struct c4iw_qp_attributes attrs;
1589 struct c4iw_ucontext *ucontext;
1590
1591 qhp = to_c4iw_qp(ib_qp);
1592 rhp = qhp->rhp;
1593
1594 attrs.next_state = C4IW_QP_STATE_ERROR;
1595 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1596 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1597 else
1598 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1599 wait_event(qhp->wait, !qhp->ep);
1600
1601 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1602 atomic_dec(&qhp->refcnt);
1603 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1604
1605 spin_lock_irq(&rhp->lock);
1606 if (!list_empty(&qhp->db_fc_entry))
1607 list_del_init(&qhp->db_fc_entry);
1608 spin_unlock_irq(&rhp->lock);
1609 free_ird(rhp, qhp->attr.max_ird);
1610
1611 ucontext = ib_qp->uobject ?
1612 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1613 destroy_qp(&rhp->rdev, &qhp->wq,
1614 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1615
1616 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1617 kfree(qhp);
1618 return 0;
1619 }
1620
c4iw_create_qp(struct ib_pd * pd,struct ib_qp_init_attr * attrs,struct ib_udata * udata)1621 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1622 struct ib_udata *udata)
1623 {
1624 struct c4iw_dev *rhp;
1625 struct c4iw_qp *qhp;
1626 struct c4iw_pd *php;
1627 struct c4iw_cq *schp;
1628 struct c4iw_cq *rchp;
1629 struct c4iw_create_qp_resp uresp;
1630 unsigned int sqsize, rqsize;
1631 struct c4iw_ucontext *ucontext;
1632 int ret;
1633 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
1634
1635 PDBG("%s ib_pd %p\n", __func__, pd);
1636
1637 if (attrs->qp_type != IB_QPT_RC)
1638 return ERR_PTR(-EINVAL);
1639
1640 php = to_c4iw_pd(pd);
1641 rhp = php->rhp;
1642 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1643 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1644 if (!schp || !rchp)
1645 return ERR_PTR(-EINVAL);
1646
1647 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1648 return ERR_PTR(-EINVAL);
1649
1650 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size)
1651 return ERR_PTR(-E2BIG);
1652 rqsize = attrs->cap.max_recv_wr + 1;
1653 if (rqsize < 8)
1654 rqsize = 8;
1655
1656 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size)
1657 return ERR_PTR(-E2BIG);
1658 sqsize = attrs->cap.max_send_wr + 1;
1659 if (sqsize < 8)
1660 sqsize = 8;
1661
1662 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1663
1664 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1665 if (!qhp)
1666 return ERR_PTR(-ENOMEM);
1667 qhp->wq.sq.size = sqsize;
1668 qhp->wq.sq.memsize =
1669 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1670 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64);
1671 qhp->wq.sq.flush_cidx = -1;
1672 qhp->wq.rq.size = rqsize;
1673 qhp->wq.rq.memsize =
1674 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1675 sizeof(*qhp->wq.rq.queue);
1676
1677 if (ucontext) {
1678 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1679 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1680 }
1681
1682 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1683 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1684 if (ret)
1685 goto err1;
1686
1687 attrs->cap.max_recv_wr = rqsize - 1;
1688 attrs->cap.max_send_wr = sqsize - 1;
1689 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1690
1691 qhp->rhp = rhp;
1692 qhp->attr.pd = php->pdid;
1693 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1694 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1695 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1696 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1697 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1698 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1699 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1700 qhp->attr.state = C4IW_QP_STATE_IDLE;
1701 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1702 qhp->attr.enable_rdma_read = 1;
1703 qhp->attr.enable_rdma_write = 1;
1704 qhp->attr.enable_bind = 1;
1705 qhp->attr.max_ord = 0;
1706 qhp->attr.max_ird = 0;
1707 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
1708 spin_lock_init(&qhp->lock);
1709 mutex_init(&qhp->mutex);
1710 init_waitqueue_head(&qhp->wait);
1711 atomic_set(&qhp->refcnt, 1);
1712
1713 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1714 if (ret)
1715 goto err2;
1716
1717 if (udata) {
1718 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1719 if (!mm1) {
1720 ret = -ENOMEM;
1721 goto err3;
1722 }
1723 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1724 if (!mm2) {
1725 ret = -ENOMEM;
1726 goto err4;
1727 }
1728 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1729 if (!mm3) {
1730 ret = -ENOMEM;
1731 goto err5;
1732 }
1733 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1734 if (!mm4) {
1735 ret = -ENOMEM;
1736 goto err6;
1737 }
1738 if (t4_sq_onchip(&qhp->wq.sq)) {
1739 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1740 if (!mm5) {
1741 ret = -ENOMEM;
1742 goto err7;
1743 }
1744 uresp.flags = C4IW_QPF_ONCHIP;
1745 } else
1746 uresp.flags = 0;
1747 uresp.qid_mask = rhp->rdev.qpmask;
1748 uresp.sqid = qhp->wq.sq.qid;
1749 uresp.sq_size = qhp->wq.sq.size;
1750 uresp.sq_memsize = qhp->wq.sq.memsize;
1751 uresp.rqid = qhp->wq.rq.qid;
1752 uresp.rq_size = qhp->wq.rq.size;
1753 uresp.rq_memsize = qhp->wq.rq.memsize;
1754 spin_lock(&ucontext->mmap_lock);
1755 if (mm5) {
1756 uresp.ma_sync_key = ucontext->key;
1757 ucontext->key += PAGE_SIZE;
1758 } else {
1759 uresp.ma_sync_key = 0;
1760 }
1761 uresp.sq_key = ucontext->key;
1762 ucontext->key += PAGE_SIZE;
1763 uresp.rq_key = ucontext->key;
1764 ucontext->key += PAGE_SIZE;
1765 uresp.sq_db_gts_key = ucontext->key;
1766 ucontext->key += PAGE_SIZE;
1767 uresp.rq_db_gts_key = ucontext->key;
1768 ucontext->key += PAGE_SIZE;
1769 spin_unlock(&ucontext->mmap_lock);
1770 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1771 if (ret)
1772 goto err8;
1773 mm1->key = uresp.sq_key;
1774 mm1->addr = qhp->wq.sq.phys_addr;
1775 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1776 insert_mmap(ucontext, mm1);
1777 mm2->key = uresp.rq_key;
1778 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1779 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1780 insert_mmap(ucontext, mm2);
1781 mm3->key = uresp.sq_db_gts_key;
1782 mm3->addr = (__force unsigned long)qhp->wq.sq.bar2_pa;
1783 mm3->len = PAGE_SIZE;
1784 insert_mmap(ucontext, mm3);
1785 mm4->key = uresp.rq_db_gts_key;
1786 mm4->addr = (__force unsigned long)qhp->wq.rq.bar2_pa;
1787 mm4->len = PAGE_SIZE;
1788 insert_mmap(ucontext, mm4);
1789 if (mm5) {
1790 mm5->key = uresp.ma_sync_key;
1791 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1792 + PCIE_MA_SYNC_A) & PAGE_MASK;
1793 mm5->len = PAGE_SIZE;
1794 insert_mmap(ucontext, mm5);
1795 }
1796 }
1797 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1798 init_timer(&(qhp->timer));
1799 INIT_LIST_HEAD(&qhp->db_fc_entry);
1800 PDBG("%s sq id %u size %u memsize %zu num_entries %u "
1801 "rq id %u size %u memsize %zu num_entries %u\n", __func__,
1802 qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize,
1803 attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size,
1804 qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
1805 return &qhp->ibqp;
1806 err8:
1807 kfree(mm5);
1808 err7:
1809 kfree(mm4);
1810 err6:
1811 kfree(mm3);
1812 err5:
1813 kfree(mm2);
1814 err4:
1815 kfree(mm1);
1816 err3:
1817 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1818 err2:
1819 destroy_qp(&rhp->rdev, &qhp->wq,
1820 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1821 err1:
1822 kfree(qhp);
1823 return ERR_PTR(ret);
1824 }
1825
c4iw_ib_modify_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)1826 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1827 int attr_mask, struct ib_udata *udata)
1828 {
1829 struct c4iw_dev *rhp;
1830 struct c4iw_qp *qhp;
1831 enum c4iw_qp_attr_mask mask = 0;
1832 struct c4iw_qp_attributes attrs;
1833
1834 PDBG("%s ib_qp %p\n", __func__, ibqp);
1835
1836 /* iwarp does not support the RTR state */
1837 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1838 attr_mask &= ~IB_QP_STATE;
1839
1840 /* Make sure we still have something left to do */
1841 if (!attr_mask)
1842 return 0;
1843
1844 memset(&attrs, 0, sizeof attrs);
1845 qhp = to_c4iw_qp(ibqp);
1846 rhp = qhp->rhp;
1847
1848 attrs.next_state = c4iw_convert_state(attr->qp_state);
1849 attrs.enable_rdma_read = (attr->qp_access_flags &
1850 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1851 attrs.enable_rdma_write = (attr->qp_access_flags &
1852 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1853 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1854
1855
1856 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1857 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1858 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1859 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1860 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1861
1862 /*
1863 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1864 * ringing the queue db when we're in DB_FULL mode.
1865 * Only allow this on T4 devices.
1866 */
1867 attrs.sq_db_inc = attr->sq_psn;
1868 attrs.rq_db_inc = attr->rq_psn;
1869 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1870 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1871 if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) &&
1872 (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB)))
1873 return -EINVAL;
1874
1875 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1876 }
1877
c4iw_get_qp(struct ib_device * dev,int qpn)1878 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1879 {
1880 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1881 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1882 }
1883
c4iw_ib_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_qp_init_attr * init_attr)1884 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1885 int attr_mask, struct ib_qp_init_attr *init_attr)
1886 {
1887 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1888
1889 memset(attr, 0, sizeof *attr);
1890 memset(init_attr, 0, sizeof *init_attr);
1891 attr->qp_state = to_ib_qp_state(qhp->attr.state);
1892 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries;
1893 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries;
1894 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges;
1895 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges;
1896 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE;
1897 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0;
1898 return 0;
1899 }
1900