1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 * Authors: Christian König <christian.koenig@amd.com>
26 */
27
28 #include <linux/firmware.h>
29 #include <linux/module.h>
30 #include <drm/drmP.h>
31 #include <drm/drm.h>
32
33 #include "amdgpu.h"
34 #include "amdgpu_pm.h"
35 #include "amdgpu_vce.h"
36 #include "cikd.h"
37
38 /* 1 second timeout */
39 #define VCE_IDLE_TIMEOUT_MS 1000
40
41 /* Firmware Names */
42 #ifdef CONFIG_DRM_AMDGPU_CIK
43 #define FIRMWARE_BONAIRE "radeon/bonaire_vce.bin"
44 #define FIRMWARE_KABINI "radeon/kabini_vce.bin"
45 #define FIRMWARE_KAVERI "radeon/kaveri_vce.bin"
46 #define FIRMWARE_HAWAII "radeon/hawaii_vce.bin"
47 #define FIRMWARE_MULLINS "radeon/mullins_vce.bin"
48 #endif
49 #define FIRMWARE_TONGA "amdgpu/tonga_vce.bin"
50 #define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin"
51 #define FIRMWARE_FIJI "amdgpu/fiji_vce.bin"
52 #define FIRMWARE_STONEY "amdgpu/stoney_vce.bin"
53
54 #ifdef CONFIG_DRM_AMDGPU_CIK
55 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
56 MODULE_FIRMWARE(FIRMWARE_KABINI);
57 MODULE_FIRMWARE(FIRMWARE_KAVERI);
58 MODULE_FIRMWARE(FIRMWARE_HAWAII);
59 MODULE_FIRMWARE(FIRMWARE_MULLINS);
60 #endif
61 MODULE_FIRMWARE(FIRMWARE_TONGA);
62 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
63 MODULE_FIRMWARE(FIRMWARE_FIJI);
64 MODULE_FIRMWARE(FIRMWARE_STONEY);
65
66 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
67
68 /**
69 * amdgpu_vce_init - allocate memory, load vce firmware
70 *
71 * @adev: amdgpu_device pointer
72 *
73 * First step to get VCE online, allocate memory and load the firmware
74 */
amdgpu_vce_sw_init(struct amdgpu_device * adev,unsigned long size)75 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
76 {
77 const char *fw_name;
78 const struct common_firmware_header *hdr;
79 unsigned ucode_version, version_major, version_minor, binary_id;
80 int i, r;
81
82 INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
83
84 switch (adev->asic_type) {
85 #ifdef CONFIG_DRM_AMDGPU_CIK
86 case CHIP_BONAIRE:
87 fw_name = FIRMWARE_BONAIRE;
88 break;
89 case CHIP_KAVERI:
90 fw_name = FIRMWARE_KAVERI;
91 break;
92 case CHIP_KABINI:
93 fw_name = FIRMWARE_KABINI;
94 break;
95 case CHIP_HAWAII:
96 fw_name = FIRMWARE_HAWAII;
97 break;
98 case CHIP_MULLINS:
99 fw_name = FIRMWARE_MULLINS;
100 break;
101 #endif
102 case CHIP_TONGA:
103 fw_name = FIRMWARE_TONGA;
104 break;
105 case CHIP_CARRIZO:
106 fw_name = FIRMWARE_CARRIZO;
107 break;
108 case CHIP_FIJI:
109 fw_name = FIRMWARE_FIJI;
110 break;
111 case CHIP_STONEY:
112 fw_name = FIRMWARE_STONEY;
113 break;
114
115 default:
116 return -EINVAL;
117 }
118
119 r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
120 if (r) {
121 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
122 fw_name);
123 return r;
124 }
125
126 r = amdgpu_ucode_validate(adev->vce.fw);
127 if (r) {
128 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
129 fw_name);
130 release_firmware(adev->vce.fw);
131 adev->vce.fw = NULL;
132 return r;
133 }
134
135 hdr = (const struct common_firmware_header *)adev->vce.fw->data;
136
137 ucode_version = le32_to_cpu(hdr->ucode_version);
138 version_major = (ucode_version >> 20) & 0xfff;
139 version_minor = (ucode_version >> 8) & 0xfff;
140 binary_id = ucode_version & 0xff;
141 DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
142 version_major, version_minor, binary_id);
143 adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
144 (binary_id << 8));
145
146 /* allocate firmware, stack and heap BO */
147
148 r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
149 AMDGPU_GEM_DOMAIN_VRAM,
150 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
151 NULL, NULL, &adev->vce.vcpu_bo);
152 if (r) {
153 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
154 return r;
155 }
156
157 r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
158 if (r) {
159 amdgpu_bo_unref(&adev->vce.vcpu_bo);
160 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
161 return r;
162 }
163
164 r = amdgpu_bo_pin(adev->vce.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
165 &adev->vce.gpu_addr);
166 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
167 if (r) {
168 amdgpu_bo_unref(&adev->vce.vcpu_bo);
169 dev_err(adev->dev, "(%d) VCE bo pin failed\n", r);
170 return r;
171 }
172
173 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
174 atomic_set(&adev->vce.handles[i], 0);
175 adev->vce.filp[i] = NULL;
176 }
177
178 return 0;
179 }
180
181 /**
182 * amdgpu_vce_fini - free memory
183 *
184 * @adev: amdgpu_device pointer
185 *
186 * Last step on VCE teardown, free firmware memory
187 */
amdgpu_vce_sw_fini(struct amdgpu_device * adev)188 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
189 {
190 if (adev->vce.vcpu_bo == NULL)
191 return 0;
192
193 amdgpu_bo_unref(&adev->vce.vcpu_bo);
194
195 amdgpu_ring_fini(&adev->vce.ring[0]);
196 amdgpu_ring_fini(&adev->vce.ring[1]);
197
198 release_firmware(adev->vce.fw);
199
200 return 0;
201 }
202
203 /**
204 * amdgpu_vce_suspend - unpin VCE fw memory
205 *
206 * @adev: amdgpu_device pointer
207 *
208 */
amdgpu_vce_suspend(struct amdgpu_device * adev)209 int amdgpu_vce_suspend(struct amdgpu_device *adev)
210 {
211 int i;
212
213 if (adev->vce.vcpu_bo == NULL)
214 return 0;
215
216 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
217 if (atomic_read(&adev->vce.handles[i]))
218 break;
219
220 if (i == AMDGPU_MAX_VCE_HANDLES)
221 return 0;
222
223 cancel_delayed_work_sync(&adev->vce.idle_work);
224 /* TODO: suspending running encoding sessions isn't supported */
225 return -EINVAL;
226 }
227
228 /**
229 * amdgpu_vce_resume - pin VCE fw memory
230 *
231 * @adev: amdgpu_device pointer
232 *
233 */
amdgpu_vce_resume(struct amdgpu_device * adev)234 int amdgpu_vce_resume(struct amdgpu_device *adev)
235 {
236 void *cpu_addr;
237 const struct common_firmware_header *hdr;
238 unsigned offset;
239 int r;
240
241 if (adev->vce.vcpu_bo == NULL)
242 return -EINVAL;
243
244 r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
245 if (r) {
246 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
247 return r;
248 }
249
250 r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
251 if (r) {
252 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
253 dev_err(adev->dev, "(%d) VCE map failed\n", r);
254 return r;
255 }
256
257 hdr = (const struct common_firmware_header *)adev->vce.fw->data;
258 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
259 memcpy(cpu_addr, (adev->vce.fw->data) + offset,
260 (adev->vce.fw->size) - offset);
261
262 amdgpu_bo_kunmap(adev->vce.vcpu_bo);
263
264 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
265
266 return 0;
267 }
268
269 /**
270 * amdgpu_vce_idle_work_handler - power off VCE
271 *
272 * @work: pointer to work structure
273 *
274 * power of VCE when it's not used any more
275 */
amdgpu_vce_idle_work_handler(struct work_struct * work)276 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
277 {
278 struct amdgpu_device *adev =
279 container_of(work, struct amdgpu_device, vce.idle_work.work);
280
281 if ((amdgpu_fence_count_emitted(&adev->vce.ring[0]) == 0) &&
282 (amdgpu_fence_count_emitted(&adev->vce.ring[1]) == 0)) {
283 if (adev->pm.dpm_enabled) {
284 amdgpu_dpm_enable_vce(adev, false);
285 } else {
286 amdgpu_asic_set_vce_clocks(adev, 0, 0);
287 }
288 } else {
289 schedule_delayed_work(&adev->vce.idle_work,
290 msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
291 }
292 }
293
294 /**
295 * amdgpu_vce_note_usage - power up VCE
296 *
297 * @adev: amdgpu_device pointer
298 *
299 * Make sure VCE is powerd up when we want to use it
300 */
amdgpu_vce_note_usage(struct amdgpu_device * adev)301 static void amdgpu_vce_note_usage(struct amdgpu_device *adev)
302 {
303 bool streams_changed = false;
304 bool set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
305 set_clocks &= schedule_delayed_work(&adev->vce.idle_work,
306 msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
307
308 if (adev->pm.dpm_enabled) {
309 /* XXX figure out if the streams changed */
310 streams_changed = false;
311 }
312
313 if (set_clocks || streams_changed) {
314 if (adev->pm.dpm_enabled) {
315 amdgpu_dpm_enable_vce(adev, true);
316 } else {
317 amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
318 }
319 }
320 }
321
322 /**
323 * amdgpu_vce_free_handles - free still open VCE handles
324 *
325 * @adev: amdgpu_device pointer
326 * @filp: drm file pointer
327 *
328 * Close all VCE handles still open by this file pointer
329 */
amdgpu_vce_free_handles(struct amdgpu_device * adev,struct drm_file * filp)330 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
331 {
332 struct amdgpu_ring *ring = &adev->vce.ring[0];
333 int i, r;
334 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
335 uint32_t handle = atomic_read(&adev->vce.handles[i]);
336 if (!handle || adev->vce.filp[i] != filp)
337 continue;
338
339 amdgpu_vce_note_usage(adev);
340
341 r = amdgpu_vce_get_destroy_msg(ring, handle, NULL);
342 if (r)
343 DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
344
345 adev->vce.filp[i] = NULL;
346 atomic_set(&adev->vce.handles[i], 0);
347 }
348 }
349
amdgpu_vce_free_job(struct amdgpu_job * job)350 static int amdgpu_vce_free_job(
351 struct amdgpu_job *job)
352 {
353 amdgpu_ib_free(job->adev, job->ibs);
354 kfree(job->ibs);
355 return 0;
356 }
357
358 /**
359 * amdgpu_vce_get_create_msg - generate a VCE create msg
360 *
361 * @adev: amdgpu_device pointer
362 * @ring: ring we should submit the msg to
363 * @handle: VCE session handle to use
364 * @fence: optional fence to return
365 *
366 * Open up a stream for HW test
367 */
amdgpu_vce_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct fence ** fence)368 int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
369 struct fence **fence)
370 {
371 const unsigned ib_size_dw = 1024;
372 struct amdgpu_ib *ib = NULL;
373 struct fence *f = NULL;
374 struct amdgpu_device *adev = ring->adev;
375 uint64_t dummy;
376 int i, r;
377
378 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
379 if (!ib)
380 return -ENOMEM;
381 r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, ib);
382 if (r) {
383 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
384 kfree(ib);
385 return r;
386 }
387
388 dummy = ib->gpu_addr + 1024;
389
390 /* stitch together an VCE create msg */
391 ib->length_dw = 0;
392 ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
393 ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
394 ib->ptr[ib->length_dw++] = handle;
395
396 if ((ring->adev->vce.fw_version >> 24) >= 52)
397 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
398 else
399 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
400 ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
401 ib->ptr[ib->length_dw++] = 0x00000000;
402 ib->ptr[ib->length_dw++] = 0x00000042;
403 ib->ptr[ib->length_dw++] = 0x0000000a;
404 ib->ptr[ib->length_dw++] = 0x00000001;
405 ib->ptr[ib->length_dw++] = 0x00000080;
406 ib->ptr[ib->length_dw++] = 0x00000060;
407 ib->ptr[ib->length_dw++] = 0x00000100;
408 ib->ptr[ib->length_dw++] = 0x00000100;
409 ib->ptr[ib->length_dw++] = 0x0000000c;
410 ib->ptr[ib->length_dw++] = 0x00000000;
411 if ((ring->adev->vce.fw_version >> 24) >= 52) {
412 ib->ptr[ib->length_dw++] = 0x00000000;
413 ib->ptr[ib->length_dw++] = 0x00000000;
414 ib->ptr[ib->length_dw++] = 0x00000000;
415 ib->ptr[ib->length_dw++] = 0x00000000;
416 }
417
418 ib->ptr[ib->length_dw++] = 0x00000014; /* len */
419 ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
420 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
421 ib->ptr[ib->length_dw++] = dummy;
422 ib->ptr[ib->length_dw++] = 0x00000001;
423
424 for (i = ib->length_dw; i < ib_size_dw; ++i)
425 ib->ptr[i] = 0x0;
426
427 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
428 &amdgpu_vce_free_job,
429 AMDGPU_FENCE_OWNER_UNDEFINED,
430 &f);
431 if (r)
432 goto err;
433 if (fence)
434 *fence = fence_get(f);
435 fence_put(f);
436 if (amdgpu_enable_scheduler)
437 return 0;
438 err:
439 amdgpu_ib_free(adev, ib);
440 kfree(ib);
441 return r;
442 }
443
444 /**
445 * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
446 *
447 * @adev: amdgpu_device pointer
448 * @ring: ring we should submit the msg to
449 * @handle: VCE session handle to use
450 * @fence: optional fence to return
451 *
452 * Close up a stream for HW test or if userspace failed to do so
453 */
amdgpu_vce_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,struct fence ** fence)454 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
455 struct fence **fence)
456 {
457 const unsigned ib_size_dw = 1024;
458 struct amdgpu_ib *ib = NULL;
459 struct fence *f = NULL;
460 struct amdgpu_device *adev = ring->adev;
461 uint64_t dummy;
462 int i, r;
463
464 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
465 if (!ib)
466 return -ENOMEM;
467
468 r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, ib);
469 if (r) {
470 kfree(ib);
471 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
472 return r;
473 }
474
475 dummy = ib->gpu_addr + 1024;
476
477 /* stitch together an VCE destroy msg */
478 ib->length_dw = 0;
479 ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
480 ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
481 ib->ptr[ib->length_dw++] = handle;
482
483 ib->ptr[ib->length_dw++] = 0x00000014; /* len */
484 ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
485 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
486 ib->ptr[ib->length_dw++] = dummy;
487 ib->ptr[ib->length_dw++] = 0x00000001;
488
489 ib->ptr[ib->length_dw++] = 0x00000008; /* len */
490 ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
491
492 for (i = ib->length_dw; i < ib_size_dw; ++i)
493 ib->ptr[i] = 0x0;
494 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
495 &amdgpu_vce_free_job,
496 AMDGPU_FENCE_OWNER_UNDEFINED,
497 &f);
498 if (r)
499 goto err;
500 if (fence)
501 *fence = fence_get(f);
502 fence_put(f);
503 if (amdgpu_enable_scheduler)
504 return 0;
505 err:
506 amdgpu_ib_free(adev, ib);
507 kfree(ib);
508 return r;
509 }
510
511 /**
512 * amdgpu_vce_cs_reloc - command submission relocation
513 *
514 * @p: parser context
515 * @lo: address of lower dword
516 * @hi: address of higher dword
517 * @size: minimum size
518 *
519 * Patch relocation inside command stream with real buffer address
520 */
amdgpu_vce_cs_reloc(struct amdgpu_cs_parser * p,uint32_t ib_idx,int lo,int hi,unsigned size,uint32_t index)521 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
522 int lo, int hi, unsigned size, uint32_t index)
523 {
524 struct amdgpu_bo_va_mapping *mapping;
525 struct amdgpu_ib *ib = &p->ibs[ib_idx];
526 struct amdgpu_bo *bo;
527 uint64_t addr;
528
529 if (index == 0xffffffff)
530 index = 0;
531
532 addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
533 ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
534 addr += ((uint64_t)size) * ((uint64_t)index);
535
536 mapping = amdgpu_cs_find_mapping(p, addr, &bo);
537 if (mapping == NULL) {
538 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
539 addr, lo, hi, size, index);
540 return -EINVAL;
541 }
542
543 if ((addr + (uint64_t)size) >
544 ((uint64_t)mapping->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
545 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
546 addr, lo, hi);
547 return -EINVAL;
548 }
549
550 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
551 addr += amdgpu_bo_gpu_offset(bo);
552 addr -= ((uint64_t)size) * ((uint64_t)index);
553
554 ib->ptr[lo] = addr & 0xFFFFFFFF;
555 ib->ptr[hi] = addr >> 32;
556
557 return 0;
558 }
559
560 /**
561 * amdgpu_vce_validate_handle - validate stream handle
562 *
563 * @p: parser context
564 * @handle: handle to validate
565 * @allocated: allocated a new handle?
566 *
567 * Validates the handle and return the found session index or -EINVAL
568 * we we don't have another free session index.
569 */
amdgpu_vce_validate_handle(struct amdgpu_cs_parser * p,uint32_t handle,bool * allocated)570 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
571 uint32_t handle, bool *allocated)
572 {
573 unsigned i;
574
575 *allocated = false;
576
577 /* validate the handle */
578 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
579 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
580 if (p->adev->vce.filp[i] != p->filp) {
581 DRM_ERROR("VCE handle collision detected!\n");
582 return -EINVAL;
583 }
584 return i;
585 }
586 }
587
588 /* handle not found try to alloc a new one */
589 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
590 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
591 p->adev->vce.filp[i] = p->filp;
592 p->adev->vce.img_size[i] = 0;
593 *allocated = true;
594 return i;
595 }
596 }
597
598 DRM_ERROR("No more free VCE handles!\n");
599 return -EINVAL;
600 }
601
602 /**
603 * amdgpu_vce_cs_parse - parse and validate the command stream
604 *
605 * @p: parser context
606 *
607 */
amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser * p,uint32_t ib_idx)608 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
609 {
610 struct amdgpu_ib *ib = &p->ibs[ib_idx];
611 unsigned fb_idx = 0, bs_idx = 0;
612 int session_idx = -1;
613 bool destroyed = false;
614 bool created = false;
615 bool allocated = false;
616 uint32_t tmp, handle = 0;
617 uint32_t *size = &tmp;
618 int i, r = 0, idx = 0;
619
620 amdgpu_vce_note_usage(p->adev);
621
622 while (idx < ib->length_dw) {
623 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
624 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
625
626 if ((len < 8) || (len & 3)) {
627 DRM_ERROR("invalid VCE command length (%d)!\n", len);
628 r = -EINVAL;
629 goto out;
630 }
631
632 if (destroyed) {
633 DRM_ERROR("No other command allowed after destroy!\n");
634 r = -EINVAL;
635 goto out;
636 }
637
638 switch (cmd) {
639 case 0x00000001: // session
640 handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
641 session_idx = amdgpu_vce_validate_handle(p, handle,
642 &allocated);
643 if (session_idx < 0)
644 return session_idx;
645 size = &p->adev->vce.img_size[session_idx];
646 break;
647
648 case 0x00000002: // task info
649 fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
650 bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
651 break;
652
653 case 0x01000001: // create
654 created = true;
655 if (!allocated) {
656 DRM_ERROR("Handle already in use!\n");
657 r = -EINVAL;
658 goto out;
659 }
660
661 *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
662 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
663 8 * 3 / 2;
664 break;
665
666 case 0x04000001: // config extension
667 case 0x04000002: // pic control
668 case 0x04000005: // rate control
669 case 0x04000007: // motion estimation
670 case 0x04000008: // rdo
671 case 0x04000009: // vui
672 case 0x05000002: // auxiliary buffer
673 break;
674
675 case 0x03000001: // encode
676 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
677 *size, 0);
678 if (r)
679 goto out;
680
681 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
682 *size / 3, 0);
683 if (r)
684 goto out;
685 break;
686
687 case 0x02000001: // destroy
688 destroyed = true;
689 break;
690
691 case 0x05000001: // context buffer
692 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
693 *size * 2, 0);
694 if (r)
695 goto out;
696 break;
697
698 case 0x05000004: // video bitstream buffer
699 tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
700 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
701 tmp, bs_idx);
702 if (r)
703 goto out;
704 break;
705
706 case 0x05000005: // feedback buffer
707 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
708 4096, fb_idx);
709 if (r)
710 goto out;
711 break;
712
713 default:
714 DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
715 r = -EINVAL;
716 goto out;
717 }
718
719 if (session_idx == -1) {
720 DRM_ERROR("no session command at start of IB\n");
721 r = -EINVAL;
722 goto out;
723 }
724
725 idx += len / 4;
726 }
727
728 if (allocated && !created) {
729 DRM_ERROR("New session without create command!\n");
730 r = -ENOENT;
731 }
732
733 out:
734 if ((!r && destroyed) || (r && allocated)) {
735 /*
736 * IB contains a destroy msg or we have allocated an
737 * handle and got an error, anyway free the handle
738 */
739 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
740 atomic_cmpxchg(&p->adev->vce.handles[i], handle, 0);
741 }
742
743 return r;
744 }
745
746 /**
747 * amdgpu_vce_ring_emit_semaphore - emit a semaphore command
748 *
749 * @ring: engine to use
750 * @semaphore: address of semaphore
751 * @emit_wait: true=emit wait, false=emit signal
752 *
753 */
amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring * ring,struct amdgpu_semaphore * semaphore,bool emit_wait)754 bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring,
755 struct amdgpu_semaphore *semaphore,
756 bool emit_wait)
757 {
758 uint64_t addr = semaphore->gpu_addr;
759
760 amdgpu_ring_write(ring, VCE_CMD_SEMAPHORE);
761 amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
762 amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
763 amdgpu_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0));
764 if (!emit_wait)
765 amdgpu_ring_write(ring, VCE_CMD_END);
766
767 return true;
768 }
769
770 /**
771 * amdgpu_vce_ring_emit_ib - execute indirect buffer
772 *
773 * @ring: engine to use
774 * @ib: the IB to execute
775 *
776 */
amdgpu_vce_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)777 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
778 {
779 amdgpu_ring_write(ring, VCE_CMD_IB);
780 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
781 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
782 amdgpu_ring_write(ring, ib->length_dw);
783 }
784
785 /**
786 * amdgpu_vce_ring_emit_fence - add a fence command to the ring
787 *
788 * @ring: engine to use
789 * @fence: the fence
790 *
791 */
amdgpu_vce_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)792 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
793 unsigned flags)
794 {
795 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
796
797 amdgpu_ring_write(ring, VCE_CMD_FENCE);
798 amdgpu_ring_write(ring, addr);
799 amdgpu_ring_write(ring, upper_32_bits(addr));
800 amdgpu_ring_write(ring, seq);
801 amdgpu_ring_write(ring, VCE_CMD_TRAP);
802 amdgpu_ring_write(ring, VCE_CMD_END);
803 }
804
805 /**
806 * amdgpu_vce_ring_test_ring - test if VCE ring is working
807 *
808 * @ring: the engine to test on
809 *
810 */
amdgpu_vce_ring_test_ring(struct amdgpu_ring * ring)811 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
812 {
813 struct amdgpu_device *adev = ring->adev;
814 uint32_t rptr = amdgpu_ring_get_rptr(ring);
815 unsigned i;
816 int r;
817
818 r = amdgpu_ring_lock(ring, 16);
819 if (r) {
820 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
821 ring->idx, r);
822 return r;
823 }
824 amdgpu_ring_write(ring, VCE_CMD_END);
825 amdgpu_ring_unlock_commit(ring);
826
827 for (i = 0; i < adev->usec_timeout; i++) {
828 if (amdgpu_ring_get_rptr(ring) != rptr)
829 break;
830 DRM_UDELAY(1);
831 }
832
833 if (i < adev->usec_timeout) {
834 DRM_INFO("ring test on %d succeeded in %d usecs\n",
835 ring->idx, i);
836 } else {
837 DRM_ERROR("amdgpu: ring %d test failed\n",
838 ring->idx);
839 r = -ETIMEDOUT;
840 }
841
842 return r;
843 }
844
845 /**
846 * amdgpu_vce_ring_test_ib - test if VCE IBs are working
847 *
848 * @ring: the engine to test on
849 *
850 */
amdgpu_vce_ring_test_ib(struct amdgpu_ring * ring)851 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring)
852 {
853 struct fence *fence = NULL;
854 int r;
855
856 /* skip vce ring1 ib test for now, since it's not reliable */
857 if (ring == &ring->adev->vce.ring[1])
858 return 0;
859
860 r = amdgpu_vce_get_create_msg(ring, 1, NULL);
861 if (r) {
862 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
863 goto error;
864 }
865
866 r = amdgpu_vce_get_destroy_msg(ring, 1, &fence);
867 if (r) {
868 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
869 goto error;
870 }
871
872 r = fence_wait(fence, false);
873 if (r) {
874 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
875 } else {
876 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
877 }
878 error:
879 fence_put(fence);
880 return r;
881 }
882