1 /*
2 This file is provided under a dual BSD/GPLv2 license. When using or
3 redistributing this file, you may do so under either license.
4
5 GPL LICENSE SUMMARY
6 Copyright(c) 2014 Intel Corporation.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of version 2 of the GNU General Public License as
9 published by the Free Software Foundation.
10
11 This program is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
15
16 Contact Information:
17 qat-linux@intel.com
18
19 BSD LICENSE
20 Copyright(c) 2014 Intel Corporation.
21 Redistribution and use in source and binary forms, with or without
22 modification, are permitted provided that the following conditions
23 are met:
24
25 * Redistributions of source code must retain the above copyright
26 notice, this list of conditions and the following disclaimer.
27 * Redistributions in binary form must reproduce the above copyright
28 notice, this list of conditions and the following disclaimer in
29 the documentation and/or other materials provided with the
30 distribution.
31 * Neither the name of Intel Corporation nor the names of its
32 contributors may be used to endorse or promote products derived
33 from this software without specific prior written permission.
34
35 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
38 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
40 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
41 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
42 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
43 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
44 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
45 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
46 */
47 #include "adf_accel_devices.h"
48 #include "adf_transport_internal.h"
49
50 #define ADF_ARB_NUM 4
51 #define ADF_ARB_REQ_RING_NUM 8
52 #define ADF_ARB_REG_SIZE 0x4
53 #define ADF_ARB_WTR_SIZE 0x20
54 #define ADF_ARB_OFFSET 0x30000
55 #define ADF_ARB_REG_SLOT 0x1000
56 #define ADF_ARB_WTR_OFFSET 0x010
57 #define ADF_ARB_RO_EN_OFFSET 0x090
58 #define ADF_ARB_WQCFG_OFFSET 0x100
59 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
60 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
61
62 #define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
63 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
64 (ADF_ARB_REG_SLOT * index), value)
65
66 #define WRITE_CSR_ARB_RESPORDERING(csr_addr, index, value) \
67 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
68 ADF_ARB_RO_EN_OFFSET) + (ADF_ARB_REG_SIZE * index), value)
69
70 #define WRITE_CSR_ARB_WEIGHT(csr_addr, arb, index, value) \
71 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
72 ADF_ARB_WTR_OFFSET) + (ADF_ARB_WTR_SIZE * arb) + \
73 (ADF_ARB_REG_SIZE * index), value)
74
75 #define WRITE_CSR_ARB_SARCONFIG(csr_addr, index, value) \
76 ADF_CSR_WR(csr_addr, ADF_ARB_OFFSET + \
77 (ADF_ARB_REG_SIZE * index), value)
78
79 #define WRITE_CSR_ARB_WRK_2_SER_MAP(csr_addr, index, value) \
80 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
81 ADF_ARB_WRK_2_SER_MAP_OFFSET) + \
82 (ADF_ARB_REG_SIZE * index), value)
83
84 #define WRITE_CSR_ARB_WQCFG(csr_addr, index, value) \
85 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
86 ADF_ARB_WQCFG_OFFSET) + (ADF_ARB_REG_SIZE * index), value)
87
adf_init_arb(struct adf_accel_dev * accel_dev)88 int adf_init_arb(struct adf_accel_dev *accel_dev)
89 {
90 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
91 void __iomem *csr = accel_dev->transport->banks[0].csr_addr;
92 u32 arb_cfg = 0x1 << 31 | 0x4 << 4 | 0x1;
93 u32 arb, i;
94 const u32 *thd_2_arb_cfg;
95
96 /* Service arb configured for 32 bytes responses and
97 * ring flow control check enabled. */
98 for (arb = 0; arb < ADF_ARB_NUM; arb++)
99 WRITE_CSR_ARB_SARCONFIG(csr, arb, arb_cfg);
100
101 /* Setup service weighting */
102 for (arb = 0; arb < ADF_ARB_NUM; arb++)
103 for (i = 0; i < ADF_ARB_REQ_RING_NUM; i++)
104 WRITE_CSR_ARB_WEIGHT(csr, arb, i, 0xFFFFFFFF);
105
106 /* Setup ring response ordering */
107 for (i = 0; i < ADF_ARB_REQ_RING_NUM; i++)
108 WRITE_CSR_ARB_RESPORDERING(csr, i, 0xFFFFFFFF);
109
110 /* Setup worker queue registers */
111 for (i = 0; i < hw_data->num_engines; i++)
112 WRITE_CSR_ARB_WQCFG(csr, i, i);
113
114 /* Map worker threads to service arbiters */
115 hw_data->get_arb_mapping(accel_dev, &thd_2_arb_cfg);
116
117 if (!thd_2_arb_cfg)
118 return -EFAULT;
119
120 for (i = 0; i < hw_data->num_engines; i++)
121 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, *(thd_2_arb_cfg + i));
122
123 return 0;
124 }
125 EXPORT_SYMBOL_GPL(adf_init_arb);
126
127 /**
128 * adf_update_ring_arb() - update ring arbitration rgister
129 * @accel_dev: Pointer to ring data.
130 *
131 * Function enables or disables rings for/from arbitration.
132 */
adf_update_ring_arb(struct adf_etr_ring_data * ring)133 void adf_update_ring_arb(struct adf_etr_ring_data *ring)
134 {
135 WRITE_CSR_ARB_RINGSRVARBEN(ring->bank->csr_addr,
136 ring->bank->bank_number,
137 ring->bank->ring_mask & 0xFF);
138 }
139 EXPORT_SYMBOL_GPL(adf_update_ring_arb);
140
adf_exit_arb(struct adf_accel_dev * accel_dev)141 void adf_exit_arb(struct adf_accel_dev *accel_dev)
142 {
143 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
144 void __iomem *csr;
145 unsigned int i;
146
147 if (!accel_dev->transport)
148 return;
149
150 csr = accel_dev->transport->banks[0].csr_addr;
151
152 /* Reset arbiter configuration */
153 for (i = 0; i < ADF_ARB_NUM; i++)
154 WRITE_CSR_ARB_SARCONFIG(csr, i, 0);
155
156 /* Shutdown work queue */
157 for (i = 0; i < hw_data->num_engines; i++)
158 WRITE_CSR_ARB_WQCFG(csr, i, 0);
159
160 /* Unmap worker threads to service arbiters */
161 for (i = 0; i < hw_data->num_engines; i++)
162 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, 0);
163
164 /* Disable arbitration on all rings */
165 for (i = 0; i < GET_MAX_BANKS(accel_dev); i++)
166 WRITE_CSR_ARB_RINGSRVARBEN(csr, i, 0);
167 }
168 EXPORT_SYMBOL_GPL(adf_exit_arb);
169