1 /*
2 This file is provided under a dual BSD/GPLv2 license. When using or
3 redistributing this file, you may do so under either license.
4
5 GPL LICENSE SUMMARY
6 Copyright(c) 2014 Intel Corporation.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of version 2 of the GNU General Public License as
9 published by the Free Software Foundation.
10
11 This program is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
15
16 Contact Information:
17 qat-linux@intel.com
18
19 BSD LICENSE
20 Copyright(c) 2014 Intel Corporation.
21 Redistribution and use in source and binary forms, with or without
22 modification, are permitted provided that the following conditions
23 are met:
24
25 * Redistributions of source code must retain the above copyright
26 notice, this list of conditions and the following disclaimer.
27 * Redistributions in binary form must reproduce the above copyright
28 notice, this list of conditions and the following disclaimer in
29 the documentation and/or other materials provided with the
30 distribution.
31 * Neither the name of Intel Corporation nor the names of its
32 contributors may be used to endorse or promote products derived
33 from this software without specific prior written permission.
34
35 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
38 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
40 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
41 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
42 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
43 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
44 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
45 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
46 */
47 #include <adf_accel_devices.h>
48 #include <adf_transport_internal.h>
49 #include "adf_drv.h"
50
51 #define ADF_ARB_NUM 4
52 #define ADF_ARB_REQ_RING_NUM 8
53 #define ADF_ARB_REG_SIZE 0x4
54 #define ADF_ARB_WTR_SIZE 0x20
55 #define ADF_ARB_OFFSET 0x30000
56 #define ADF_ARB_REG_SLOT 0x1000
57 #define ADF_ARB_WTR_OFFSET 0x010
58 #define ADF_ARB_RO_EN_OFFSET 0x090
59 #define ADF_ARB_WQCFG_OFFSET 0x100
60 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
61 #define ADF_ARB_WRK_2_SER_MAP 10
62 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
63
64 #define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
65 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
66 (ADF_ARB_REG_SLOT * index), value)
67
68 #define WRITE_CSR_ARB_RESPORDERING(csr_addr, index, value) \
69 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
70 ADF_ARB_RO_EN_OFFSET) + (ADF_ARB_REG_SIZE * index), value)
71
72 #define WRITE_CSR_ARB_WEIGHT(csr_addr, arb, index, value) \
73 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
74 ADF_ARB_WTR_OFFSET) + (ADF_ARB_WTR_SIZE * arb) + \
75 (ADF_ARB_REG_SIZE * index), value)
76
77 #define WRITE_CSR_ARB_SARCONFIG(csr_addr, index, value) \
78 ADF_CSR_WR(csr_addr, ADF_ARB_OFFSET + \
79 (ADF_ARB_REG_SIZE * index), value)
80
81 #define WRITE_CSR_ARB_WRK_2_SER_MAP(csr_addr, index, value) \
82 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
83 ADF_ARB_WRK_2_SER_MAP_OFFSET) + \
84 (ADF_ARB_REG_SIZE * index), value)
85
86 #define WRITE_CSR_ARB_WQCFG(csr_addr, index, value) \
87 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
88 ADF_ARB_WQCFG_OFFSET) + (ADF_ARB_REG_SIZE * index), value)
89
adf_init_arb(struct adf_accel_dev * accel_dev)90 int adf_init_arb(struct adf_accel_dev *accel_dev)
91 {
92 void __iomem *csr = accel_dev->transport->banks[0].csr_addr;
93 uint32_t arb_cfg = 0x1 << 31 | 0x4 << 4 | 0x1;
94 uint32_t arb, i;
95 const uint32_t *thd_2_arb_cfg;
96
97 /* Service arb configured for 32 bytes responses and
98 * ring flow control check enabled. */
99 for (arb = 0; arb < ADF_ARB_NUM; arb++)
100 WRITE_CSR_ARB_SARCONFIG(csr, arb, arb_cfg);
101
102 /* Setup service weighting */
103 for (arb = 0; arb < ADF_ARB_NUM; arb++)
104 for (i = 0; i < ADF_ARB_REQ_RING_NUM; i++)
105 WRITE_CSR_ARB_WEIGHT(csr, arb, i, 0xFFFFFFFF);
106
107 /* Setup ring response ordering */
108 for (i = 0; i < ADF_ARB_REQ_RING_NUM; i++)
109 WRITE_CSR_ARB_RESPORDERING(csr, i, 0xFFFFFFFF);
110
111 /* Setup worker queue registers */
112 for (i = 0; i < ADF_ARB_WRK_2_SER_MAP; i++)
113 WRITE_CSR_ARB_WQCFG(csr, i, i);
114
115 /* Map worker threads to service arbiters */
116 adf_get_arbiter_mapping(accel_dev, &thd_2_arb_cfg);
117
118 if (!thd_2_arb_cfg)
119 return -EFAULT;
120
121 for (i = 0; i < ADF_ARB_WRK_2_SER_MAP; i++)
122 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, *(thd_2_arb_cfg + i));
123
124 return 0;
125 }
126
adf_update_ring_arb_enable(struct adf_etr_ring_data * ring)127 void adf_update_ring_arb_enable(struct adf_etr_ring_data *ring)
128 {
129 WRITE_CSR_ARB_RINGSRVARBEN(ring->bank->csr_addr,
130 ring->bank->bank_number,
131 ring->bank->ring_mask & 0xFF);
132 }
133
adf_exit_arb(struct adf_accel_dev * accel_dev)134 void adf_exit_arb(struct adf_accel_dev *accel_dev)
135 {
136 void __iomem *csr;
137 unsigned int i;
138
139 if (!accel_dev->transport)
140 return;
141
142 csr = accel_dev->transport->banks[0].csr_addr;
143
144 /* Reset arbiter configuration */
145 for (i = 0; i < ADF_ARB_NUM; i++)
146 WRITE_CSR_ARB_SARCONFIG(csr, i, 0);
147
148 /* Shutdown work queue */
149 for (i = 0; i < ADF_ARB_WRK_2_SER_MAP; i++)
150 WRITE_CSR_ARB_WQCFG(csr, i, 0);
151
152 /* Unmap worker threads to service arbiters */
153 for (i = 0; i < ADF_ARB_WRK_2_SER_MAP; i++)
154 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, 0);
155
156 /* Disable arbitration on all rings */
157 for (i = 0; i < GET_MAX_BANKS(accel_dev); i++)
158 WRITE_CSR_ARB_RINGSRVARBEN(csr, i, 0);
159 }
160