1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 *
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
7 * more details.
8 *
9 * The full GNU General Public License is included in this distribution in the
10 * file called LICENSE.
11 *
12 * Contact Information:
13 * wlanfae <wlanfae@realtek.com>
14 ******************************************************************************/
15
16 #include <linux/bitops.h>
17 #include "rtl_core.h"
18 #include "r8192E_hw.h"
19 #include "r8192E_phyreg.h"
20 #include "r8190P_rtl8256.h"
21 #include "r8192E_phy.h"
22 #include "rtl_dm.h"
23
24 #include "r8192E_hwimg.h"
25
26 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
27 0,
28 0x085c,
29 0x08dc,
30 0x095c,
31 0x09dc,
32 0x0a5c,
33 0x0adc,
34 0x0b5c,
35 0x0bdc,
36 0x0c5c,
37 0x0cdc,
38 0x0d5c,
39 0x0ddc,
40 0x0e5c,
41 0x0f72,
42 };
43
44 /*************************Define local function prototype**********************/
45
46 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev,
47 enum rf90_radio_path eRFPath, u32 Offset);
48 static void _rtl92e_phy_rf_fw_write(struct net_device *dev,
49 enum rf90_radio_path eRFPath, u32 Offset,
50 u32 Data);
51
_rtl92e_calculate_bit_shift(u32 dwBitMask)52 static u32 _rtl92e_calculate_bit_shift(u32 dwBitMask)
53 {
54 if (!dwBitMask)
55 return 32;
56 return ffs(dwBitMask) - 1;
57 }
58
rtl92e_is_legal_rf_path(struct net_device * dev,u32 eRFPath)59 u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath)
60 {
61 u8 ret = 1;
62 struct r8192_priv *priv = rtllib_priv(dev);
63
64 if (priv->rf_type == RF_2T4R)
65 ret = 0;
66 else if (priv->rf_type == RF_1T2R) {
67 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
68 ret = 1;
69 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
70 ret = 0;
71 }
72 return ret;
73 }
74
rtl92e_set_bb_reg(struct net_device * dev,u32 dwRegAddr,u32 dwBitMask,u32 dwData)75 void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
76 u32 dwData)
77 {
78
79 u32 OriginalValue, BitShift, NewValue;
80
81 if (dwBitMask != bMaskDWord) {
82 OriginalValue = rtl92e_readl(dev, dwRegAddr);
83 BitShift = _rtl92e_calculate_bit_shift(dwBitMask);
84 NewValue = (((OriginalValue) & (~dwBitMask)) |
85 (dwData << BitShift));
86 rtl92e_writel(dev, dwRegAddr, NewValue);
87 } else
88 rtl92e_writel(dev, dwRegAddr, dwData);
89 }
90
rtl92e_get_bb_reg(struct net_device * dev,u32 dwRegAddr,u32 dwBitMask)91 u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
92 {
93 u32 Ret = 0, OriginalValue, BitShift;
94
95 OriginalValue = rtl92e_readl(dev, dwRegAddr);
96 BitShift = _rtl92e_calculate_bit_shift(dwBitMask);
97 Ret = (OriginalValue & dwBitMask) >> BitShift;
98
99 return Ret;
100 }
101
_rtl92e_phy_rf_read(struct net_device * dev,enum rf90_radio_path eRFPath,u32 Offset)102 static u32 _rtl92e_phy_rf_read(struct net_device *dev,
103 enum rf90_radio_path eRFPath, u32 Offset)
104 {
105 struct r8192_priv *priv = rtllib_priv(dev);
106 u32 ret = 0;
107 u32 NewOffset = 0;
108 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
109
110 Offset &= 0x3f;
111
112 if (priv->rf_chip == RF_8256) {
113 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
114 if (Offset >= 31) {
115 priv->RfReg0Value[eRFPath] |= 0x140;
116 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
117 bMaskDWord,
118 (priv->RfReg0Value[eRFPath]<<16));
119 NewOffset = Offset - 30;
120 } else if (Offset >= 16) {
121 priv->RfReg0Value[eRFPath] |= 0x100;
122 priv->RfReg0Value[eRFPath] &= (~0x40);
123 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
124 bMaskDWord,
125 (priv->RfReg0Value[eRFPath]<<16));
126
127 NewOffset = Offset - 15;
128 } else
129 NewOffset = Offset;
130 } else {
131 RT_TRACE((COMP_PHY|COMP_ERR),
132 "check RF type here, need to be 8256\n");
133 NewOffset = Offset;
134 }
135 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
136 NewOffset);
137 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
138 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
139
140 mdelay(1);
141
142 ret = rtl92e_get_bb_reg(dev, pPhyReg->rfLSSIReadBack,
143 bLSSIReadBackData);
144
145 if (priv->rf_chip == RF_8256) {
146 priv->RfReg0Value[eRFPath] &= 0xebf;
147
148 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
149 (priv->RfReg0Value[eRFPath] << 16));
150
151 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
152 }
153
154
155 return ret;
156
157 }
158
_rtl92e_phy_rf_write(struct net_device * dev,enum rf90_radio_path eRFPath,u32 Offset,u32 Data)159 static void _rtl92e_phy_rf_write(struct net_device *dev,
160 enum rf90_radio_path eRFPath, u32 Offset,
161 u32 Data)
162 {
163 struct r8192_priv *priv = rtllib_priv(dev);
164 u32 DataAndAddr = 0, NewOffset = 0;
165 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
166
167 Offset &= 0x3f;
168 if (priv->rf_chip == RF_8256) {
169 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
170
171 if (Offset >= 31) {
172 priv->RfReg0Value[eRFPath] |= 0x140;
173 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
174 bMaskDWord,
175 (priv->RfReg0Value[eRFPath] << 16));
176 NewOffset = Offset - 30;
177 } else if (Offset >= 16) {
178 priv->RfReg0Value[eRFPath] |= 0x100;
179 priv->RfReg0Value[eRFPath] &= (~0x40);
180 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
181 bMaskDWord,
182 (priv->RfReg0Value[eRFPath] << 16));
183 NewOffset = Offset - 15;
184 } else
185 NewOffset = Offset;
186 } else {
187 RT_TRACE((COMP_PHY|COMP_ERR),
188 "check RF type here, need to be 8256\n");
189 NewOffset = Offset;
190 }
191
192 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
193
194 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
195
196 if (Offset == 0x0)
197 priv->RfReg0Value[eRFPath] = Data;
198
199 if (priv->rf_chip == RF_8256) {
200 if (Offset != 0) {
201 priv->RfReg0Value[eRFPath] &= 0xebf;
202 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
203 bMaskDWord,
204 (priv->RfReg0Value[eRFPath] << 16));
205 }
206 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
207 }
208 }
209
rtl92e_set_rf_reg(struct net_device * dev,enum rf90_radio_path eRFPath,u32 RegAddr,u32 BitMask,u32 Data)210 void rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
211 u32 RegAddr, u32 BitMask, u32 Data)
212 {
213 struct r8192_priv *priv = rtllib_priv(dev);
214 u32 Original_Value, BitShift, New_Value;
215
216 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
217 return;
218 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
219 return;
220
221 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
222 if (priv->Rf_Mode == RF_OP_By_FW) {
223 if (BitMask != bMask12Bits) {
224 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath,
225 RegAddr);
226 BitShift = _rtl92e_calculate_bit_shift(BitMask);
227 New_Value = (((Original_Value) & (~BitMask)) |
228 (Data << BitShift));
229
230 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr,
231 New_Value);
232 } else
233 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, Data);
234 udelay(200);
235
236 } else {
237 if (BitMask != bMask12Bits) {
238 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath,
239 RegAddr);
240 BitShift = _rtl92e_calculate_bit_shift(BitMask);
241 New_Value = (((Original_Value) & (~BitMask)) |
242 (Data << BitShift));
243
244 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, New_Value);
245 } else
246 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, Data);
247 }
248 }
249
rtl92e_get_rf_reg(struct net_device * dev,enum rf90_radio_path eRFPath,u32 RegAddr,u32 BitMask)250 u32 rtl92e_get_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
251 u32 RegAddr, u32 BitMask)
252 {
253 u32 Original_Value, Readback_Value, BitShift;
254 struct r8192_priv *priv = rtllib_priv(dev);
255
256 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
257 return 0;
258 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
259 return 0;
260 down(&priv->rf_sem);
261 if (priv->Rf_Mode == RF_OP_By_FW) {
262 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, RegAddr);
263 udelay(200);
264 } else {
265 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, RegAddr);
266 }
267 BitShift = _rtl92e_calculate_bit_shift(BitMask);
268 Readback_Value = (Original_Value & BitMask) >> BitShift;
269 up(&priv->rf_sem);
270 return Readback_Value;
271 }
272
_rtl92e_phy_rf_fw_read(struct net_device * dev,enum rf90_radio_path eRFPath,u32 Offset)273 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev,
274 enum rf90_radio_path eRFPath, u32 Offset)
275 {
276 u32 Data = 0;
277 u8 time = 0;
278
279 Data |= ((Offset & 0xFF) << 12);
280 Data |= ((eRFPath & 0x3) << 20);
281 Data |= 0x80000000;
282 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
283 if (time++ < 100)
284 udelay(10);
285 else
286 break;
287 }
288 rtl92e_writel(dev, QPNR, Data);
289 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
290 if (time++ < 100)
291 udelay(10);
292 else
293 return 0;
294 }
295 return rtl92e_readl(dev, RF_DATA);
296
297 }
298
_rtl92e_phy_rf_fw_write(struct net_device * dev,enum rf90_radio_path eRFPath,u32 Offset,u32 Data)299 static void _rtl92e_phy_rf_fw_write(struct net_device *dev,
300 enum rf90_radio_path eRFPath, u32 Offset,
301 u32 Data)
302 {
303 u8 time = 0;
304
305 Data |= ((Offset & 0xFF) << 12);
306 Data |= ((eRFPath & 0x3) << 20);
307 Data |= 0x400000;
308 Data |= 0x80000000;
309
310 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
311 if (time++ < 100)
312 udelay(10);
313 else
314 break;
315 }
316 rtl92e_writel(dev, QPNR, Data);
317
318 }
319
320
rtl92e_config_mac(struct net_device * dev)321 void rtl92e_config_mac(struct net_device *dev)
322 {
323 u32 dwArrayLen = 0, i = 0;
324 u32 *pdwArray = NULL;
325 struct r8192_priv *priv = rtllib_priv(dev);
326
327 if (priv->bTXPowerDataReadFromEEPORM) {
328 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
329 dwArrayLen = MACPHY_Array_PGLength;
330 pdwArray = Rtl819XMACPHY_Array_PG;
331
332 } else {
333 RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n");
334 dwArrayLen = MACPHY_ArrayLength;
335 pdwArray = Rtl819XMACPHY_Array;
336 }
337 for (i = 0; i < dwArrayLen; i += 3) {
338 RT_TRACE(COMP_DBG,
339 "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
340 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
341 if (pdwArray[i] == 0x318)
342 pdwArray[i+2] = 0x00000800;
343 rtl92e_set_bb_reg(dev, pdwArray[i], pdwArray[i+1],
344 pdwArray[i+2]);
345 }
346 return;
347
348 }
349
_rtl92e_phy_config_bb(struct net_device * dev,u8 ConfigType)350 static void _rtl92e_phy_config_bb(struct net_device *dev, u8 ConfigType)
351 {
352 int i;
353 u32 *Rtl819XPHY_REGArray_Table = NULL;
354 u32 *Rtl819XAGCTAB_Array_Table = NULL;
355 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
356 struct r8192_priv *priv = rtllib_priv(dev);
357
358 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
359 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
360 if (priv->rf_type == RF_2T4R) {
361 PHY_REGArrayLen = PHY_REGArrayLength;
362 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
363 } else if (priv->rf_type == RF_1T2R) {
364 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
365 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
366 }
367
368 if (ConfigType == BaseBand_Config_PHY_REG) {
369 for (i = 0; i < PHY_REGArrayLen; i += 2) {
370 rtl92e_set_bb_reg(dev, Rtl819XPHY_REGArray_Table[i],
371 bMaskDWord,
372 Rtl819XPHY_REGArray_Table[i+1]);
373 RT_TRACE(COMP_DBG,
374 "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",
375 i, Rtl819XPHY_REGArray_Table[i],
376 Rtl819XPHY_REGArray_Table[i+1]);
377 }
378 } else if (ConfigType == BaseBand_Config_AGC_TAB) {
379 for (i = 0; i < AGCTAB_ArrayLen; i += 2) {
380 rtl92e_set_bb_reg(dev, Rtl819XAGCTAB_Array_Table[i],
381 bMaskDWord,
382 Rtl819XAGCTAB_Array_Table[i+1]);
383 RT_TRACE(COMP_DBG,
384 "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n",
385 i, Rtl819XAGCTAB_Array_Table[i],
386 Rtl819XAGCTAB_Array_Table[i+1]);
387 }
388 }
389 }
390
_rtl92e_init_bb_rf_reg_def(struct net_device * dev)391 static void _rtl92e_init_bb_rf_reg_def(struct net_device *dev)
392 {
393 struct r8192_priv *priv = rtllib_priv(dev);
394
395 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
396 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
397 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
398 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
399
400 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
401 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
402 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
403 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
404
405 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
406 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
407 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
408 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
409
410 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
411 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
412 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
413 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
414
415 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
416 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
417 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
418 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
419
420 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
421 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
422 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
423 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
424
425 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
426 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
427 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
428 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
429
430 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
431 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
432 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
433 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
434
435 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
436 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
437 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
438 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
439
440 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
441 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
442 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
443 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
444
445 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
446 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
447 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
448 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
449
450 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
451 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
452 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
453 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
454
455 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
456 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
457 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
458 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
459
460 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
461 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
462 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
463 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
464
465 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
466 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
467 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
468 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
469
470 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
471 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
472 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
473 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
474
475 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
476 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
477 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
478 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
479
480 }
481
rtl92e_check_bb_and_rf(struct net_device * dev,enum hw90_block CheckBlock,enum rf90_radio_path eRFPath)482 bool rtl92e_check_bb_and_rf(struct net_device *dev, enum hw90_block CheckBlock,
483 enum rf90_radio_path eRFPath)
484 {
485 bool ret = true;
486 u32 i, CheckTimes = 4, dwRegRead = 0;
487 u32 WriteAddr[4];
488 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
489
490 WriteAddr[HW90_BLOCK_MAC] = 0x100;
491 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
492 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
493 WriteAddr[HW90_BLOCK_RF] = 0x3;
494 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__,
495 CheckBlock);
496
497 if (CheckBlock == HW90_BLOCK_MAC) {
498 netdev_warn(dev, "%s(): No checks available for MAC block.\n",
499 __func__);
500 return ret;
501 }
502
503 for (i = 0; i < CheckTimes; i++) {
504 switch (CheckBlock) {
505 case HW90_BLOCK_PHY0:
506 case HW90_BLOCK_PHY1:
507 rtl92e_writel(dev, WriteAddr[CheckBlock],
508 WriteData[i]);
509 dwRegRead = rtl92e_readl(dev, WriteAddr[CheckBlock]);
510 break;
511
512 case HW90_BLOCK_RF:
513 WriteData[i] &= 0xfff;
514 rtl92e_set_rf_reg(dev, eRFPath,
515 WriteAddr[HW90_BLOCK_RF],
516 bMask12Bits, WriteData[i]);
517 mdelay(10);
518 dwRegRead = rtl92e_get_rf_reg(dev, eRFPath,
519 WriteAddr[HW90_BLOCK_RF],
520 bMaskDWord);
521 mdelay(10);
522 break;
523
524 default:
525 ret = false;
526 break;
527 }
528
529
530 if (dwRegRead != WriteData[i]) {
531 netdev_warn(dev, "%s(): Check failed.\n", __func__);
532 ret = false;
533 break;
534 }
535 }
536
537 return ret;
538 }
539
_rtl92e_bb_config_para_file(struct net_device * dev)540 static bool _rtl92e_bb_config_para_file(struct net_device *dev)
541 {
542 struct r8192_priv *priv = rtllib_priv(dev);
543 bool rtStatus = true;
544 u8 bRegValue = 0, eCheckItem = 0;
545 u32 dwRegValue = 0;
546
547 bRegValue = rtl92e_readb(dev, BB_GLOBAL_RESET);
548 rtl92e_writeb(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT));
549
550 dwRegValue = rtl92e_readl(dev, CPU_GEN);
551 rtl92e_writel(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
552
553 for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0;
554 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
555 rtStatus = rtl92e_check_bb_and_rf(dev,
556 (enum hw90_block)eCheckItem,
557 (enum rf90_radio_path)0);
558 if (!rtStatus) {
559 RT_TRACE((COMP_ERR | COMP_PHY),
560 "rtl92e_config_rf():Check PHY%d Fail!!\n",
561 eCheckItem-1);
562 return rtStatus;
563 }
564 }
565 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
566 _rtl92e_phy_config_bb(dev, BaseBand_Config_PHY_REG);
567
568 dwRegValue = rtl92e_readl(dev, CPU_GEN);
569 rtl92e_writel(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
570
571 _rtl92e_phy_config_bb(dev, BaseBand_Config_AGC_TAB);
572
573 if (priv->IC_Cut > VERSION_8190_BD) {
574 if (priv->rf_type == RF_2T4R)
575 dwRegValue = (priv->AntennaTxPwDiff[2]<<8 |
576 priv->AntennaTxPwDiff[1]<<4 |
577 priv->AntennaTxPwDiff[0]);
578 else
579 dwRegValue = 0x0;
580 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
581 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
582
583
584 dwRegValue = priv->CrystalCap;
585 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, bXtalCap92x,
586 dwRegValue);
587 }
588
589 return rtStatus;
590 }
rtl92e_config_bb(struct net_device * dev)591 bool rtl92e_config_bb(struct net_device *dev)
592 {
593 _rtl92e_init_bb_rf_reg_def(dev);
594 return _rtl92e_bb_config_para_file(dev);
595 }
596
rtl92e_get_tx_power(struct net_device * dev)597 void rtl92e_get_tx_power(struct net_device *dev)
598 {
599 struct r8192_priv *priv = rtllib_priv(dev);
600
601 priv->MCSTxPowerLevelOriginalOffset[0] =
602 rtl92e_readl(dev, rTxAGC_Rate18_06);
603 priv->MCSTxPowerLevelOriginalOffset[1] =
604 rtl92e_readl(dev, rTxAGC_Rate54_24);
605 priv->MCSTxPowerLevelOriginalOffset[2] =
606 rtl92e_readl(dev, rTxAGC_Mcs03_Mcs00);
607 priv->MCSTxPowerLevelOriginalOffset[3] =
608 rtl92e_readl(dev, rTxAGC_Mcs07_Mcs04);
609 priv->MCSTxPowerLevelOriginalOffset[4] =
610 rtl92e_readl(dev, rTxAGC_Mcs11_Mcs08);
611 priv->MCSTxPowerLevelOriginalOffset[5] =
612 rtl92e_readl(dev, rTxAGC_Mcs15_Mcs12);
613
614 priv->DefaultInitialGain[0] = rtl92e_readb(dev, rOFDM0_XAAGCCore1);
615 priv->DefaultInitialGain[1] = rtl92e_readb(dev, rOFDM0_XBAGCCore1);
616 priv->DefaultInitialGain[2] = rtl92e_readb(dev, rOFDM0_XCAGCCore1);
617 priv->DefaultInitialGain[3] = rtl92e_readb(dev, rOFDM0_XDAGCCore1);
618 RT_TRACE(COMP_INIT,
619 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
620 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
621 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
622
623 priv->framesync = rtl92e_readb(dev, rOFDM0_RxDetector3);
624 priv->framesyncC34 = rtl92e_readl(dev, rOFDM0_RxDetector2);
625 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
626 rOFDM0_RxDetector3, priv->framesync);
627 priv->SifsTime = rtl92e_readw(dev, SIFS);
628 }
629
rtl92e_set_tx_power(struct net_device * dev,u8 channel)630 void rtl92e_set_tx_power(struct net_device *dev, u8 channel)
631 {
632 struct r8192_priv *priv = rtllib_priv(dev);
633 u8 powerlevel = 0, powerlevelOFDM24G = 0;
634 char ant_pwr_diff;
635 u32 u4RegValue;
636
637 if (priv->epromtype == EEPROM_93C46) {
638 powerlevel = priv->TxPowerLevelCCK[channel-1];
639 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
640 } else if (priv->epromtype == EEPROM_93C56) {
641 if (priv->rf_type == RF_1T2R) {
642 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
643 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
644 } else if (priv->rf_type == RF_2T4R) {
645 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
646 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
647
648 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
649 - priv->TxPowerLevelOFDM24G_A[channel-1];
650
651 priv->RF_C_TxPwDiff = ant_pwr_diff;
652
653 ant_pwr_diff &= 0xf;
654
655 priv->AntennaTxPwDiff[2] = 0;
656 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);
657 priv->AntennaTxPwDiff[0] = 0;
658
659 u4RegValue = (priv->AntennaTxPwDiff[2]<<8 |
660 priv->AntennaTxPwDiff[1]<<4 |
661 priv->AntennaTxPwDiff[0]);
662
663 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
664 (bXBTxAGC|bXCTxAGC|bXDTxAGC),
665 u4RegValue);
666 }
667 }
668 switch (priv->rf_chip) {
669 case RF_8225:
670 break;
671 case RF_8256:
672 rtl92e_set_cck_tx_power(dev, powerlevel);
673 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G);
674 break;
675 case RF_8258:
676 break;
677 default:
678 netdev_err(dev, "Invalid RF Chip ID.\n");
679 break;
680 }
681 }
682
rtl92e_config_phy(struct net_device * dev)683 bool rtl92e_config_phy(struct net_device *dev)
684 {
685 struct r8192_priv *priv = rtllib_priv(dev);
686 bool rtStatus = true;
687
688 switch (priv->rf_chip) {
689 case RF_8225:
690 break;
691 case RF_8256:
692 rtStatus = rtl92e_config_rf(dev);
693 break;
694
695 case RF_8258:
696 break;
697 case RF_PSEUDO_11N:
698 break;
699
700 default:
701 netdev_err(dev, "Invalid RF Chip ID.\n");
702 break;
703 }
704 return rtStatus;
705 }
706
rtl92e_config_rf_path(struct net_device * dev,enum rf90_radio_path eRFPath)707 u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath)
708 {
709
710 int i;
711
712 switch (eRFPath) {
713 case RF90_PATH_A:
714 for (i = 0; i < RadioA_ArrayLength; i += 2) {
715 if (Rtl819XRadioA_Array[i] == 0xfe) {
716 msleep(100);
717 continue;
718 }
719 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioA_Array[i],
720 bMask12Bits,
721 Rtl819XRadioA_Array[i+1]);
722
723 }
724 break;
725 case RF90_PATH_B:
726 for (i = 0; i < RadioB_ArrayLength; i += 2) {
727 if (Rtl819XRadioB_Array[i] == 0xfe) {
728 msleep(100);
729 continue;
730 }
731 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioB_Array[i],
732 bMask12Bits,
733 Rtl819XRadioB_Array[i+1]);
734
735 }
736 break;
737 case RF90_PATH_C:
738 for (i = 0; i < RadioC_ArrayLength; i += 2) {
739 if (Rtl819XRadioC_Array[i] == 0xfe) {
740 msleep(100);
741 continue;
742 }
743 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioC_Array[i],
744 bMask12Bits,
745 Rtl819XRadioC_Array[i+1]);
746
747 }
748 break;
749 case RF90_PATH_D:
750 for (i = 0; i < RadioD_ArrayLength; i += 2) {
751 if (Rtl819XRadioD_Array[i] == 0xfe) {
752 msleep(100);
753 continue;
754 }
755 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioD_Array[i],
756 bMask12Bits,
757 Rtl819XRadioD_Array[i+1]);
758
759 }
760 break;
761 default:
762 break;
763 }
764
765 return 0;
766
767 }
768
_rtl92e_set_tx_power_level(struct net_device * dev,u8 channel)769 static void _rtl92e_set_tx_power_level(struct net_device *dev, u8 channel)
770 {
771 struct r8192_priv *priv = rtllib_priv(dev);
772 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
773 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
774
775 switch (priv->rf_chip) {
776 case RF_8225:
777 break;
778
779 case RF_8256:
780 rtl92e_set_cck_tx_power(dev, powerlevel);
781 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G);
782 break;
783
784 case RF_8258:
785 break;
786 default:
787 netdev_warn(dev, "%s(): Invalid RF Chip ID\n", __func__);
788 break;
789 }
790 }
791
_rtl92e_phy_set_sw_chnl_cmd_array(struct net_device * dev,struct sw_chnl_cmd * CmdTable,u32 CmdTableIdx,u32 CmdTableSz,enum sw_chnl_cmd_id CmdID,u32 Para1,u32 Para2,u32 msDelay)792 static u8 _rtl92e_phy_set_sw_chnl_cmd_array(struct net_device *dev,
793 struct sw_chnl_cmd *CmdTable,
794 u32 CmdTableIdx, u32 CmdTableSz,
795 enum sw_chnl_cmd_id CmdID,
796 u32 Para1, u32 Para2, u32 msDelay)
797 {
798 struct sw_chnl_cmd *pCmd;
799
800 if (CmdTable == NULL) {
801 netdev_err(dev, "%s(): CmdTable cannot be NULL.\n", __func__);
802 return false;
803 }
804 if (CmdTableIdx >= CmdTableSz) {
805 netdev_err(dev, "%s(): Invalid index requested.\n", __func__);
806 return false;
807 }
808
809 pCmd = CmdTable + CmdTableIdx;
810 pCmd->CmdID = CmdID;
811 pCmd->Para1 = Para1;
812 pCmd->Para2 = Para2;
813 pCmd->msDelay = msDelay;
814
815 return true;
816 }
817
_rtl92e_phy_switch_channel_step(struct net_device * dev,u8 channel,u8 * stage,u8 * step,u32 * delay)818 static u8 _rtl92e_phy_switch_channel_step(struct net_device *dev, u8 channel,
819 u8 *stage, u8 *step, u32 *delay)
820 {
821 struct r8192_priv *priv = rtllib_priv(dev);
822 struct rtllib_device *ieee = priv->rtllib;
823 u32 PreCommonCmdCnt;
824 u32 PostCommonCmdCnt;
825 u32 RfDependCmdCnt;
826 struct sw_chnl_cmd *CurrentCmd = NULL;
827 u8 eRFPath;
828
829 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n",
830 __func__, *stage, *step, channel);
831
832 if (!rtllib_legal_channel(priv->rtllib, channel)) {
833 netdev_err(dev, "Invalid channel requested: %d\n", channel);
834 return true;
835 }
836
837 {
838 PreCommonCmdCnt = 0;
839 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd,
840 PreCommonCmdCnt++,
841 MAX_PRECMD_CNT,
842 CmdID_SetTxPowerLevel,
843 0, 0, 0);
844 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd,
845 PreCommonCmdCnt++,
846 MAX_PRECMD_CNT, CmdID_End,
847 0, 0, 0);
848
849 PostCommonCmdCnt = 0;
850
851 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PostCommonCmd,
852 PostCommonCmdCnt++,
853 MAX_POSTCMD_CNT, CmdID_End,
854 0, 0, 0);
855
856 RfDependCmdCnt = 0;
857 switch (priv->rf_chip) {
858 case RF_8225:
859 if (!(channel >= 1 && channel <= 14)) {
860 netdev_err(dev,
861 "Invalid channel requested for 8225: %d\n",
862 channel);
863 return false;
864 }
865 _rtl92e_phy_set_sw_chnl_cmd_array(dev,
866 ieee->RfDependCmd,
867 RfDependCmdCnt++,
868 MAX_RFDEPENDCMD_CNT,
869 CmdID_RF_WriteReg,
870 rZebra1_Channel,
871 RF_CHANNEL_TABLE_ZEBRA[channel],
872 10);
873 _rtl92e_phy_set_sw_chnl_cmd_array(dev,
874 ieee->RfDependCmd,
875 RfDependCmdCnt++,
876 MAX_RFDEPENDCMD_CNT,
877 CmdID_End, 0, 0, 0);
878 break;
879
880 case RF_8256:
881 if (!(channel >= 1 && channel <= 14)) {
882 netdev_err(dev,
883 "Invalid channel requested for 8256: %d\n",
884 channel);
885 return false;
886 }
887 _rtl92e_phy_set_sw_chnl_cmd_array(dev,
888 ieee->RfDependCmd,
889 RfDependCmdCnt++,
890 MAX_RFDEPENDCMD_CNT,
891 CmdID_RF_WriteReg,
892 rZebra1_Channel,
893 channel, 10);
894 _rtl92e_phy_set_sw_chnl_cmd_array(dev,
895 ieee->RfDependCmd,
896 RfDependCmdCnt++,
897 MAX_RFDEPENDCMD_CNT,
898 CmdID_End, 0, 0, 0);
899 break;
900
901 case RF_8258:
902 break;
903
904 default:
905 netdev_warn(dev, "Unknown RF Chip ID\n");
906 return false;
907 }
908
909
910 do {
911 switch (*stage) {
912 case 0:
913 CurrentCmd = &ieee->PreCommonCmd[*step];
914 break;
915 case 1:
916 CurrentCmd = &ieee->RfDependCmd[*step];
917 break;
918 case 2:
919 CurrentCmd = &ieee->PostCommonCmd[*step];
920 break;
921 }
922
923 if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) {
924 if ((*stage) == 2)
925 return true;
926 (*stage)++;
927 (*step) = 0;
928 continue;
929 }
930
931 if (!CurrentCmd)
932 continue;
933 switch (CurrentCmd->CmdID) {
934 case CmdID_SetTxPowerLevel:
935 if (priv->IC_Cut > (u8)VERSION_8190_BD)
936 _rtl92e_set_tx_power_level(dev,
937 channel);
938 break;
939 case CmdID_WritePortUlong:
940 rtl92e_writel(dev, CurrentCmd->Para1,
941 CurrentCmd->Para2);
942 break;
943 case CmdID_WritePortUshort:
944 rtl92e_writew(dev, CurrentCmd->Para1,
945 (u16)CurrentCmd->Para2);
946 break;
947 case CmdID_WritePortUchar:
948 rtl92e_writeb(dev, CurrentCmd->Para1,
949 (u8)CurrentCmd->Para2);
950 break;
951 case CmdID_RF_WriteReg:
952 for (eRFPath = 0; eRFPath <
953 priv->NumTotalRFPath; eRFPath++)
954 rtl92e_set_rf_reg(dev,
955 (enum rf90_radio_path)eRFPath,
956 CurrentCmd->Para1, bMask12Bits,
957 CurrentCmd->Para2<<7);
958 break;
959 default:
960 break;
961 }
962
963 break;
964 } while (true);
965 } /*for (Number of RF paths)*/
966
967 (*delay) = CurrentCmd->msDelay;
968 (*step)++;
969 return false;
970 }
971
_rtl92e_phy_switch_channel(struct net_device * dev,u8 channel)972 static void _rtl92e_phy_switch_channel(struct net_device *dev, u8 channel)
973 {
974 struct r8192_priv *priv = rtllib_priv(dev);
975 u32 delay = 0;
976
977 while (!_rtl92e_phy_switch_channel_step(dev, channel,
978 &priv->SwChnlStage,
979 &priv->SwChnlStep, &delay)) {
980 if (delay > 0)
981 msleep(delay);
982 if (!priv->up)
983 break;
984 }
985 }
986
_rtl92e_phy_switch_channel_work_item(struct net_device * dev)987 static void _rtl92e_phy_switch_channel_work_item(struct net_device *dev)
988 {
989
990 struct r8192_priv *priv = rtllib_priv(dev);
991
992 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
993
994 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__,
995 priv->chan, priv);
996
997 _rtl92e_phy_switch_channel(dev, priv->chan);
998
999 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
1000 }
1001
rtl92e_set_channel(struct net_device * dev,u8 channel)1002 u8 rtl92e_set_channel(struct net_device *dev, u8 channel)
1003 {
1004 struct r8192_priv *priv = rtllib_priv(dev);
1005
1006 RT_TRACE(COMP_PHY, "=====>%s()\n", __func__);
1007 if (!priv->up) {
1008 netdev_err(dev, "%s(): Driver is not initialized\n", __func__);
1009 return false;
1010 }
1011 if (priv->SwChnlInProgress)
1012 return false;
1013
1014
1015 switch (priv->rtllib->mode) {
1016 case WIRELESS_MODE_A:
1017 case WIRELESS_MODE_N_5G:
1018 if (channel <= 14) {
1019 netdev_warn(dev,
1020 "Channel %d not available in 802.11a.\n",
1021 channel);
1022 return false;
1023 }
1024 break;
1025 case WIRELESS_MODE_B:
1026 if (channel > 14) {
1027 netdev_warn(dev,
1028 "Channel %d not available in 802.11b.\n",
1029 channel);
1030 return false;
1031 }
1032 break;
1033 case WIRELESS_MODE_G:
1034 case WIRELESS_MODE_N_24G:
1035 if (channel > 14) {
1036 netdev_warn(dev,
1037 "Channel %d not available in 802.11g.\n",
1038 channel);
1039 return false;
1040 }
1041 break;
1042 }
1043
1044 priv->SwChnlInProgress = true;
1045 if (channel == 0)
1046 channel = 1;
1047
1048 priv->chan = channel;
1049
1050 priv->SwChnlStage = 0;
1051 priv->SwChnlStep = 0;
1052
1053 if (priv->up)
1054 _rtl92e_phy_switch_channel_work_item(dev);
1055 priv->SwChnlInProgress = false;
1056 return true;
1057 }
1058
_rtl92e_cck_tx_power_track_bw_switch_tssi(struct net_device * dev)1059 static void _rtl92e_cck_tx_power_track_bw_switch_tssi(struct net_device *dev)
1060 {
1061 struct r8192_priv *priv = rtllib_priv(dev);
1062
1063 switch (priv->CurrentChannelBW) {
1064 case HT_CHANNEL_WIDTH_20:
1065 priv->CCKPresentAttentuation =
1066 priv->CCKPresentAttentuation_20Mdefault +
1067 priv->CCKPresentAttentuation_difference;
1068
1069 if (priv->CCKPresentAttentuation >
1070 (CCKTxBBGainTableLength-1))
1071 priv->CCKPresentAttentuation =
1072 CCKTxBBGainTableLength-1;
1073 if (priv->CCKPresentAttentuation < 0)
1074 priv->CCKPresentAttentuation = 0;
1075
1076 RT_TRACE(COMP_POWER_TRACKING,
1077 "20M, priv->CCKPresentAttentuation = %d\n",
1078 priv->CCKPresentAttentuation);
1079
1080 if (priv->rtllib->current_network.channel == 14 &&
1081 !priv->bcck_in_ch14) {
1082 priv->bcck_in_ch14 = true;
1083 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1084 } else if (priv->rtllib->current_network.channel !=
1085 14 && priv->bcck_in_ch14) {
1086 priv->bcck_in_ch14 = false;
1087 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1088 } else {
1089 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1090 }
1091 break;
1092
1093 case HT_CHANNEL_WIDTH_20_40:
1094 priv->CCKPresentAttentuation =
1095 priv->CCKPresentAttentuation_40Mdefault +
1096 priv->CCKPresentAttentuation_difference;
1097
1098 RT_TRACE(COMP_POWER_TRACKING,
1099 "40M, priv->CCKPresentAttentuation = %d\n",
1100 priv->CCKPresentAttentuation);
1101 if (priv->CCKPresentAttentuation >
1102 (CCKTxBBGainTableLength - 1))
1103 priv->CCKPresentAttentuation =
1104 CCKTxBBGainTableLength-1;
1105 if (priv->CCKPresentAttentuation < 0)
1106 priv->CCKPresentAttentuation = 0;
1107
1108 if (priv->rtllib->current_network.channel == 14 &&
1109 !priv->bcck_in_ch14) {
1110 priv->bcck_in_ch14 = true;
1111 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1112 } else if (priv->rtllib->current_network.channel != 14
1113 && priv->bcck_in_ch14) {
1114 priv->bcck_in_ch14 = false;
1115 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1116 } else {
1117 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1118 }
1119 break;
1120 }
1121 }
1122
_rtl92e_cck_tx_power_track_bw_switch_thermal(struct net_device * dev)1123 static void _rtl92e_cck_tx_power_track_bw_switch_thermal(struct net_device *dev)
1124 {
1125 struct r8192_priv *priv = rtllib_priv(dev);
1126
1127 if (priv->rtllib->current_network.channel == 14 &&
1128 !priv->bcck_in_ch14)
1129 priv->bcck_in_ch14 = true;
1130 else if (priv->rtllib->current_network.channel != 14 &&
1131 priv->bcck_in_ch14)
1132 priv->bcck_in_ch14 = false;
1133
1134 switch (priv->CurrentChannelBW) {
1135 case HT_CHANNEL_WIDTH_20:
1136 if (priv->Record_CCK_20Mindex == 0)
1137 priv->Record_CCK_20Mindex = 6;
1138 priv->CCK_index = priv->Record_CCK_20Mindex;
1139 RT_TRACE(COMP_POWER_TRACKING,
1140 "20MHz, _rtl92e_cck_tx_power_track_bw_switch_thermal(),CCK_index = %d\n",
1141 priv->CCK_index);
1142 break;
1143
1144 case HT_CHANNEL_WIDTH_20_40:
1145 priv->CCK_index = priv->Record_CCK_40Mindex;
1146 RT_TRACE(COMP_POWER_TRACKING,
1147 "40MHz, _rtl92e_cck_tx_power_track_bw_switch_thermal(), CCK_index = %d\n",
1148 priv->CCK_index);
1149 break;
1150 }
1151 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1152 }
1153
_rtl92e_cck_tx_power_track_bw_switch(struct net_device * dev)1154 static void _rtl92e_cck_tx_power_track_bw_switch(struct net_device *dev)
1155 {
1156 struct r8192_priv *priv = rtllib_priv(dev);
1157
1158 if (priv->IC_Cut >= IC_VersionCut_D)
1159 _rtl92e_cck_tx_power_track_bw_switch_tssi(dev);
1160 else
1161 _rtl92e_cck_tx_power_track_bw_switch_thermal(dev);
1162 }
1163
_rtl92e_set_bw_mode_work_item(struct net_device * dev)1164 static void _rtl92e_set_bw_mode_work_item(struct net_device *dev)
1165 {
1166
1167 struct r8192_priv *priv = rtllib_priv(dev);
1168 u8 regBwOpMode;
1169
1170 RT_TRACE(COMP_SWBW,
1171 "==>_rtl92e_set_bw_mode_work_item() Switch to %s bandwidth\n",
1172 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ?
1173 "20MHz" : "40MHz");
1174
1175
1176 if (priv->rf_chip == RF_PSEUDO_11N) {
1177 priv->SetBWModeInProgress = false;
1178 return;
1179 }
1180 if (!priv->up) {
1181 netdev_err(dev, "%s(): Driver is not initialized\n", __func__);
1182 return;
1183 }
1184 regBwOpMode = rtl92e_readb(dev, BW_OPMODE);
1185
1186 switch (priv->CurrentChannelBW) {
1187 case HT_CHANNEL_WIDTH_20:
1188 regBwOpMode |= BW_OPMODE_20MHZ;
1189 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
1190 break;
1191
1192 case HT_CHANNEL_WIDTH_20_40:
1193 regBwOpMode &= ~BW_OPMODE_20MHZ;
1194 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
1195 break;
1196
1197 default:
1198 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__,
1199 priv->CurrentChannelBW);
1200 break;
1201 }
1202
1203 switch (priv->CurrentChannelBW) {
1204 case HT_CHANNEL_WIDTH_20:
1205 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1206 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1207
1208 if (!priv->btxpower_tracking) {
1209 rtl92e_writel(dev, rCCK0_TxFilter1, 0x1a1b0000);
1210 rtl92e_writel(dev, rCCK0_TxFilter2, 0x090e1317);
1211 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000204);
1212 } else {
1213 _rtl92e_cck_tx_power_track_bw_switch(dev);
1214 }
1215
1216 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1217
1218 break;
1219 case HT_CHANNEL_WIDTH_20_40:
1220 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1221 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1222
1223 if (!priv->btxpower_tracking) {
1224 rtl92e_writel(dev, rCCK0_TxFilter1, 0x35360000);
1225 rtl92e_writel(dev, rCCK0_TxFilter2, 0x121c252e);
1226 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000409);
1227 } else {
1228 _rtl92e_cck_tx_power_track_bw_switch(dev);
1229 }
1230
1231 rtl92e_set_bb_reg(dev, rCCK0_System, bCCKSideBand,
1232 (priv->nCur40MhzPrimeSC>>1));
1233 rtl92e_set_bb_reg(dev, rOFDM1_LSTF, 0xC00,
1234 priv->nCur40MhzPrimeSC);
1235
1236 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1237 break;
1238 default:
1239 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__,
1240 priv->CurrentChannelBW);
1241 break;
1242
1243 }
1244
1245 switch (priv->rf_chip) {
1246 case RF_8225:
1247 break;
1248
1249 case RF_8256:
1250 rtl92e_set_bandwidth(dev, priv->CurrentChannelBW);
1251 break;
1252
1253 case RF_8258:
1254 break;
1255
1256 case RF_PSEUDO_11N:
1257 break;
1258
1259 default:
1260 netdev_info(dev, "%s(): Unknown RFChipID: %d\n", __func__,
1261 priv->rf_chip);
1262 break;
1263 }
1264
1265 atomic_dec(&(priv->rtllib->atm_swbw));
1266 priv->SetBWModeInProgress = false;
1267
1268 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
1269 }
1270
rtl92e_set_bw_mode(struct net_device * dev,enum ht_channel_width Bandwidth,enum ht_extchnl_offset Offset)1271 void rtl92e_set_bw_mode(struct net_device *dev, enum ht_channel_width Bandwidth,
1272 enum ht_extchnl_offset Offset)
1273 {
1274 struct r8192_priv *priv = rtllib_priv(dev);
1275
1276
1277 if (priv->SetBWModeInProgress)
1278 return;
1279
1280 atomic_inc(&(priv->rtllib->atm_swbw));
1281 priv->SetBWModeInProgress = true;
1282
1283 priv->CurrentChannelBW = Bandwidth;
1284
1285 if (Offset == HT_EXTCHNL_OFFSET_LOWER)
1286 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1287 else if (Offset == HT_EXTCHNL_OFFSET_UPPER)
1288 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1289 else
1290 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1291
1292 _rtl92e_set_bw_mode_work_item(dev);
1293
1294 }
1295
rtl92e_init_gain(struct net_device * dev,u8 Operation)1296 void rtl92e_init_gain(struct net_device *dev, u8 Operation)
1297 {
1298 #define SCAN_RX_INITIAL_GAIN 0x17
1299 #define POWER_DETECTION_TH 0x08
1300 struct r8192_priv *priv = rtllib_priv(dev);
1301 u32 BitMask;
1302 u8 initial_gain;
1303
1304 if (priv->up) {
1305 switch (Operation) {
1306 case IG_Backup:
1307 RT_TRACE(COMP_SCAN,
1308 "IG_Backup, backup the initial gain.\n");
1309 initial_gain = SCAN_RX_INITIAL_GAIN;
1310 BitMask = bMaskByte0;
1311 if (dm_digtable.dig_algorithm ==
1312 DIG_ALGO_BY_FALSE_ALARM)
1313 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
1314 priv->initgain_backup.xaagccore1 =
1315 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1,
1316 BitMask);
1317 priv->initgain_backup.xbagccore1 =
1318 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XBAGCCore1,
1319 BitMask);
1320 priv->initgain_backup.xcagccore1 =
1321 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XCAGCCore1,
1322 BitMask);
1323 priv->initgain_backup.xdagccore1 =
1324 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XDAGCCore1,
1325 BitMask);
1326 BitMask = bMaskByte2;
1327 priv->initgain_backup.cca = (u8)rtl92e_get_bb_reg(dev,
1328 rCCK0_CCA, BitMask);
1329
1330 RT_TRACE(COMP_SCAN,
1331 "Scan InitialGainBackup 0xc50 is %x\n",
1332 priv->initgain_backup.xaagccore1);
1333 RT_TRACE(COMP_SCAN,
1334 "Scan InitialGainBackup 0xc58 is %x\n",
1335 priv->initgain_backup.xbagccore1);
1336 RT_TRACE(COMP_SCAN,
1337 "Scan InitialGainBackup 0xc60 is %x\n",
1338 priv->initgain_backup.xcagccore1);
1339 RT_TRACE(COMP_SCAN,
1340 "Scan InitialGainBackup 0xc68 is %x\n",
1341 priv->initgain_backup.xdagccore1);
1342 RT_TRACE(COMP_SCAN,
1343 "Scan InitialGainBackup 0xa0a is %x\n",
1344 priv->initgain_backup.cca);
1345
1346 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1347 initial_gain);
1348 rtl92e_writeb(dev, rOFDM0_XAAGCCore1, initial_gain);
1349 rtl92e_writeb(dev, rOFDM0_XBAGCCore1, initial_gain);
1350 rtl92e_writeb(dev, rOFDM0_XCAGCCore1, initial_gain);
1351 rtl92e_writeb(dev, rOFDM0_XDAGCCore1, initial_gain);
1352 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1353 POWER_DETECTION_TH);
1354 rtl92e_writeb(dev, 0xa0a, POWER_DETECTION_TH);
1355 break;
1356 case IG_Restore:
1357 RT_TRACE(COMP_SCAN,
1358 "IG_Restore, restore the initial gain.\n");
1359 BitMask = 0x7f;
1360 if (dm_digtable.dig_algorithm ==
1361 DIG_ALGO_BY_FALSE_ALARM)
1362 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
1363
1364 rtl92e_set_bb_reg(dev, rOFDM0_XAAGCCore1, BitMask,
1365 (u32)priv->initgain_backup.xaagccore1);
1366 rtl92e_set_bb_reg(dev, rOFDM0_XBAGCCore1, BitMask,
1367 (u32)priv->initgain_backup.xbagccore1);
1368 rtl92e_set_bb_reg(dev, rOFDM0_XCAGCCore1, BitMask,
1369 (u32)priv->initgain_backup.xcagccore1);
1370 rtl92e_set_bb_reg(dev, rOFDM0_XDAGCCore1, BitMask,
1371 (u32)priv->initgain_backup.xdagccore1);
1372 BitMask = bMaskByte2;
1373 rtl92e_set_bb_reg(dev, rCCK0_CCA, BitMask,
1374 (u32)priv->initgain_backup.cca);
1375
1376 RT_TRACE(COMP_SCAN,
1377 "Scan BBInitialGainRestore 0xc50 is %x\n",
1378 priv->initgain_backup.xaagccore1);
1379 RT_TRACE(COMP_SCAN,
1380 "Scan BBInitialGainRestore 0xc58 is %x\n",
1381 priv->initgain_backup.xbagccore1);
1382 RT_TRACE(COMP_SCAN,
1383 "Scan BBInitialGainRestore 0xc60 is %x\n",
1384 priv->initgain_backup.xcagccore1);
1385 RT_TRACE(COMP_SCAN,
1386 "Scan BBInitialGainRestore 0xc68 is %x\n",
1387 priv->initgain_backup.xdagccore1);
1388 RT_TRACE(COMP_SCAN,
1389 "Scan BBInitialGainRestore 0xa0a is %x\n",
1390 priv->initgain_backup.cca);
1391
1392 rtl92e_set_tx_power(dev,
1393 priv->rtllib->current_network.channel);
1394
1395 if (dm_digtable.dig_algorithm ==
1396 DIG_ALGO_BY_FALSE_ALARM)
1397 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1);
1398 break;
1399 default:
1400 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
1401 break;
1402 }
1403 }
1404 }
1405
rtl92e_set_rf_off(struct net_device * dev)1406 void rtl92e_set_rf_off(struct net_device *dev)
1407 {
1408
1409 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
1410 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);
1411 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);
1412 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1413 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1414 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
1415 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
1416 rtl92e_writeb(dev, ANAPAR_FOR_8192PciE, 0x07);
1417
1418 }
1419
_rtl92e_set_rf_power_state(struct net_device * dev,enum rt_rf_power_state eRFPowerState)1420 static bool _rtl92e_set_rf_power_state(struct net_device *dev,
1421 enum rt_rf_power_state eRFPowerState)
1422 {
1423 struct r8192_priv *priv = rtllib_priv(dev);
1424 struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)
1425 (&(priv->rtllib->PowerSaveControl));
1426 bool bResult = true;
1427 u8 i = 0, QueueID = 0;
1428 struct rtl8192_tx_ring *ring = NULL;
1429
1430 if (priv->SetRFPowerStateInProgress)
1431 return false;
1432 RT_TRACE(COMP_PS, "===========> _rtl92e_set_rf_power_state()!\n");
1433 priv->SetRFPowerStateInProgress = true;
1434
1435 switch (priv->rf_chip) {
1436 case RF_8256:
1437 switch (eRFPowerState) {
1438 case eRfOn:
1439 RT_TRACE(COMP_PS,
1440 "_rtl92e_set_rf_power_state() eRfOn!\n");
1441 if ((priv->rtllib->eRFPowerState == eRfOff) &&
1442 RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1443 bool rtstatus = true;
1444 u32 InitilizeCount = 3;
1445
1446 do {
1447 InitilizeCount--;
1448 priv->RegRfOff = false;
1449 rtstatus = rtl92e_enable_nic(dev);
1450 } while (!rtstatus && (InitilizeCount > 0));
1451
1452 if (!rtstatus) {
1453 netdev_err(dev,
1454 "%s(): Failed to initialize Adapter.\n",
1455 __func__);
1456 priv->SetRFPowerStateInProgress = false;
1457 return false;
1458 }
1459
1460 RT_CLEAR_PS_LEVEL(pPSC,
1461 RT_RF_OFF_LEVL_HALT_NIC);
1462 } else {
1463 rtl92e_writeb(dev, ANAPAR, 0x37);
1464 mdelay(1);
1465 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1466 0x4, 0x1);
1467 priv->bHwRfOffAction = 0;
1468
1469 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE,
1470 BIT4, 0x1);
1471 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4,
1472 0x300, 0x3);
1473 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1474 0x18, 0x3);
1475 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable,
1476 0x3, 0x3);
1477 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable,
1478 0x3, 0x3);
1479 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1480 0x60, 0x3);
1481
1482 }
1483
1484 break;
1485
1486 case eRfSleep:
1487 if (priv->rtllib->eRFPowerState == eRfOff)
1488 break;
1489
1490
1491 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1492 ring = &priv->tx_ring[QueueID];
1493
1494 if (skb_queue_len(&ring->queue) == 0) {
1495 QueueID++;
1496 continue;
1497 } else {
1498 RT_TRACE((COMP_POWER|COMP_RF),
1499 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n",
1500 (i+1), QueueID);
1501 udelay(10);
1502 i++;
1503 }
1504
1505 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1506 RT_TRACE(COMP_POWER,
1507 "\n\n\n TimeOut!! _rtl92e_set_rf_power_state(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n",
1508 MAX_DOZE_WAITING_TIMES_9x,
1509 QueueID);
1510 break;
1511 }
1512 }
1513 rtl92e_set_rf_off(dev);
1514 break;
1515
1516 case eRfOff:
1517 RT_TRACE(COMP_PS,
1518 "_rtl92e_set_rf_power_state() eRfOff/Sleep !\n");
1519
1520 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1521 ring = &priv->tx_ring[QueueID];
1522
1523 if (skb_queue_len(&ring->queue) == 0) {
1524 QueueID++;
1525 continue;
1526 } else {
1527 RT_TRACE(COMP_POWER,
1528 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n",
1529 (i+1), QueueID);
1530 udelay(10);
1531 i++;
1532 }
1533
1534 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1535 RT_TRACE(COMP_POWER,
1536 "\n\n\n SetZebra: RFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n",
1537 MAX_DOZE_WAITING_TIMES_9x,
1538 QueueID);
1539 break;
1540 }
1541 }
1542
1543 if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC &&
1544 !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1545 rtl92e_disable_nic(dev);
1546 RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1547 } else if (!(pPSC->RegRfPsLevel &
1548 RT_RF_OFF_LEVL_HALT_NIC)) {
1549 rtl92e_set_rf_off(dev);
1550 }
1551
1552 break;
1553
1554 default:
1555 bResult = false;
1556 netdev_warn(dev,
1557 "%s(): Unknown state requested: 0x%X.\n",
1558 __func__, eRFPowerState);
1559 break;
1560 }
1561
1562 break;
1563
1564 default:
1565 netdev_warn(dev, "%s(): Unknown RF type\n", __func__);
1566 break;
1567 }
1568
1569 if (bResult) {
1570 priv->rtllib->eRFPowerState = eRFPowerState;
1571
1572 switch (priv->rf_chip) {
1573 case RF_8256:
1574 break;
1575
1576 default:
1577 netdev_warn(dev, "%s(): Unknown RF type\n", __func__);
1578 break;
1579 }
1580 }
1581
1582 priv->SetRFPowerStateInProgress = false;
1583 RT_TRACE(COMP_PS,
1584 "<=========== _rtl92e_set_rf_power_state() bResult = %d!\n",
1585 bResult);
1586 return bResult;
1587 }
1588
rtl92e_set_rf_power_state(struct net_device * dev,enum rt_rf_power_state eRFPowerState)1589 bool rtl92e_set_rf_power_state(struct net_device *dev,
1590 enum rt_rf_power_state eRFPowerState)
1591 {
1592 struct r8192_priv *priv = rtllib_priv(dev);
1593
1594 bool bResult = false;
1595
1596 RT_TRACE(COMP_PS,
1597 "---------> rtl92e_set_rf_power_state(): eRFPowerState(%d)\n",
1598 eRFPowerState);
1599 if (eRFPowerState == priv->rtllib->eRFPowerState &&
1600 priv->bHwRfOffAction == 0) {
1601 RT_TRACE(COMP_PS,
1602 "<--------- rtl92e_set_rf_power_state(): discard the request for eRFPowerState(%d) is the same.\n",
1603 eRFPowerState);
1604 return bResult;
1605 }
1606
1607 bResult = _rtl92e_set_rf_power_state(dev, eRFPowerState);
1608
1609 RT_TRACE(COMP_PS,
1610 "<--------- rtl92e_set_rf_power_state(): bResult(%d)\n",
1611 bResult);
1612
1613 return bResult;
1614 }
1615
rtl92e_scan_op_backup(struct net_device * dev,u8 Operation)1616 void rtl92e_scan_op_backup(struct net_device *dev, u8 Operation)
1617 {
1618 struct r8192_priv *priv = rtllib_priv(dev);
1619
1620 if (priv->up) {
1621 switch (Operation) {
1622 case SCAN_OPT_BACKUP:
1623 priv->rtllib->InitialGainHandler(dev, IG_Backup);
1624 break;
1625
1626 case SCAN_OPT_RESTORE:
1627 priv->rtllib->InitialGainHandler(dev, IG_Restore);
1628 break;
1629
1630 default:
1631 RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n");
1632 break;
1633 }
1634 }
1635
1636 }
1637