1 /*
2 * TI Palmas
3 *
4 * Copyright 2011-2013 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Ian Lartey <ian@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16 #ifndef __LINUX_MFD_PALMAS_H
17 #define __LINUX_MFD_PALMAS_H
18
19 #include <linux/usb/otg.h>
20 #include <linux/leds.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/driver.h>
23 #include <linux/extcon.h>
24 #include <linux/of_gpio.h>
25 #include <linux/usb/phy_companion.h>
26
27 #define PALMAS_NUM_CLIENTS 3
28
29 /* The ID_REVISION NUMBERS */
30 #define PALMAS_CHIP_OLD_ID 0x0000
31 #define PALMAS_CHIP_ID 0xC035
32 #define PALMAS_CHIP_CHARGER_ID 0xC036
33
34 #define TPS65917_RESERVED -1
35
36 #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
37 ((a) == PALMAS_CHIP_ID))
38 #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
39
40 /**
41 * Palmas PMIC feature types
42 *
43 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
44 * regulator.
45 *
46 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
47 * specific feature (above) or not. Return non-zero, if yes.
48 */
49 #define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
50 #define PALMAS_PMIC_HAS(b, f) \
51 ((b)->features & PALMAS_PMIC_FEATURE_ ## f)
52
53 struct palmas_pmic;
54 struct palmas_gpadc;
55 struct palmas_resource;
56 struct palmas_usb;
57 struct palmas_pmic_driver_data;
58 struct palmas_pmic_platform_data;
59
60 enum palmas_usb_state {
61 PALMAS_USB_STATE_DISCONNECT,
62 PALMAS_USB_STATE_VBUS,
63 PALMAS_USB_STATE_ID,
64 };
65
66 struct palmas {
67 struct device *dev;
68
69 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
70 struct regmap *regmap[PALMAS_NUM_CLIENTS];
71
72 /* Stored chip id */
73 int id;
74
75 unsigned int features;
76 /* IRQ Data */
77 int irq;
78 u32 irq_mask;
79 struct mutex irq_lock;
80 struct regmap_irq_chip_data *irq_data;
81
82 struct palmas_pmic_driver_data *pmic_ddata;
83
84 /* Child Devices */
85 struct palmas_pmic *pmic;
86 struct palmas_gpadc *gpadc;
87 struct palmas_resource *resource;
88 struct palmas_usb *usb;
89
90 /* GPIO MUXing */
91 u8 gpio_muxed;
92 u8 led_muxed;
93 u8 pwm_muxed;
94 };
95
96 #define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
97 PALMAS_EXT_CONTROL_ENABLE2 | \
98 PALMAS_EXT_CONTROL_NSLEEP)
99
100 struct palmas_sleep_requestor_info {
101 int id;
102 int reg_offset;
103 int bit_pos;
104 };
105
106 struct palmas_regs_info {
107 char *name;
108 char *sname;
109 u8 vsel_addr;
110 u8 ctrl_addr;
111 u8 tstep_addr;
112 int sleep_id;
113 };
114
115 struct palmas_pmic_driver_data {
116 int smps_start;
117 int smps_end;
118 int ldo_begin;
119 int ldo_end;
120 int max_reg;
121 bool has_regen3;
122 struct palmas_regs_info *palmas_regs_info;
123 struct of_regulator_match *palmas_matches;
124 struct palmas_sleep_requestor_info *sleep_req_info;
125 int (*smps_register)(struct palmas_pmic *pmic,
126 struct palmas_pmic_driver_data *ddata,
127 struct palmas_pmic_platform_data *pdata,
128 const char *pdev_name,
129 struct regulator_config config);
130 int (*ldo_register)(struct palmas_pmic *pmic,
131 struct palmas_pmic_driver_data *ddata,
132 struct palmas_pmic_platform_data *pdata,
133 const char *pdev_name,
134 struct regulator_config config);
135 };
136
137 struct palmas_gpadc_platform_data {
138 /* Channel 3 current source is only enabled during conversion */
139 int ch3_current;
140
141 /* Channel 0 current source can be used for battery detection.
142 * If used for battery detection this will cause a permanent current
143 * consumption depending on current level set here.
144 */
145 int ch0_current;
146
147 /* default BAT_REMOVAL_DAT setting on device probe */
148 int bat_removal;
149
150 /* Sets the START_POLARITY bit in the RT_CTRL register */
151 int start_polarity;
152 };
153
154 struct palmas_reg_init {
155 /* warm_rest controls the voltage levels after a warm reset
156 *
157 * 0: reload default values from OTP on warm reset
158 * 1: maintain voltage from VSEL on warm reset
159 */
160 int warm_reset;
161
162 /* roof_floor controls whether the regulator uses the i2c style
163 * of DVS or uses the method where a GPIO or other control method is
164 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
165 *
166 * For SMPS
167 *
168 * 0: i2c selection of voltage
169 * 1: pin selection of voltage.
170 *
171 * For LDO unused
172 */
173 int roof_floor;
174
175 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
176 * the data sheet.
177 *
178 * For SMPS
179 *
180 * 0: Off
181 * 1: AUTO
182 * 2: ECO
183 * 3: Forced PWM
184 *
185 * For LDO
186 *
187 * 0: Off
188 * 1: On
189 */
190 int mode_sleep;
191
192 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
193 * register. Set this is the default voltage set in OTP needs
194 * to be overridden.
195 */
196 u8 vsel;
197
198 };
199
200 enum palmas_regulators {
201 /* SMPS regulators */
202 PALMAS_REG_SMPS12,
203 PALMAS_REG_SMPS123,
204 PALMAS_REG_SMPS3,
205 PALMAS_REG_SMPS45,
206 PALMAS_REG_SMPS457,
207 PALMAS_REG_SMPS6,
208 PALMAS_REG_SMPS7,
209 PALMAS_REG_SMPS8,
210 PALMAS_REG_SMPS9,
211 PALMAS_REG_SMPS10_OUT2,
212 PALMAS_REG_SMPS10_OUT1,
213 /* LDO regulators */
214 PALMAS_REG_LDO1,
215 PALMAS_REG_LDO2,
216 PALMAS_REG_LDO3,
217 PALMAS_REG_LDO4,
218 PALMAS_REG_LDO5,
219 PALMAS_REG_LDO6,
220 PALMAS_REG_LDO7,
221 PALMAS_REG_LDO8,
222 PALMAS_REG_LDO9,
223 PALMAS_REG_LDOLN,
224 PALMAS_REG_LDOUSB,
225 /* External regulators */
226 PALMAS_REG_REGEN1,
227 PALMAS_REG_REGEN2,
228 PALMAS_REG_REGEN3,
229 PALMAS_REG_SYSEN1,
230 PALMAS_REG_SYSEN2,
231 /* Total number of regulators */
232 PALMAS_NUM_REGS,
233 };
234
235 enum tps65917_regulators {
236 /* SMPS regulators */
237 TPS65917_REG_SMPS1,
238 TPS65917_REG_SMPS2,
239 TPS65917_REG_SMPS3,
240 TPS65917_REG_SMPS4,
241 TPS65917_REG_SMPS5,
242 /* LDO regulators */
243 TPS65917_REG_LDO1,
244 TPS65917_REG_LDO2,
245 TPS65917_REG_LDO3,
246 TPS65917_REG_LDO4,
247 TPS65917_REG_LDO5,
248 TPS65917_REG_REGEN1,
249 TPS65917_REG_REGEN2,
250 TPS65917_REG_REGEN3,
251
252 /* Total number of regulators */
253 TPS65917_NUM_REGS,
254 };
255
256 /* External controll signal name */
257 enum {
258 PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
259 PALMAS_EXT_CONTROL_ENABLE2 = 0x2,
260 PALMAS_EXT_CONTROL_NSLEEP = 0x4,
261 };
262
263 /*
264 * Palmas device resources can be controlled externally for
265 * enabling/disabling it rather than register write through i2c.
266 * Add the external controlled requestor ID for different resources.
267 */
268 enum palmas_external_requestor_id {
269 PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
270 PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
271 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
272 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
273 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
274 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
275 PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
276 PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
277 PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
278 PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
279 PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
280 PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
281 PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
282 PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
283 PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
284 PALMAS_EXTERNAL_REQSTR_ID_LDO1,
285 PALMAS_EXTERNAL_REQSTR_ID_LDO2,
286 PALMAS_EXTERNAL_REQSTR_ID_LDO3,
287 PALMAS_EXTERNAL_REQSTR_ID_LDO4,
288 PALMAS_EXTERNAL_REQSTR_ID_LDO5,
289 PALMAS_EXTERNAL_REQSTR_ID_LDO6,
290 PALMAS_EXTERNAL_REQSTR_ID_LDO7,
291 PALMAS_EXTERNAL_REQSTR_ID_LDO8,
292 PALMAS_EXTERNAL_REQSTR_ID_LDO9,
293 PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
294 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
295
296 /* Last entry */
297 PALMAS_EXTERNAL_REQSTR_ID_MAX,
298 };
299
300 enum tps65917_external_requestor_id {
301 TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
302 TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
303 TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
304 TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
305 TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
306 TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
307 TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
308 TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
309 TPS65917_EXTERNAL_REQSTR_ID_LDO1,
310 TPS65917_EXTERNAL_REQSTR_ID_LDO2,
311 TPS65917_EXTERNAL_REQSTR_ID_LDO3,
312 TPS65917_EXTERNAL_REQSTR_ID_LDO4,
313 TPS65917_EXTERNAL_REQSTR_ID_LDO5,
314 /* Last entry */
315 TPS65917_EXTERNAL_REQSTR_ID_MAX,
316 };
317
318 struct palmas_pmic_platform_data {
319 /* An array of pointers to regulator init data indexed by regulator
320 * ID
321 */
322 struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
323
324 /* An array of pointers to structures containing sleep mode and DVS
325 * configuration for regulators indexed by ID
326 */
327 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
328
329 /* use LDO6 for vibrator control */
330 int ldo6_vibrator;
331
332 /* Enable tracking mode of LDO8 */
333 bool enable_ldo8_tracking;
334 };
335
336 struct palmas_usb_platform_data {
337 /* Do we enable the wakeup comparator on probe */
338 int wakeup;
339 };
340
341 struct palmas_resource_platform_data {
342 int regen1_mode_sleep;
343 int regen2_mode_sleep;
344 int sysen1_mode_sleep;
345 int sysen2_mode_sleep;
346
347 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
348 u8 nsleep_res;
349 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
350 u8 nsleep_smps;
351 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
352 u8 nsleep_ldo1;
353 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
354 u8 nsleep_ldo2;
355
356 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
357 u8 enable1_res;
358 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
359 u8 enable1_smps;
360 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
361 u8 enable1_ldo1;
362 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
363 u8 enable1_ldo2;
364
365 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
366 u8 enable2_res;
367 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
368 u8 enable2_smps;
369 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
370 u8 enable2_ldo1;
371 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
372 u8 enable2_ldo2;
373 };
374
375 struct palmas_clk_platform_data {
376 int clk32kg_mode_sleep;
377 int clk32kgaudio_mode_sleep;
378 };
379
380 struct palmas_platform_data {
381 int irq_flags;
382 int gpio_base;
383
384 /* bit value to be loaded to the POWER_CTRL register */
385 u8 power_ctrl;
386
387 /*
388 * boolean to select if we want to configure muxing here
389 * then the two value to load into the registers if true
390 */
391 int mux_from_pdata;
392 u8 pad1, pad2;
393 bool pm_off;
394
395 struct palmas_pmic_platform_data *pmic_pdata;
396 struct palmas_gpadc_platform_data *gpadc_pdata;
397 struct palmas_usb_platform_data *usb_pdata;
398 struct palmas_resource_platform_data *resource_pdata;
399 struct palmas_clk_platform_data *clk_pdata;
400 };
401
402 struct palmas_gpadc_calibration {
403 s32 gain;
404 s32 gain_error;
405 s32 offset_error;
406 };
407
408 struct palmas_gpadc {
409 struct device *dev;
410 struct palmas *palmas;
411
412 int ch3_current;
413 int ch0_current;
414
415 int gpadc_force;
416
417 int bat_removal;
418
419 struct mutex reading_lock;
420 struct completion irq_complete;
421
422 int eoc_sw_irq;
423
424 struct palmas_gpadc_calibration *palmas_cal_tbl;
425
426 int conv0_channel;
427 int conv1_channel;
428 int rt_channel;
429 };
430
431 struct palmas_gpadc_result {
432 s32 raw_code;
433 s32 corrected_code;
434 s32 result;
435 };
436
437 #define PALMAS_MAX_CHANNELS 16
438
439 /* Define the tps65917 IRQ numbers */
440 enum tps65917_irqs {
441 /* INT1 registers */
442 TPS65917_RESERVED1,
443 TPS65917_PWRON_IRQ,
444 TPS65917_LONG_PRESS_KEY_IRQ,
445 TPS65917_RESERVED2,
446 TPS65917_PWRDOWN_IRQ,
447 TPS65917_HOTDIE_IRQ,
448 TPS65917_VSYS_MON_IRQ,
449 TPS65917_RESERVED3,
450 /* INT2 registers */
451 TPS65917_RESERVED4,
452 TPS65917_OTP_ERROR_IRQ,
453 TPS65917_WDT_IRQ,
454 TPS65917_RESERVED5,
455 TPS65917_RESET_IN_IRQ,
456 TPS65917_FSD_IRQ,
457 TPS65917_SHORT_IRQ,
458 TPS65917_RESERVED6,
459 /* INT3 registers */
460 TPS65917_GPADC_AUTO_0_IRQ,
461 TPS65917_GPADC_AUTO_1_IRQ,
462 TPS65917_GPADC_EOC_SW_IRQ,
463 TPS65917_RESREVED6,
464 TPS65917_RESERVED7,
465 TPS65917_RESERVED8,
466 TPS65917_RESERVED9,
467 TPS65917_VBUS_IRQ,
468 /* INT4 registers */
469 TPS65917_GPIO_0_IRQ,
470 TPS65917_GPIO_1_IRQ,
471 TPS65917_GPIO_2_IRQ,
472 TPS65917_GPIO_3_IRQ,
473 TPS65917_GPIO_4_IRQ,
474 TPS65917_GPIO_5_IRQ,
475 TPS65917_GPIO_6_IRQ,
476 TPS65917_RESERVED10,
477 /* Total Number IRQs */
478 TPS65917_NUM_IRQ,
479 };
480
481 /* Define the palmas IRQ numbers */
482 enum palmas_irqs {
483 /* INT1 registers */
484 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
485 PALMAS_PWRON_IRQ,
486 PALMAS_LONG_PRESS_KEY_IRQ,
487 PALMAS_RPWRON_IRQ,
488 PALMAS_PWRDOWN_IRQ,
489 PALMAS_HOTDIE_IRQ,
490 PALMAS_VSYS_MON_IRQ,
491 PALMAS_VBAT_MON_IRQ,
492 /* INT2 registers */
493 PALMAS_RTC_ALARM_IRQ,
494 PALMAS_RTC_TIMER_IRQ,
495 PALMAS_WDT_IRQ,
496 PALMAS_BATREMOVAL_IRQ,
497 PALMAS_RESET_IN_IRQ,
498 PALMAS_FBI_BB_IRQ,
499 PALMAS_SHORT_IRQ,
500 PALMAS_VAC_ACOK_IRQ,
501 /* INT3 registers */
502 PALMAS_GPADC_AUTO_0_IRQ,
503 PALMAS_GPADC_AUTO_1_IRQ,
504 PALMAS_GPADC_EOC_SW_IRQ,
505 PALMAS_GPADC_EOC_RT_IRQ,
506 PALMAS_ID_OTG_IRQ,
507 PALMAS_ID_IRQ,
508 PALMAS_VBUS_OTG_IRQ,
509 PALMAS_VBUS_IRQ,
510 /* INT4 registers */
511 PALMAS_GPIO_0_IRQ,
512 PALMAS_GPIO_1_IRQ,
513 PALMAS_GPIO_2_IRQ,
514 PALMAS_GPIO_3_IRQ,
515 PALMAS_GPIO_4_IRQ,
516 PALMAS_GPIO_5_IRQ,
517 PALMAS_GPIO_6_IRQ,
518 PALMAS_GPIO_7_IRQ,
519 /* Total Number IRQs */
520 PALMAS_NUM_IRQ,
521 };
522
523 struct palmas_pmic {
524 struct palmas *palmas;
525 struct device *dev;
526 struct regulator_desc desc[PALMAS_NUM_REGS];
527 struct regulator_dev *rdev[PALMAS_NUM_REGS];
528 struct mutex mutex;
529
530 int smps123;
531 int smps457;
532 int smps12;
533
534 int range[PALMAS_REG_SMPS10_OUT1];
535 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
536 unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1];
537 };
538
539 struct palmas_resource {
540 struct palmas *palmas;
541 struct device *dev;
542 };
543
544 struct palmas_usb {
545 struct palmas *palmas;
546 struct device *dev;
547
548 struct extcon_dev *edev;
549
550 int id_otg_irq;
551 int id_irq;
552 int vbus_otg_irq;
553 int vbus_irq;
554
555 int gpio_id_irq;
556 struct gpio_desc *id_gpiod;
557 unsigned long sw_debounce_jiffies;
558 struct delayed_work wq_detectid;
559
560 enum palmas_usb_state linkstat;
561 int wakeup;
562 bool enable_vbus_detection;
563 bool enable_id_detection;
564 bool enable_gpio_id_detection;
565 };
566
567 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
568
569 enum usb_irq_events {
570 /* Wakeup events from INT3 */
571 PALMAS_USB_ID_WAKEPUP,
572 PALMAS_USB_VBUS_WAKEUP,
573
574 /* ID_OTG_EVENTS */
575 PALMAS_USB_ID_GND,
576 N_PALMAS_USB_ID_GND,
577 PALMAS_USB_ID_C,
578 N_PALMAS_USB_ID_C,
579 PALMAS_USB_ID_B,
580 N_PALMAS_USB_ID_B,
581 PALMAS_USB_ID_A,
582 N_PALMAS_USB_ID_A,
583 PALMAS_USB_ID_FLOAT,
584 N_PALMAS_USB_ID_FLOAT,
585
586 /* VBUS_OTG_EVENTS */
587 PALMAS_USB_VB_SESS_END,
588 N_PALMAS_USB_VB_SESS_END,
589 PALMAS_USB_VB_SESS_VLD,
590 N_PALMAS_USB_VB_SESS_VLD,
591 PALMAS_USB_VA_SESS_VLD,
592 N_PALMAS_USB_VA_SESS_VLD,
593 PALMAS_USB_VA_VBUS_VLD,
594 N_PALMAS_USB_VA_VBUS_VLD,
595 PALMAS_USB_VADP_SNS,
596 N_PALMAS_USB_VADP_SNS,
597 PALMAS_USB_VADP_PRB,
598 N_PALMAS_USB_VADP_PRB,
599 PALMAS_USB_VOTG_SESS_VLD,
600 N_PALMAS_USB_VOTG_SESS_VLD,
601 };
602
603 /* defines so we can store the mux settings */
604 #define PALMAS_GPIO_0_MUXED (1 << 0)
605 #define PALMAS_GPIO_1_MUXED (1 << 1)
606 #define PALMAS_GPIO_2_MUXED (1 << 2)
607 #define PALMAS_GPIO_3_MUXED (1 << 3)
608 #define PALMAS_GPIO_4_MUXED (1 << 4)
609 #define PALMAS_GPIO_5_MUXED (1 << 5)
610 #define PALMAS_GPIO_6_MUXED (1 << 6)
611 #define PALMAS_GPIO_7_MUXED (1 << 7)
612
613 #define PALMAS_LED1_MUXED (1 << 0)
614 #define PALMAS_LED2_MUXED (1 << 1)
615
616 #define PALMAS_PWM1_MUXED (1 << 0)
617 #define PALMAS_PWM2_MUXED (1 << 1)
618
619 /* helper macro to get correct slave number */
620 #define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
621 #define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y)
622
623 /* Base addresses of IP blocks in Palmas */
624 #define PALMAS_SMPS_DVS_BASE 0x020
625 #define PALMAS_RTC_BASE 0x100
626 #define PALMAS_VALIDITY_BASE 0x118
627 #define PALMAS_SMPS_BASE 0x120
628 #define PALMAS_LDO_BASE 0x150
629 #define PALMAS_DVFS_BASE 0x180
630 #define PALMAS_PMU_CONTROL_BASE 0x1A0
631 #define PALMAS_RESOURCE_BASE 0x1D4
632 #define PALMAS_PU_PD_OD_BASE 0x1F0
633 #define PALMAS_LED_BASE 0x200
634 #define PALMAS_INTERRUPT_BASE 0x210
635 #define PALMAS_USB_OTG_BASE 0x250
636 #define PALMAS_VIBRATOR_BASE 0x270
637 #define PALMAS_GPIO_BASE 0x280
638 #define PALMAS_USB_BASE 0x290
639 #define PALMAS_GPADC_BASE 0x2C0
640 #define PALMAS_TRIM_GPADC_BASE 0x3CD
641
642 /* Registers for function RTC */
643 #define PALMAS_SECONDS_REG 0x00
644 #define PALMAS_MINUTES_REG 0x01
645 #define PALMAS_HOURS_REG 0x02
646 #define PALMAS_DAYS_REG 0x03
647 #define PALMAS_MONTHS_REG 0x04
648 #define PALMAS_YEARS_REG 0x05
649 #define PALMAS_WEEKS_REG 0x06
650 #define PALMAS_ALARM_SECONDS_REG 0x08
651 #define PALMAS_ALARM_MINUTES_REG 0x09
652 #define PALMAS_ALARM_HOURS_REG 0x0A
653 #define PALMAS_ALARM_DAYS_REG 0x0B
654 #define PALMAS_ALARM_MONTHS_REG 0x0C
655 #define PALMAS_ALARM_YEARS_REG 0x0D
656 #define PALMAS_RTC_CTRL_REG 0x10
657 #define PALMAS_RTC_STATUS_REG 0x11
658 #define PALMAS_RTC_INTERRUPTS_REG 0x12
659 #define PALMAS_RTC_COMP_LSB_REG 0x13
660 #define PALMAS_RTC_COMP_MSB_REG 0x14
661 #define PALMAS_RTC_RES_PROG_REG 0x15
662 #define PALMAS_RTC_RESET_STATUS_REG 0x16
663
664 /* Bit definitions for SECONDS_REG */
665 #define PALMAS_SECONDS_REG_SEC1_MASK 0x70
666 #define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04
667 #define PALMAS_SECONDS_REG_SEC0_MASK 0x0F
668 #define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00
669
670 /* Bit definitions for MINUTES_REG */
671 #define PALMAS_MINUTES_REG_MIN1_MASK 0x70
672 #define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04
673 #define PALMAS_MINUTES_REG_MIN0_MASK 0x0F
674 #define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00
675
676 /* Bit definitions for HOURS_REG */
677 #define PALMAS_HOURS_REG_PM_NAM 0x80
678 #define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07
679 #define PALMAS_HOURS_REG_HOUR1_MASK 0x30
680 #define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04
681 #define PALMAS_HOURS_REG_HOUR0_MASK 0x0F
682 #define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00
683
684 /* Bit definitions for DAYS_REG */
685 #define PALMAS_DAYS_REG_DAY1_MASK 0x30
686 #define PALMAS_DAYS_REG_DAY1_SHIFT 0x04
687 #define PALMAS_DAYS_REG_DAY0_MASK 0x0F
688 #define PALMAS_DAYS_REG_DAY0_SHIFT 0x00
689
690 /* Bit definitions for MONTHS_REG */
691 #define PALMAS_MONTHS_REG_MONTH1 0x10
692 #define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04
693 #define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F
694 #define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00
695
696 /* Bit definitions for YEARS_REG */
697 #define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
698 #define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04
699 #define PALMAS_YEARS_REG_YEAR0_MASK 0x0F
700 #define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00
701
702 /* Bit definitions for WEEKS_REG */
703 #define PALMAS_WEEKS_REG_WEEK_MASK 0x07
704 #define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00
705
706 /* Bit definitions for ALARM_SECONDS_REG */
707 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
708 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04
709 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F
710 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00
711
712 /* Bit definitions for ALARM_MINUTES_REG */
713 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
714 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04
715 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F
716 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00
717
718 /* Bit definitions for ALARM_HOURS_REG */
719 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
720 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07
721 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
722 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04
723 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F
724 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00
725
726 /* Bit definitions for ALARM_DAYS_REG */
727 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
728 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04
729 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F
730 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00
731
732 /* Bit definitions for ALARM_MONTHS_REG */
733 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
734 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04
735 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F
736 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00
737
738 /* Bit definitions for ALARM_YEARS_REG */
739 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
740 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04
741 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F
742 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00
743
744 /* Bit definitions for RTC_CTRL_REG */
745 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
746 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07
747 #define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
748 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06
749 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
750 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05
751 #define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
752 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04
753 #define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
754 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03
755 #define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
756 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02
757 #define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
758 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01
759 #define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
760 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00
761
762 /* Bit definitions for RTC_STATUS_REG */
763 #define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
764 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07
765 #define PALMAS_RTC_STATUS_REG_ALARM 0x40
766 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06
767 #define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
768 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05
769 #define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
770 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04
771 #define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
772 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03
773 #define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
774 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02
775 #define PALMAS_RTC_STATUS_REG_RUN 0x02
776 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01
777
778 /* Bit definitions for RTC_INTERRUPTS_REG */
779 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
780 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04
781 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
782 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03
783 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
784 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02
785 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
786 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00
787
788 /* Bit definitions for RTC_COMP_LSB_REG */
789 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF
790 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00
791
792 /* Bit definitions for RTC_COMP_MSB_REG */
793 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF
794 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00
795
796 /* Bit definitions for RTC_RES_PROG_REG */
797 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F
798 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00
799
800 /* Bit definitions for RTC_RESET_STATUS_REG */
801 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
802 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00
803
804 /* Registers for function BACKUP */
805 #define PALMAS_BACKUP0 0x00
806 #define PALMAS_BACKUP1 0x01
807 #define PALMAS_BACKUP2 0x02
808 #define PALMAS_BACKUP3 0x03
809 #define PALMAS_BACKUP4 0x04
810 #define PALMAS_BACKUP5 0x05
811 #define PALMAS_BACKUP6 0x06
812 #define PALMAS_BACKUP7 0x07
813
814 /* Bit definitions for BACKUP0 */
815 #define PALMAS_BACKUP0_BACKUP_MASK 0xFF
816 #define PALMAS_BACKUP0_BACKUP_SHIFT 0x00
817
818 /* Bit definitions for BACKUP1 */
819 #define PALMAS_BACKUP1_BACKUP_MASK 0xFF
820 #define PALMAS_BACKUP1_BACKUP_SHIFT 0x00
821
822 /* Bit definitions for BACKUP2 */
823 #define PALMAS_BACKUP2_BACKUP_MASK 0xFF
824 #define PALMAS_BACKUP2_BACKUP_SHIFT 0x00
825
826 /* Bit definitions for BACKUP3 */
827 #define PALMAS_BACKUP3_BACKUP_MASK 0xFF
828 #define PALMAS_BACKUP3_BACKUP_SHIFT 0x00
829
830 /* Bit definitions for BACKUP4 */
831 #define PALMAS_BACKUP4_BACKUP_MASK 0xFF
832 #define PALMAS_BACKUP4_BACKUP_SHIFT 0x00
833
834 /* Bit definitions for BACKUP5 */
835 #define PALMAS_BACKUP5_BACKUP_MASK 0xFF
836 #define PALMAS_BACKUP5_BACKUP_SHIFT 0x00
837
838 /* Bit definitions for BACKUP6 */
839 #define PALMAS_BACKUP6_BACKUP_MASK 0xFF
840 #define PALMAS_BACKUP6_BACKUP_SHIFT 0x00
841
842 /* Bit definitions for BACKUP7 */
843 #define PALMAS_BACKUP7_BACKUP_MASK 0xFF
844 #define PALMAS_BACKUP7_BACKUP_SHIFT 0x00
845
846 /* Registers for function SMPS */
847 #define PALMAS_SMPS12_CTRL 0x00
848 #define PALMAS_SMPS12_TSTEP 0x01
849 #define PALMAS_SMPS12_FORCE 0x02
850 #define PALMAS_SMPS12_VOLTAGE 0x03
851 #define PALMAS_SMPS3_CTRL 0x04
852 #define PALMAS_SMPS3_VOLTAGE 0x07
853 #define PALMAS_SMPS45_CTRL 0x08
854 #define PALMAS_SMPS45_TSTEP 0x09
855 #define PALMAS_SMPS45_FORCE 0x0A
856 #define PALMAS_SMPS45_VOLTAGE 0x0B
857 #define PALMAS_SMPS6_CTRL 0x0C
858 #define PALMAS_SMPS6_TSTEP 0x0D
859 #define PALMAS_SMPS6_FORCE 0x0E
860 #define PALMAS_SMPS6_VOLTAGE 0x0F
861 #define PALMAS_SMPS7_CTRL 0x10
862 #define PALMAS_SMPS7_VOLTAGE 0x13
863 #define PALMAS_SMPS8_CTRL 0x14
864 #define PALMAS_SMPS8_TSTEP 0x15
865 #define PALMAS_SMPS8_FORCE 0x16
866 #define PALMAS_SMPS8_VOLTAGE 0x17
867 #define PALMAS_SMPS9_CTRL 0x18
868 #define PALMAS_SMPS9_VOLTAGE 0x1B
869 #define PALMAS_SMPS10_CTRL 0x1C
870 #define PALMAS_SMPS10_STATUS 0x1F
871 #define PALMAS_SMPS_CTRL 0x24
872 #define PALMAS_SMPS_PD_CTRL 0x25
873 #define PALMAS_SMPS_DITHER_EN 0x26
874 #define PALMAS_SMPS_THERMAL_EN 0x27
875 #define PALMAS_SMPS_THERMAL_STATUS 0x28
876 #define PALMAS_SMPS_SHORT_STATUS 0x29
877 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
878 #define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
879 #define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
880
881 /* Bit definitions for SMPS12_CTRL */
882 #define PALMAS_SMPS12_CTRL_WR_S 0x80
883 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07
884 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
885 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
886 #define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
887 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04
888 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
889 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02
890 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
891 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00
892
893 /* Bit definitions for SMPS12_TSTEP */
894 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
895 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00
896
897 /* Bit definitions for SMPS12_FORCE */
898 #define PALMAS_SMPS12_FORCE_CMD 0x80
899 #define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07
900 #define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F
901 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00
902
903 /* Bit definitions for SMPS12_VOLTAGE */
904 #define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
905 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07
906 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F
907 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00
908
909 /* Bit definitions for SMPS3_CTRL */
910 #define PALMAS_SMPS3_CTRL_WR_S 0x80
911 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07
912 #define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
913 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04
914 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
915 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
916 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
917 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
918
919 /* Bit definitions for SMPS3_VOLTAGE */
920 #define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
921 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
922 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F
923 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
924
925 /* Bit definitions for SMPS45_CTRL */
926 #define PALMAS_SMPS45_CTRL_WR_S 0x80
927 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07
928 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
929 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
930 #define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
931 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04
932 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
933 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02
934 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
935 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00
936
937 /* Bit definitions for SMPS45_TSTEP */
938 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
939 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00
940
941 /* Bit definitions for SMPS45_FORCE */
942 #define PALMAS_SMPS45_FORCE_CMD 0x80
943 #define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07
944 #define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F
945 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00
946
947 /* Bit definitions for SMPS45_VOLTAGE */
948 #define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
949 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07
950 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F
951 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00
952
953 /* Bit definitions for SMPS6_CTRL */
954 #define PALMAS_SMPS6_CTRL_WR_S 0x80
955 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07
956 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
957 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
958 #define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
959 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04
960 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
961 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02
962 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
963 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00
964
965 /* Bit definitions for SMPS6_TSTEP */
966 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
967 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00
968
969 /* Bit definitions for SMPS6_FORCE */
970 #define PALMAS_SMPS6_FORCE_CMD 0x80
971 #define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07
972 #define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F
973 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00
974
975 /* Bit definitions for SMPS6_VOLTAGE */
976 #define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
977 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07
978 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F
979 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00
980
981 /* Bit definitions for SMPS7_CTRL */
982 #define PALMAS_SMPS7_CTRL_WR_S 0x80
983 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07
984 #define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
985 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04
986 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
987 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02
988 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
989 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00
990
991 /* Bit definitions for SMPS7_VOLTAGE */
992 #define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
993 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07
994 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F
995 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00
996
997 /* Bit definitions for SMPS8_CTRL */
998 #define PALMAS_SMPS8_CTRL_WR_S 0x80
999 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07
1000 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
1001 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
1002 #define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
1003 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04
1004 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
1005 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02
1006 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
1007 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00
1008
1009 /* Bit definitions for SMPS8_TSTEP */
1010 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
1011 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00
1012
1013 /* Bit definitions for SMPS8_FORCE */
1014 #define PALMAS_SMPS8_FORCE_CMD 0x80
1015 #define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07
1016 #define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F
1017 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00
1018
1019 /* Bit definitions for SMPS8_VOLTAGE */
1020 #define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
1021 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07
1022 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F
1023 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00
1024
1025 /* Bit definitions for SMPS9_CTRL */
1026 #define PALMAS_SMPS9_CTRL_WR_S 0x80
1027 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07
1028 #define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
1029 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04
1030 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
1031 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02
1032 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
1033 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00
1034
1035 /* Bit definitions for SMPS9_VOLTAGE */
1036 #define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
1037 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07
1038 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F
1039 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00
1040
1041 /* Bit definitions for SMPS10_CTRL */
1042 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
1043 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04
1044 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F
1045 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00
1046
1047 /* Bit definitions for SMPS10_STATUS */
1048 #define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F
1049 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00
1050
1051 /* Bit definitions for SMPS_CTRL */
1052 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
1053 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05
1054 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
1055 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04
1056 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
1057 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02
1058 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
1059 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00
1060
1061 /* Bit definitions for SMPS_PD_CTRL */
1062 #define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
1063 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06
1064 #define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
1065 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05
1066 #define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
1067 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04
1068 #define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
1069 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03
1070 #define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
1071 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02
1072 #define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
1073 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01
1074 #define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
1075 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00
1076
1077 /* Bit definitions for SMPS_THERMAL_EN */
1078 #define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
1079 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06
1080 #define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
1081 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05
1082 #define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
1083 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03
1084 #define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
1085 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02
1086 #define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
1087 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00
1088
1089 /* Bit definitions for SMPS_THERMAL_STATUS */
1090 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
1091 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06
1092 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
1093 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05
1094 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
1095 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03
1096 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
1097 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02
1098 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
1099 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00
1100
1101 /* Bit definitions for SMPS_SHORT_STATUS */
1102 #define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
1103 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07
1104 #define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
1105 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06
1106 #define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
1107 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05
1108 #define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
1109 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04
1110 #define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
1111 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03
1112 #define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
1113 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02
1114 #define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
1115 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01
1116 #define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
1117 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00
1118
1119 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
1120 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
1121 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06
1122 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
1123 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05
1124 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
1125 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04
1126 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
1127 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03
1128 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
1129 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02
1130 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
1131 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01
1132 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
1133 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00
1134
1135 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
1136 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
1137 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07
1138 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
1139 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06
1140 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
1141 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05
1142 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
1143 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04
1144 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
1145 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03
1146 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
1147 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02
1148 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
1149 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01
1150 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
1151 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00
1152
1153 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
1154 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
1155 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
1156 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
1157 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02
1158 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
1159 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01
1160 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
1161 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00
1162
1163 /* Registers for function LDO */
1164 #define PALMAS_LDO1_CTRL 0x00
1165 #define PALMAS_LDO1_VOLTAGE 0x01
1166 #define PALMAS_LDO2_CTRL 0x02
1167 #define PALMAS_LDO2_VOLTAGE 0x03
1168 #define PALMAS_LDO3_CTRL 0x04
1169 #define PALMAS_LDO3_VOLTAGE 0x05
1170 #define PALMAS_LDO4_CTRL 0x06
1171 #define PALMAS_LDO4_VOLTAGE 0x07
1172 #define PALMAS_LDO5_CTRL 0x08
1173 #define PALMAS_LDO5_VOLTAGE 0x09
1174 #define PALMAS_LDO6_CTRL 0x0A
1175 #define PALMAS_LDO6_VOLTAGE 0x0B
1176 #define PALMAS_LDO7_CTRL 0x0C
1177 #define PALMAS_LDO7_VOLTAGE 0x0D
1178 #define PALMAS_LDO8_CTRL 0x0E
1179 #define PALMAS_LDO8_VOLTAGE 0x0F
1180 #define PALMAS_LDO9_CTRL 0x10
1181 #define PALMAS_LDO9_VOLTAGE 0x11
1182 #define PALMAS_LDOLN_CTRL 0x12
1183 #define PALMAS_LDOLN_VOLTAGE 0x13
1184 #define PALMAS_LDOUSB_CTRL 0x14
1185 #define PALMAS_LDOUSB_VOLTAGE 0x15
1186 #define PALMAS_LDO_CTRL 0x1A
1187 #define PALMAS_LDO_PD_CTRL1 0x1B
1188 #define PALMAS_LDO_PD_CTRL2 0x1C
1189 #define PALMAS_LDO_SHORT_STATUS1 0x1D
1190 #define PALMAS_LDO_SHORT_STATUS2 0x1E
1191
1192 /* Bit definitions for LDO1_CTRL */
1193 #define PALMAS_LDO1_CTRL_WR_S 0x80
1194 #define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07
1195 #define PALMAS_LDO1_CTRL_STATUS 0x10
1196 #define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04
1197 #define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
1198 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
1199 #define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
1200 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
1201
1202 /* Bit definitions for LDO1_VOLTAGE */
1203 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F
1204 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00
1205
1206 /* Bit definitions for LDO2_CTRL */
1207 #define PALMAS_LDO2_CTRL_WR_S 0x80
1208 #define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07
1209 #define PALMAS_LDO2_CTRL_STATUS 0x10
1210 #define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04
1211 #define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
1212 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
1213 #define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
1214 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
1215
1216 /* Bit definitions for LDO2_VOLTAGE */
1217 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F
1218 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00
1219
1220 /* Bit definitions for LDO3_CTRL */
1221 #define PALMAS_LDO3_CTRL_WR_S 0x80
1222 #define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07
1223 #define PALMAS_LDO3_CTRL_STATUS 0x10
1224 #define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04
1225 #define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
1226 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
1227 #define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
1228 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
1229
1230 /* Bit definitions for LDO3_VOLTAGE */
1231 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F
1232 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00
1233
1234 /* Bit definitions for LDO4_CTRL */
1235 #define PALMAS_LDO4_CTRL_WR_S 0x80
1236 #define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07
1237 #define PALMAS_LDO4_CTRL_STATUS 0x10
1238 #define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04
1239 #define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
1240 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
1241 #define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
1242 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
1243
1244 /* Bit definitions for LDO4_VOLTAGE */
1245 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F
1246 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00
1247
1248 /* Bit definitions for LDO5_CTRL */
1249 #define PALMAS_LDO5_CTRL_WR_S 0x80
1250 #define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07
1251 #define PALMAS_LDO5_CTRL_STATUS 0x10
1252 #define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04
1253 #define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
1254 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
1255 #define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
1256 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
1257
1258 /* Bit definitions for LDO5_VOLTAGE */
1259 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F
1260 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00
1261
1262 /* Bit definitions for LDO6_CTRL */
1263 #define PALMAS_LDO6_CTRL_WR_S 0x80
1264 #define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07
1265 #define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
1266 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06
1267 #define PALMAS_LDO6_CTRL_STATUS 0x10
1268 #define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04
1269 #define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
1270 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02
1271 #define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
1272 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00
1273
1274 /* Bit definitions for LDO6_VOLTAGE */
1275 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F
1276 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00
1277
1278 /* Bit definitions for LDO7_CTRL */
1279 #define PALMAS_LDO7_CTRL_WR_S 0x80
1280 #define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07
1281 #define PALMAS_LDO7_CTRL_STATUS 0x10
1282 #define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04
1283 #define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
1284 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02
1285 #define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
1286 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00
1287
1288 /* Bit definitions for LDO7_VOLTAGE */
1289 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F
1290 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00
1291
1292 /* Bit definitions for LDO8_CTRL */
1293 #define PALMAS_LDO8_CTRL_WR_S 0x80
1294 #define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07
1295 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
1296 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06
1297 #define PALMAS_LDO8_CTRL_STATUS 0x10
1298 #define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04
1299 #define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
1300 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02
1301 #define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
1302 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00
1303
1304 /* Bit definitions for LDO8_VOLTAGE */
1305 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F
1306 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00
1307
1308 /* Bit definitions for LDO9_CTRL */
1309 #define PALMAS_LDO9_CTRL_WR_S 0x80
1310 #define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07
1311 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
1312 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06
1313 #define PALMAS_LDO9_CTRL_STATUS 0x10
1314 #define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04
1315 #define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
1316 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02
1317 #define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
1318 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00
1319
1320 /* Bit definitions for LDO9_VOLTAGE */
1321 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F
1322 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00
1323
1324 /* Bit definitions for LDOLN_CTRL */
1325 #define PALMAS_LDOLN_CTRL_WR_S 0x80
1326 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07
1327 #define PALMAS_LDOLN_CTRL_STATUS 0x10
1328 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04
1329 #define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
1330 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02
1331 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
1332 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00
1333
1334 /* Bit definitions for LDOLN_VOLTAGE */
1335 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F
1336 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00
1337
1338 /* Bit definitions for LDOUSB_CTRL */
1339 #define PALMAS_LDOUSB_CTRL_WR_S 0x80
1340 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07
1341 #define PALMAS_LDOUSB_CTRL_STATUS 0x10
1342 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04
1343 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
1344 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02
1345 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
1346 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00
1347
1348 /* Bit definitions for LDOUSB_VOLTAGE */
1349 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F
1350 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00
1351
1352 /* Bit definitions for LDO_CTRL */
1353 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
1354 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00
1355
1356 /* Bit definitions for LDO_PD_CTRL1 */
1357 #define PALMAS_LDO_PD_CTRL1_LDO8 0x80
1358 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07
1359 #define PALMAS_LDO_PD_CTRL1_LDO7 0x40
1360 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06
1361 #define PALMAS_LDO_PD_CTRL1_LDO6 0x20
1362 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05
1363 #define PALMAS_LDO_PD_CTRL1_LDO5 0x10
1364 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04
1365 #define PALMAS_LDO_PD_CTRL1_LDO4 0x08
1366 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03
1367 #define PALMAS_LDO_PD_CTRL1_LDO3 0x04
1368 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02
1369 #define PALMAS_LDO_PD_CTRL1_LDO2 0x02
1370 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01
1371 #define PALMAS_LDO_PD_CTRL1_LDO1 0x01
1372 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00
1373
1374 /* Bit definitions for LDO_PD_CTRL2 */
1375 #define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
1376 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02
1377 #define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1378 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01
1379 #define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1380 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00
1381
1382 /* Bit definitions for LDO_SHORT_STATUS1 */
1383 #define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1384 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07
1385 #define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1386 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06
1387 #define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1388 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05
1389 #define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1390 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04
1391 #define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1392 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03
1393 #define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1394 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02
1395 #define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1396 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
1397 #define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1398 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
1399
1400 /* Bit definitions for LDO_SHORT_STATUS2 */
1401 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1402 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03
1403 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1404 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02
1405 #define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1406 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01
1407 #define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1408 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00
1409
1410 /* Registers for function PMU_CONTROL */
1411 #define PALMAS_DEV_CTRL 0x00
1412 #define PALMAS_POWER_CTRL 0x01
1413 #define PALMAS_VSYS_LO 0x02
1414 #define PALMAS_VSYS_MON 0x03
1415 #define PALMAS_VBAT_MON 0x04
1416 #define PALMAS_WATCHDOG 0x05
1417 #define PALMAS_BOOT_STATUS 0x06
1418 #define PALMAS_BATTERY_BOUNCE 0x07
1419 #define PALMAS_BACKUP_BATTERY_CTRL 0x08
1420 #define PALMAS_LONG_PRESS_KEY 0x09
1421 #define PALMAS_OSC_THERM_CTRL 0x0A
1422 #define PALMAS_BATDEBOUNCING 0x0B
1423 #define PALMAS_SWOFF_HWRST 0x0F
1424 #define PALMAS_SWOFF_COLDRST 0x10
1425 #define PALMAS_SWOFF_STATUS 0x11
1426 #define PALMAS_PMU_CONFIG 0x12
1427 #define PALMAS_SPARE 0x14
1428 #define PALMAS_PMU_SECONDARY_INT 0x15
1429 #define PALMAS_SW_REVISION 0x17
1430 #define PALMAS_EXT_CHRG_CTRL 0x18
1431 #define PALMAS_PMU_SECONDARY_INT2 0x19
1432
1433 /* Bit definitions for DEV_CTRL */
1434 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1435 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02
1436 #define PALMAS_DEV_CTRL_SW_RST 0x02
1437 #define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01
1438 #define PALMAS_DEV_CTRL_DEV_ON 0x01
1439 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00
1440
1441 /* Bit definitions for POWER_CTRL */
1442 #define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1443 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02
1444 #define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1445 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01
1446 #define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1447 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00
1448
1449 /* Bit definitions for VSYS_LO */
1450 #define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F
1451 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00
1452
1453 /* Bit definitions for VSYS_MON */
1454 #define PALMAS_VSYS_MON_ENABLE 0x80
1455 #define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07
1456 #define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F
1457 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00
1458
1459 /* Bit definitions for VBAT_MON */
1460 #define PALMAS_VBAT_MON_ENABLE 0x80
1461 #define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07
1462 #define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F
1463 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00
1464
1465 /* Bit definitions for WATCHDOG */
1466 #define PALMAS_WATCHDOG_LOCK 0x20
1467 #define PALMAS_WATCHDOG_LOCK_SHIFT 0x05
1468 #define PALMAS_WATCHDOG_ENABLE 0x10
1469 #define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04
1470 #define PALMAS_WATCHDOG_MODE 0x08
1471 #define PALMAS_WATCHDOG_MODE_SHIFT 0x03
1472 #define PALMAS_WATCHDOG_TIMER_MASK 0x07
1473 #define PALMAS_WATCHDOG_TIMER_SHIFT 0x00
1474
1475 /* Bit definitions for BOOT_STATUS */
1476 #define PALMAS_BOOT_STATUS_BOOT1 0x02
1477 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01
1478 #define PALMAS_BOOT_STATUS_BOOT0 0x01
1479 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00
1480
1481 /* Bit definitions for BATTERY_BOUNCE */
1482 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F
1483 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00
1484
1485 /* Bit definitions for BACKUP_BATTERY_CTRL */
1486 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1487 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07
1488 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1489 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06
1490 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1491 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05
1492 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1493 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04
1494 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1495 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03
1496 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1497 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01
1498 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1499 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00
1500
1501 /* Bit definitions for LONG_PRESS_KEY */
1502 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1503 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07
1504 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1505 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04
1506 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1507 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02
1508 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1509 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00
1510
1511 /* Bit definitions for OSC_THERM_CTRL */
1512 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1513 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07
1514 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1515 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06
1516 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1517 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05
1518 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1519 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04
1520 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1521 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02
1522 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1523 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01
1524 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1525 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00
1526
1527 /* Bit definitions for BATDEBOUNCING */
1528 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1529 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07
1530 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1531 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03
1532 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1533 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00
1534
1535 /* Bit definitions for SWOFF_HWRST */
1536 #define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1537 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07
1538 #define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1539 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06
1540 #define PALMAS_SWOFF_HWRST_WTD 0x20
1541 #define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05
1542 #define PALMAS_SWOFF_HWRST_TSHUT 0x10
1543 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04
1544 #define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1545 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03
1546 #define PALMAS_SWOFF_HWRST_SW_RST 0x04
1547 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02
1548 #define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1549 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01
1550 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1551 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00
1552
1553 /* Bit definitions for SWOFF_COLDRST */
1554 #define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1555 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07
1556 #define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1557 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06
1558 #define PALMAS_SWOFF_COLDRST_WTD 0x20
1559 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05
1560 #define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1561 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04
1562 #define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1563 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03
1564 #define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1565 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02
1566 #define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1567 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01
1568 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1569 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00
1570
1571 /* Bit definitions for SWOFF_STATUS */
1572 #define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1573 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07
1574 #define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1575 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06
1576 #define PALMAS_SWOFF_STATUS_WTD 0x20
1577 #define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05
1578 #define PALMAS_SWOFF_STATUS_TSHUT 0x10
1579 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04
1580 #define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1581 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03
1582 #define PALMAS_SWOFF_STATUS_SW_RST 0x04
1583 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02
1584 #define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1585 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01
1586 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1587 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00
1588
1589 /* Bit definitions for PMU_CONFIG */
1590 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1591 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06
1592 #define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1593 #define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04
1594 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1595 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02
1596 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1597 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01
1598 #define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1599 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00
1600
1601 /* Bit definitions for SPARE */
1602 #define PALMAS_SPARE_SPARE_MASK 0xf8
1603 #define PALMAS_SPARE_SPARE_SHIFT 0x03
1604 #define PALMAS_SPARE_REGEN3_OD 0x04
1605 #define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02
1606 #define PALMAS_SPARE_REGEN2_OD 0x02
1607 #define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01
1608 #define PALMAS_SPARE_REGEN1_OD 0x01
1609 #define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00
1610
1611 /* Bit definitions for PMU_SECONDARY_INT */
1612 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1613 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07
1614 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1615 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06
1616 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1617 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05
1618 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1619 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04
1620 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1621 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03
1622 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1623 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02
1624 #define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1625 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01
1626 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1627 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00
1628
1629 /* Bit definitions for SW_REVISION */
1630 #define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF
1631 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00
1632
1633 /* Bit definitions for EXT_CHRG_CTRL */
1634 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1635 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07
1636 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1637 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06
1638 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1639 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03
1640 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1641 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02
1642 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1643 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01
1644 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1645 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00
1646
1647 /* Bit definitions for PMU_SECONDARY_INT2 */
1648 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1649 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05
1650 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1651 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04
1652 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1653 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01
1654 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1655 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00
1656
1657 /* Registers for function RESOURCE */
1658 #define PALMAS_CLK32KG_CTRL 0x00
1659 #define PALMAS_CLK32KGAUDIO_CTRL 0x01
1660 #define PALMAS_REGEN1_CTRL 0x02
1661 #define PALMAS_REGEN2_CTRL 0x03
1662 #define PALMAS_SYSEN1_CTRL 0x04
1663 #define PALMAS_SYSEN2_CTRL 0x05
1664 #define PALMAS_NSLEEP_RES_ASSIGN 0x06
1665 #define PALMAS_NSLEEP_SMPS_ASSIGN 0x07
1666 #define PALMAS_NSLEEP_LDO_ASSIGN1 0x08
1667 #define PALMAS_NSLEEP_LDO_ASSIGN2 0x09
1668 #define PALMAS_ENABLE1_RES_ASSIGN 0x0A
1669 #define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B
1670 #define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C
1671 #define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D
1672 #define PALMAS_ENABLE2_RES_ASSIGN 0x0E
1673 #define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F
1674 #define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1675 #define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1676 #define PALMAS_REGEN3_CTRL 0x12
1677
1678 /* Bit definitions for CLK32KG_CTRL */
1679 #define PALMAS_CLK32KG_CTRL_STATUS 0x10
1680 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04
1681 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1682 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02
1683 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1684 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00
1685
1686 /* Bit definitions for CLK32KGAUDIO_CTRL */
1687 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1688 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04
1689 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1690 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03
1691 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1692 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02
1693 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1694 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00
1695
1696 /* Bit definitions for REGEN1_CTRL */
1697 #define PALMAS_REGEN1_CTRL_STATUS 0x10
1698 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04
1699 #define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1700 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1701 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1702 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1703
1704 /* Bit definitions for REGEN2_CTRL */
1705 #define PALMAS_REGEN2_CTRL_STATUS 0x10
1706 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04
1707 #define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1708 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1709 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1710 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1711
1712 /* Bit definitions for SYSEN1_CTRL */
1713 #define PALMAS_SYSEN1_CTRL_STATUS 0x10
1714 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04
1715 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1716 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1717 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1718 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1719
1720 /* Bit definitions for SYSEN2_CTRL */
1721 #define PALMAS_SYSEN2_CTRL_STATUS 0x10
1722 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04
1723 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1724 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1725 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1726 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1727
1728 /* Bit definitions for NSLEEP_RES_ASSIGN */
1729 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1730 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06
1731 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1732 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1733 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1734 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04
1735 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1736 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03
1737 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1738 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02
1739 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1740 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
1741 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1742 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
1743
1744 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1745 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1746 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1747 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1748 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1749 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1750 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1751 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1752 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1753 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1754 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1755 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1756 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1757 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1758 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1759 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1760 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1761
1762 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1763 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1764 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07
1765 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1766 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06
1767 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1768 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05
1769 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1770 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04
1771 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1772 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03
1773 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1774 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02
1775 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1776 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
1777 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1778 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
1779
1780 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1781 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1782 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1783 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1784 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1785 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1786 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00
1787
1788 /* Bit definitions for ENABLE1_RES_ASSIGN */
1789 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1790 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06
1791 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1792 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1793 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1794 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04
1795 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1796 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03
1797 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1798 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02
1799 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1800 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
1801 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1802 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
1803
1804 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1805 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1806 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1807 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1808 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1809 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1810 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1811 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1812 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1813 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1814 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1815 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1816 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1817 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1818 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1819 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1820 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1821
1822 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1823 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1824 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07
1825 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1826 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06
1827 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1828 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05
1829 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1830 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04
1831 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1832 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03
1833 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1834 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02
1835 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1836 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
1837 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1838 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
1839
1840 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1841 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1842 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1843 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1844 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1845 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1846 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00
1847
1848 /* Bit definitions for ENABLE2_RES_ASSIGN */
1849 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1850 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06
1851 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1852 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1853 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1854 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04
1855 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1856 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03
1857 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1858 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02
1859 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1860 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
1861 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1862 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
1863
1864 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1865 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1866 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1867 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1868 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1869 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1870 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1871 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1872 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1873 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1874 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1875 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1876 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1877 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1878 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1879 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1880 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1881
1882 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1883 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1884 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07
1885 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1886 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06
1887 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1888 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05
1889 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1890 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04
1891 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1892 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03
1893 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1894 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02
1895 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1896 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
1897 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1898 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
1899
1900 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1901 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1902 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1903 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1904 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1905 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1906 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00
1907
1908 /* Bit definitions for REGEN3_CTRL */
1909 #define PALMAS_REGEN3_CTRL_STATUS 0x10
1910 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04
1911 #define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1912 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
1913 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1914 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
1915
1916 /* Registers for function PAD_CONTROL */
1917 #define PALMAS_OD_OUTPUT_CTRL2 0x02
1918 #define PALMAS_POLARITY_CTRL2 0x03
1919 #define PALMAS_PU_PD_INPUT_CTRL1 0x04
1920 #define PALMAS_PU_PD_INPUT_CTRL2 0x05
1921 #define PALMAS_PU_PD_INPUT_CTRL3 0x06
1922 #define PALMAS_PU_PD_INPUT_CTRL5 0x07
1923 #define PALMAS_OD_OUTPUT_CTRL 0x08
1924 #define PALMAS_POLARITY_CTRL 0x09
1925 #define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A
1926 #define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B
1927 #define PALMAS_I2C_SPI 0x0C
1928 #define PALMAS_PU_PD_INPUT_CTRL4 0x0D
1929 #define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E
1930 #define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F
1931
1932 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1933 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1934 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06
1935 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1936 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05
1937 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1938 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04
1939 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1940 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02
1941 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1942 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01
1943
1944 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1945 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1946 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05
1947 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1948 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04
1949 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1950 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03
1951 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1952 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02
1953 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1954 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01
1955 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1956 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00
1957
1958 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1959 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1960 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06
1961 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1962 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04
1963 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1964 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02
1965 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1966 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00
1967
1968 /* Bit definitions for OD_OUTPUT_CTRL */
1969 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
1970 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07
1971 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
1972 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06
1973 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
1974 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05
1975 #define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
1976 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03
1977
1978 /* Bit definitions for POLARITY_CTRL */
1979 #define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
1980 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07
1981 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
1982 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06
1983 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
1984 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05
1985 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
1986 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04
1987 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
1988 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03
1989 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
1990 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02
1991 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
1992 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01
1993 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
1994 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00
1995
1996 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1997 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
1998 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07
1999 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
2000 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05
2001 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
2002 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03
2003 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
2004 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02
2005 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
2006 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01
2007 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
2008 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00
2009
2010 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
2011 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
2012 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04
2013 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
2014 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03
2015 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
2016 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01
2017 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
2018 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00
2019
2020 /* Bit definitions for I2C_SPI */
2021 #define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
2022 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07
2023 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
2024 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06
2025 #define PALMAS_I2C_SPI_ID_I2C2 0x20
2026 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05
2027 #define PALMAS_I2C_SPI_I2C_SPI 0x10
2028 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04
2029 #define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F
2030 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00
2031
2032 /* Bit definitions for PU_PD_INPUT_CTRL4 */
2033 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
2034 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06
2035 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
2036 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04
2037 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
2038 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02
2039 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
2040 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00
2041
2042 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
2043 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
2044 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01
2045 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
2046 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00
2047
2048 /* Registers for function LED_PWM */
2049 #define PALMAS_LED_PERIOD_CTRL 0x00
2050 #define PALMAS_LED_CTRL 0x01
2051 #define PALMAS_PWM_CTRL1 0x02
2052 #define PALMAS_PWM_CTRL2 0x03
2053
2054 /* Bit definitions for LED_PERIOD_CTRL */
2055 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
2056 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03
2057 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
2058 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00
2059
2060 /* Bit definitions for LED_CTRL */
2061 #define PALMAS_LED_CTRL_LED_2_SEQ 0x20
2062 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05
2063 #define PALMAS_LED_CTRL_LED_1_SEQ 0x10
2064 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04
2065 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
2066 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02
2067 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
2068 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00
2069
2070 /* Bit definitions for PWM_CTRL1 */
2071 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
2072 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01
2073 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
2074 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00
2075
2076 /* Bit definitions for PWM_CTRL2 */
2077 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF
2078 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00
2079
2080 /* Registers for function INTERRUPT */
2081 #define PALMAS_INT1_STATUS 0x00
2082 #define PALMAS_INT1_MASK 0x01
2083 #define PALMAS_INT1_LINE_STATE 0x02
2084 #define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03
2085 #define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04
2086 #define PALMAS_INT2_STATUS 0x05
2087 #define PALMAS_INT2_MASK 0x06
2088 #define PALMAS_INT2_LINE_STATE 0x07
2089 #define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08
2090 #define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09
2091 #define PALMAS_INT3_STATUS 0x0A
2092 #define PALMAS_INT3_MASK 0x0B
2093 #define PALMAS_INT3_LINE_STATE 0x0C
2094 #define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D
2095 #define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E
2096 #define PALMAS_INT4_STATUS 0x0F
2097 #define PALMAS_INT4_MASK 0x10
2098 #define PALMAS_INT4_LINE_STATE 0x11
2099 #define PALMAS_INT4_EDGE_DETECT1 0x12
2100 #define PALMAS_INT4_EDGE_DETECT2 0x13
2101 #define PALMAS_INT_CTRL 0x14
2102
2103 /* Bit definitions for INT1_STATUS */
2104 #define PALMAS_INT1_STATUS_VBAT_MON 0x80
2105 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07
2106 #define PALMAS_INT1_STATUS_VSYS_MON 0x40
2107 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06
2108 #define PALMAS_INT1_STATUS_HOTDIE 0x20
2109 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05
2110 #define PALMAS_INT1_STATUS_PWRDOWN 0x10
2111 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04
2112 #define PALMAS_INT1_STATUS_RPWRON 0x08
2113 #define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03
2114 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
2115 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
2116 #define PALMAS_INT1_STATUS_PWRON 0x02
2117 #define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01
2118 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
2119 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2120
2121 /* Bit definitions for INT1_MASK */
2122 #define PALMAS_INT1_MASK_VBAT_MON 0x80
2123 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07
2124 #define PALMAS_INT1_MASK_VSYS_MON 0x40
2125 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06
2126 #define PALMAS_INT1_MASK_HOTDIE 0x20
2127 #define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05
2128 #define PALMAS_INT1_MASK_PWRDOWN 0x10
2129 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04
2130 #define PALMAS_INT1_MASK_RPWRON 0x08
2131 #define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03
2132 #define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
2133 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
2134 #define PALMAS_INT1_MASK_PWRON 0x02
2135 #define PALMAS_INT1_MASK_PWRON_SHIFT 0x01
2136 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
2137 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2138
2139 /* Bit definitions for INT1_LINE_STATE */
2140 #define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
2141 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07
2142 #define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
2143 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
2144 #define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
2145 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
2146 #define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
2147 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
2148 #define PALMAS_INT1_LINE_STATE_RPWRON 0x08
2149 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03
2150 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
2151 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
2152 #define PALMAS_INT1_LINE_STATE_PWRON 0x02
2153 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01
2154 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
2155 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2156
2157 /* Bit definitions for INT2_STATUS */
2158 #define PALMAS_INT2_STATUS_VAC_ACOK 0x80
2159 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07
2160 #define PALMAS_INT2_STATUS_SHORT 0x40
2161 #define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06
2162 #define PALMAS_INT2_STATUS_FBI_BB 0x20
2163 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05
2164 #define PALMAS_INT2_STATUS_RESET_IN 0x10
2165 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04
2166 #define PALMAS_INT2_STATUS_BATREMOVAL 0x08
2167 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03
2168 #define PALMAS_INT2_STATUS_WDT 0x04
2169 #define PALMAS_INT2_STATUS_WDT_SHIFT 0x02
2170 #define PALMAS_INT2_STATUS_RTC_TIMER 0x02
2171 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01
2172 #define PALMAS_INT2_STATUS_RTC_ALARM 0x01
2173 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00
2174
2175 /* Bit definitions for INT2_MASK */
2176 #define PALMAS_INT2_MASK_VAC_ACOK 0x80
2177 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07
2178 #define PALMAS_INT2_MASK_SHORT 0x40
2179 #define PALMAS_INT2_MASK_SHORT_SHIFT 0x06
2180 #define PALMAS_INT2_MASK_FBI_BB 0x20
2181 #define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05
2182 #define PALMAS_INT2_MASK_RESET_IN 0x10
2183 #define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04
2184 #define PALMAS_INT2_MASK_BATREMOVAL 0x08
2185 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03
2186 #define PALMAS_INT2_MASK_WDT 0x04
2187 #define PALMAS_INT2_MASK_WDT_SHIFT 0x02
2188 #define PALMAS_INT2_MASK_RTC_TIMER 0x02
2189 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01
2190 #define PALMAS_INT2_MASK_RTC_ALARM 0x01
2191 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00
2192
2193 /* Bit definitions for INT2_LINE_STATE */
2194 #define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
2195 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07
2196 #define PALMAS_INT2_LINE_STATE_SHORT 0x40
2197 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06
2198 #define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
2199 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05
2200 #define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
2201 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
2202 #define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
2203 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03
2204 #define PALMAS_INT2_LINE_STATE_WDT 0x04
2205 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02
2206 #define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
2207 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01
2208 #define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
2209 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00
2210
2211 /* Bit definitions for INT3_STATUS */
2212 #define PALMAS_INT3_STATUS_VBUS 0x80
2213 #define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07
2214 #define PALMAS_INT3_STATUS_VBUS_OTG 0x40
2215 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06
2216 #define PALMAS_INT3_STATUS_ID 0x20
2217 #define PALMAS_INT3_STATUS_ID_SHIFT 0x05
2218 #define PALMAS_INT3_STATUS_ID_OTG 0x10
2219 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04
2220 #define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
2221 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03
2222 #define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
2223 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
2224 #define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
2225 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
2226 #define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
2227 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
2228
2229 /* Bit definitions for INT3_MASK */
2230 #define PALMAS_INT3_MASK_VBUS 0x80
2231 #define PALMAS_INT3_MASK_VBUS_SHIFT 0x07
2232 #define PALMAS_INT3_MASK_VBUS_OTG 0x40
2233 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06
2234 #define PALMAS_INT3_MASK_ID 0x20
2235 #define PALMAS_INT3_MASK_ID_SHIFT 0x05
2236 #define PALMAS_INT3_MASK_ID_OTG 0x10
2237 #define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04
2238 #define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
2239 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03
2240 #define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
2241 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
2242 #define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
2243 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
2244 #define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
2245 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
2246
2247 /* Bit definitions for INT3_LINE_STATE */
2248 #define PALMAS_INT3_LINE_STATE_VBUS 0x80
2249 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07
2250 #define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
2251 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06
2252 #define PALMAS_INT3_LINE_STATE_ID 0x20
2253 #define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05
2254 #define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
2255 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04
2256 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
2257 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03
2258 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
2259 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
2260 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
2261 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
2262 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
2263 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
2264
2265 /* Bit definitions for INT4_STATUS */
2266 #define PALMAS_INT4_STATUS_GPIO_7 0x80
2267 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07
2268 #define PALMAS_INT4_STATUS_GPIO_6 0x40
2269 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06
2270 #define PALMAS_INT4_STATUS_GPIO_5 0x20
2271 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05
2272 #define PALMAS_INT4_STATUS_GPIO_4 0x10
2273 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04
2274 #define PALMAS_INT4_STATUS_GPIO_3 0x08
2275 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03
2276 #define PALMAS_INT4_STATUS_GPIO_2 0x04
2277 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02
2278 #define PALMAS_INT4_STATUS_GPIO_1 0x02
2279 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01
2280 #define PALMAS_INT4_STATUS_GPIO_0 0x01
2281 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00
2282
2283 /* Bit definitions for INT4_MASK */
2284 #define PALMAS_INT4_MASK_GPIO_7 0x80
2285 #define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07
2286 #define PALMAS_INT4_MASK_GPIO_6 0x40
2287 #define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06
2288 #define PALMAS_INT4_MASK_GPIO_5 0x20
2289 #define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05
2290 #define PALMAS_INT4_MASK_GPIO_4 0x10
2291 #define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04
2292 #define PALMAS_INT4_MASK_GPIO_3 0x08
2293 #define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03
2294 #define PALMAS_INT4_MASK_GPIO_2 0x04
2295 #define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02
2296 #define PALMAS_INT4_MASK_GPIO_1 0x02
2297 #define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01
2298 #define PALMAS_INT4_MASK_GPIO_0 0x01
2299 #define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00
2300
2301 /* Bit definitions for INT4_LINE_STATE */
2302 #define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
2303 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07
2304 #define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
2305 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
2306 #define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
2307 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
2308 #define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
2309 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
2310 #define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
2311 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
2312 #define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
2313 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
2314 #define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
2315 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
2316 #define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
2317 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
2318
2319 /* Bit definitions for INT4_EDGE_DETECT1 */
2320 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
2321 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
2322 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
2323 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
2324 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
2325 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
2326 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
2327 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
2328 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
2329 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
2330 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
2331 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
2332 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
2333 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
2334 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
2335 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
2336
2337 /* Bit definitions for INT4_EDGE_DETECT2 */
2338 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
2339 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07
2340 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
2341 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06
2342 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
2343 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
2344 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
2345 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
2346 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
2347 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
2348 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
2349 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
2350 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
2351 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
2352 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
2353 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
2354
2355 /* Bit definitions for INT_CTRL */
2356 #define PALMAS_INT_CTRL_INT_PENDING 0x04
2357 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02
2358 #define PALMAS_INT_CTRL_INT_CLEAR 0x01
2359 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00
2360
2361 /* Registers for function USB_OTG */
2362 #define PALMAS_USB_WAKEUP 0x03
2363 #define PALMAS_USB_VBUS_CTRL_SET 0x04
2364 #define PALMAS_USB_VBUS_CTRL_CLR 0x05
2365 #define PALMAS_USB_ID_CTRL_SET 0x06
2366 #define PALMAS_USB_ID_CTRL_CLEAR 0x07
2367 #define PALMAS_USB_VBUS_INT_SRC 0x08
2368 #define PALMAS_USB_VBUS_INT_LATCH_SET 0x09
2369 #define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A
2370 #define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B
2371 #define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C
2372 #define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D
2373 #define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E
2374 #define PALMAS_USB_ID_INT_SRC 0x0F
2375 #define PALMAS_USB_ID_INT_LATCH_SET 0x10
2376 #define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2377 #define PALMAS_USB_ID_INT_EN_LO_SET 0x12
2378 #define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
2379 #define PALMAS_USB_ID_INT_EN_HI_SET 0x14
2380 #define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2381 #define PALMAS_USB_OTG_ADP_CTRL 0x16
2382 #define PALMAS_USB_OTG_ADP_HIGH 0x17
2383 #define PALMAS_USB_OTG_ADP_LOW 0x18
2384 #define PALMAS_USB_OTG_ADP_RISE 0x19
2385 #define PALMAS_USB_OTG_REVISION 0x1A
2386
2387 /* Bit definitions for USB_WAKEUP */
2388 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2389 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00
2390
2391 /* Bit definitions for USB_VBUS_CTRL_SET */
2392 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2393 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07
2394 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2395 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05
2396 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2397 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04
2398 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2399 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03
2400 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2401 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02
2402
2403 /* Bit definitions for USB_VBUS_CTRL_CLR */
2404 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2405 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07
2406 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2407 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05
2408 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2409 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04
2410 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2411 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03
2412 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2413 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02
2414
2415 /* Bit definitions for USB_ID_CTRL_SET */
2416 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2417 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07
2418 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2419 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06
2420 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2421 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05
2422 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2423 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04
2424 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2425 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03
2426 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2427 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02
2428
2429 /* Bit definitions for USB_ID_CTRL_CLEAR */
2430 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2431 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07
2432 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2433 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06
2434 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2435 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05
2436 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2437 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04
2438 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2439 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03
2440 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2441 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02
2442
2443 /* Bit definitions for USB_VBUS_INT_SRC */
2444 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2445 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07
2446 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2447 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06
2448 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2449 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05
2450 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2451 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03
2452 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2453 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02
2454 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2455 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01
2456 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2457 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00
2458
2459 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2460 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2461 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07
2462 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2463 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06
2464 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2465 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05
2466 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2467 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04
2468 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2469 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03
2470 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2471 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02
2472 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2473 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01
2474 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2475 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00
2476
2477 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2478 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2479 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07
2480 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2481 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06
2482 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2483 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05
2484 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2485 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04
2486 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2487 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03
2488 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2489 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02
2490 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2491 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01
2492 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2493 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00
2494
2495 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2496 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2497 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07
2498 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2499 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06
2500 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2501 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05
2502 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2503 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03
2504 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2505 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02
2506 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2507 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01
2508 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2509 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00
2510
2511 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2512 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2513 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07
2514 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2515 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06
2516 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2517 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05
2518 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2519 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03
2520 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2521 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02
2522 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2523 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01
2524 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2525 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00
2526
2527 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2528 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2529 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07
2530 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2531 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06
2532 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2533 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05
2534 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2535 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04
2536 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2537 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03
2538 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2539 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02
2540 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2541 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01
2542 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2543 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00
2544
2545 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2546 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2547 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07
2548 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2549 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06
2550 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2551 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05
2552 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2553 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04
2554 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2555 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03
2556 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2557 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02
2558 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2559 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01
2560 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2561 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00
2562
2563 /* Bit definitions for USB_ID_INT_SRC */
2564 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2565 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04
2566 #define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2567 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03
2568 #define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2569 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02
2570 #define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2571 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01
2572 #define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2573 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00
2574
2575 /* Bit definitions for USB_ID_INT_LATCH_SET */
2576 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2577 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04
2578 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2579 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03
2580 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2581 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02
2582 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2583 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01
2584 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2585 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00
2586
2587 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2588 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2589 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04
2590 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2591 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03
2592 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2593 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02
2594 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2595 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01
2596 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2597 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00
2598
2599 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2600 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2601 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04
2602 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2603 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03
2604 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2605 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02
2606 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2607 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01
2608 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2609 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00
2610
2611 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2612 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2613 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04
2614 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2615 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03
2616 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2617 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02
2618 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2619 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01
2620 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2621 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00
2622
2623 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2624 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2625 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04
2626 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2627 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03
2628 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2629 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02
2630 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2631 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01
2632 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2633 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00
2634
2635 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2636 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2637 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04
2638 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2639 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03
2640 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2641 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02
2642 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2643 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01
2644 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2645 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00
2646
2647 /* Bit definitions for USB_OTG_ADP_CTRL */
2648 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2649 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02
2650 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2651 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00
2652
2653 /* Bit definitions for USB_OTG_ADP_HIGH */
2654 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF
2655 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00
2656
2657 /* Bit definitions for USB_OTG_ADP_LOW */
2658 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF
2659 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00
2660
2661 /* Bit definitions for USB_OTG_ADP_RISE */
2662 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF
2663 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00
2664
2665 /* Bit definitions for USB_OTG_REVISION */
2666 #define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2667 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00
2668
2669 /* Registers for function VIBRATOR */
2670 #define PALMAS_VIBRA_CTRL 0x00
2671
2672 /* Bit definitions for VIBRA_CTRL */
2673 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2674 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01
2675 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2676 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00
2677
2678 /* Registers for function GPIO */
2679 #define PALMAS_GPIO_DATA_IN 0x00
2680 #define PALMAS_GPIO_DATA_DIR 0x01
2681 #define PALMAS_GPIO_DATA_OUT 0x02
2682 #define PALMAS_GPIO_DEBOUNCE_EN 0x03
2683 #define PALMAS_GPIO_CLEAR_DATA_OUT 0x04
2684 #define PALMAS_GPIO_SET_DATA_OUT 0x05
2685 #define PALMAS_PU_PD_GPIO_CTRL1 0x06
2686 #define PALMAS_PU_PD_GPIO_CTRL2 0x07
2687 #define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08
2688 #define PALMAS_GPIO_DATA_IN2 0x09
2689 #define PALMAS_GPIO_DATA_DIR2 0x0A
2690 #define PALMAS_GPIO_DATA_OUT2 0x0B
2691 #define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
2692 #define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D
2693 #define PALMAS_GPIO_SET_DATA_OUT2 0x0E
2694 #define PALMAS_PU_PD_GPIO_CTRL3 0x0F
2695 #define PALMAS_PU_PD_GPIO_CTRL4 0x10
2696 #define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11
2697
2698 /* Bit definitions for GPIO_DATA_IN */
2699 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2700 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07
2701 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2702 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06
2703 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2704 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05
2705 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2706 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04
2707 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2708 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03
2709 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2710 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02
2711 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2712 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01
2713 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2714 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00
2715
2716 /* Bit definitions for GPIO_DATA_DIR */
2717 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2718 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07
2719 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2720 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06
2721 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2722 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05
2723 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2724 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04
2725 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2726 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03
2727 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2728 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02
2729 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2730 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01
2731 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2732 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00
2733
2734 /* Bit definitions for GPIO_DATA_OUT */
2735 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2736 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07
2737 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2738 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06
2739 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2740 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05
2741 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2742 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04
2743 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2744 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03
2745 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2746 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02
2747 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2748 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01
2749 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2750 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00
2751
2752 /* Bit definitions for GPIO_DEBOUNCE_EN */
2753 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2754 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07
2755 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2756 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06
2757 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2758 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05
2759 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2760 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04
2761 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2762 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03
2763 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2764 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02
2765 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2766 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01
2767 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2768 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00
2769
2770 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2771 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2772 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07
2773 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2774 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06
2775 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2776 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05
2777 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2778 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04
2779 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2780 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03
2781 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2782 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02
2783 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2784 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01
2785 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2786 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00
2787
2788 /* Bit definitions for GPIO_SET_DATA_OUT */
2789 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2790 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07
2791 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2792 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06
2793 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2794 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05
2795 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2796 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04
2797 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2798 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03
2799 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2800 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02
2801 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2802 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01
2803 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2804 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00
2805
2806 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2807 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2808 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06
2809 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2810 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05
2811 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2812 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04
2813 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2814 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03
2815 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2816 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02
2817 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2818 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00
2819
2820 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2821 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2822 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06
2823 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2824 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05
2825 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2826 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04
2827 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2828 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03
2829 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2830 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02
2831 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2832 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01
2833 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2834 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00
2835
2836 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2837 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2838 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05
2839 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2840 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02
2841 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2842 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01
2843
2844 /* Registers for function GPADC */
2845 #define PALMAS_GPADC_CTRL1 0x00
2846 #define PALMAS_GPADC_CTRL2 0x01
2847 #define PALMAS_GPADC_RT_CTRL 0x02
2848 #define PALMAS_GPADC_AUTO_CTRL 0x03
2849 #define PALMAS_GPADC_STATUS 0x04
2850 #define PALMAS_GPADC_RT_SELECT 0x05
2851 #define PALMAS_GPADC_RT_CONV0_LSB 0x06
2852 #define PALMAS_GPADC_RT_CONV0_MSB 0x07
2853 #define PALMAS_GPADC_AUTO_SELECT 0x08
2854 #define PALMAS_GPADC_AUTO_CONV0_LSB 0x09
2855 #define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A
2856 #define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B
2857 #define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C
2858 #define PALMAS_GPADC_SW_SELECT 0x0D
2859 #define PALMAS_GPADC_SW_CONV0_LSB 0x0E
2860 #define PALMAS_GPADC_SW_CONV0_MSB 0x0F
2861 #define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2862 #define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2863 #define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2864 #define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2865 #define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2866 #define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2867
2868 /* Bit definitions for GPADC_CTRL1 */
2869 #define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2870 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06
2871 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2872 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04
2873 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2874 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02
2875 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2876 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01
2877 #define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2878 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00
2879
2880 /* Bit definitions for GPADC_CTRL2 */
2881 #define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2882 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01
2883
2884 /* Bit definitions for GPADC_RT_CTRL */
2885 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2886 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01
2887 #define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2888 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00
2889
2890 /* Bit definitions for GPADC_AUTO_CTRL */
2891 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2892 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07
2893 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2894 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06
2895 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2896 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05
2897 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2898 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04
2899 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F
2900 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00
2901
2902 /* Bit definitions for GPADC_STATUS */
2903 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2904 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04
2905
2906 /* Bit definitions for GPADC_RT_SELECT */
2907 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2908 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07
2909 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F
2910 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00
2911
2912 /* Bit definitions for GPADC_RT_CONV0_LSB */
2913 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF
2914 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00
2915
2916 /* Bit definitions for GPADC_RT_CONV0_MSB */
2917 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F
2918 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00
2919
2920 /* Bit definitions for GPADC_AUTO_SELECT */
2921 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0
2922 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04
2923 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F
2924 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00
2925
2926 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2927 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF
2928 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00
2929
2930 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2931 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F
2932 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00
2933
2934 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2935 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF
2936 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00
2937
2938 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2939 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F
2940 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00
2941
2942 /* Bit definitions for GPADC_SW_SELECT */
2943 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2944 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07
2945 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2946 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04
2947 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F
2948 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00
2949
2950 /* Bit definitions for GPADC_SW_CONV0_LSB */
2951 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF
2952 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00
2953
2954 /* Bit definitions for GPADC_SW_CONV0_MSB */
2955 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F
2956 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00
2957
2958 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2959 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF
2960 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00
2961
2962 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2963 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2964 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07
2965 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F
2966 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00
2967
2968 /* Bit definitions for GPADC_THRES_CONV1_LSB */
2969 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF
2970 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00
2971
2972 /* Bit definitions for GPADC_THRES_CONV1_MSB */
2973 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
2974 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07
2975 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F
2976 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00
2977
2978 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2979 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
2980 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05
2981 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
2982 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04
2983 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F
2984 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00
2985
2986 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2987 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
2988 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07
2989 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F
2990 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00
2991
2992 /* Registers for function GPADC */
2993 #define PALMAS_GPADC_TRIM1 0x00
2994 #define PALMAS_GPADC_TRIM2 0x01
2995 #define PALMAS_GPADC_TRIM3 0x02
2996 #define PALMAS_GPADC_TRIM4 0x03
2997 #define PALMAS_GPADC_TRIM5 0x04
2998 #define PALMAS_GPADC_TRIM6 0x05
2999 #define PALMAS_GPADC_TRIM7 0x06
3000 #define PALMAS_GPADC_TRIM8 0x07
3001 #define PALMAS_GPADC_TRIM9 0x08
3002 #define PALMAS_GPADC_TRIM10 0x09
3003 #define PALMAS_GPADC_TRIM11 0x0A
3004 #define PALMAS_GPADC_TRIM12 0x0B
3005 #define PALMAS_GPADC_TRIM13 0x0C
3006 #define PALMAS_GPADC_TRIM14 0x0D
3007 #define PALMAS_GPADC_TRIM15 0x0E
3008 #define PALMAS_GPADC_TRIM16 0x0F
3009
3010 /* TPS659038 regen2_ctrl offset iss different from palmas */
3011 #define TPS659038_REGEN2_CTRL 0x12
3012
3013 /* TPS65917 Interrupt registers */
3014
3015 /* Registers for function INTERRUPT */
3016 #define TPS65917_INT1_STATUS 0x00
3017 #define TPS65917_INT1_MASK 0x01
3018 #define TPS65917_INT1_LINE_STATE 0x02
3019 #define TPS65917_INT2_STATUS 0x05
3020 #define TPS65917_INT2_MASK 0x06
3021 #define TPS65917_INT2_LINE_STATE 0x07
3022 #define TPS65917_INT3_STATUS 0x0A
3023 #define TPS65917_INT3_MASK 0x0B
3024 #define TPS65917_INT3_LINE_STATE 0x0C
3025 #define TPS65917_INT4_STATUS 0x0F
3026 #define TPS65917_INT4_MASK 0x10
3027 #define TPS65917_INT4_LINE_STATE 0x11
3028 #define TPS65917_INT4_EDGE_DETECT1 0x12
3029 #define TPS65917_INT4_EDGE_DETECT2 0x13
3030 #define TPS65917_INT_CTRL 0x14
3031
3032 /* Bit definitions for INT1_STATUS */
3033 #define TPS65917_INT1_STATUS_VSYS_MON 0x40
3034 #define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06
3035 #define TPS65917_INT1_STATUS_HOTDIE 0x20
3036 #define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05
3037 #define TPS65917_INT1_STATUS_PWRDOWN 0x10
3038 #define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04
3039 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04
3040 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
3041 #define TPS65917_INT1_STATUS_PWRON 0x02
3042 #define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01
3043
3044 /* Bit definitions for INT1_MASK */
3045 #define TPS65917_INT1_MASK_VSYS_MON 0x40
3046 #define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06
3047 #define TPS65917_INT1_MASK_HOTDIE 0x20
3048 #define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05
3049 #define TPS65917_INT1_MASK_PWRDOWN 0x10
3050 #define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04
3051 #define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04
3052 #define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
3053 #define TPS65917_INT1_MASK_PWRON 0x02
3054 #define TPS65917_INT1_MASK_PWRON_SHIFT 0x01
3055
3056 /* Bit definitions for INT1_LINE_STATE */
3057 #define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40
3058 #define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
3059 #define TPS65917_INT1_LINE_STATE_HOTDIE 0x20
3060 #define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
3061 #define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10
3062 #define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
3063 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
3064 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
3065 #define TPS65917_INT1_LINE_STATE_PWRON 0x02
3066 #define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01
3067
3068 /* Bit definitions for INT2_STATUS */
3069 #define TPS65917_INT2_STATUS_SHORT 0x40
3070 #define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06
3071 #define TPS65917_INT2_STATUS_FSD 0x20
3072 #define TPS65917_INT2_STATUS_FSD_SHIFT 0x05
3073 #define TPS65917_INT2_STATUS_RESET_IN 0x10
3074 #define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04
3075 #define TPS65917_INT2_STATUS_WDT 0x04
3076 #define TPS65917_INT2_STATUS_WDT_SHIFT 0x02
3077 #define TPS65917_INT2_STATUS_OTP_ERROR 0x02
3078 #define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01
3079
3080 /* Bit definitions for INT2_MASK */
3081 #define TPS65917_INT2_MASK_SHORT 0x40
3082 #define TPS65917_INT2_MASK_SHORT_SHIFT 0x06
3083 #define TPS65917_INT2_MASK_FSD 0x20
3084 #define TPS65917_INT2_MASK_FSD_SHIFT 0x05
3085 #define TPS65917_INT2_MASK_RESET_IN 0x10
3086 #define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04
3087 #define TPS65917_INT2_MASK_WDT 0x04
3088 #define TPS65917_INT2_MASK_WDT_SHIFT 0x02
3089 #define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02
3090 #define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01
3091
3092 /* Bit definitions for INT2_LINE_STATE */
3093 #define TPS65917_INT2_LINE_STATE_SHORT 0x40
3094 #define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06
3095 #define TPS65917_INT2_LINE_STATE_FSD 0x20
3096 #define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05
3097 #define TPS65917_INT2_LINE_STATE_RESET_IN 0x10
3098 #define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
3099 #define TPS65917_INT2_LINE_STATE_WDT 0x04
3100 #define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02
3101 #define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02
3102 #define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01
3103
3104 /* Bit definitions for INT3_STATUS */
3105 #define TPS65917_INT3_STATUS_VBUS 0x80
3106 #define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07
3107 #define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04
3108 #define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
3109 #define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02
3110 #define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
3111 #define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01
3112 #define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
3113
3114 /* Bit definitions for INT3_MASK */
3115 #define TPS65917_INT3_MASK_VBUS 0x80
3116 #define TPS65917_INT3_MASK_VBUS_SHIFT 0x07
3117 #define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04
3118 #define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
3119 #define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02
3120 #define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
3121 #define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01
3122 #define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
3123
3124 /* Bit definitions for INT3_LINE_STATE */
3125 #define TPS65917_INT3_LINE_STATE_VBUS 0x80
3126 #define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07
3127 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04
3128 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
3129 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02
3130 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
3131 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01
3132 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
3133
3134 /* Bit definitions for INT4_STATUS */
3135 #define TPS65917_INT4_STATUS_GPIO_6 0x40
3136 #define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06
3137 #define TPS65917_INT4_STATUS_GPIO_5 0x20
3138 #define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05
3139 #define TPS65917_INT4_STATUS_GPIO_4 0x10
3140 #define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04
3141 #define TPS65917_INT4_STATUS_GPIO_3 0x08
3142 #define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03
3143 #define TPS65917_INT4_STATUS_GPIO_2 0x04
3144 #define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02
3145 #define TPS65917_INT4_STATUS_GPIO_1 0x02
3146 #define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01
3147 #define TPS65917_INT4_STATUS_GPIO_0 0x01
3148 #define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00
3149
3150 /* Bit definitions for INT4_MASK */
3151 #define TPS65917_INT4_MASK_GPIO_6 0x40
3152 #define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06
3153 #define TPS65917_INT4_MASK_GPIO_5 0x20
3154 #define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05
3155 #define TPS65917_INT4_MASK_GPIO_4 0x10
3156 #define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04
3157 #define TPS65917_INT4_MASK_GPIO_3 0x08
3158 #define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03
3159 #define TPS65917_INT4_MASK_GPIO_2 0x04
3160 #define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02
3161 #define TPS65917_INT4_MASK_GPIO_1 0x02
3162 #define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01
3163 #define TPS65917_INT4_MASK_GPIO_0 0x01
3164 #define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00
3165
3166 /* Bit definitions for INT4_LINE_STATE */
3167 #define TPS65917_INT4_LINE_STATE_GPIO_6 0x40
3168 #define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
3169 #define TPS65917_INT4_LINE_STATE_GPIO_5 0x20
3170 #define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
3171 #define TPS65917_INT4_LINE_STATE_GPIO_4 0x10
3172 #define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
3173 #define TPS65917_INT4_LINE_STATE_GPIO_3 0x08
3174 #define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
3175 #define TPS65917_INT4_LINE_STATE_GPIO_2 0x04
3176 #define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
3177 #define TPS65917_INT4_LINE_STATE_GPIO_1 0x02
3178 #define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
3179 #define TPS65917_INT4_LINE_STATE_GPIO_0 0x01
3180 #define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
3181
3182 /* Bit definitions for INT4_EDGE_DETECT1 */
3183 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
3184 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
3185 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
3186 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
3187 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
3188 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
3189 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
3190 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
3191 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
3192 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
3193 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
3194 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
3195 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
3196 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
3197 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
3198 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
3199
3200 /* Bit definitions for INT4_EDGE_DETECT2 */
3201 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
3202 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
3203 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
3204 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
3205 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
3206 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
3207 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
3208 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
3209 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
3210 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
3211 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
3212 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
3213
3214 /* Bit definitions for INT_CTRL */
3215 #define TPS65917_INT_CTRL_INT_PENDING 0x04
3216 #define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02
3217 #define TPS65917_INT_CTRL_INT_CLEAR 0x01
3218 #define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00
3219
3220 /* TPS65917 SMPS Registers */
3221
3222 /* Registers for function SMPS */
3223 #define TPS65917_SMPS1_CTRL 0x00
3224 #define TPS65917_SMPS1_FORCE 0x02
3225 #define TPS65917_SMPS1_VOLTAGE 0x03
3226 #define TPS65917_SMPS2_CTRL 0x04
3227 #define TPS65917_SMPS2_FORCE 0x06
3228 #define TPS65917_SMPS2_VOLTAGE 0x07
3229 #define TPS65917_SMPS3_CTRL 0x0C
3230 #define TPS65917_SMPS3_FORCE 0x0E
3231 #define TPS65917_SMPS3_VOLTAGE 0x0F
3232 #define TPS65917_SMPS4_CTRL 0x10
3233 #define TPS65917_SMPS4_VOLTAGE 0x13
3234 #define TPS65917_SMPS5_CTRL 0x18
3235 #define TPS65917_SMPS5_VOLTAGE 0x1B
3236 #define TPS65917_SMPS_CTRL 0x24
3237 #define TPS65917_SMPS_PD_CTRL 0x25
3238 #define TPS65917_SMPS_THERMAL_EN 0x27
3239 #define TPS65917_SMPS_THERMAL_STATUS 0x28
3240 #define TPS65917_SMPS_SHORT_STATUS 0x29
3241 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
3242 #define TPS65917_SMPS_POWERGOOD_MASK1 0x2B
3243 #define TPS65917_SMPS_POWERGOOD_MASK2 0x2C
3244
3245 /* Bit definitions for SMPS1_CTRL */
3246 #define TPS65917_SMPS1_CTRL_WR_S 0x80
3247 #define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07
3248 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40
3249 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3250 #define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30
3251 #define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04
3252 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C
3253 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02
3254 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03
3255 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00
3256
3257 /* Bit definitions for SMPS1_FORCE */
3258 #define TPS65917_SMPS1_FORCE_CMD 0x80
3259 #define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07
3260 #define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F
3261 #define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00
3262
3263 /* Bit definitions for SMPS1_VOLTAGE */
3264 #define TPS65917_SMPS1_VOLTAGE_RANGE 0x80
3265 #define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07
3266 #define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F
3267 #define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00
3268
3269 /* Bit definitions for SMPS2_CTRL */
3270 #define TPS65917_SMPS2_CTRL_WR_S 0x80
3271 #define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07
3272 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40
3273 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3274 #define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30
3275 #define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04
3276 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C
3277 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02
3278 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03
3279 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00
3280
3281 /* Bit definitions for SMPS2_FORCE */
3282 #define TPS65917_SMPS2_FORCE_CMD 0x80
3283 #define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07
3284 #define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F
3285 #define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00
3286
3287 /* Bit definitions for SMPS2_VOLTAGE */
3288 #define TPS65917_SMPS2_VOLTAGE_RANGE 0x80
3289 #define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07
3290 #define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F
3291 #define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00
3292
3293 /* Bit definitions for SMPS3_CTRL */
3294 #define TPS65917_SMPS3_CTRL_WR_S 0x80
3295 #define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07
3296 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40
3297 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3298 #define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30
3299 #define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04
3300 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C
3301 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
3302 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
3303 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
3304
3305 /* Bit definitions for SMPS3_FORCE */
3306 #define TPS65917_SMPS3_FORCE_CMD 0x80
3307 #define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07
3308 #define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F
3309 #define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00
3310
3311 /* Bit definitions for SMPS3_VOLTAGE */
3312 #define TPS65917_SMPS3_VOLTAGE_RANGE 0x80
3313 #define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
3314 #define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F
3315 #define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
3316
3317 /* Bit definitions for SMPS4_CTRL */
3318 #define TPS65917_SMPS4_CTRL_WR_S 0x80
3319 #define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07
3320 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40
3321 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3322 #define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30
3323 #define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04
3324 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C
3325 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02
3326 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03
3327 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00
3328
3329 /* Bit definitions for SMPS4_VOLTAGE */
3330 #define TPS65917_SMPS4_VOLTAGE_RANGE 0x80
3331 #define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07
3332 #define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F
3333 #define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00
3334
3335 /* Bit definitions for SMPS5_CTRL */
3336 #define TPS65917_SMPS5_CTRL_WR_S 0x80
3337 #define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07
3338 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40
3339 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3340 #define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30
3341 #define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04
3342 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C
3343 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02
3344 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03
3345 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00
3346
3347 /* Bit definitions for SMPS5_VOLTAGE */
3348 #define TPS65917_SMPS5_VOLTAGE_RANGE 0x80
3349 #define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07
3350 #define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F
3351 #define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00
3352
3353 /* Bit definitions for SMPS_CTRL */
3354 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10
3355 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04
3356 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03
3357 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00
3358
3359 /* Bit definitions for SMPS_PD_CTRL */
3360 #define TPS65917_SMPS_PD_CTRL_SMPS5 0x40
3361 #define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06
3362 #define TPS65917_SMPS_PD_CTRL_SMPS4 0x10
3363 #define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04
3364 #define TPS65917_SMPS_PD_CTRL_SMPS3 0x08
3365 #define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03
3366 #define TPS65917_SMPS_PD_CTRL_SMPS2 0x02
3367 #define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01
3368 #define TPS65917_SMPS_PD_CTRL_SMPS1 0x01
3369 #define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00
3370
3371 /* Bit definitions for SMPS_THERMAL_EN */
3372 #define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40
3373 #define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06
3374 #define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08
3375 #define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03
3376 #define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01
3377 #define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00
3378
3379 /* Bit definitions for SMPS_THERMAL_STATUS */
3380 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40
3381 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06
3382 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08
3383 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03
3384 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01
3385 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00
3386
3387 /* Bit definitions for SMPS_SHORT_STATUS */
3388 #define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40
3389 #define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06
3390 #define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10
3391 #define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04
3392 #define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08
3393 #define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03
3394 #define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02
3395 #define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01
3396 #define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01
3397 #define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00
3398
3399 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
3400 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40
3401 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06
3402 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10
3403 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04
3404 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08
3405 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03
3406 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02
3407 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01
3408 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01
3409 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00
3410
3411 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
3412 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40
3413 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06
3414 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10
3415 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04
3416 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08
3417 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03
3418 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02
3419 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01
3420 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01
3421 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00
3422
3423 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
3424 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
3425 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
3426 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10
3427 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04
3428
3429 /* Bit definitions for SMPS_PLL_CTRL */
3430
3431 #define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08
3432 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03
3433 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04
3434 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02
3435
3436 /* Registers for function LDO */
3437 #define TPS65917_LDO1_CTRL 0x00
3438 #define TPS65917_LDO1_VOLTAGE 0x01
3439 #define TPS65917_LDO2_CTRL 0x02
3440 #define TPS65917_LDO2_VOLTAGE 0x03
3441 #define TPS65917_LDO3_CTRL 0x04
3442 #define TPS65917_LDO3_VOLTAGE 0x05
3443 #define TPS65917_LDO4_CTRL 0x0E
3444 #define TPS65917_LDO4_VOLTAGE 0x0F
3445 #define TPS65917_LDO5_CTRL 0x12
3446 #define TPS65917_LDO5_VOLTAGE 0x13
3447 #define TPS65917_LDO_PD_CTRL1 0x1B
3448 #define TPS65917_LDO_PD_CTRL2 0x1C
3449 #define TPS65917_LDO_SHORT_STATUS1 0x1D
3450 #define TPS65917_LDO_SHORT_STATUS2 0x1E
3451 #define TPS65917_LDO_PD_CTRL3 0x2D
3452 #define TPS65917_LDO_SHORT_STATUS3 0x2E
3453
3454 /* Bit definitions for LDO1_CTRL */
3455 #define TPS65917_LDO1_CTRL_WR_S 0x80
3456 #define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07
3457 #define TPS65917_LDO1_CTRL_BYPASS_EN 0x40
3458 #define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06
3459 #define TPS65917_LDO1_CTRL_STATUS 0x10
3460 #define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04
3461 #define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04
3462 #define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
3463 #define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01
3464 #define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
3465
3466 /* Bit definitions for LDO1_VOLTAGE */
3467 #define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F
3468 #define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00
3469
3470 /* Bit definitions for LDO2_CTRL */
3471 #define TPS65917_LDO2_CTRL_WR_S 0x80
3472 #define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07
3473 #define TPS65917_LDO2_CTRL_BYPASS_EN 0x40
3474 #define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06
3475 #define TPS65917_LDO2_CTRL_STATUS 0x10
3476 #define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04
3477 #define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04
3478 #define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
3479 #define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01
3480 #define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
3481
3482 /* Bit definitions for LDO2_VOLTAGE */
3483 #define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F
3484 #define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00
3485
3486 /* Bit definitions for LDO3_CTRL */
3487 #define TPS65917_LDO3_CTRL_WR_S 0x80
3488 #define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07
3489 #define TPS65917_LDO3_CTRL_STATUS 0x10
3490 #define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04
3491 #define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04
3492 #define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
3493 #define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01
3494 #define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
3495
3496 /* Bit definitions for LDO3_VOLTAGE */
3497 #define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F
3498 #define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00
3499
3500 /* Bit definitions for LDO4_CTRL */
3501 #define TPS65917_LDO4_CTRL_WR_S 0x80
3502 #define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07
3503 #define TPS65917_LDO4_CTRL_STATUS 0x10
3504 #define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04
3505 #define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04
3506 #define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
3507 #define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01
3508 #define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
3509
3510 /* Bit definitions for LDO4_VOLTAGE */
3511 #define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F
3512 #define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00
3513
3514 /* Bit definitions for LDO5_CTRL */
3515 #define TPS65917_LDO5_CTRL_WR_S 0x80
3516 #define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07
3517 #define TPS65917_LDO5_CTRL_STATUS 0x10
3518 #define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04
3519 #define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04
3520 #define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
3521 #define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01
3522 #define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
3523
3524 /* Bit definitions for LDO5_VOLTAGE */
3525 #define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F
3526 #define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00
3527
3528 /* Bit definitions for LDO_PD_CTRL1 */
3529 #define TPS65917_LDO_PD_CTRL1_LDO4 0x80
3530 #define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07
3531 #define TPS65917_LDO_PD_CTRL1_LDO2 0x02
3532 #define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01
3533 #define TPS65917_LDO_PD_CTRL1_LDO1 0x01
3534 #define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00
3535
3536 /* Bit definitions for LDO_PD_CTRL2 */
3537 #define TPS65917_LDO_PD_CTRL2_LDO3 0x04
3538 #define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02
3539 #define TPS65917_LDO_PD_CTRL2_LDO5 0x02
3540 #define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01
3541
3542 /* Bit definitions for LDO_PD_CTRL3 */
3543 #define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80
3544 #define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07
3545
3546 /* Bit definitions for LDO_SHORT_STATUS1 */
3547 #define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80
3548 #define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07
3549 #define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02
3550 #define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
3551 #define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01
3552 #define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
3553
3554 /* Bit definitions for LDO_SHORT_STATUS2 */
3555 #define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04
3556 #define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02
3557 #define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02
3558 #define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01
3559
3560 /* Bit definitions for LDO_SHORT_STATUS2 */
3561 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80
3562 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07
3563
3564 /* Bit definitions for REGEN1_CTRL */
3565 #define TPS65917_REGEN1_CTRL_STATUS 0x10
3566 #define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04
3567 #define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04
3568 #define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
3569 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01
3570 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
3571
3572 /* Bit definitions for PLLEN_CTRL */
3573 #define TPS65917_PLLEN_CTRL_STATUS 0x10
3574 #define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04
3575 #define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04
3576 #define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02
3577 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01
3578 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00
3579
3580 /* Bit definitions for REGEN2_CTRL */
3581 #define TPS65917_REGEN2_CTRL_STATUS 0x10
3582 #define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04
3583 #define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04
3584 #define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
3585 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01
3586 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
3587
3588 /* Bit definitions for NSLEEP_RES_ASSIGN */
3589 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08
3590 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03
3591 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04
3592 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02
3593 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02
3594 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
3595 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01
3596 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
3597
3598 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
3599 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40
3600 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3601 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10
3602 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3603 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08
3604 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3605 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02
3606 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3607 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01
3608 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3609
3610 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
3611 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80
3612 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07
3613 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02
3614 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
3615 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01
3616 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
3617
3618 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
3619 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04
3620 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02
3621 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02
3622 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01
3623
3624 /* Bit definitions for ENABLE1_RES_ASSIGN */
3625 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08
3626 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03
3627 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04
3628 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02
3629 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02
3630 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
3631 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01
3632 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
3633
3634 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
3635 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40
3636 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3637 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10
3638 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3639 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08
3640 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3641 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02
3642 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3643 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01
3644 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3645
3646 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
3647 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80
3648 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07
3649 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02
3650 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
3651 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01
3652 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
3653
3654 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
3655 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04
3656 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02
3657 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02
3658 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01
3659
3660 /* Bit definitions for ENABLE2_RES_ASSIGN */
3661 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08
3662 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03
3663 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04
3664 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02
3665 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02
3666 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
3667 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01
3668 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
3669
3670 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
3671 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40
3672 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3673 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10
3674 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3675 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08
3676 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3677 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02
3678 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3679 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01
3680 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3681
3682 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
3683 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80
3684 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07
3685 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02
3686 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
3687 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01
3688 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
3689
3690 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
3691 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04
3692 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02
3693 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02
3694 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01
3695
3696 /* Bit definitions for REGEN3_CTRL */
3697 #define TPS65917_REGEN3_CTRL_STATUS 0x10
3698 #define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04
3699 #define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04
3700 #define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
3701 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01
3702 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
3703
3704 /* Registers for function RESOURCE */
3705 #define TPS65917_REGEN1_CTRL 0x2
3706 #define TPS65917_PLLEN_CTRL 0x3
3707 #define TPS65917_NSLEEP_RES_ASSIGN 0x6
3708 #define TPS65917_NSLEEP_SMPS_ASSIGN 0x7
3709 #define TPS65917_NSLEEP_LDO_ASSIGN1 0x8
3710 #define TPS65917_NSLEEP_LDO_ASSIGN2 0x9
3711 #define TPS65917_ENABLE1_RES_ASSIGN 0xA
3712 #define TPS65917_ENABLE1_SMPS_ASSIGN 0xB
3713 #define TPS65917_ENABLE1_LDO_ASSIGN1 0xC
3714 #define TPS65917_ENABLE1_LDO_ASSIGN2 0xD
3715 #define TPS65917_ENABLE2_RES_ASSIGN 0xE
3716 #define TPS65917_ENABLE2_SMPS_ASSIGN 0xF
3717 #define TPS65917_ENABLE2_LDO_ASSIGN1 0x10
3718 #define TPS65917_ENABLE2_LDO_ASSIGN2 0x11
3719 #define TPS65917_REGEN2_CTRL 0x12
3720 #define TPS65917_REGEN3_CTRL 0x13
3721
palmas_read(struct palmas * palmas,unsigned int base,unsigned int reg,unsigned int * val)3722 static inline int palmas_read(struct palmas *palmas, unsigned int base,
3723 unsigned int reg, unsigned int *val)
3724 {
3725 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3726 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3727
3728 return regmap_read(palmas->regmap[slave_id], addr, val);
3729 }
3730
palmas_write(struct palmas * palmas,unsigned int base,unsigned int reg,unsigned int value)3731 static inline int palmas_write(struct palmas *palmas, unsigned int base,
3732 unsigned int reg, unsigned int value)
3733 {
3734 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3735 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3736
3737 return regmap_write(palmas->regmap[slave_id], addr, value);
3738 }
3739
palmas_bulk_write(struct palmas * palmas,unsigned int base,unsigned int reg,const void * val,size_t val_count)3740 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
3741 unsigned int reg, const void *val, size_t val_count)
3742 {
3743 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3744 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3745
3746 return regmap_bulk_write(palmas->regmap[slave_id], addr,
3747 val, val_count);
3748 }
3749
palmas_bulk_read(struct palmas * palmas,unsigned int base,unsigned int reg,void * val,size_t val_count)3750 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
3751 unsigned int reg, void *val, size_t val_count)
3752 {
3753 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3754 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3755
3756 return regmap_bulk_read(palmas->regmap[slave_id], addr,
3757 val, val_count);
3758 }
3759
palmas_update_bits(struct palmas * palmas,unsigned int base,unsigned int reg,unsigned int mask,unsigned int val)3760 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
3761 unsigned int reg, unsigned int mask, unsigned int val)
3762 {
3763 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3764 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3765
3766 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
3767 }
3768
palmas_irq_get_virq(struct palmas * palmas,int irq)3769 static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
3770 {
3771 return regmap_irq_get_virq(palmas->irq_data, irq);
3772 }
3773
3774
3775 int palmas_ext_control_req_config(struct palmas *palmas,
3776 enum palmas_external_requestor_id ext_control_req_id,
3777 int ext_ctrl, bool enable);
3778
3779 #endif /* __LINUX_MFD_PALMAS_H */
3780