1 /* 2 * Definitions for the NVM Express interface 3 * Copyright (c) 2011-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef _UAPI_LINUX_NVME_H 16 #define _UAPI_LINUX_NVME_H 17 18 #include <linux/types.h> 19 20 struct nvme_id_power_state { 21 __le16 max_power; /* centiwatts */ 22 __u8 rsvd2; 23 __u8 flags; 24 __le32 entry_lat; /* microseconds */ 25 __le32 exit_lat; /* microseconds */ 26 __u8 read_tput; 27 __u8 read_lat; 28 __u8 write_tput; 29 __u8 write_lat; 30 __le16 idle_power; 31 __u8 idle_scale; 32 __u8 rsvd19; 33 __le16 active_power; 34 __u8 active_work_scale; 35 __u8 rsvd23[9]; 36 }; 37 38 enum { 39 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 40 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 41 }; 42 43 struct nvme_id_ctrl { 44 __le16 vid; 45 __le16 ssvid; 46 char sn[20]; 47 char mn[40]; 48 char fr[8]; 49 __u8 rab; 50 __u8 ieee[3]; 51 __u8 mic; 52 __u8 mdts; 53 __u16 cntlid; 54 __u32 ver; 55 __u8 rsvd84[172]; 56 __le16 oacs; 57 __u8 acl; 58 __u8 aerl; 59 __u8 frmw; 60 __u8 lpa; 61 __u8 elpe; 62 __u8 npss; 63 __u8 avscc; 64 __u8 apsta; 65 __le16 wctemp; 66 __le16 cctemp; 67 __u8 rsvd270[242]; 68 __u8 sqes; 69 __u8 cqes; 70 __u8 rsvd514[2]; 71 __le32 nn; 72 __le16 oncs; 73 __le16 fuses; 74 __u8 fna; 75 __u8 vwc; 76 __le16 awun; 77 __le16 awupf; 78 __u8 nvscc; 79 __u8 rsvd531; 80 __le16 acwu; 81 __u8 rsvd534[2]; 82 __le32 sgls; 83 __u8 rsvd540[1508]; 84 struct nvme_id_power_state psd[32]; 85 __u8 vs[1024]; 86 }; 87 88 enum { 89 NVME_CTRL_ONCS_COMPARE = 1 << 0, 90 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 91 NVME_CTRL_ONCS_DSM = 1 << 2, 92 NVME_CTRL_VWC_PRESENT = 1 << 0, 93 }; 94 95 struct nvme_lbaf { 96 __le16 ms; 97 __u8 ds; 98 __u8 rp; 99 }; 100 101 struct nvme_id_ns { 102 __le64 nsze; 103 __le64 ncap; 104 __le64 nuse; 105 __u8 nsfeat; 106 __u8 nlbaf; 107 __u8 flbas; 108 __u8 mc; 109 __u8 dpc; 110 __u8 dps; 111 __u8 nmic; 112 __u8 rescap; 113 __u8 fpi; 114 __u8 rsvd33; 115 __le16 nawun; 116 __le16 nawupf; 117 __le16 nacwu; 118 __le16 nabsn; 119 __le16 nabo; 120 __le16 nabspf; 121 __u16 rsvd46; 122 __le64 nvmcap[2]; 123 __u8 rsvd64[40]; 124 __u8 nguid[16]; 125 __u8 eui64[8]; 126 struct nvme_lbaf lbaf[16]; 127 __u8 rsvd192[192]; 128 __u8 vs[3712]; 129 }; 130 131 enum { 132 NVME_NS_FEAT_THIN = 1 << 0, 133 NVME_NS_FLBAS_LBA_MASK = 0xf, 134 NVME_NS_FLBAS_META_EXT = 0x10, 135 NVME_LBAF_RP_BEST = 0, 136 NVME_LBAF_RP_BETTER = 1, 137 NVME_LBAF_RP_GOOD = 2, 138 NVME_LBAF_RP_DEGRADED = 3, 139 NVME_NS_DPC_PI_LAST = 1 << 4, 140 NVME_NS_DPC_PI_FIRST = 1 << 3, 141 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 142 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 143 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 144 NVME_NS_DPS_PI_FIRST = 1 << 3, 145 NVME_NS_DPS_PI_MASK = 0x7, 146 NVME_NS_DPS_PI_TYPE1 = 1, 147 NVME_NS_DPS_PI_TYPE2 = 2, 148 NVME_NS_DPS_PI_TYPE3 = 3, 149 }; 150 151 struct nvme_smart_log { 152 __u8 critical_warning; 153 __u8 temperature[2]; 154 __u8 avail_spare; 155 __u8 spare_thresh; 156 __u8 percent_used; 157 __u8 rsvd6[26]; 158 __u8 data_units_read[16]; 159 __u8 data_units_written[16]; 160 __u8 host_reads[16]; 161 __u8 host_writes[16]; 162 __u8 ctrl_busy_time[16]; 163 __u8 power_cycles[16]; 164 __u8 power_on_hours[16]; 165 __u8 unsafe_shutdowns[16]; 166 __u8 media_errors[16]; 167 __u8 num_err_log_entries[16]; 168 __le32 warning_temp_time; 169 __le32 critical_comp_time; 170 __le16 temp_sensor[8]; 171 __u8 rsvd216[296]; 172 }; 173 174 enum { 175 NVME_SMART_CRIT_SPARE = 1 << 0, 176 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 177 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 178 NVME_SMART_CRIT_MEDIA = 1 << 3, 179 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 180 }; 181 182 struct nvme_lba_range_type { 183 __u8 type; 184 __u8 attributes; 185 __u8 rsvd2[14]; 186 __u64 slba; 187 __u64 nlb; 188 __u8 guid[16]; 189 __u8 rsvd48[16]; 190 }; 191 192 enum { 193 NVME_LBART_TYPE_FS = 0x01, 194 NVME_LBART_TYPE_RAID = 0x02, 195 NVME_LBART_TYPE_CACHE = 0x03, 196 NVME_LBART_TYPE_SWAP = 0x04, 197 198 NVME_LBART_ATTRIB_TEMP = 1 << 0, 199 NVME_LBART_ATTRIB_HIDE = 1 << 1, 200 }; 201 202 struct nvme_reservation_status { 203 __le32 gen; 204 __u8 rtype; 205 __u8 regctl[2]; 206 __u8 resv5[2]; 207 __u8 ptpls; 208 __u8 resv10[13]; 209 struct { 210 __le16 cntlid; 211 __u8 rcsts; 212 __u8 resv3[5]; 213 __le64 hostid; 214 __le64 rkey; 215 } regctl_ds[]; 216 }; 217 218 /* I/O commands */ 219 220 enum nvme_opcode { 221 nvme_cmd_flush = 0x00, 222 nvme_cmd_write = 0x01, 223 nvme_cmd_read = 0x02, 224 nvme_cmd_write_uncor = 0x04, 225 nvme_cmd_compare = 0x05, 226 nvme_cmd_write_zeroes = 0x08, 227 nvme_cmd_dsm = 0x09, 228 nvme_cmd_resv_register = 0x0d, 229 nvme_cmd_resv_report = 0x0e, 230 nvme_cmd_resv_acquire = 0x11, 231 nvme_cmd_resv_release = 0x15, 232 }; 233 234 struct nvme_common_command { 235 __u8 opcode; 236 __u8 flags; 237 __u16 command_id; 238 __le32 nsid; 239 __le32 cdw2[2]; 240 __le64 metadata; 241 __le64 prp1; 242 __le64 prp2; 243 __le32 cdw10[6]; 244 }; 245 246 struct nvme_rw_command { 247 __u8 opcode; 248 __u8 flags; 249 __u16 command_id; 250 __le32 nsid; 251 __u64 rsvd2; 252 __le64 metadata; 253 __le64 prp1; 254 __le64 prp2; 255 __le64 slba; 256 __le16 length; 257 __le16 control; 258 __le32 dsmgmt; 259 __le32 reftag; 260 __le16 apptag; 261 __le16 appmask; 262 }; 263 264 enum { 265 NVME_RW_LR = 1 << 15, 266 NVME_RW_FUA = 1 << 14, 267 NVME_RW_DSM_FREQ_UNSPEC = 0, 268 NVME_RW_DSM_FREQ_TYPICAL = 1, 269 NVME_RW_DSM_FREQ_RARE = 2, 270 NVME_RW_DSM_FREQ_READS = 3, 271 NVME_RW_DSM_FREQ_WRITES = 4, 272 NVME_RW_DSM_FREQ_RW = 5, 273 NVME_RW_DSM_FREQ_ONCE = 6, 274 NVME_RW_DSM_FREQ_PREFETCH = 7, 275 NVME_RW_DSM_FREQ_TEMP = 8, 276 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 277 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 278 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 279 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 280 NVME_RW_DSM_SEQ_REQ = 1 << 6, 281 NVME_RW_DSM_COMPRESSED = 1 << 7, 282 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 283 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 284 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 285 NVME_RW_PRINFO_PRACT = 1 << 13, 286 }; 287 288 struct nvme_dsm_cmd { 289 __u8 opcode; 290 __u8 flags; 291 __u16 command_id; 292 __le32 nsid; 293 __u64 rsvd2[2]; 294 __le64 prp1; 295 __le64 prp2; 296 __le32 nr; 297 __le32 attributes; 298 __u32 rsvd12[4]; 299 }; 300 301 enum { 302 NVME_DSMGMT_IDR = 1 << 0, 303 NVME_DSMGMT_IDW = 1 << 1, 304 NVME_DSMGMT_AD = 1 << 2, 305 }; 306 307 struct nvme_dsm_range { 308 __le32 cattr; 309 __le32 nlb; 310 __le64 slba; 311 }; 312 313 /* Admin commands */ 314 315 enum nvme_admin_opcode { 316 nvme_admin_delete_sq = 0x00, 317 nvme_admin_create_sq = 0x01, 318 nvme_admin_get_log_page = 0x02, 319 nvme_admin_delete_cq = 0x04, 320 nvme_admin_create_cq = 0x05, 321 nvme_admin_identify = 0x06, 322 nvme_admin_abort_cmd = 0x08, 323 nvme_admin_set_features = 0x09, 324 nvme_admin_get_features = 0x0a, 325 nvme_admin_async_event = 0x0c, 326 nvme_admin_activate_fw = 0x10, 327 nvme_admin_download_fw = 0x11, 328 nvme_admin_format_nvm = 0x80, 329 nvme_admin_security_send = 0x81, 330 nvme_admin_security_recv = 0x82, 331 }; 332 333 enum { 334 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 335 NVME_CQ_IRQ_ENABLED = (1 << 1), 336 NVME_SQ_PRIO_URGENT = (0 << 1), 337 NVME_SQ_PRIO_HIGH = (1 << 1), 338 NVME_SQ_PRIO_MEDIUM = (2 << 1), 339 NVME_SQ_PRIO_LOW = (3 << 1), 340 NVME_FEAT_ARBITRATION = 0x01, 341 NVME_FEAT_POWER_MGMT = 0x02, 342 NVME_FEAT_LBA_RANGE = 0x03, 343 NVME_FEAT_TEMP_THRESH = 0x04, 344 NVME_FEAT_ERR_RECOVERY = 0x05, 345 NVME_FEAT_VOLATILE_WC = 0x06, 346 NVME_FEAT_NUM_QUEUES = 0x07, 347 NVME_FEAT_IRQ_COALESCE = 0x08, 348 NVME_FEAT_IRQ_CONFIG = 0x09, 349 NVME_FEAT_WRITE_ATOMIC = 0x0a, 350 NVME_FEAT_ASYNC_EVENT = 0x0b, 351 NVME_FEAT_AUTO_PST = 0x0c, 352 NVME_FEAT_SW_PROGRESS = 0x80, 353 NVME_FEAT_HOST_ID = 0x81, 354 NVME_FEAT_RESV_MASK = 0x82, 355 NVME_FEAT_RESV_PERSIST = 0x83, 356 NVME_LOG_ERROR = 0x01, 357 NVME_LOG_SMART = 0x02, 358 NVME_LOG_FW_SLOT = 0x03, 359 NVME_LOG_RESERVATION = 0x80, 360 NVME_FWACT_REPL = (0 << 3), 361 NVME_FWACT_REPL_ACTV = (1 << 3), 362 NVME_FWACT_ACTV = (2 << 3), 363 }; 364 365 struct nvme_identify { 366 __u8 opcode; 367 __u8 flags; 368 __u16 command_id; 369 __le32 nsid; 370 __u64 rsvd2[2]; 371 __le64 prp1; 372 __le64 prp2; 373 __le32 cns; 374 __u32 rsvd11[5]; 375 }; 376 377 struct nvme_features { 378 __u8 opcode; 379 __u8 flags; 380 __u16 command_id; 381 __le32 nsid; 382 __u64 rsvd2[2]; 383 __le64 prp1; 384 __le64 prp2; 385 __le32 fid; 386 __le32 dword11; 387 __u32 rsvd12[4]; 388 }; 389 390 struct nvme_create_cq { 391 __u8 opcode; 392 __u8 flags; 393 __u16 command_id; 394 __u32 rsvd1[5]; 395 __le64 prp1; 396 __u64 rsvd8; 397 __le16 cqid; 398 __le16 qsize; 399 __le16 cq_flags; 400 __le16 irq_vector; 401 __u32 rsvd12[4]; 402 }; 403 404 struct nvme_create_sq { 405 __u8 opcode; 406 __u8 flags; 407 __u16 command_id; 408 __u32 rsvd1[5]; 409 __le64 prp1; 410 __u64 rsvd8; 411 __le16 sqid; 412 __le16 qsize; 413 __le16 sq_flags; 414 __le16 cqid; 415 __u32 rsvd12[4]; 416 }; 417 418 struct nvme_delete_queue { 419 __u8 opcode; 420 __u8 flags; 421 __u16 command_id; 422 __u32 rsvd1[9]; 423 __le16 qid; 424 __u16 rsvd10; 425 __u32 rsvd11[5]; 426 }; 427 428 struct nvme_abort_cmd { 429 __u8 opcode; 430 __u8 flags; 431 __u16 command_id; 432 __u32 rsvd1[9]; 433 __le16 sqid; 434 __u16 cid; 435 __u32 rsvd11[5]; 436 }; 437 438 struct nvme_download_firmware { 439 __u8 opcode; 440 __u8 flags; 441 __u16 command_id; 442 __u32 rsvd1[5]; 443 __le64 prp1; 444 __le64 prp2; 445 __le32 numd; 446 __le32 offset; 447 __u32 rsvd12[4]; 448 }; 449 450 struct nvme_format_cmd { 451 __u8 opcode; 452 __u8 flags; 453 __u16 command_id; 454 __le32 nsid; 455 __u64 rsvd2[4]; 456 __le32 cdw10; 457 __u32 rsvd11[5]; 458 }; 459 460 struct nvme_command { 461 union { 462 struct nvme_common_command common; 463 struct nvme_rw_command rw; 464 struct nvme_identify identify; 465 struct nvme_features features; 466 struct nvme_create_cq create_cq; 467 struct nvme_create_sq create_sq; 468 struct nvme_delete_queue delete_queue; 469 struct nvme_download_firmware dlfw; 470 struct nvme_format_cmd format; 471 struct nvme_dsm_cmd dsm; 472 struct nvme_abort_cmd abort; 473 }; 474 }; 475 476 enum { 477 NVME_SC_SUCCESS = 0x0, 478 NVME_SC_INVALID_OPCODE = 0x1, 479 NVME_SC_INVALID_FIELD = 0x2, 480 NVME_SC_CMDID_CONFLICT = 0x3, 481 NVME_SC_DATA_XFER_ERROR = 0x4, 482 NVME_SC_POWER_LOSS = 0x5, 483 NVME_SC_INTERNAL = 0x6, 484 NVME_SC_ABORT_REQ = 0x7, 485 NVME_SC_ABORT_QUEUE = 0x8, 486 NVME_SC_FUSED_FAIL = 0x9, 487 NVME_SC_FUSED_MISSING = 0xa, 488 NVME_SC_INVALID_NS = 0xb, 489 NVME_SC_CMD_SEQ_ERROR = 0xc, 490 NVME_SC_SGL_INVALID_LAST = 0xd, 491 NVME_SC_SGL_INVALID_COUNT = 0xe, 492 NVME_SC_SGL_INVALID_DATA = 0xf, 493 NVME_SC_SGL_INVALID_METADATA = 0x10, 494 NVME_SC_SGL_INVALID_TYPE = 0x11, 495 NVME_SC_LBA_RANGE = 0x80, 496 NVME_SC_CAP_EXCEEDED = 0x81, 497 NVME_SC_NS_NOT_READY = 0x82, 498 NVME_SC_RESERVATION_CONFLICT = 0x83, 499 NVME_SC_CQ_INVALID = 0x100, 500 NVME_SC_QID_INVALID = 0x101, 501 NVME_SC_QUEUE_SIZE = 0x102, 502 NVME_SC_ABORT_LIMIT = 0x103, 503 NVME_SC_ABORT_MISSING = 0x104, 504 NVME_SC_ASYNC_LIMIT = 0x105, 505 NVME_SC_FIRMWARE_SLOT = 0x106, 506 NVME_SC_FIRMWARE_IMAGE = 0x107, 507 NVME_SC_INVALID_VECTOR = 0x108, 508 NVME_SC_INVALID_LOG_PAGE = 0x109, 509 NVME_SC_INVALID_FORMAT = 0x10a, 510 NVME_SC_FIRMWARE_NEEDS_RESET = 0x10b, 511 NVME_SC_INVALID_QUEUE = 0x10c, 512 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 513 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 514 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 515 NVME_SC_FW_NEEDS_RESET_SUBSYS = 0x110, 516 NVME_SC_BAD_ATTRIBUTES = 0x180, 517 NVME_SC_INVALID_PI = 0x181, 518 NVME_SC_READ_ONLY = 0x182, 519 NVME_SC_WRITE_FAULT = 0x280, 520 NVME_SC_READ_ERROR = 0x281, 521 NVME_SC_GUARD_CHECK = 0x282, 522 NVME_SC_APPTAG_CHECK = 0x283, 523 NVME_SC_REFTAG_CHECK = 0x284, 524 NVME_SC_COMPARE_FAILED = 0x285, 525 NVME_SC_ACCESS_DENIED = 0x286, 526 NVME_SC_DNR = 0x4000, 527 }; 528 529 struct nvme_completion { 530 __le32 result; /* Used by admin commands to return data */ 531 __u32 rsvd; 532 __le16 sq_head; /* how much of this queue may be reclaimed */ 533 __le16 sq_id; /* submission queue that generated this entry */ 534 __u16 command_id; /* of the command which completed */ 535 __le16 status; /* did the command fail, and if so, why? */ 536 }; 537 538 struct nvme_user_io { 539 __u8 opcode; 540 __u8 flags; 541 __u16 control; 542 __u16 nblocks; 543 __u16 rsvd; 544 __u64 metadata; 545 __u64 addr; 546 __u64 slba; 547 __u32 dsmgmt; 548 __u32 reftag; 549 __u16 apptag; 550 __u16 appmask; 551 }; 552 553 struct nvme_passthru_cmd { 554 __u8 opcode; 555 __u8 flags; 556 __u16 rsvd1; 557 __u32 nsid; 558 __u32 cdw2; 559 __u32 cdw3; 560 __u64 metadata; 561 __u64 addr; 562 __u32 metadata_len; 563 __u32 data_len; 564 __u32 cdw10; 565 __u32 cdw11; 566 __u32 cdw12; 567 __u32 cdw13; 568 __u32 cdw14; 569 __u32 cdw15; 570 __u32 timeout_ms; 571 __u32 result; 572 }; 573 574 #define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8)) 575 576 #define nvme_admin_cmd nvme_passthru_cmd 577 578 #define NVME_IOCTL_ID _IO('N', 0x40) 579 #define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd) 580 #define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io) 581 #define NVME_IOCTL_IO_CMD _IOWR('N', 0x43, struct nvme_passthru_cmd) 582 583 #endif /* _UAPI_LINUX_NVME_H */ 584