1 /*
2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #ifndef _LINUX_NVME_H
16 #define _LINUX_NVME_H
17
18 #include <uapi/linux/nvme.h>
19 #include <linux/pci.h>
20 #include <linux/kref.h>
21 #include <linux/blk-mq.h>
22
23 struct nvme_bar {
24 __u64 cap; /* Controller Capabilities */
25 __u32 vs; /* Version */
26 __u32 intms; /* Interrupt Mask Set */
27 __u32 intmc; /* Interrupt Mask Clear */
28 __u32 cc; /* Controller Configuration */
29 __u32 rsvd1; /* Reserved */
30 __u32 csts; /* Controller Status */
31 __u32 rsvd2; /* Reserved */
32 __u32 aqa; /* Admin Queue Attributes */
33 __u64 asq; /* Admin SQ Base Address */
34 __u64 acq; /* Admin CQ Base Address */
35 };
36
37 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
38 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
39 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
40 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
41 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
42
43 enum {
44 NVME_CC_ENABLE = 1 << 0,
45 NVME_CC_CSS_NVM = 0 << 4,
46 NVME_CC_MPS_SHIFT = 7,
47 NVME_CC_ARB_RR = 0 << 11,
48 NVME_CC_ARB_WRRU = 1 << 11,
49 NVME_CC_ARB_VS = 7 << 11,
50 NVME_CC_SHN_NONE = 0 << 14,
51 NVME_CC_SHN_NORMAL = 1 << 14,
52 NVME_CC_SHN_ABRUPT = 2 << 14,
53 NVME_CC_SHN_MASK = 3 << 14,
54 NVME_CC_IOSQES = 6 << 16,
55 NVME_CC_IOCQES = 4 << 20,
56 NVME_CSTS_RDY = 1 << 0,
57 NVME_CSTS_CFS = 1 << 1,
58 NVME_CSTS_SHST_NORMAL = 0 << 2,
59 NVME_CSTS_SHST_OCCUR = 1 << 2,
60 NVME_CSTS_SHST_CMPLT = 2 << 2,
61 NVME_CSTS_SHST_MASK = 3 << 2,
62 };
63
64 extern unsigned char nvme_io_timeout;
65 #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
66
67 /*
68 * Represents an NVM Express device. Each nvme_dev is a PCI function.
69 */
70 struct nvme_dev {
71 struct list_head node;
72 struct nvme_queue **queues;
73 struct request_queue *admin_q;
74 struct blk_mq_tag_set tagset;
75 struct blk_mq_tag_set admin_tagset;
76 u32 __iomem *dbs;
77 struct pci_dev *pci_dev;
78 struct dma_pool *prp_page_pool;
79 struct dma_pool *prp_small_pool;
80 int instance;
81 unsigned queue_count;
82 unsigned online_queues;
83 unsigned max_qid;
84 int q_depth;
85 u32 db_stride;
86 u32 ctrl_config;
87 struct msix_entry *entry;
88 struct nvme_bar __iomem *bar;
89 struct list_head namespaces;
90 struct kref kref;
91 struct device *device;
92 work_func_t reset_workfn;
93 struct work_struct reset_work;
94 struct work_struct probe_work;
95 char name[12];
96 char serial[20];
97 char model[40];
98 char firmware_rev[8];
99 u32 max_hw_sectors;
100 u32 stripe_size;
101 u32 page_size;
102 u16 oncs;
103 u16 abort_limit;
104 u8 event_limit;
105 u8 vwc;
106 };
107
108 /*
109 * An NVM Express namespace is equivalent to a SCSI LUN
110 */
111 struct nvme_ns {
112 struct list_head list;
113
114 struct nvme_dev *dev;
115 struct request_queue *queue;
116 struct gendisk *disk;
117
118 unsigned ns_id;
119 int lba_shift;
120 u16 ms;
121 bool ext;
122 u8 pi_type;
123 u64 mode_select_num_blocks;
124 u32 mode_select_block_len;
125 };
126
127 /*
128 * The nvme_iod describes the data in an I/O, including the list of PRP
129 * entries. You can't see it in this data structure because C doesn't let
130 * me express that. Use nvme_alloc_iod to ensure there's enough space
131 * allocated to store the PRP list.
132 */
133 struct nvme_iod {
134 unsigned long private; /* For the use of the submitter of the I/O */
135 int npages; /* In the PRP list. 0 means small pool in use */
136 int offset; /* Of PRP list */
137 int nents; /* Used in scatterlist */
138 int length; /* Of data, in bytes */
139 dma_addr_t first_dma;
140 struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
141 struct scatterlist sg[0];
142 };
143
nvme_block_nr(struct nvme_ns * ns,sector_t sector)144 static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
145 {
146 return (sector >> (ns->lba_shift - 9));
147 }
148
149 /**
150 * nvme_free_iod - frees an nvme_iod
151 * @dev: The device that the I/O was submitted to
152 * @iod: The memory to free
153 */
154 void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod);
155
156 int nvme_setup_prps(struct nvme_dev *, struct nvme_iod *, int, gfp_t);
157 struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
158 unsigned long addr, unsigned length);
159 void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
160 struct nvme_iod *iod);
161 int nvme_submit_io_cmd(struct nvme_dev *, struct nvme_ns *,
162 struct nvme_command *, u32 *);
163 int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns);
164 int nvme_submit_admin_cmd(struct nvme_dev *, struct nvme_command *,
165 u32 *result);
166 int nvme_identify(struct nvme_dev *, unsigned nsid, unsigned cns,
167 dma_addr_t dma_addr);
168 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
169 dma_addr_t dma_addr, u32 *result);
170 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
171 dma_addr_t dma_addr, u32 *result);
172
173 struct sg_io_hdr;
174
175 int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
176 int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
177 int nvme_sg_get_version_num(int __user *ip);
178
179 #endif /* _LINUX_NVME_H */
180