1 /* 2 * Include file for Gigabit Ethernet device driver for Network 3 * Interface Cards (NICs) utilizing the Tamarack Microelectronics 4 * Inc. IPG Gigabit or Triple Speed Ethernet Media Access 5 * Controller. 6 */ 7 #ifndef __LINUX_IPG_H 8 #define __LINUX_IPG_H 9 10 #include <linux/module.h> 11 12 #include <linux/kernel.h> 13 #include <linux/pci.h> 14 #include <linux/ioport.h> 15 #include <linux/errno.h> 16 #include <asm/io.h> 17 #include <linux/delay.h> 18 #include <linux/types.h> 19 #include <linux/netdevice.h> 20 #include <linux/etherdevice.h> 21 #include <linux/skbuff.h> 22 #include <asm/bitops.h> 23 24 /* 25 * Constants 26 */ 27 28 /* GMII based PHY IDs */ 29 #define NS 0x2000 30 #define MARVELL 0x0141 31 #define ICPLUS_PHY 0x243 32 33 /* NIC Physical Layer Device MII register fields. */ 34 #define MII_PHY_SELECTOR_IEEE8023 0x0001 35 #define MII_PHY_TECHABILITYFIELD 0x1FE0 36 37 /* GMII_PHY_1000 need to set to prefer master */ 38 #define GMII_PHY_1000BASETCONTROL_PreferMaster 0x0400 39 40 /* NIC Physical Layer Device GMII constants. */ 41 #define GMII_PREAMBLE 0xFFFFFFFF 42 #define GMII_ST 0x1 43 #define GMII_READ 0x2 44 #define GMII_WRITE 0x1 45 #define GMII_TA_READ_MASK 0x1 46 #define GMII_TA_WRITE 0x2 47 48 /* I/O register offsets. */ 49 enum ipg_regs { 50 DMA_CTRL = 0x00, 51 RX_DMA_STATUS = 0x08, /* Unused + reserved */ 52 TFD_LIST_PTR_0 = 0x10, 53 TFD_LIST_PTR_1 = 0x14, 54 TX_DMA_BURST_THRESH = 0x18, 55 TX_DMA_URGENT_THRESH = 0x19, 56 TX_DMA_POLL_PERIOD = 0x1a, 57 RFD_LIST_PTR_0 = 0x1c, 58 RFD_LIST_PTR_1 = 0x20, 59 RX_DMA_BURST_THRESH = 0x24, 60 RX_DMA_URGENT_THRESH = 0x25, 61 RX_DMA_POLL_PERIOD = 0x26, 62 DEBUG_CTRL = 0x2c, 63 ASIC_CTRL = 0x30, 64 FIFO_CTRL = 0x38, /* Unused */ 65 FLOW_OFF_THRESH = 0x3c, 66 FLOW_ON_THRESH = 0x3e, 67 EEPROM_DATA = 0x48, 68 EEPROM_CTRL = 0x4a, 69 EXPROM_ADDR = 0x4c, /* Unused */ 70 EXPROM_DATA = 0x50, /* Unused */ 71 WAKE_EVENT = 0x51, /* Unused */ 72 COUNTDOWN = 0x54, /* Unused */ 73 INT_STATUS_ACK = 0x5a, 74 INT_ENABLE = 0x5c, 75 INT_STATUS = 0x5e, /* Unused */ 76 TX_STATUS = 0x60, 77 MAC_CTRL = 0x6c, 78 VLAN_TAG = 0x70, /* Unused */ 79 PHY_SET = 0x75, 80 PHY_CTRL = 0x76, 81 STATION_ADDRESS_0 = 0x78, 82 STATION_ADDRESS_1 = 0x7a, 83 STATION_ADDRESS_2 = 0x7c, 84 MAX_FRAME_SIZE = 0x86, 85 RECEIVE_MODE = 0x88, 86 HASHTABLE_0 = 0x8c, 87 HASHTABLE_1 = 0x90, 88 RMON_STATISTICS_MASK = 0x98, 89 STATISTICS_MASK = 0x9c, 90 RX_JUMBO_FRAMES = 0xbc, /* Unused */ 91 TCP_CHECKSUM_ERRORS = 0xc0, /* Unused */ 92 IP_CHECKSUM_ERRORS = 0xc2, /* Unused */ 93 UDP_CHECKSUM_ERRORS = 0xc4, /* Unused */ 94 TX_JUMBO_FRAMES = 0xf4 /* Unused */ 95 }; 96 97 /* Ethernet MIB statistic register offsets. */ 98 #define IPG_OCTETRCVOK 0xA8 99 #define IPG_MCSTOCTETRCVDOK 0xAC 100 #define IPG_BCSTOCTETRCVOK 0xB0 101 #define IPG_FRAMESRCVDOK 0xB4 102 #define IPG_MCSTFRAMESRCVDOK 0xB8 103 #define IPG_BCSTFRAMESRCVDOK 0xBE 104 #define IPG_MACCONTROLFRAMESRCVD 0xC6 105 #define IPG_FRAMETOOLONGERRRORS 0xC8 106 #define IPG_INRANGELENGTHERRORS 0xCA 107 #define IPG_FRAMECHECKSEQERRORS 0xCC 108 #define IPG_FRAMESLOSTRXERRORS 0xCE 109 #define IPG_OCTETXMTOK 0xD0 110 #define IPG_MCSTOCTETXMTOK 0xD4 111 #define IPG_BCSTOCTETXMTOK 0xD8 112 #define IPG_FRAMESXMTDOK 0xDC 113 #define IPG_MCSTFRAMESXMTDOK 0xE0 114 #define IPG_FRAMESWDEFERREDXMT 0xE4 115 #define IPG_LATECOLLISIONS 0xE8 116 #define IPG_MULTICOLFRAMES 0xEC 117 #define IPG_SINGLECOLFRAMES 0xF0 118 #define IPG_BCSTFRAMESXMTDOK 0xF6 119 #define IPG_CARRIERSENSEERRORS 0xF8 120 #define IPG_MACCONTROLFRAMESXMTDOK 0xFA 121 #define IPG_FRAMESABORTXSCOLLS 0xFC 122 #define IPG_FRAMESWEXDEFERRAL 0xFE 123 124 /* RMON statistic register offsets. */ 125 #define IPG_ETHERSTATSCOLLISIONS 0x100 126 #define IPG_ETHERSTATSOCTETSTRANSMIT 0x104 127 #define IPG_ETHERSTATSPKTSTRANSMIT 0x108 128 #define IPG_ETHERSTATSPKTS64OCTESTSTRANSMIT 0x10C 129 #define IPG_ETHERSTATSPKTS65TO127OCTESTSTRANSMIT 0x110 130 #define IPG_ETHERSTATSPKTS128TO255OCTESTSTRANSMIT 0x114 131 #define IPG_ETHERSTATSPKTS256TO511OCTESTSTRANSMIT 0x118 132 #define IPG_ETHERSTATSPKTS512TO1023OCTESTSTRANSMIT 0x11C 133 #define IPG_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT 0x120 134 #define IPG_ETHERSTATSCRCALIGNERRORS 0x124 135 #define IPG_ETHERSTATSUNDERSIZEPKTS 0x128 136 #define IPG_ETHERSTATSFRAGMENTS 0x12C 137 #define IPG_ETHERSTATSJABBERS 0x130 138 #define IPG_ETHERSTATSOCTETS 0x134 139 #define IPG_ETHERSTATSPKTS 0x138 140 #define IPG_ETHERSTATSPKTS64OCTESTS 0x13C 141 #define IPG_ETHERSTATSPKTS65TO127OCTESTS 0x140 142 #define IPG_ETHERSTATSPKTS128TO255OCTESTS 0x144 143 #define IPG_ETHERSTATSPKTS256TO511OCTESTS 0x148 144 #define IPG_ETHERSTATSPKTS512TO1023OCTESTS 0x14C 145 #define IPG_ETHERSTATSPKTS1024TO1518OCTESTS 0x150 146 147 /* RMON statistic register equivalents. */ 148 #define IPG_ETHERSTATSMULTICASTPKTSTRANSMIT 0xE0 149 #define IPG_ETHERSTATSBROADCASTPKTSTRANSMIT 0xF6 150 #define IPG_ETHERSTATSMULTICASTPKTS 0xB8 151 #define IPG_ETHERSTATSBROADCASTPKTS 0xBE 152 #define IPG_ETHERSTATSOVERSIZEPKTS 0xC8 153 #define IPG_ETHERSTATSDROPEVENTS 0xCE 154 155 /* Serial EEPROM offsets */ 156 #define IPG_EEPROM_CONFIGPARAM 0x00 157 #define IPG_EEPROM_ASICCTRL 0x01 158 #define IPG_EEPROM_SUBSYSTEMVENDORID 0x02 159 #define IPG_EEPROM_SUBSYSTEMID 0x03 160 #define IPG_EEPROM_STATIONADDRESS0 0x10 161 #define IPG_EEPROM_STATIONADDRESS1 0x11 162 #define IPG_EEPROM_STATIONADDRESS2 0x12 163 164 /* Register & data structure bit masks */ 165 166 /* PCI register masks. */ 167 168 /* IOBaseAddress */ 169 #define IPG_PIB_RSVD_MASK 0xFFFFFE01 170 #define IPG_PIB_IOBASEADDRESS 0xFFFFFF00 171 #define IPG_PIB_IOBASEADDRIND 0x00000001 172 173 /* MemBaseAddress */ 174 #define IPG_PMB_RSVD_MASK 0xFFFFFE07 175 #define IPG_PMB_MEMBASEADDRIND 0x00000001 176 #define IPG_PMB_MEMMAPTYPE 0x00000006 177 #define IPG_PMB_MEMMAPTYPE0 0x00000002 178 #define IPG_PMB_MEMMAPTYPE1 0x00000004 179 #define IPG_PMB_MEMBASEADDRESS 0xFFFFFE00 180 181 /* ConfigStatus */ 182 #define IPG_CS_RSVD_MASK 0xFFB0 183 #define IPG_CS_CAPABILITIES 0x0010 184 #define IPG_CS_66MHZCAPABLE 0x0020 185 #define IPG_CS_FASTBACK2BACK 0x0080 186 #define IPG_CS_DATAPARITYREPORTED 0x0100 187 #define IPG_CS_DEVSELTIMING 0x0600 188 #define IPG_CS_SIGNALEDTARGETABORT 0x0800 189 #define IPG_CS_RECEIVEDTARGETABORT 0x1000 190 #define IPG_CS_RECEIVEDMASTERABORT 0x2000 191 #define IPG_CS_SIGNALEDSYSTEMERROR 0x4000 192 #define IPG_CS_DETECTEDPARITYERROR 0x8000 193 194 /* TFD data structure masks. */ 195 196 /* TFDList, TFC */ 197 #define IPG_TFC_RSVD_MASK 0x0000FFFF9FFFFFFFULL 198 #define IPG_TFC_FRAMEID 0x000000000000FFFFULL 199 #define IPG_TFC_WORDALIGN 0x0000000000030000ULL 200 #define IPG_TFC_WORDALIGNTODWORD 0x0000000000000000ULL 201 #define IPG_TFC_WORDALIGNTOWORD 0x0000000000020000ULL 202 #define IPG_TFC_WORDALIGNDISABLED 0x0000000000030000ULL 203 #define IPG_TFC_TCPCHECKSUMENABLE 0x0000000000040000ULL 204 #define IPG_TFC_UDPCHECKSUMENABLE 0x0000000000080000ULL 205 #define IPG_TFC_IPCHECKSUMENABLE 0x0000000000100000ULL 206 #define IPG_TFC_FCSAPPENDDISABLE 0x0000000000200000ULL 207 #define IPG_TFC_TXINDICATE 0x0000000000400000ULL 208 #define IPG_TFC_TXDMAINDICATE 0x0000000000800000ULL 209 #define IPG_TFC_FRAGCOUNT 0x000000000F000000ULL 210 #define IPG_TFC_VLANTAGINSERT 0x0000000010000000ULL 211 #define IPG_TFC_TFDDONE 0x0000000080000000ULL 212 #define IPG_TFC_VID 0x00000FFF00000000ULL 213 #define IPG_TFC_CFI 0x0000100000000000ULL 214 #define IPG_TFC_USERPRIORITY 0x0000E00000000000ULL 215 216 /* TFDList, FragInfo */ 217 #define IPG_TFI_RSVD_MASK 0xFFFF00FFFFFFFFFFULL 218 #define IPG_TFI_FRAGADDR 0x000000FFFFFFFFFFULL 219 #define IPG_TFI_FRAGLEN 0xFFFF000000000000ULL 220 221 /* RFD data structure masks. */ 222 223 /* RFDList, RFS */ 224 #define IPG_RFS_RSVD_MASK 0x0000FFFFFFFFFFFFULL 225 #define IPG_RFS_RXFRAMELEN 0x000000000000FFFFULL 226 #define IPG_RFS_RXFIFOOVERRUN 0x0000000000010000ULL 227 #define IPG_RFS_RXRUNTFRAME 0x0000000000020000ULL 228 #define IPG_RFS_RXALIGNMENTERROR 0x0000000000040000ULL 229 #define IPG_RFS_RXFCSERROR 0x0000000000080000ULL 230 #define IPG_RFS_RXOVERSIZEDFRAME 0x0000000000100000ULL 231 #define IPG_RFS_RXLENGTHERROR 0x0000000000200000ULL 232 #define IPG_RFS_VLANDETECTED 0x0000000000400000ULL 233 #define IPG_RFS_TCPDETECTED 0x0000000000800000ULL 234 #define IPG_RFS_TCPERROR 0x0000000001000000ULL 235 #define IPG_RFS_UDPDETECTED 0x0000000002000000ULL 236 #define IPG_RFS_UDPERROR 0x0000000004000000ULL 237 #define IPG_RFS_IPDETECTED 0x0000000008000000ULL 238 #define IPG_RFS_IPERROR 0x0000000010000000ULL 239 #define IPG_RFS_FRAMESTART 0x0000000020000000ULL 240 #define IPG_RFS_FRAMEEND 0x0000000040000000ULL 241 #define IPG_RFS_RFDDONE 0x0000000080000000ULL 242 #define IPG_RFS_TCI 0x0000FFFF00000000ULL 243 244 /* RFDList, FragInfo */ 245 #define IPG_RFI_RSVD_MASK 0xFFFF00FFFFFFFFFFULL 246 #define IPG_RFI_FRAGADDR 0x000000FFFFFFFFFFULL 247 #define IPG_RFI_FRAGLEN 0xFFFF000000000000ULL 248 249 /* I/O Register masks. */ 250 251 /* RMON Statistics Mask */ 252 #define IPG_RZ_ALL 0x0FFFFFFF 253 254 /* Statistics Mask */ 255 #define IPG_SM_ALL 0x0FFFFFFF 256 #define IPG_SM_OCTETRCVOK_FRAMESRCVDOK 0x00000001 257 #define IPG_SM_MCSTOCTETRCVDOK_MCSTFRAMESRCVDOK 0x00000002 258 #define IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK 0x00000004 259 #define IPG_SM_RXJUMBOFRAMES 0x00000008 260 #define IPG_SM_TCPCHECKSUMERRORS 0x00000010 261 #define IPG_SM_IPCHECKSUMERRORS 0x00000020 262 #define IPG_SM_UDPCHECKSUMERRORS 0x00000040 263 #define IPG_SM_MACCONTROLFRAMESRCVD 0x00000080 264 #define IPG_SM_FRAMESTOOLONGERRORS 0x00000100 265 #define IPG_SM_INRANGELENGTHERRORS 0x00000200 266 #define IPG_SM_FRAMECHECKSEQERRORS 0x00000400 267 #define IPG_SM_FRAMESLOSTRXERRORS 0x00000800 268 #define IPG_SM_OCTETXMTOK_FRAMESXMTOK 0x00001000 269 #define IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK 0x00002000 270 #define IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK 0x00004000 271 #define IPG_SM_FRAMESWDEFERREDXMT 0x00008000 272 #define IPG_SM_LATECOLLISIONS 0x00010000 273 #define IPG_SM_MULTICOLFRAMES 0x00020000 274 #define IPG_SM_SINGLECOLFRAMES 0x00040000 275 #define IPG_SM_TXJUMBOFRAMES 0x00080000 276 #define IPG_SM_CARRIERSENSEERRORS 0x00100000 277 #define IPG_SM_MACCONTROLFRAMESXMTD 0x00200000 278 #define IPG_SM_FRAMESABORTXSCOLLS 0x00400000 279 #define IPG_SM_FRAMESWEXDEFERAL 0x00800000 280 281 /* Countdown */ 282 #define IPG_CD_RSVD_MASK 0x0700FFFF 283 #define IPG_CD_COUNT 0x0000FFFF 284 #define IPG_CD_COUNTDOWNSPEED 0x01000000 285 #define IPG_CD_COUNTDOWNMODE 0x02000000 286 #define IPG_CD_COUNTINTENABLED 0x04000000 287 288 /* TxDMABurstThresh */ 289 #define IPG_TB_RSVD_MASK 0xFF 290 291 /* TxDMAUrgentThresh */ 292 #define IPG_TU_RSVD_MASK 0xFF 293 294 /* TxDMAPollPeriod */ 295 #define IPG_TP_RSVD_MASK 0xFF 296 297 /* RxDMAUrgentThresh */ 298 #define IPG_RU_RSVD_MASK 0xFF 299 300 /* RxDMAPollPeriod */ 301 #define IPG_RP_RSVD_MASK 0xFF 302 303 /* ReceiveMode */ 304 #define IPG_RM_RSVD_MASK 0x3F 305 #define IPG_RM_RECEIVEUNICAST 0x01 306 #define IPG_RM_RECEIVEMULTICAST 0x02 307 #define IPG_RM_RECEIVEBROADCAST 0x04 308 #define IPG_RM_RECEIVEALLFRAMES 0x08 309 #define IPG_RM_RECEIVEMULTICASTHASH 0x10 310 #define IPG_RM_RECEIVEIPMULTICAST 0x20 311 312 /* PhySet */ 313 #define IPG_PS_MEM_LENB9B 0x01 314 #define IPG_PS_MEM_LEN9 0x02 315 #define IPG_PS_NON_COMPDET 0x04 316 317 /* PhyCtrl */ 318 #define IPG_PC_RSVD_MASK 0xFF 319 #define IPG_PC_MGMTCLK_LO 0x00 320 #define IPG_PC_MGMTCLK_HI 0x01 321 #define IPG_PC_MGMTCLK 0x01 322 #define IPG_PC_MGMTDATA 0x02 323 #define IPG_PC_MGMTDIR 0x04 324 #define IPG_PC_DUPLEX_POLARITY 0x08 325 #define IPG_PC_DUPLEX_STATUS 0x10 326 #define IPG_PC_LINK_POLARITY 0x20 327 #define IPG_PC_LINK_SPEED 0xC0 328 #define IPG_PC_LINK_SPEED_10MBPS 0x40 329 #define IPG_PC_LINK_SPEED_100MBPS 0x80 330 #define IPG_PC_LINK_SPEED_1000MBPS 0xC0 331 332 /* DMACtrl */ 333 #define IPG_DC_RSVD_MASK 0xC07D9818 334 #define IPG_DC_RX_DMA_COMPLETE 0x00000008 335 #define IPG_DC_RX_DMA_POLL_NOW 0x00000010 336 #define IPG_DC_TX_DMA_COMPLETE 0x00000800 337 #define IPG_DC_TX_DMA_POLL_NOW 0x00001000 338 #define IPG_DC_TX_DMA_IN_PROG 0x00008000 339 #define IPG_DC_RX_EARLY_DISABLE 0x00010000 340 #define IPG_DC_MWI_DISABLE 0x00040000 341 #define IPG_DC_TX_WRITE_BACK_DISABLE 0x00080000 342 #define IPG_DC_TX_BURST_LIMIT 0x00700000 343 #define IPG_DC_TARGET_ABORT 0x40000000 344 #define IPG_DC_MASTER_ABORT 0x80000000 345 346 /* ASICCtrl */ 347 #define IPG_AC_RSVD_MASK 0x07FFEFF2 348 #define IPG_AC_EXP_ROM_SIZE 0x00000002 349 #define IPG_AC_PHY_SPEED10 0x00000010 350 #define IPG_AC_PHY_SPEED100 0x00000020 351 #define IPG_AC_PHY_SPEED1000 0x00000040 352 #define IPG_AC_PHY_MEDIA 0x00000080 353 #define IPG_AC_FORCED_CFG 0x00000700 354 #define IPG_AC_D3RESETDISABLE 0x00000800 355 #define IPG_AC_SPEED_UP_MODE 0x00002000 356 #define IPG_AC_LED_MODE 0x00004000 357 #define IPG_AC_RST_OUT_POLARITY 0x00008000 358 #define IPG_AC_GLOBAL_RESET 0x00010000 359 #define IPG_AC_RX_RESET 0x00020000 360 #define IPG_AC_TX_RESET 0x00040000 361 #define IPG_AC_DMA 0x00080000 362 #define IPG_AC_FIFO 0x00100000 363 #define IPG_AC_NETWORK 0x00200000 364 #define IPG_AC_HOST 0x00400000 365 #define IPG_AC_AUTO_INIT 0x00800000 366 #define IPG_AC_RST_OUT 0x01000000 367 #define IPG_AC_INT_REQUEST 0x02000000 368 #define IPG_AC_RESET_BUSY 0x04000000 369 #define IPG_AC_LED_SPEED 0x08000000 370 #define IPG_AC_LED_MODE_BIT_1 0x20000000 371 372 /* EepromCtrl */ 373 #define IPG_EC_RSVD_MASK 0x83FF 374 #define IPG_EC_EEPROM_ADDR 0x00FF 375 #define IPG_EC_EEPROM_OPCODE 0x0300 376 #define IPG_EC_EEPROM_SUBCOMMAD 0x0000 377 #define IPG_EC_EEPROM_WRITEOPCODE 0x0100 378 #define IPG_EC_EEPROM_READOPCODE 0x0200 379 #define IPG_EC_EEPROM_ERASEOPCODE 0x0300 380 #define IPG_EC_EEPROM_BUSY 0x8000 381 382 /* FIFOCtrl */ 383 #define IPG_FC_RSVD_MASK 0xC001 384 #define IPG_FC_RAM_TEST_MODE 0x0001 385 #define IPG_FC_TRANSMITTING 0x4000 386 #define IPG_FC_RECEIVING 0x8000 387 388 /* TxStatus */ 389 #define IPG_TS_RSVD_MASK 0xFFFF00DD 390 #define IPG_TS_TX_ERROR 0x00000001 391 #define IPG_TS_LATE_COLLISION 0x00000004 392 #define IPG_TS_TX_MAX_COLL 0x00000008 393 #define IPG_TS_TX_UNDERRUN 0x00000010 394 #define IPG_TS_TX_IND_REQD 0x00000040 395 #define IPG_TS_TX_COMPLETE 0x00000080 396 #define IPG_TS_TX_FRAMEID 0xFFFF0000 397 398 /* WakeEvent */ 399 #define IPG_WE_WAKE_PKT_ENABLE 0x01 400 #define IPG_WE_MAGIC_PKT_ENABLE 0x02 401 #define IPG_WE_LINK_EVT_ENABLE 0x04 402 #define IPG_WE_WAKE_POLARITY 0x08 403 #define IPG_WE_WAKE_PKT_EVT 0x10 404 #define IPG_WE_MAGIC_PKT_EVT 0x20 405 #define IPG_WE_LINK_EVT 0x40 406 #define IPG_WE_WOL_ENABLE 0x80 407 408 /* IntEnable */ 409 #define IPG_IE_RSVD_MASK 0x1FFE 410 #define IPG_IE_HOST_ERROR 0x0002 411 #define IPG_IE_TX_COMPLETE 0x0004 412 #define IPG_IE_MAC_CTRL_FRAME 0x0008 413 #define IPG_IE_RX_COMPLETE 0x0010 414 #define IPG_IE_RX_EARLY 0x0020 415 #define IPG_IE_INT_REQUESTED 0x0040 416 #define IPG_IE_UPDATE_STATS 0x0080 417 #define IPG_IE_LINK_EVENT 0x0100 418 #define IPG_IE_TX_DMA_COMPLETE 0x0200 419 #define IPG_IE_RX_DMA_COMPLETE 0x0400 420 #define IPG_IE_RFD_LIST_END 0x0800 421 #define IPG_IE_RX_DMA_PRIORITY 0x1000 422 423 /* IntStatus */ 424 #define IPG_IS_RSVD_MASK 0x1FFF 425 #define IPG_IS_INTERRUPT_STATUS 0x0001 426 #define IPG_IS_HOST_ERROR 0x0002 427 #define IPG_IS_TX_COMPLETE 0x0004 428 #define IPG_IS_MAC_CTRL_FRAME 0x0008 429 #define IPG_IS_RX_COMPLETE 0x0010 430 #define IPG_IS_RX_EARLY 0x0020 431 #define IPG_IS_INT_REQUESTED 0x0040 432 #define IPG_IS_UPDATE_STATS 0x0080 433 #define IPG_IS_LINK_EVENT 0x0100 434 #define IPG_IS_TX_DMA_COMPLETE 0x0200 435 #define IPG_IS_RX_DMA_COMPLETE 0x0400 436 #define IPG_IS_RFD_LIST_END 0x0800 437 #define IPG_IS_RX_DMA_PRIORITY 0x1000 438 439 /* MACCtrl */ 440 #define IPG_MC_RSVD_MASK 0x7FE33FA3 441 #define IPG_MC_IFS_SELECT 0x00000003 442 #define IPG_MC_IFS_4352BIT 0x00000003 443 #define IPG_MC_IFS_1792BIT 0x00000002 444 #define IPG_MC_IFS_1024BIT 0x00000001 445 #define IPG_MC_IFS_96BIT 0x00000000 446 #define IPG_MC_DUPLEX_SELECT 0x00000020 447 #define IPG_MC_DUPLEX_SELECT_FD 0x00000020 448 #define IPG_MC_DUPLEX_SELECT_HD 0x00000000 449 #define IPG_MC_TX_FLOW_CONTROL_ENABLE 0x00000080 450 #define IPG_MC_RX_FLOW_CONTROL_ENABLE 0x00000100 451 #define IPG_MC_RCV_FCS 0x00000200 452 #define IPG_MC_FIFO_LOOPBACK 0x00000400 453 #define IPG_MC_MAC_LOOPBACK 0x00000800 454 #define IPG_MC_AUTO_VLAN_TAGGING 0x00001000 455 #define IPG_MC_AUTO_VLAN_UNTAGGING 0x00002000 456 #define IPG_MC_COLLISION_DETECT 0x00010000 457 #define IPG_MC_CARRIER_SENSE 0x00020000 458 #define IPG_MC_STATISTICS_ENABLE 0x00200000 459 #define IPG_MC_STATISTICS_DISABLE 0x00400000 460 #define IPG_MC_STATISTICS_ENABLED 0x00800000 461 #define IPG_MC_TX_ENABLE 0x01000000 462 #define IPG_MC_TX_DISABLE 0x02000000 463 #define IPG_MC_TX_ENABLED 0x04000000 464 #define IPG_MC_RX_ENABLE 0x08000000 465 #define IPG_MC_RX_DISABLE 0x10000000 466 #define IPG_MC_RX_ENABLED 0x20000000 467 #define IPG_MC_PAUSED 0x40000000 468 469 /* 470 * Tune 471 */ 472 473 /* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS append on TX. */ 474 #define IPG_APPEND_FCS_ON_TX 1 475 476 /* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS strip on RX. */ 477 #define IPG_STRIP_FCS_ON_RX 1 478 479 /* Assign IPG_DROP_ON_RX_ETH_ERRORS > 0 to drop RX frames with 480 * Ethernet errors. 481 */ 482 #define IPG_DROP_ON_RX_ETH_ERRORS 1 483 484 /* Assign IPG_INSERT_MANUAL_VLAN_TAG > 0 to insert VLAN tags manually 485 * (via TFC). 486 */ 487 #define IPG_INSERT_MANUAL_VLAN_TAG 0 488 489 /* Assign IPG_ADD_IPCHECKSUM_ON_TX > 0 for auto IP checksum on TX. */ 490 #define IPG_ADD_IPCHECKSUM_ON_TX 0 491 492 /* Assign IPG_ADD_TCPCHECKSUM_ON_TX > 0 for auto TCP checksum on TX. 493 * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER. 494 */ 495 #define IPG_ADD_TCPCHECKSUM_ON_TX 0 496 497 /* Assign IPG_ADD_UDPCHECKSUM_ON_TX > 0 for auto UDP checksum on TX. 498 * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER. 499 */ 500 #define IPG_ADD_UDPCHECKSUM_ON_TX 0 501 502 /* If inserting VLAN tags manually, assign the IPG_MANUAL_VLAN_xx 503 * constants as desired. 504 */ 505 #define IPG_MANUAL_VLAN_VID 0xABC 506 #define IPG_MANUAL_VLAN_CFI 0x1 507 #define IPG_MANUAL_VLAN_USERPRIORITY 0x5 508 509 #define IPG_IO_REG_RANGE 0xFF 510 #define IPG_MEM_REG_RANGE 0x154 511 #define IPG_DRIVER_NAME "Sundance Technology IPG Triple-Speed Ethernet" 512 #define IPG_NIC_PHY_ADDRESS 0x01 513 #define IPG_DMALIST_ALIGN_PAD 0x07 514 #define IPG_MULTICAST_HASHTABLE_SIZE 0x40 515 516 /* Number of milliseconds to wait after issuing a software reset. 517 * 0x05 <= IPG_AC_RESETWAIT to account for proper 10Mbps operation. 518 */ 519 #define IPG_AC_RESETWAIT 0x05 520 521 /* Number of IPG_AC_RESETWAIT timeperiods before declaring timeout. */ 522 #define IPG_AC_RESET_TIMEOUT 0x0A 523 524 /* Minimum number of nanoseconds used to toggle MDC clock during 525 * MII/GMII register access. 526 */ 527 #define IPG_PC_PHYCTRLWAIT_NS 200 528 529 #define IPG_TFDLIST_LENGTH 0x100 530 531 /* Number of frames between TxDMAComplete interrupt. 532 * 0 < IPG_FRAMESBETWEENTXDMACOMPLETES <= IPG_TFDLIST_LENGTH 533 */ 534 #define IPG_FRAMESBETWEENTXDMACOMPLETES 0x1 535 536 #define IPG_RFDLIST_LENGTH 0x100 537 538 /* Maximum number of RFDs to process per interrupt. 539 * 1 < IPG_MAXRFDPROCESS_COUNT < IPG_RFDLIST_LENGTH 540 */ 541 #define IPG_MAXRFDPROCESS_COUNT 0x80 542 543 /* Minimum margin between last freed RFD, and current RFD. 544 * 1 < IPG_MINUSEDRFDSTOFREE < IPG_RFDLIST_LENGTH 545 */ 546 #define IPG_MINUSEDRFDSTOFREE 0x80 547 548 /* specify the jumbo frame maximum size 549 * per unit is 0x600 (the rx_buffer size that one RFD can carry) 550 */ 551 #define MAX_JUMBOSIZE 0x8 /* max is 12K */ 552 553 /* Key register values loaded at driver start up. */ 554 555 /* TXDMAPollPeriod is specified in 320ns increments. 556 * 557 * Value Time 558 * --------------------- 559 * 0x00-0x01 320ns 560 * 0x03 ~1us 561 * 0x1F ~10us 562 * 0xFF ~82us 563 */ 564 #define IPG_TXDMAPOLLPERIOD_VALUE 0x26 565 566 /* TxDMAUrgentThresh specifies the minimum amount of 567 * data in the transmit FIFO before asserting an 568 * urgent transmit DMA request. 569 * 570 * Value Min TxFIFO occupied space before urgent TX request 571 * --------------------------------------------------------------- 572 * 0x00-0x04 128 bytes (1024 bits) 573 * 0x27 1248 bytes (~10000 bits) 574 * 0x30 1536 bytes (12288 bits) 575 * 0xFF 8192 bytes (65535 bits) 576 */ 577 #define IPG_TXDMAURGENTTHRESH_VALUE 0x04 578 579 /* TxDMABurstThresh specifies the minimum amount of 580 * free space in the transmit FIFO before asserting an 581 * transmit DMA request. 582 * 583 * Value Min TxFIFO free space before TX request 584 * ---------------------------------------------------- 585 * 0x00-0x08 256 bytes 586 * 0x30 1536 bytes 587 * 0xFF 8192 bytes 588 */ 589 #define IPG_TXDMABURSTTHRESH_VALUE 0x30 590 591 /* RXDMAPollPeriod is specified in 320ns increments. 592 * 593 * Value Time 594 * --------------------- 595 * 0x00-0x01 320ns 596 * 0x03 ~1us 597 * 0x1F ~10us 598 * 0xFF ~82us 599 */ 600 #define IPG_RXDMAPOLLPERIOD_VALUE 0x01 601 602 /* RxDMAUrgentThresh specifies the minimum amount of 603 * free space within the receive FIFO before asserting 604 * a urgent receive DMA request. 605 * 606 * Value Min RxFIFO free space before urgent RX request 607 * --------------------------------------------------------------- 608 * 0x00-0x04 128 bytes (1024 bits) 609 * 0x27 1248 bytes (~10000 bits) 610 * 0x30 1536 bytes (12288 bits) 611 * 0xFF 8192 bytes (65535 bits) 612 */ 613 #define IPG_RXDMAURGENTTHRESH_VALUE 0x30 614 615 /* RxDMABurstThresh specifies the minimum amount of 616 * occupied space within the receive FIFO before asserting 617 * a receive DMA request. 618 * 619 * Value Min TxFIFO free space before TX request 620 * ---------------------------------------------------- 621 * 0x00-0x08 256 bytes 622 * 0x30 1536 bytes 623 * 0xFF 8192 bytes 624 */ 625 #define IPG_RXDMABURSTTHRESH_VALUE 0x30 626 627 /* FlowOnThresh specifies the maximum amount of occupied 628 * space in the receive FIFO before a PAUSE frame with 629 * maximum pause time transmitted. 630 * 631 * Value Max RxFIFO occupied space before PAUSE 632 * --------------------------------------------------- 633 * 0x0000 0 bytes 634 * 0x0740 29,696 bytes 635 * 0x07FF 32,752 bytes 636 */ 637 #define IPG_FLOWONTHRESH_VALUE 0x0740 638 639 /* FlowOffThresh specifies the minimum amount of occupied 640 * space in the receive FIFO before a PAUSE frame with 641 * zero pause time is transmitted. 642 * 643 * Value Max RxFIFO occupied space before PAUSE 644 * --------------------------------------------------- 645 * 0x0000 0 bytes 646 * 0x00BF 3056 bytes 647 * 0x07FF 32,752 bytes 648 */ 649 #define IPG_FLOWOFFTHRESH_VALUE 0x00BF 650 651 /* 652 * Miscellaneous macros. 653 */ 654 655 /* Macros for printing debug statements. */ 656 #ifdef IPG_DEBUG 657 # define IPG_DEBUG_MSG(fmt, args...) \ 658 do { \ 659 if (0) \ 660 printk(KERN_DEBUG "IPG: " fmt, ##args); \ 661 } while (0) 662 # define IPG_DDEBUG_MSG(fmt, args...) \ 663 printk(KERN_DEBUG "IPG: " fmt, ##args) 664 # define IPG_DUMPRFDLIST(args) ipg_dump_rfdlist(args) 665 # define IPG_DUMPTFDLIST(args) ipg_dump_tfdlist(args) 666 #else 667 # define IPG_DEBUG_MSG(fmt, args...) \ 668 do { \ 669 if (0) \ 670 printk(KERN_DEBUG "IPG: " fmt, ##args); \ 671 } while (0) 672 # define IPG_DDEBUG_MSG(fmt, args...) \ 673 do { \ 674 if (0) \ 675 printk(KERN_DEBUG "IPG: " fmt, ##args); \ 676 } while (0) 677 # define IPG_DUMPRFDLIST(args) 678 # define IPG_DUMPTFDLIST(args) 679 #endif 680 681 /* 682 * End miscellaneous macros. 683 */ 684 685 /* Transmit Frame Descriptor. The IPG supports 15 fragments, 686 * however Linux requires only a single fragment. Note, each 687 * TFD field is 64 bits wide. 688 */ 689 struct ipg_tx { 690 __le64 next_desc; 691 __le64 tfc; 692 __le64 frag_info; 693 }; 694 695 /* Receive Frame Descriptor. Note, each RFD field is 64 bits wide. 696 */ 697 struct ipg_rx { 698 __le64 next_desc; 699 __le64 rfs; 700 __le64 frag_info; 701 }; 702 703 struct ipg_jumbo { 704 int found_start; 705 int current_size; 706 struct sk_buff *skb; 707 }; 708 709 /* Structure of IPG NIC specific data. */ 710 struct ipg_nic_private { 711 void __iomem *ioaddr; 712 struct ipg_tx *txd; 713 struct ipg_rx *rxd; 714 dma_addr_t txd_map; 715 dma_addr_t rxd_map; 716 struct sk_buff *tx_buff[IPG_TFDLIST_LENGTH]; 717 struct sk_buff *rx_buff[IPG_RFDLIST_LENGTH]; 718 unsigned int tx_current; 719 unsigned int tx_dirty; 720 unsigned int rx_current; 721 unsigned int rx_dirty; 722 bool is_jumbo; 723 struct ipg_jumbo jumbo; 724 unsigned long rxfrag_size; 725 unsigned long rxsupport_size; 726 unsigned long max_rxframe_size; 727 unsigned int rx_buf_sz; 728 struct pci_dev *pdev; 729 struct net_device *dev; 730 struct net_device_stats stats; 731 spinlock_t lock; 732 int tenmbpsmode; 733 734 u16 led_mode; 735 u16 station_addr[3]; /* Station Address in EEPROM Reg 0x10..0x12 */ 736 737 struct mutex mii_mutex; 738 struct mii_if_info mii_if; 739 int reset_current_tfd; 740 #ifdef IPG_DEBUG 741 int RFDlistendCount; 742 int RFDListCheckedCount; 743 int EmptyRFDListCount; 744 #endif 745 struct delayed_work task; 746 }; 747 748 #endif /* __LINUX_IPG_H */ 749