1 /* 2 * Copyright (C) 2012 Texas Instruments Inc 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 16 * 17 * Contributors: 18 * Manjunath Hadli <manjunath.hadli@ti.com> 19 * Prabhakar Lad <prabhakar.lad@ti.com> 20 */ 21 22 #ifndef _DAVINCI_VPFE_DM365_ISIF_REGS_H 23 #define _DAVINCI_VPFE_DM365_ISIF_REGS_H 24 25 /* ISIF registers relative offsets */ 26 #define SYNCEN 0x00 27 #define MODESET 0x04 28 #define HDW 0x08 29 #define VDW 0x0c 30 #define PPLN 0x10 31 #define LPFR 0x14 32 #define SPH 0x18 33 #define LNH 0x1c 34 #define SLV0 0x20 35 #define SLV1 0x24 36 #define LNV 0x28 37 #define CULH 0x2c 38 #define CULV 0x30 39 #define HSIZE 0x34 40 #define SDOFST 0x38 41 #define CADU 0x3c 42 #define CADL 0x40 43 #define LINCFG0 0x44 44 #define LINCFG1 0x48 45 #define CCOLP 0x4c 46 #define CRGAIN 0x50 47 #define CGRGAIN 0x54 48 #define CGBGAIN 0x58 49 #define CBGAIN 0x5c 50 #define COFSTA 0x60 51 #define FLSHCFG0 0x64 52 #define FLSHCFG1 0x68 53 #define FLSHCFG2 0x6c 54 #define VDINT0 0x70 55 #define VDINT1 0x74 56 #define VDINT2 0x78 57 #define MISC 0x7c 58 #define CGAMMAWD 0x80 59 #define REC656IF 0x84 60 #define CCDCFG 0x88 61 /***************************************************** 62 * Defect Correction registers 63 *****************************************************/ 64 #define DFCCTL 0x8c 65 #define VDFSATLV 0x90 66 #define DFCMEMCTL 0x94 67 #define DFCMEM0 0x98 68 #define DFCMEM1 0x9c 69 #define DFCMEM2 0xa0 70 #define DFCMEM3 0xa4 71 #define DFCMEM4 0xa8 72 /**************************************************** 73 * Black Clamp registers 74 ****************************************************/ 75 #define CLAMPCFG 0xac 76 #define CLDCOFST 0xb0 77 #define CLSV 0xb4 78 #define CLHWIN0 0xb8 79 #define CLHWIN1 0xbc 80 #define CLHWIN2 0xc0 81 #define CLVRV 0xc4 82 #define CLVWIN0 0xc8 83 #define CLVWIN1 0xcc 84 #define CLVWIN2 0xd0 85 #define CLVWIN3 0xd4 86 /**************************************************** 87 * Lense Shading Correction 88 ****************************************************/ 89 #define DATAHOFST 0xd8 90 #define DATAVOFST 0xdc 91 #define LSCHVAL 0xe0 92 #define LSCVVAL 0xe4 93 #define TWODLSCCFG 0xe8 94 #define TWODLSCOFST 0xec 95 #define TWODLSCINI 0xf0 96 #define TWODLSCGRBU 0xf4 97 #define TWODLSCGRBL 0xf8 98 #define TWODLSCGROF 0xfc 99 #define TWODLSCORBU 0x100 100 #define TWODLSCORBL 0x104 101 #define TWODLSCOROF 0x108 102 #define TWODLSCIRQEN 0x10c 103 #define TWODLSCIRQST 0x110 104 /**************************************************** 105 * Data formatter 106 ****************************************************/ 107 #define FMTCFG 0x114 108 #define FMTPLEN 0x118 109 #define FMTSPH 0x11c 110 #define FMTLNH 0x120 111 #define FMTSLV 0x124 112 #define FMTLNV 0x128 113 #define FMTRLEN 0x12c 114 #define FMTHCNT 0x130 115 #define FMTAPTR_BASE 0x134 116 /* Below macro for addresses FMTAPTR0 - FMTAPTR15 */ 117 #define FMTAPTR(i) (FMTAPTR_BASE + (i * 4)) 118 #define FMTPGMVF0 0x174 119 #define FMTPGMVF1 0x178 120 #define FMTPGMAPU0 0x17c 121 #define FMTPGMAPU1 0x180 122 #define FMTPGMAPS0 0x184 123 #define FMTPGMAPS1 0x188 124 #define FMTPGMAPS2 0x18c 125 #define FMTPGMAPS3 0x190 126 #define FMTPGMAPS4 0x194 127 #define FMTPGMAPS5 0x198 128 #define FMTPGMAPS6 0x19c 129 #define FMTPGMAPS7 0x1a0 130 /************************************************ 131 * Color Space Converter 132 ************************************************/ 133 #define CSCCTL 0x1a4 134 #define CSCM0 0x1a8 135 #define CSCM1 0x1ac 136 #define CSCM2 0x1b0 137 #define CSCM3 0x1b4 138 #define CSCM4 0x1b8 139 #define CSCM5 0x1bc 140 #define CSCM6 0x1c0 141 #define CSCM7 0x1c4 142 #define OBWIN0 0x1c8 143 #define OBWIN1 0x1cc 144 #define OBWIN2 0x1d0 145 #define OBWIN3 0x1d4 146 #define OBVAL0 0x1d8 147 #define OBVAL1 0x1dc 148 #define OBVAL2 0x1e0 149 #define OBVAL3 0x1e4 150 #define OBVAL4 0x1e8 151 #define OBVAL5 0x1ec 152 #define OBVAL6 0x1f0 153 #define OBVAL7 0x1f4 154 #define CLKCTL 0x1f8 155 156 /* Masks & Shifts below */ 157 #define START_PX_HOR_MASK 0x7fff 158 #define NUM_PX_HOR_MASK 0x7fff 159 #define START_VER_ONE_MASK 0x7fff 160 #define START_VER_TWO_MASK 0x7fff 161 #define NUM_LINES_VER 0x7fff 162 163 /* gain - offset masks */ 164 #define OFFSET_MASK 0xfff 165 #define GAIN_SDRAM_EN_SHIFT 12 166 #define GAIN_IPIPE_EN_SHIFT 13 167 #define GAIN_H3A_EN_SHIFT 14 168 #define OFST_SDRAM_EN_SHIFT 8 169 #define OFST_IPIPE_EN_SHIFT 9 170 #define OFST_H3A_EN_SHIFT 10 171 #define GAIN_OFFSET_EN_MASK 0x7700 172 173 /* Culling */ 174 #define CULL_PAT_EVEN_LINE_SHIFT 8 175 176 /* CCDCFG register */ 177 #define ISIF_YCINSWP_RAW (0x00 << 4) 178 #define ISIF_YCINSWP_YCBCR (0x01 << 4) 179 #define ISIF_CCDCFG_FIDMD_LATCH_VSYNC (0x00 << 6) 180 #define ISIF_CCDCFG_WENLOG_AND (0x00 << 8) 181 #define ISIF_CCDCFG_TRGSEL_WEN (0x00 << 9) 182 #define ISIF_CCDCFG_EXTRG_DISABLE (0x00 << 10) 183 #define ISIF_LATCH_ON_VSYNC_DISABLE (0x01 << 15) 184 #define ISIF_LATCH_ON_VSYNC_ENABLE (0x00 << 15) 185 #define ISIF_DATA_PACK_MASK 0x03 186 #define ISIF_PIX_ORDER_SHIFT 11 187 #define ISIF_PIX_ORDER_MASK 0x01 188 #define ISIF_BW656_ENABLE (0x01 << 5) 189 190 /* MODESET registers */ 191 #define ISIF_VDHDOUT_INPUT (0x00 << 0) 192 #define ISIF_INPUT_MASK 0x03 193 #define ISIF_INPUT_SHIFT 12 194 #define ISIF_FID_POL_MASK 0x01 195 #define ISIF_FID_POL_SHIFT 4 196 #define ISIF_HD_POL_MASK 0x01 197 #define ISIF_HD_POL_SHIFT 3 198 #define ISIF_VD_POL_MASK 0x01 199 #define ISIF_VD_POL_SHIFT 2 200 #define ISIF_DATAPOL_NORMAL 0x00 201 #define ISIF_DATAPOL_MASK 0x01 202 #define ISIF_DATAPOL_SHIFT 6 203 #define ISIF_EXWEN_DISABLE 0x00 204 #define ISIF_EXWEN_MASK 0x01 205 #define ISIF_EXWEN_SHIFT 5 206 #define ISIF_FRM_FMT_MASK 0x01 207 #define ISIF_FRM_FMT_SHIFT 7 208 #define ISIF_DATASFT_MASK 0x07 209 #define ISIF_DATASFT_SHIFT 8 210 #define ISIF_LPF_SHIFT 14 211 #define ISIF_LPF_MASK 0x1 212 213 /* GAMMAWD registers */ 214 #define ISIF_ALAW_GAMA_WD_MASK 0xf 215 #define ISIF_ALAW_GAMA_WD_SHIFT 1 216 #define ISIF_ALAW_ENABLE 0x01 217 #define ISIF_GAMMAWD_CFA_MASK 0x01 218 #define ISIF_GAMMAWD_CFA_SHIFT 5 219 220 /* HSIZE registers */ 221 #define ISIF_HSIZE_FLIP_MASK 0x01 222 #define ISIF_HSIZE_FLIP_SHIFT 12 223 #define ISIF_LINEOFST_MASK 0xfff 224 225 /* MISC registers */ 226 #define ISIF_DPCM_EN_SHIFT 12 227 #define ISIF_DPCM_PREDICTOR_SHIFT 13 228 #define ISIF_DPCM_PREDICTOR_MASK 1 229 230 /* Black clamp related */ 231 #define ISIF_BC_DCOFFSET_MASK 0x1fff 232 #define ISIF_BC_MODE_COLOR_MASK 1 233 #define ISIF_BC_MODE_COLOR_SHIFT 4 234 #define ISIF_HORZ_BC_MODE_MASK 3 235 #define ISIF_HORZ_BC_MODE_SHIFT 1 236 #define ISIF_HORZ_BC_WIN_COUNT_MASK 0x1f 237 #define ISIF_HORZ_BC_WIN_SEL_SHIFT 5 238 #define ISIF_HORZ_BC_PIX_LIMIT_SHIFT 6 239 #define ISIF_HORZ_BC_WIN_H_SIZE_MASK 3 240 #define ISIF_HORZ_BC_WIN_H_SIZE_SHIFT 8 241 #define ISIF_HORZ_BC_WIN_V_SIZE_MASK 3 242 #define ISIF_HORZ_BC_WIN_V_SIZE_SHIFT 12 243 #define ISIF_HORZ_BC_WIN_START_H_MASK 0x1fff 244 #define ISIF_HORZ_BC_WIN_START_V_MASK 0x1fff 245 #define ISIF_VERT_BC_OB_H_SZ_MASK 7 246 #define ISIF_VERT_BC_RST_VAL_SEL_MASK 3 247 #define ISIF_VERT_BC_RST_VAL_SEL_SHIFT 4 248 #define ISIF_VERT_BC_LINE_AVE_COEF_SHIFT 8 249 #define ISIF_VERT_BC_OB_START_HORZ_MASK 0x1fff 250 #define ISIF_VERT_BC_OB_START_VERT_MASK 0x1fff 251 #define ISIF_VERT_BC_OB_VERT_SZ_MASK 0x1fff 252 #define ISIF_VERT_BC_RST_VAL_MASK 0xfff 253 #define ISIF_BC_VERT_START_SUB_V_MASK 0x1fff 254 255 /* VDFC registers */ 256 #define ISIF_VDFC_EN_SHIFT 4 257 #define ISIF_VDFC_CORR_MOD_MASK 3 258 #define ISIF_VDFC_CORR_MOD_SHIFT 5 259 #define ISIF_VDFC_CORR_WHOLE_LN_SHIFT 7 260 #define ISIF_VDFC_LEVEL_SHFT_MASK 7 261 #define ISIF_VDFC_LEVEL_SHFT_SHIFT 8 262 #define ISIF_VDFC_SAT_LEVEL_MASK 0xfff 263 #define ISIF_VDFC_POS_MASK 0x1fff 264 #define ISIF_DFCMEMCTL_DFCMARST_SHIFT 2 265 266 /* CSC registers */ 267 #define ISIF_CSC_COEF_INTEG_MASK 7 268 #define ISIF_CSC_COEF_DECIMAL_MASK 0x1f 269 #define ISIF_CSC_COEF_INTEG_SHIFT 5 270 #define ISIF_CSCM_MSB_SHIFT 8 271 #define ISIF_DF_CSC_SPH_MASK 0x1fff 272 #define ISIF_DF_CSC_LNH_MASK 0x1fff 273 #define ISIF_DF_CSC_SLV_MASK 0x1fff 274 #define ISIF_DF_CSC_LNV_MASK 0x1fff 275 #define ISIF_DF_NUMLINES 0x7fff 276 #define ISIF_DF_NUMPIX 0x1fff 277 278 /* Offsets for LSC/DFC/Gain */ 279 #define ISIF_DATA_H_OFFSET_MASK 0x1fff 280 #define ISIF_DATA_V_OFFSET_MASK 0x1fff 281 282 /* Linearization */ 283 #define ISIF_LIN_CORRSFT_MASK 7 284 #define ISIF_LIN_CORRSFT_SHIFT 4 285 #define ISIF_LIN_SCALE_FACT_INTEG_SHIFT 10 286 #define ISIF_LIN_SCALE_FACT_DECIMAL_MASK 0x3ff 287 #define ISIF_LIN_ENTRY_MASK 0x3ff 288 289 /* masks and shifts*/ 290 #define ISIF_SYNCEN_VDHDEN_MASK (1 << 0) 291 #define ISIF_SYNCEN_WEN_MASK (1 << 1) 292 #define ISIF_SYNCEN_WEN_SHIFT 1 293 294 #endif /* _DAVINCI_VPFE_DM365_ISIF_REGS_H */ 295