1 /* 2 * Copyright 2005-2009 Freescale Semiconductor, Inc. 3 * 4 * The code contained herein is licensed under the GNU Lesser General 5 * Public License. You may obtain a copy of the GNU Lesser General 6 * Public License Version 2.1 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/lgpl-license.html 9 * http://www.gnu.org/copyleft/lgpl.html 10 */ 11 12 #ifndef __DRM_IPU_H__ 13 #define __DRM_IPU_H__ 14 15 #include <linux/types.h> 16 #include <linux/videodev2.h> 17 #include <linux/bitmap.h> 18 #include <linux/fb.h> 19 #include <linux/of.h> 20 #include <media/v4l2-mediabus.h> 21 #include <video/videomode.h> 22 23 struct ipu_soc; 24 25 enum ipuv3_type { 26 IPUV3EX, 27 IPUV3M, 28 IPUV3H, 29 }; 30 31 #define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3') 32 33 /* 34 * Bitfield of Display Interface signal polarities. 35 */ 36 struct ipu_di_signal_cfg { 37 unsigned data_pol:1; /* true = inverted */ 38 unsigned clk_pol:1; /* true = rising edge */ 39 unsigned enable_pol:1; 40 41 struct videomode mode; 42 43 u32 bus_format; 44 u32 v_to_h_sync; 45 46 #define IPU_DI_CLKMODE_SYNC (1 << 0) 47 #define IPU_DI_CLKMODE_EXT (1 << 1) 48 unsigned long clkflags; 49 50 u8 hsync_pin; 51 u8 vsync_pin; 52 }; 53 54 /* 55 * Enumeration of CSI destinations 56 */ 57 enum ipu_csi_dest { 58 IPU_CSI_DEST_IDMAC, /* to memory via SMFC */ 59 IPU_CSI_DEST_IC, /* to Image Converter */ 60 IPU_CSI_DEST_VDIC, /* to VDIC */ 61 }; 62 63 /* 64 * Enumeration of IPU rotation modes 65 */ 66 enum ipu_rotate_mode { 67 IPU_ROTATE_NONE = 0, 68 IPU_ROTATE_VERT_FLIP, 69 IPU_ROTATE_HORIZ_FLIP, 70 IPU_ROTATE_180, 71 IPU_ROTATE_90_RIGHT, 72 IPU_ROTATE_90_RIGHT_VFLIP, 73 IPU_ROTATE_90_RIGHT_HFLIP, 74 IPU_ROTATE_90_LEFT, 75 }; 76 77 enum ipu_color_space { 78 IPUV3_COLORSPACE_RGB, 79 IPUV3_COLORSPACE_YUV, 80 IPUV3_COLORSPACE_UNKNOWN, 81 }; 82 83 struct ipuv3_channel; 84 85 enum ipu_channel_irq { 86 IPU_IRQ_EOF = 0, 87 IPU_IRQ_NFACK = 64, 88 IPU_IRQ_NFB4EOF = 128, 89 IPU_IRQ_EOS = 192, 90 }; 91 92 /* 93 * Enumeration of IDMAC channels 94 */ 95 #define IPUV3_CHANNEL_CSI0 0 96 #define IPUV3_CHANNEL_CSI1 1 97 #define IPUV3_CHANNEL_CSI2 2 98 #define IPUV3_CHANNEL_CSI3 3 99 #define IPUV3_CHANNEL_VDI_MEM_IC_VF 5 100 #define IPUV3_CHANNEL_MEM_IC_PP 11 101 #define IPUV3_CHANNEL_MEM_IC_PRP_VF 12 102 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14 103 #define IPUV3_CHANNEL_G_MEM_IC_PP 15 104 #define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20 105 #define IPUV3_CHANNEL_IC_PRP_VF_MEM 21 106 #define IPUV3_CHANNEL_IC_PP_MEM 22 107 #define IPUV3_CHANNEL_MEM_BG_SYNC 23 108 #define IPUV3_CHANNEL_MEM_BG_ASYNC 24 109 #define IPUV3_CHANNEL_MEM_FG_SYNC 27 110 #define IPUV3_CHANNEL_MEM_DC_SYNC 28 111 #define IPUV3_CHANNEL_MEM_FG_ASYNC 29 112 #define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31 113 #define IPUV3_CHANNEL_MEM_DC_ASYNC 41 114 #define IPUV3_CHANNEL_MEM_ROT_ENC 45 115 #define IPUV3_CHANNEL_MEM_ROT_VF 46 116 #define IPUV3_CHANNEL_MEM_ROT_PP 47 117 #define IPUV3_CHANNEL_ROT_ENC_MEM 48 118 #define IPUV3_CHANNEL_ROT_VF_MEM 49 119 #define IPUV3_CHANNEL_ROT_PP_MEM 50 120 #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51 121 122 int ipu_map_irq(struct ipu_soc *ipu, int irq); 123 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, 124 enum ipu_channel_irq irq); 125 126 #define IPU_IRQ_DP_SF_START (448 + 2) 127 #define IPU_IRQ_DP_SF_END (448 + 3) 128 #define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END, 129 #define IPU_IRQ_DC_FC_0 (448 + 8) 130 #define IPU_IRQ_DC_FC_1 (448 + 9) 131 #define IPU_IRQ_DC_FC_2 (448 + 10) 132 #define IPU_IRQ_DC_FC_3 (448 + 11) 133 #define IPU_IRQ_DC_FC_4 (448 + 12) 134 #define IPU_IRQ_DC_FC_6 (448 + 13) 135 #define IPU_IRQ_VSYNC_PRE_0 (448 + 14) 136 #define IPU_IRQ_VSYNC_PRE_1 (448 + 15) 137 138 /* 139 * IPU Common functions 140 */ 141 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2); 142 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi); 143 void ipu_dump(struct ipu_soc *ipu); 144 145 /* 146 * IPU Image DMA Controller (idmac) functions 147 */ 148 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel); 149 void ipu_idmac_put(struct ipuv3_channel *); 150 151 int ipu_idmac_enable_channel(struct ipuv3_channel *channel); 152 int ipu_idmac_disable_channel(struct ipuv3_channel *channel); 153 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable); 154 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts); 155 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms); 156 157 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, 158 bool doublebuffer); 159 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel); 160 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num); 161 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num); 162 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num); 163 164 /* 165 * IPU Channel Parameter Memory (cpmem) functions 166 */ 167 struct ipu_rgb { 168 struct fb_bitfield red; 169 struct fb_bitfield green; 170 struct fb_bitfield blue; 171 struct fb_bitfield transp; 172 int bits_per_pixel; 173 }; 174 175 struct ipu_image { 176 struct v4l2_pix_format pix; 177 struct v4l2_rect rect; 178 dma_addr_t phys0; 179 dma_addr_t phys1; 180 }; 181 182 void ipu_cpmem_zero(struct ipuv3_channel *ch); 183 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres); 184 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride); 185 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch); 186 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf); 187 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride); 188 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id); 189 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize); 190 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch); 191 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch, 192 enum ipu_rotate_mode rot); 193 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch, 194 const struct ipu_rgb *rgb); 195 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width); 196 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format); 197 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, 198 u32 pixel_format, int stride, 199 int u_offset, int v_offset); 200 void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch, 201 u32 pixel_format, int stride, int height); 202 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc); 203 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image); 204 void ipu_cpmem_dump(struct ipuv3_channel *ch); 205 206 /* 207 * IPU Display Controller (dc) functions 208 */ 209 struct ipu_dc; 210 struct ipu_di; 211 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel); 212 void ipu_dc_put(struct ipu_dc *dc); 213 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, 214 u32 pixel_fmt, u32 width); 215 void ipu_dc_enable(struct ipu_soc *ipu); 216 void ipu_dc_enable_channel(struct ipu_dc *dc); 217 void ipu_dc_disable_channel(struct ipu_dc *dc); 218 void ipu_dc_disable(struct ipu_soc *ipu); 219 220 /* 221 * IPU Display Interface (di) functions 222 */ 223 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp); 224 void ipu_di_put(struct ipu_di *); 225 int ipu_di_disable(struct ipu_di *); 226 int ipu_di_enable(struct ipu_di *); 227 int ipu_di_get_num(struct ipu_di *); 228 int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode); 229 int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig); 230 231 /* 232 * IPU Display Multi FIFO Controller (dmfc) functions 233 */ 234 struct dmfc_channel; 235 int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc); 236 void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc); 237 int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc, 238 unsigned long bandwidth_mbs, int burstsize); 239 void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc); 240 int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width); 241 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel); 242 void ipu_dmfc_put(struct dmfc_channel *dmfc); 243 244 /* 245 * IPU Display Processor (dp) functions 246 */ 247 #define IPU_DP_FLOW_SYNC_BG 0 248 #define IPU_DP_FLOW_SYNC_FG 1 249 #define IPU_DP_FLOW_ASYNC0_BG 2 250 #define IPU_DP_FLOW_ASYNC0_FG 3 251 #define IPU_DP_FLOW_ASYNC1_BG 4 252 #define IPU_DP_FLOW_ASYNC1_FG 5 253 254 struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow); 255 void ipu_dp_put(struct ipu_dp *); 256 int ipu_dp_enable(struct ipu_soc *ipu); 257 int ipu_dp_enable_channel(struct ipu_dp *dp); 258 void ipu_dp_disable_channel(struct ipu_dp *dp); 259 void ipu_dp_disable(struct ipu_soc *ipu); 260 int ipu_dp_setup_channel(struct ipu_dp *dp, 261 enum ipu_color_space in, enum ipu_color_space out); 262 int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos); 263 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha, 264 bool bg_chan); 265 266 /* 267 * IPU CMOS Sensor Interface (csi) functions 268 */ 269 struct ipu_csi; 270 int ipu_csi_init_interface(struct ipu_csi *csi, 271 struct v4l2_mbus_config *mbus_cfg, 272 struct v4l2_mbus_framefmt *mbus_fmt); 273 bool ipu_csi_is_interlaced(struct ipu_csi *csi); 274 void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w); 275 void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w); 276 void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active, 277 u32 r_value, u32 g_value, u32 b_value, 278 u32 pix_clk); 279 int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc, 280 struct v4l2_mbus_framefmt *mbus_fmt); 281 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip, 282 u32 max_ratio, u32 id); 283 int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest); 284 int ipu_csi_enable(struct ipu_csi *csi); 285 int ipu_csi_disable(struct ipu_csi *csi); 286 struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id); 287 void ipu_csi_put(struct ipu_csi *csi); 288 void ipu_csi_dump(struct ipu_csi *csi); 289 290 /* 291 * IPU Image Converter (ic) functions 292 */ 293 enum ipu_ic_task { 294 IC_TASK_ENCODER, 295 IC_TASK_VIEWFINDER, 296 IC_TASK_POST_PROCESSOR, 297 IC_NUM_TASKS, 298 }; 299 300 struct ipu_ic; 301 int ipu_ic_task_init(struct ipu_ic *ic, 302 int in_width, int in_height, 303 int out_width, int out_height, 304 enum ipu_color_space in_cs, 305 enum ipu_color_space out_cs); 306 int ipu_ic_task_graphics_init(struct ipu_ic *ic, 307 enum ipu_color_space in_g_cs, 308 bool galpha_en, u32 galpha, 309 bool colorkey_en, u32 colorkey); 310 void ipu_ic_task_enable(struct ipu_ic *ic); 311 void ipu_ic_task_disable(struct ipu_ic *ic); 312 int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel, 313 u32 width, u32 height, int burst_size, 314 enum ipu_rotate_mode rot); 315 int ipu_ic_enable(struct ipu_ic *ic); 316 int ipu_ic_disable(struct ipu_ic *ic); 317 struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task); 318 void ipu_ic_put(struct ipu_ic *ic); 319 void ipu_ic_dump(struct ipu_ic *ic); 320 321 /* 322 * IPU Sensor Multiple FIFO Controller (SMFC) functions 323 */ 324 struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno); 325 void ipu_smfc_put(struct ipu_smfc *smfc); 326 int ipu_smfc_enable(struct ipu_smfc *smfc); 327 int ipu_smfc_disable(struct ipu_smfc *smfc); 328 int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id); 329 int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize); 330 int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level); 331 332 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc); 333 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat); 334 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code); 335 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat); 336 bool ipu_pixelformat_is_planar(u32 pixelformat); 337 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees, 338 bool hflip, bool vflip); 339 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode, 340 bool hflip, bool vflip); 341 342 struct ipu_client_platformdata { 343 int csi; 344 int di; 345 int dc; 346 int dp; 347 int dma[2]; 348 struct device_node *of_node; 349 }; 350 351 #endif /* __DRM_IPU_H__ */ 352