1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 ******************************************************************************/
15 /*++
16 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
17
18 Module Name:
19 HalPwrSeqCmd.c
20
21 Abstract:
22 Implement HW Power sequence configuration CMD handling routine for
23 Realtek devices.
24
25 Major Change History:
26 When Who What
27 ---------- --------------- -------------------------------
28 2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
29 2011-07-07 Roger Create.
30
31 --*/
32 #include <HalPwrSeqCmd.h>
33 #include <usb_ops_linux.h>
34
35 /* */
36 /* Description: */
37 /* This routine deal with the Power Configuration CMDs parsing
38 for RTL8723/RTL8188E Series IC. */
39 /* */
40 /* Assumption: */
41 /* We should follow specific format which was released from
42 HW SD. */
43 /* */
44 /* 2011.07.07, added by Roger. */
45 /* */
HalPwrSeqCmdParsing23a(struct rtw_adapter * padapter,u8 CutVersion,u8 FabVersion,u8 InterfaceType,struct wlan_pwr_cfg PwrSeqCmd[])46 u8 HalPwrSeqCmdParsing23a(struct rtw_adapter *padapter, u8 CutVersion,
47 u8 FabVersion, u8 InterfaceType,
48 struct wlan_pwr_cfg PwrSeqCmd[])
49 {
50 struct wlan_pwr_cfg PwrCfgCmd;
51 u8 bPollingBit;
52 u32 AryIdx = 0;
53 u8 value;
54 u32 offset;
55 u32 pollingCount = 0; /* polling autoload done. */
56 u32 maxPollingCnt = 5000;
57
58 do {
59 PwrCfgCmd = PwrSeqCmd[AryIdx];
60
61 RT_TRACE(_module_hal_init_c_, _drv_info_,
62 "HalPwrSeqCmdParsing23a: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
63 GET_PWR_CFG_OFFSET(PwrCfgCmd),
64 GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
65 GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
66 GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
67 GET_PWR_CFG_BASE(PwrCfgCmd),
68 GET_PWR_CFG_CMD(PwrCfgCmd),
69 GET_PWR_CFG_MASK(PwrCfgCmd),
70 GET_PWR_CFG_VALUE(PwrCfgCmd));
71
72 /* 2 Only Handle the command whose FAB, CUT, and Interface are
73 matched */
74 if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
75 (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
76 (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
77 switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
78 case PWR_CMD_READ:
79 RT_TRACE(_module_hal_init_c_, _drv_info_,
80 "HalPwrSeqCmdParsing23a: PWR_CMD_READ\n");
81 break;
82
83 case PWR_CMD_WRITE:
84 RT_TRACE(_module_hal_init_c_, _drv_info_,
85 "HalPwrSeqCmdParsing23a: PWR_CMD_WRITE\n");
86 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
87
88 /* Read the value from system register */
89 value = rtl8723au_read8(padapter, offset);
90
91 value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
92 value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) &
93 GET_PWR_CFG_MASK(PwrCfgCmd));
94
95 /* Write the value back to system register */
96 rtl8723au_write8(padapter, offset, value);
97 break;
98
99 case PWR_CMD_POLLING:
100 RT_TRACE(_module_hal_init_c_, _drv_info_,
101 "HalPwrSeqCmdParsing23a: PWR_CMD_POLLING\n");
102
103 bPollingBit = false;
104 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
105 do {
106 value = rtl8723au_read8(padapter,
107 offset);
108
109 value &= GET_PWR_CFG_MASK(PwrCfgCmd);
110 if (value ==
111 (GET_PWR_CFG_VALUE(PwrCfgCmd) &
112 GET_PWR_CFG_MASK(PwrCfgCmd)))
113 bPollingBit = true;
114 else
115 udelay(10);
116
117 if (pollingCount++ > maxPollingCnt) {
118 DBG_8723A("Fail to polling "
119 "Offset[%#x]\n",
120 offset);
121 return false;
122 }
123 } while (!bPollingBit);
124
125 break;
126
127 case PWR_CMD_DELAY:
128 RT_TRACE(_module_hal_init_c_, _drv_info_,
129 "HalPwrSeqCmdParsing23a: PWR_CMD_DELAY\n");
130 if (GET_PWR_CFG_VALUE(PwrCfgCmd) ==
131 PWRSEQ_DELAY_US)
132 udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd));
133 else
134 udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd) *
135 1000);
136 break;
137
138 case PWR_CMD_END:
139 /* When this command is parsed, end
140 the process */
141 RT_TRACE(_module_hal_init_c_, _drv_info_,
142 "HalPwrSeqCmdParsing23a: PWR_CMD_END\n");
143 return true;
144
145 default:
146 RT_TRACE(_module_hal_init_c_, _drv_err_,
147 "HalPwrSeqCmdParsing23a: Unknown CMD!!\n");
148 break;
149 }
150 }
151
152 AryIdx++; /* Add Array Index */
153 } while (1);
154
155 return true;
156 }
157