1 /******************************************************************************
2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3  *
4  * This program is distributed in the hope that it will be useful, but WITHOUT
5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
7  * more details.
8  *
9  * You should have received a copy of the GNU General Public License along with
10  * this program; if not, write to the Free Software Foundation, Inc.,
11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
12  *
13  * The full GNU General Public License is included in this distribution in the
14  * file called LICENSE.
15  *
16  * Contact Information:
17  * wlanfae <wlanfae@realtek.com>
18 ******************************************************************************/
19 #ifndef _RTL819XU_HTTYPE_H_
20 #define _RTL819XU_HTTYPE_H_
21 
22 
23 #define HT_OPMODE_NO_PROTECT		0
24 #define HT_OPMODE_OPTIONAL		1
25 #define HT_OPMODE_40MHZ_PROTECT	2
26 #define HT_OPMODE_MIXED			3
27 
28 #define MIMO_PS_STATIC				0
29 #define MIMO_PS_DYNAMIC			1
30 #define MIMO_PS_NOLIMIT			3
31 
32 
33 
34 #define sHTCLng	4
35 
36 
37 #define HT_SUPPORTED_MCS_1SS_BITMAP			0x000000ff
38 #define HT_SUPPORTED_MCS_2SS_BITMAP			0x0000ff00
39 #define HT_SUPPORTED_MCS_1SS_2SS_BITMAP			\
40 	(HT_MCS_1SS_BITMAP | HT_MCS_1SS_2SS_BITMAP)
41 
42 enum ht_mcs_rate {
43 	HT_MCS0   = 0x00000001,
44 	HT_MCS1   = 0x00000002,
45 	HT_MCS2   = 0x00000004,
46 	HT_MCS3   = 0x00000008,
47 	HT_MCS4   = 0x00000010,
48 	HT_MCS5   = 0x00000020,
49 	HT_MCS6   = 0x00000040,
50 	HT_MCS7   = 0x00000080,
51 	HT_MCS8   = 0x00000100,
52 	HT_MCS9   = 0x00000200,
53 	HT_MCS10 = 0x00000400,
54 	HT_MCS11 = 0x00000800,
55 	HT_MCS12 = 0x00001000,
56 	HT_MCS13 = 0x00002000,
57 	HT_MCS14 = 0x00004000,
58 	HT_MCS15 = 0x00008000,
59 };
60 
61 enum ht_channel_width {
62 	HT_CHANNEL_WIDTH_20 = 0,
63 	HT_CHANNEL_WIDTH_20_40 = 1,
64 };
65 
66 enum ht_extchnl_offset {
67 	HT_EXTCHNL_OFFSET_NO_EXT = 0,
68 	HT_EXTCHNL_OFFSET_UPPER = 1,
69 	HT_EXTCHNL_OFFSET_NO_DEF = 2,
70 	HT_EXTCHNL_OFFSET_LOWER = 3,
71 };
72 
73 enum chnl_op {
74 	CHNLOP_NONE = 0,
75 	CHNLOP_SCAN = 1,
76 	CHNLOP_SWBW = 2,
77 	CHNLOP_SWCHNL = 3,
78 };
79 
80 enum ht_action {
81 	ACT_RECOMMAND_WIDTH		= 0,
82 	ACT_MIMO_PWR_SAVE		= 1,
83 	ACT_PSMP					= 2,
84 	ACT_SET_PCO_PHASE		= 3,
85 	ACT_MIMO_CHL_MEASURE	= 4,
86 	ACT_RECIPROCITY_CORRECT	= 5,
87 	ACT_MIMO_CSI_MATRICS		= 6,
88 	ACT_MIMO_NOCOMPR_STEER	= 7,
89 	ACT_MIMO_COMPR_STEER		= 8,
90 	ACT_ANTENNA_SELECT		= 9,
91 };
92 
93 
94 enum ht_bw40_sc {
95 	SC_MODE_DUPLICATE = 0,
96 	SC_MODE_LOWER = 1,
97 	SC_MODE_UPPER = 2,
98 	SC_MODE_FULL40MHZ = 3,
99 };
100 
101 struct ht_capab_ele {
102 
103 	u8	AdvCoding:1;
104 	u8	ChlWidth:1;
105 	u8	MimoPwrSave:2;
106 	u8	GreenField:1;
107 	u8	ShortGI20Mhz:1;
108 	u8	ShortGI40Mhz:1;
109 	u8	TxSTBC:1;
110 	u8	RxSTBC:2;
111 	u8	DelayBA:1;
112 	u8	MaxAMSDUSize:1;
113 	u8	DssCCk:1;
114 	u8	PSMP:1;
115 	u8	Rsvd1:1;
116 	u8	LSigTxopProtect:1;
117 
118 	u8	MaxRxAMPDUFactor:2;
119 	u8	MPDUDensity:3;
120 	u8	Rsvd2:3;
121 
122 	u8	MCS[16];
123 
124 
125 	u16	ExtHTCapInfo;
126 
127 	u8	TxBFCap[4];
128 
129 	u8	ASCap;
130 
131 } __packed;
132 
133 
134 struct ht_info_ele {
135 	u8	ControlChl;
136 
137 	u8	ExtChlOffset:2;
138 	u8	RecommemdedTxWidth:1;
139 	u8	RIFS:1;
140 	u8	PSMPAccessOnly:1;
141 	u8	SrvIntGranularity:3;
142 
143 	u8	OptMode:2;
144 	u8	NonGFDevPresent:1;
145 	u8	Revd1:5;
146 	u8	Revd2:8;
147 
148 	u8	Rsvd3:6;
149 	u8	DualBeacon:1;
150 	u8	DualCTSProtect:1;
151 
152 	u8	SecondaryBeacon:1;
153 	u8	LSigTxopProtectFull:1;
154 	u8	PcoActive:1;
155 	u8	PcoPhase:1;
156 	u8	Rsvd4:4;
157 
158 	u8	BasicMSC[16];
159 } __packed;
160 
161 struct mimops_ctrl {
162 	u8	MimoPsEnable:1;
163 	u8	MimoPsMode:1;
164 	u8	Reserved:6;
165 };
166 
167 enum ht_spec_ver {
168 	HT_SPEC_VER_IEEE = 0,
169 	HT_SPEC_VER_EWC = 1,
170 };
171 
172 enum ht_aggre_mode {
173 	HT_AGG_AUTO = 0,
174 	HT_AGG_FORCE_ENABLE = 1,
175 	HT_AGG_FORCE_DISABLE = 2,
176 };
177 
178 
179 struct rt_hi_throughput {
180 	u8				bEnableHT;
181 	u8				bCurrentHTSupport;
182 
183 	u8				bRegBW40MHz;
184 	u8				bCurBW40MHz;
185 
186 	u8				bRegShortGI40MHz;
187 	u8				bCurShortGI40MHz;
188 
189 	u8				bRegShortGI20MHz;
190 	u8				bCurShortGI20MHz;
191 
192 	u8				bRegSuppCCK;
193 	u8				bCurSuppCCK;
194 
195 	enum ht_spec_ver ePeerHTSpecVer;
196 
197 
198 	struct ht_capab_ele SelfHTCap;
199 	struct ht_info_ele SelfHTInfo;
200 
201 	u8				PeerHTCapBuf[32];
202 	u8				PeerHTInfoBuf[32];
203 
204 
205 	u8				bAMSDU_Support;
206 	u16				nAMSDU_MaxSize;
207 	u8				bCurrent_AMSDU_Support;
208 	u16				nCurrent_AMSDU_MaxSize;
209 
210 	u8				bAMPDUEnable;
211 	u8				bCurrentAMPDUEnable;
212 	u8				AMPDU_Factor;
213 	u8				CurrentAMPDUFactor;
214 	u8				MPDU_Density;
215 	u8				CurrentMPDUDensity;
216 
217 	enum ht_aggre_mode ForcedAMPDUMode;
218 	u8				ForcedAMPDUFactor;
219 	u8				ForcedMPDUDensity;
220 
221 	enum ht_aggre_mode ForcedAMSDUMode;
222 	u16				ForcedAMSDUMaxSize;
223 
224 	u8				bForcedShortGI;
225 
226 	u8				CurrentOpMode;
227 
228 	u8				SelfMimoPs;
229 	u8				PeerMimoPs;
230 
231 	enum ht_extchnl_offset CurSTAExtChnlOffset;
232 	u8				bCurTxBW40MHz;
233 	u8				PeerBandwidth;
234 
235 	u8				bSwBwInProgress;
236 	enum chnl_op ChnlOp;
237 	u8				SwBwStep;
238 
239 	u8				bRegRT2RTAggregation;
240 	u8				RT2RT_HT_Mode;
241 	u8				bCurrentRT2RTAggregation;
242 	u8				bCurrentRT2RTLongSlotTime;
243 	u8				szRT2RTAggBuffer[10];
244 
245 	u8				bRegRxReorderEnable;
246 	u8				bCurRxReorderEnable;
247 	u8				RxReorderWinSize;
248 	u8				RxReorderPendingTime;
249 	u16				RxReorderDropCounter;
250 
251 	u8				bIsPeerBcm;
252 
253 	u8				IOTPeer;
254 	u32				IOTAction;
255 	u8				IOTRaFunc;
256 
257 	u8	bWAIotBroadcom;
258 	u8	WAIotTH;
259 
260 	u8				bAcceptAddbaReq;
261 } __packed;
262 
263 
264 
265 struct rt_htinfo_sta_entry {
266 	u8			bEnableHT;
267 
268 	u8			bSupportCck;
269 
270 	u16			AMSDU_MaxSize;
271 
272 	u8			AMPDU_Factor;
273 	u8			MPDU_Density;
274 
275 	u8			HTHighestOperaRate;
276 
277 	u8			bBw40MHz;
278 
279 	u8			bCurTxBW40MHz;
280 
281 	u8			bCurShortGI20MHz;
282 
283 	u8			bCurShortGI40MHz;
284 
285 	u8			MimoPs;
286 
287 	u8			McsRateSet[16];
288 
289 	u8                      bCurRxReorderEnable;
290 
291 	u16                     nAMSDU_MaxSize;
292 
293 };
294 
295 
296 
297 
298 
299 
300 struct bss_ht {
301 
302 	u8				bdSupportHT;
303 
304 	u8					bdHTCapBuf[32];
305 	u16					bdHTCapLen;
306 	u8					bdHTInfoBuf[32];
307 	u16					bdHTInfoLen;
308 
309 	enum ht_spec_ver bdHTSpecVer;
310 	enum ht_channel_width bdBandWidth;
311 
312 	u8					bdRT2RTAggregation;
313 	u8					bdRT2RTLongSlotTime;
314 	u8					RT2RT_HT_Mode;
315 	u8					bdHT1R;
316 };
317 
318 struct mimo_rssi {
319 	u32	EnableAntenna;
320 	u32	AntennaA;
321 	u32	AntennaB;
322 	u32	AntennaC;
323 	u32	AntennaD;
324 	u32	Average;
325 };
326 
327 struct mimo_evm {
328 	u32	EVM1;
329 	u32    EVM2;
330 };
331 
332 struct false_alarm_stats {
333 	u32	Cnt_Parity_Fail;
334 	u32	Cnt_Rate_Illegal;
335 	u32	Cnt_Crc8_fail;
336 	u32	Cnt_Mcs_fail;
337 	u32	Cnt_Ofdm_fail;
338 	u32	Cnt_Cck_fail;
339 	u32	Cnt_all;
340 };
341 
342 
343 extern u8 MCS_FILTER_ALL[16];
344 extern u8 MCS_FILTER_1SS[16];
345 
346 #define	RATE_ADPT_1SS_MASK		0xFF
347 #define	RATE_ADPT_2SS_MASK		0xF0
348 #define	RATE_ADPT_MCS32_MASK		0x01
349 
350 #define		IS_11N_MCS_RATE(rate)		(rate&0x80)
351 
352 enum ht_aggre_size {
353 	HT_AGG_SIZE_8K = 0,
354 	HT_AGG_SIZE_16K = 1,
355 	HT_AGG_SIZE_32K = 2,
356 	HT_AGG_SIZE_64K = 3,
357 };
358 
359 enum ht_iot_peer {
360 	HT_IOT_PEER_UNKNOWN = 0,
361 	HT_IOT_PEER_REALTEK = 1,
362 	HT_IOT_PEER_REALTEK_92SE = 2,
363 	HT_IOT_PEER_BROADCOM = 3,
364 	HT_IOT_PEER_RALINK = 4,
365 	HT_IOT_PEER_ATHEROS = 5,
366 	HT_IOT_PEER_CISCO = 6,
367 	HT_IOT_PEER_MARVELL = 7,
368 	HT_IOT_PEER_92U_SOFTAP = 8,
369 	HT_IOT_PEER_SELF_SOFTAP = 9,
370 	HT_IOT_PEER_AIRGO = 10,
371 	HT_IOT_PEER_MAX = 11,
372 };
373 
374 enum ht_iot_peer_subtype {
375 	HT_IOT_PEER_ATHEROS_DIR635 = 0,
376 };
377 
378 enum ht_iot_action {
379 	HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
380 	HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
381 	HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
382 	HT_IOT_ACT_DISABLE_MCS15 = 0x00000008,
383 	HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010,
384 	HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020,
385 	HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040,
386 	HT_IOT_ACT_CDD_FSYNC = 0x00000080,
387 	HT_IOT_ACT_PURE_N_MODE = 0x00000100,
388 	HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200,
389 	HT_IOT_ACT_FORCED_RTS = 0x00000400,
390 	HT_IOT_ACT_AMSDU_ENABLE = 0x00000800,
391 	HT_IOT_ACT_REJECT_ADDBA_REQ = 0x00001000,
392 	HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT = 0x00002000,
393 	HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00004000,
394 
395 	HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000,
396 	HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000,
397 	HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000,
398 	HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000,
399 	HT_IOT_ACT_TX_NO_AGGREGATION = 0x00100000,
400 	HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000,
401 
402 	HT_IOT_ACT_MID_HIGHPOWER = 0x00400000,
403 	HT_IOT_ACT_NULL_DATA_POWER_SAVING = 0x00800000,
404 
405 	HT_IOT_ACT_DISABLE_CCK_RATE = 0x01000000,
406 	HT_IOT_ACT_FORCED_ENABLE_BE_TXOP = 0x02000000,
407 	HT_IOT_ACT_WA_IOT_Broadcom = 0x04000000,
408 
409 	HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI = 0x08000000,
410 
411 };
412 
413 enum ht_iot_rafunc {
414 	HT_IOT_RAFUNC_DISABLE_ALL = 0x00,
415 	HT_IOT_RAFUNC_PEER_1R = 0x01,
416 	HT_IOT_RAFUNC_TX_AMSDU = 0x02,
417 };
418 
419 enum rt_ht_capability {
420 	RT_HT_CAP_USE_TURBO_AGGR = 0x01,
421 	RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
422 	RT_HT_CAP_USE_AMPDU = 0x04,
423 	RT_HT_CAP_USE_WOW = 0x8,
424 	RT_HT_CAP_USE_SOFTAP = 0x10,
425 	RT_HT_CAP_USE_92SE = 0x20,
426 };
427 
428 #endif
429