1 /*
2     drivers/ni_tio_internal.h
3     Header file for NI general purpose counter support code (ni_tio.c and
4     ni_tiocmd.c)
5 
6     COMEDI - Linux Control and Measurement Device Interface
7 
8     This program is free software; you can redistribute it and/or modify
9     it under the terms of the GNU General Public License as published by
10     the Free Software Foundation; either version 2 of the License, or
11     (at your option) any later version.
12 
13     This program is distributed in the hope that it will be useful,
14     but WITHOUT ANY WARRANTY; without even the implied warranty of
15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16     GNU General Public License for more details.
17 */
18 
19 #ifndef _COMEDI_NI_TIO_INTERNAL_H
20 #define _COMEDI_NI_TIO_INTERNAL_H
21 
22 #include "ni_tio.h"
23 
24 #define NITIO_AUTO_INC_REG(x)		(NITIO_G0_AUTO_INC + (x))
25 #define GI_AUTO_INC_MASK		0xff
26 #define NITIO_CMD_REG(x)		(NITIO_G0_CMD + (x))
27 #define GI_ARM				(1 << 0)
28 #define GI_SAVE_TRACE			(1 << 1)
29 #define GI_LOAD				(1 << 2)
30 #define GI_DISARM			(1 << 4)
31 #define GI_CNT_DIR(x)			(((x) & 0x3) << 5)
32 #define GI_CNT_DIR_MASK			(3 << 5)
33 #define GI_WRITE_SWITCH			(1 << 7)
34 #define GI_SYNC_GATE			(1 << 8)
35 #define GI_LITTLE_BIG_ENDIAN		(1 << 9)
36 #define GI_BANK_SWITCH_START		(1 << 10)
37 #define GI_BANK_SWITCH_MODE		(1 << 11)
38 #define GI_BANK_SWITCH_ENABLE		(1 << 12)
39 #define GI_ARM_COPY			(1 << 13)
40 #define GI_SAVE_TRACE_COPY		(1 << 14)
41 #define GI_DISARM_COPY			(1 << 15)
42 #define NITIO_HW_SAVE_REG(x)		(NITIO_G0_HW_SAVE + (x))
43 #define NITIO_SW_SAVE_REG(x)		(NITIO_G0_SW_SAVE + (x))
44 #define NITIO_MODE_REG(x)		(NITIO_G0_MODE + (x))
45 #define GI_GATING_DISABLED		(0 << 0)
46 #define GI_LEVEL_GATING			(1 << 0)
47 #define GI_RISING_EDGE_GATING		(2 << 0)
48 #define GI_FALLING_EDGE_GATING		(3 << 0)
49 #define GI_GATING_MODE_MASK		(3 << 0)
50 #define GI_GATE_ON_BOTH_EDGES		(1 << 2)
51 #define GI_EDGE_GATE_STARTS_STOPS	(0 << 3)
52 #define GI_EDGE_GATE_STOPS_STARTS	(1 << 3)
53 #define GI_EDGE_GATE_STARTS		(2 << 3)
54 #define GI_EDGE_GATE_NO_STARTS_OR_STOPS	(3 << 3)
55 #define GI_EDGE_GATE_MODE_MASK		(3 << 3)
56 #define GI_STOP_ON_GATE			(0 << 5)
57 #define GI_STOP_ON_GATE_OR_TC		(1 << 5)
58 #define GI_STOP_ON_GATE_OR_SECOND_TC	(2 << 5)
59 #define GI_STOP_MODE_MASK		(3 << 5)
60 #define GI_LOAD_SRC_SEL			(1 << 7)
61 #define GI_OUTPUT_TC_PULSE		(1 << 8)
62 #define GI_OUTPUT_TC_TOGGLE		(2 << 8)
63 #define GI_OUTPUT_TC_OR_GATE_TOGGLE	(3 << 8)
64 #define GI_OUTPUT_MODE_MASK		(3 << 8)
65 #define GI_NO_HARDWARE_DISARM		(0 << 10)
66 #define GI_DISARM_AT_TC			(1 << 10)
67 #define GI_DISARM_AT_GATE		(2 << 10)
68 #define GI_DISARM_AT_TC_OR_GATE		(3 << 10)
69 #define GI_COUNTING_ONCE_MASK		(3 << 10)
70 #define GI_LOADING_ON_TC		(1 << 12)
71 #define GI_GATE_POL_INVERT		(1 << 13)
72 #define GI_LOADING_ON_GATE		(1 << 14)
73 #define GI_RELOAD_SRC_SWITCHING		(1 << 15)
74 #define NITIO_LOADA_REG(x)		(NITIO_G0_LOADA + (x))
75 #define NITIO_LOADB_REG(x)		(NITIO_G0_LOADB + (x))
76 #define NITIO_INPUT_SEL_REG(x)		(NITIO_G0_INPUT_SEL + (x))
77 #define GI_READ_ACKS_IRQ		(1 << 0)
78 #define GI_WRITE_ACKS_IRQ		(1 << 1)
79 #define GI_BITS_TO_SRC(x)		(((x) >> 2) & 0x1f)
80 #define GI_SRC_SEL(x)			(((x) & 0x1f) << 2)
81 #define GI_SRC_SEL_MASK			(0x1f << 2)
82 #define GI_BITS_TO_GATE(x)		(((x) >> 7) & 0x1f)
83 #define GI_GATE_SEL(x)			(((x) & 0x1f) << 7)
84 #define GI_GATE_SEL_MASK		(0x1f << 7)
85 #define GI_GATE_SEL_LOAD_SRC		(1 << 12)
86 #define GI_OR_GATE			(1 << 13)
87 #define GI_OUTPUT_POL_INVERT		(1 << 14)
88 #define GI_SRC_POL_INVERT		(1 << 15)
89 #define NITIO_CNT_MODE_REG(x)		(NITIO_G0_CNT_MODE + (x))
90 #define GI_CNT_MODE(x)			(((x) & 0x7) << 0)
91 #define GI_CNT_MODE_NORMAL		GI_CNT_MODE(0)
92 #define GI_CNT_MODE_QUADX1		GI_CNT_MODE(1)
93 #define GI_CNT_MODE_QUADX2		GI_CNT_MODE(2)
94 #define GI_CNT_MODE_QUADX4		GI_CNT_MODE(3)
95 #define GI_CNT_MODE_TWO_PULSE		GI_CNT_MODE(4)
96 #define GI_CNT_MODE_SYNC_SRC		GI_CNT_MODE(6)
97 #define GI_CNT_MODE_MASK		(7 << 0)
98 #define GI_INDEX_MODE			(1 << 4)
99 #define GI_INDEX_PHASE(x)		(((x) & 0x3) << 5)
100 #define GI_INDEX_PHASE_MASK		(3 << 5)
101 #define GI_HW_ARM_ENA			(1 << 7)
102 #define GI_HW_ARM_SEL(x)		((x) << 8)
103 #define GI_660X_HW_ARM_SEL_MASK		(0x7 << 8)
104 #define GI_M_HW_ARM_SEL_MASK		(0x1f << 8)
105 #define GI_660X_PRESCALE_X8		(1 << 12)
106 #define GI_M_PRESCALE_X8		(1 << 13)
107 #define GI_660X_ALT_SYNC		(1 << 13)
108 #define GI_M_ALT_SYNC			(1 << 14)
109 #define GI_660X_PRESCALE_X2		(1 << 14)
110 #define GI_M_PRESCALE_X2		(1 << 15)
111 #define NITIO_GATE2_REG(x)		(NITIO_G0_GATE2 + (x))
112 #define GI_GATE2_MODE			(1 << 0)
113 #define GI_BITS_TO_GATE2(x)		(((x) >> 7) & 0x1f)
114 #define GI_GATE2_SEL(x)			(((x) & 0x1f) << 7)
115 #define GI_GATE2_SEL_MASK		(0x1f << 7)
116 #define GI_GATE2_POL_INVERT		(1 << 13)
117 #define GI_GATE2_SUBSEL			(1 << 14)
118 #define GI_SRC_SUBSEL			(1 << 15)
119 #define NITIO_SHARED_STATUS_REG(x)	(NITIO_G01_STATUS + ((x) / 2))
120 #define GI_SAVE(x)			(((x) % 2) ? (1 << 1) : (1 << 0))
121 #define GI_COUNTING(x)			(((x) % 2) ? (1 << 3) : (1 << 2))
122 #define GI_NEXT_LOAD_SRC(x)		(((x) % 2) ? (1 << 5) : (1 << 4))
123 #define GI_STALE_DATA(x)		(((x) % 2) ? (1 << 7) : (1 << 6))
124 #define GI_ARMED(x)			(((x) % 2) ? (1 << 9) : (1 << 8))
125 #define GI_NO_LOAD_BETWEEN_GATES(x)	(((x) % 2) ? (1 << 11) : (1 << 10))
126 #define GI_TC_ERROR(x)			(((x) % 2) ? (1 << 13) : (1 << 12))
127 #define GI_GATE_ERROR(x)		(((x) % 2) ? (1 << 15) : (1 << 14))
128 #define NITIO_RESET_REG(x)		(NITIO_G01_RESET + ((x) / 2))
129 #define GI_RESET(x)			(1 << (2 + ((x) % 2)))
130 #define NITIO_STATUS1_REG(x)		(NITIO_G01_STATUS1 + ((x) / 2))
131 #define NITIO_STATUS2_REG(x)		(NITIO_G01_STATUS2 + ((x) / 2))
132 #define GI_OUTPUT(x)			(((x) % 2) ? (1 << 1) : (1 << 0))
133 #define GI_HW_SAVE(x)			(((x) % 2) ? (1 << 13) : (1 << 12))
134 #define GI_PERMANENT_STALE(x)		(((x) % 2) ? (1 << 15) : (1 << 14))
135 #define NITIO_DMA_CFG_REG(x)		(NITIO_G0_DMA_CFG + (x))
136 #define GI_DMA_ENABLE			(1 << 0)
137 #define GI_DMA_WRITE			(1 << 1)
138 #define GI_DMA_INT_ENA			(1 << 2)
139 #define GI_DMA_RESET			(1 << 3)
140 #define GI_DMA_BANKSW_ERROR		(1 << 4)
141 #define NITIO_DMA_STATUS_REG(x)		(NITIO_G0_DMA_STATUS + (x))
142 #define GI_DMA_READBANK			(1 << 13)
143 #define GI_DRQ_ERROR			(1 << 14)
144 #define GI_DRQ_STATUS			(1 << 15)
145 #define NITIO_ABZ_REG(x)		(NITIO_G0_ABZ + (x))
146 #define NITIO_INT_ACK_REG(x)		(NITIO_G0_INT_ACK + (x))
147 #define GI_GATE_ERROR_CONFIRM(x)	(((x) % 2) ? (1 << 1) : (1 << 5))
148 #define GI_TC_ERROR_CONFIRM(x)		(((x) % 2) ? (1 << 2) : (1 << 6))
149 #define GI_TC_INTERRUPT_ACK		(1 << 14)
150 #define GI_GATE_INTERRUPT_ACK		(1 << 15)
151 #define NITIO_STATUS_REG(x)		(NITIO_G0_STATUS + (x))
152 #define GI_GATE_INTERRUPT		(1 << 2)
153 #define GI_TC				(1 << 3)
154 #define GI_INTERRUPT			(1 << 15)
155 #define NITIO_INT_ENA_REG(x)		(NITIO_G0_INT_ENA + (x))
156 #define GI_TC_INTERRUPT_ENABLE(x)	(((x) % 2) ? (1 << 9) : (1 << 6))
157 #define GI_GATE_INTERRUPT_ENABLE(x)	(((x) % 2) ? (1 << 10) : (1 << 8))
158 
write_register(struct ni_gpct * counter,unsigned bits,enum ni_gpct_register reg)159 static inline void write_register(struct ni_gpct *counter, unsigned bits,
160 				  enum ni_gpct_register reg)
161 {
162 	BUG_ON(reg >= NITIO_NUM_REGS);
163 	counter->counter_dev->write_register(counter, bits, reg);
164 }
165 
read_register(struct ni_gpct * counter,enum ni_gpct_register reg)166 static inline unsigned read_register(struct ni_gpct *counter,
167 				     enum ni_gpct_register reg)
168 {
169 	BUG_ON(reg >= NITIO_NUM_REGS);
170 	return counter->counter_dev->read_register(counter, reg);
171 }
172 
ni_tio_counting_mode_registers_present(const struct ni_gpct_device * counter_dev)173 static inline int ni_tio_counting_mode_registers_present(const struct
174 							 ni_gpct_device
175 							 *counter_dev)
176 {
177 	switch (counter_dev->variant) {
178 	case ni_gpct_variant_e_series:
179 		return 0;
180 	case ni_gpct_variant_m_series:
181 	case ni_gpct_variant_660x:
182 		return 1;
183 	default:
184 		BUG();
185 		break;
186 	}
187 	return 0;
188 }
189 
ni_tio_set_bits_transient(struct ni_gpct * counter,enum ni_gpct_register register_index,unsigned bit_mask,unsigned bit_values,unsigned transient_bit_values)190 static inline void ni_tio_set_bits_transient(struct ni_gpct *counter,
191 					     enum ni_gpct_register
192 					     register_index, unsigned bit_mask,
193 					     unsigned bit_values,
194 					     unsigned transient_bit_values)
195 {
196 	struct ni_gpct_device *counter_dev = counter->counter_dev;
197 	unsigned long flags;
198 
199 	BUG_ON(register_index >= NITIO_NUM_REGS);
200 	spin_lock_irqsave(&counter_dev->regs_lock, flags);
201 	counter_dev->regs[register_index] &= ~bit_mask;
202 	counter_dev->regs[register_index] |= (bit_values & bit_mask);
203 	write_register(counter,
204 		       counter_dev->regs[register_index] | transient_bit_values,
205 		       register_index);
206 	mmiowb();
207 	spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
208 }
209 
210 /* ni_tio_set_bits( ) is for safely writing to registers whose bits may be
211  * twiddled in interrupt context, or whose software copy may be read in
212  * interrupt context.
213  */
ni_tio_set_bits(struct ni_gpct * counter,enum ni_gpct_register register_index,unsigned bit_mask,unsigned bit_values)214 static inline void ni_tio_set_bits(struct ni_gpct *counter,
215 				   enum ni_gpct_register register_index,
216 				   unsigned bit_mask, unsigned bit_values)
217 {
218 	ni_tio_set_bits_transient(counter, register_index, bit_mask, bit_values,
219 				  0x0);
220 }
221 
222 /* ni_tio_get_soft_copy( ) is for safely reading the software copy of a register
223 whose bits might be modified in interrupt context, or whose software copy
224 might need to be read in interrupt context.
225 */
ni_tio_get_soft_copy(const struct ni_gpct * counter,enum ni_gpct_register register_index)226 static inline unsigned ni_tio_get_soft_copy(const struct ni_gpct *counter,
227 					    enum ni_gpct_register
228 					    register_index)
229 {
230 	struct ni_gpct_device *counter_dev = counter->counter_dev;
231 	unsigned long flags;
232 	unsigned value;
233 
234 	BUG_ON(register_index >= NITIO_NUM_REGS);
235 	spin_lock_irqsave(&counter_dev->regs_lock, flags);
236 	value = counter_dev->regs[register_index];
237 	spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
238 	return value;
239 }
240 
241 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger);
242 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
243 			unsigned int gate_source);
244 
245 #endif /* _COMEDI_NI_TIO_INTERNAL_H */
246