1 /*
2  * DA9150 MFD Driver - Registers
3  *
4  * Copyright (c) 2014 Dialog Semiconductor
5  *
6  * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
7  *
8  * This program is free software; you can redistribute  it and/or modify it
9  * under  the terms of  the GNU General  Public License as published by the
10  * Free Software Foundation;  either version 2 of the  License, or (at your
11  * option) any later version.
12  */
13 
14 #ifndef __DA9150_REGISTERS_H
15 #define __DA9150_REGISTERS_H
16 
17 #include <linux/bitops.h>
18 
19 /* Registers */
20 #define DA9150_PAGE_CON			0x000
21 #define DA9150_STATUS_A			0x068
22 #define DA9150_STATUS_B			0x069
23 #define DA9150_STATUS_C			0x06A
24 #define DA9150_STATUS_D			0x06B
25 #define DA9150_STATUS_E			0x06C
26 #define DA9150_STATUS_F			0x06D
27 #define DA9150_STATUS_G			0x06E
28 #define DA9150_STATUS_H			0x06F
29 #define DA9150_STATUS_I			0x070
30 #define DA9150_STATUS_J			0x071
31 #define DA9150_STATUS_K			0x072
32 #define DA9150_STATUS_L			0x073
33 #define DA9150_STATUS_N			0x074
34 #define DA9150_FAULT_LOG_A		0x076
35 #define DA9150_FAULT_LOG_B		0x077
36 #define DA9150_EVENT_E			0x078
37 #define DA9150_EVENT_F			0x079
38 #define DA9150_EVENT_G			0x07A
39 #define DA9150_EVENT_H			0x07B
40 #define DA9150_IRQ_MASK_E		0x07C
41 #define DA9150_IRQ_MASK_F		0x07D
42 #define DA9150_IRQ_MASK_G		0x07E
43 #define DA9150_IRQ_MASK_H		0x07F
44 #define DA9150_PAGE_CON_1		0x080
45 #define DA9150_CONFIG_A			0x0E0
46 #define DA9150_CONFIG_B			0x0E1
47 #define DA9150_CONFIG_C			0x0E2
48 #define DA9150_CONFIG_D			0x0E3
49 #define DA9150_CONFIG_E			0x0E4
50 #define DA9150_CONTROL_A		0x0E5
51 #define DA9150_CONTROL_B		0x0E6
52 #define DA9150_CONTROL_C		0x0E7
53 #define DA9150_GPIO_A_B			0x0E8
54 #define DA9150_GPIO_C_D			0x0E9
55 #define DA9150_GPIO_MODE_CONT		0x0EA
56 #define DA9150_GPIO_CTRL_B		0x0EB
57 #define DA9150_GPIO_CTRL_A		0x0EC
58 #define DA9150_GPIO_CTRL_C		0x0ED
59 #define DA9150_GPIO_CFG_A		0x0EE
60 #define DA9150_GPIO_CFG_B		0x0EF
61 #define DA9150_GPIO_CFG_C		0x0F0
62 #define DA9150_GPADC_MAN		0x0F2
63 #define DA9150_GPADC_RES_A		0x0F4
64 #define DA9150_GPADC_RES_B		0x0F5
65 #define DA9150_PAGE_CON_2		0x100
66 #define DA9150_OTP_CONT_SHARED		0x101
67 #define DA9150_INTERFACE_SHARED		0x105
68 #define DA9150_CONFIG_A_SHARED		0x106
69 #define DA9150_CONFIG_D_SHARED		0x109
70 #define DA9150_ADETVB_CFG_C		0x150
71 #define DA9150_ADETD_STAT		0x151
72 #define DA9150_ADET_CMPSTAT		0x152
73 #define DA9150_ADET_CTRL_A		0x153
74 #define DA9150_ADETVB_CFG_B		0x154
75 #define DA9150_ADETVB_CFG_A		0x155
76 #define DA9150_ADETAC_CFG_A		0x156
77 #define DA9150_ADDETAC_CFG_B		0x157
78 #define DA9150_ADETAC_CFG_C		0x158
79 #define DA9150_ADETAC_CFG_D		0x159
80 #define DA9150_ADETVB_CFG_D		0x15A
81 #define DA9150_ADETID_CFG_A		0x15B
82 #define DA9150_ADET_RID_PT_CHG_H	0x15C
83 #define DA9150_ADET_RID_PT_CHG_L	0x15D
84 #define DA9150_PPR_TCTR_B		0x160
85 #define DA9150_PPR_BKCTRL_A		0x163
86 #define DA9150_PPR_BKCFG_A		0x164
87 #define DA9150_PPR_BKCFG_B		0x165
88 #define DA9150_PPR_CHGCTRL_A		0x166
89 #define DA9150_PPR_CHGCTRL_B		0x167
90 #define DA9150_PPR_CHGCTRL_C		0x168
91 #define DA9150_PPR_TCTR_A		0x169
92 #define DA9150_PPR_CHGCTRL_D		0x16A
93 #define DA9150_PPR_CHGCTRL_E		0x16B
94 #define DA9150_PPR_CHGCTRL_F		0x16C
95 #define DA9150_PPR_CHGCTRL_G		0x16D
96 #define DA9150_PPR_CHGCTRL_H		0x16E
97 #define DA9150_PPR_CHGCTRL_I		0x16F
98 #define DA9150_PPR_CHGCTRL_J		0x170
99 #define DA9150_PPR_CHGCTRL_K		0x171
100 #define DA9150_PPR_CHGCTRL_L		0x172
101 #define DA9150_PPR_CHGCTRL_M		0x173
102 #define DA9150_PPR_THYST_A		0x174
103 #define DA9150_PPR_THYST_B		0x175
104 #define DA9150_PPR_THYST_C		0x176
105 #define DA9150_PPR_THYST_D		0x177
106 #define DA9150_PPR_THYST_E		0x178
107 #define DA9150_PPR_THYST_F		0x179
108 #define DA9150_PPR_THYST_G		0x17A
109 #define DA9150_PAGE_CON_3		0x180
110 #define DA9150_PAGE_CON_4		0x200
111 #define DA9150_PAGE_CON_5		0x280
112 #define DA9150_PAGE_CON_6		0x300
113 #define DA9150_COREBTLD_STAT_A		0x302
114 #define DA9150_COREBTLD_CTRL_A		0x303
115 #define DA9150_CORE_CONFIG_A		0x304
116 #define DA9150_CORE_CONFIG_C		0x305
117 #define DA9150_CORE_CONFIG_B		0x306
118 #define DA9150_CORE_CFG_DATA_A		0x307
119 #define DA9150_CORE_CFG_DATA_B		0x308
120 #define DA9150_CORE_CMD_A		0x309
121 #define DA9150_CORE_DATA_A		0x30A
122 #define DA9150_CORE_DATA_B		0x30B
123 #define DA9150_CORE_DATA_C		0x30C
124 #define DA9150_CORE_DATA_D		0x30D
125 #define DA9150_CORE2WIRE_STAT_A		0x310
126 #define DA9150_CORE2WIRE_CTRL_A		0x311
127 #define DA9150_FW_CTRL_A		0x312
128 #define DA9150_FW_CTRL_C		0x313
129 #define DA9150_FW_CTRL_D		0x314
130 #define DA9150_FG_CTRL_A		0x315
131 #define DA9150_FG_CTRL_B		0x316
132 #define DA9150_FW_CTRL_E		0x317
133 #define DA9150_FW_CTRL_B		0x318
134 #define DA9150_GPADC_CMAN		0x320
135 #define DA9150_GPADC_CRES_A		0x322
136 #define DA9150_GPADC_CRES_B		0x323
137 #define DA9150_CC_CFG_A			0x328
138 #define DA9150_CC_CFG_B			0x329
139 #define DA9150_CC_ICHG_RES_A		0x32A
140 #define DA9150_CC_ICHG_RES_B		0x32B
141 #define DA9150_CC_IAVG_RES_A		0x32C
142 #define DA9150_CC_IAVG_RES_B		0x32D
143 #define DA9150_TAUX_CTRL_A		0x330
144 #define DA9150_TAUX_RELOAD_H		0x332
145 #define DA9150_TAUX_RELOAD_L		0x333
146 #define DA9150_TAUX_VALUE_H		0x334
147 #define DA9150_TAUX_VALUE_L		0x335
148 #define DA9150_AUX_DATA_0		0x338
149 #define DA9150_AUX_DATA_1		0x339
150 #define DA9150_AUX_DATA_2		0x33A
151 #define DA9150_AUX_DATA_3		0x33B
152 #define DA9150_BIF_CTRL			0x340
153 #define DA9150_TBAT_CTRL_A		0x342
154 #define DA9150_TBAT_CTRL_B		0x343
155 #define DA9150_TBAT_RES_A		0x344
156 #define DA9150_TBAT_RES_B		0x345
157 
158 /* DA9150_PAGE_CON = 0x000 */
159 #define DA9150_PAGE_SHIFT			0
160 #define DA9150_PAGE_MASK			(0x3f << 0)
161 #define DA9150_I2C_PAGE_SHIFT			1
162 #define DA9150_I2C_PAGE_MASK			(0x1f << 1)
163 #define DA9150_WRITE_MODE_SHIFT			6
164 #define DA9150_WRITE_MODE_MASK			BIT(6)
165 #define DA9150_REVERT_SHIFT			7
166 #define DA9150_REVERT_MASK			BIT(7)
167 
168 /* DA9150_STATUS_A = 0x068 */
169 #define DA9150_WKUP_STAT_SHIFT			2
170 #define DA9150_WKUP_STAT_MASK			(0x0f << 2)
171 #define DA9150_SLEEP_STAT_SHIFT			6
172 #define DA9150_SLEEP_STAT_MASK			(0x03 << 6)
173 
174 /* DA9150_STATUS_B = 0x069 */
175 #define DA9150_VFAULT_STAT_SHIFT		0
176 #define DA9150_VFAULT_STAT_MASK			BIT(0)
177 #define DA9150_TFAULT_STAT_SHIFT		1
178 #define DA9150_TFAULT_STAT_MASK			BIT(1)
179 
180 /* DA9150_STATUS_C = 0x06A */
181 #define DA9150_VDD33_STAT_SHIFT			0
182 #define DA9150_VDD33_STAT_MASK			BIT(0)
183 #define DA9150_VDD33_SLEEP_SHIFT		1
184 #define DA9150_VDD33_SLEEP_MASK			BIT(1)
185 #define DA9150_LFOSC_STAT_SHIFT			7
186 #define DA9150_LFOSC_STAT_MASK			BIT(7)
187 
188 /* DA9150_STATUS_D = 0x06B */
189 #define DA9150_GPIOA_STAT_SHIFT			0
190 #define DA9150_GPIOA_STAT_MASK			BIT(0)
191 #define DA9150_GPIOB_STAT_SHIFT			1
192 #define DA9150_GPIOB_STAT_MASK			BIT(1)
193 #define DA9150_GPIOC_STAT_SHIFT			2
194 #define DA9150_GPIOC_STAT_MASK			BIT(2)
195 #define DA9150_GPIOD_STAT_SHIFT			3
196 #define DA9150_GPIOD_STAT_MASK			BIT(3)
197 
198 /* DA9150_STATUS_E = 0x06C */
199 #define DA9150_DTYPE_SHIFT			0
200 #define DA9150_DTYPE_MASK			(0x1f << 0)
201 #define DA9150_DTYPE_DT_NIL			(0x00 << 0)
202 #define DA9150_DTYPE_DT_USB_OTG			BIT(0)
203 #define DA9150_DTYPE_DT_USB_STD			(0x02 << 0)
204 #define DA9150_DTYPE_DT_USB_CHG			(0x03 << 0)
205 #define DA9150_DTYPE_DT_ACA_CHG			(0x04 << 0)
206 #define DA9150_DTYPE_DT_ACA_OTG			(0x05 << 0)
207 #define DA9150_DTYPE_DT_ACA_DOC			(0x06 << 0)
208 #define DA9150_DTYPE_DT_DED_CHG			(0x07 << 0)
209 #define DA9150_DTYPE_DT_CR5_CHG			(0x08 << 0)
210 #define DA9150_DTYPE_DT_CR4_CHG			(0x0c << 0)
211 #define DA9150_DTYPE_DT_PT_CHG			(0x11 << 0)
212 #define DA9150_DTYPE_DT_NN_ACC			(0x16 << 0)
213 #define DA9150_DTYPE_DT_NN_CHG			(0x17 << 0)
214 
215 /* DA9150_STATUS_F = 0x06D */
216 #define DA9150_SESS_VLD_SHIFT			0
217 #define DA9150_SESS_VLD_MASK			BIT(0)
218 #define DA9150_ID_ERR_SHIFT			1
219 #define DA9150_ID_ERR_MASK			BIT(1)
220 #define DA9150_PT_CHG_SHIFT			2
221 #define DA9150_PT_CHG_MASK			BIT(2)
222 
223 /* DA9150_STATUS_G = 0x06E */
224 #define DA9150_RID_SHIFT			0
225 #define DA9150_RID_MASK				(0xff << 0)
226 
227 /* DA9150_STATUS_H = 0x06F */
228 #define DA9150_VBUS_STAT_SHIFT			0
229 #define DA9150_VBUS_STAT_MASK			(0x07 << 0)
230 #define DA9150_VBUS_STAT_OFF			(0x00 << 0)
231 #define DA9150_VBUS_STAT_WAIT			BIT(0)
232 #define DA9150_VBUS_STAT_CHG			(0x02 << 0)
233 #define DA9150_VBUS_TRED_SHIFT			3
234 #define DA9150_VBUS_TRED_MASK			BIT(3)
235 #define DA9150_VBUS_DROP_STAT_SHIFT		4
236 #define DA9150_VBUS_DROP_STAT_MASK		(0x0f << 4)
237 
238 /* DA9150_STATUS_I = 0x070 */
239 #define DA9150_VBUS_ISET_STAT_SHIFT		0
240 #define DA9150_VBUS_ISET_STAT_MASK		(0x1f << 0)
241 #define DA9150_VBUS_OT_SHIFT			7
242 #define DA9150_VBUS_OT_MASK			BIT(7)
243 
244 /* DA9150_STATUS_J = 0x071 */
245 #define DA9150_CHG_STAT_SHIFT			0
246 #define DA9150_CHG_STAT_MASK			(0x0f << 0)
247 #define DA9150_CHG_STAT_OFF			(0x00 << 0)
248 #define DA9150_CHG_STAT_SUSP			BIT(0)
249 #define DA9150_CHG_STAT_ACT			(0x02 << 0)
250 #define DA9150_CHG_STAT_PRE			(0x03 << 0)
251 #define DA9150_CHG_STAT_CC			(0x04 << 0)
252 #define DA9150_CHG_STAT_CV			(0x05 << 0)
253 #define DA9150_CHG_STAT_FULL			(0x06 << 0)
254 #define DA9150_CHG_STAT_TEMP			(0x07 << 0)
255 #define DA9150_CHG_STAT_TIME			(0x08 << 0)
256 #define DA9150_CHG_STAT_BAT			(0x09 << 0)
257 #define DA9150_CHG_TEMP_SHIFT			4
258 #define DA9150_CHG_TEMP_MASK			(0x07 << 4)
259 #define DA9150_CHG_TEMP_UNDER			(0x06 << 4)
260 #define DA9150_CHG_TEMP_OVER			(0x07 << 4)
261 #define DA9150_CHG_IEND_STAT_SHIFT		7
262 #define DA9150_CHG_IEND_STAT_MASK		BIT(7)
263 
264 /* DA9150_STATUS_K = 0x072 */
265 #define DA9150_CHG_IAV_H_SHIFT			0
266 #define DA9150_CHG_IAV_H_MASK			(0xff << 0)
267 
268 /* DA9150_STATUS_L = 0x073 */
269 #define DA9150_CHG_IAV_L_SHIFT			5
270 #define DA9150_CHG_IAV_L_MASK			(0x07 << 5)
271 
272 /* DA9150_STATUS_N = 0x074 */
273 #define DA9150_CHG_TIME_SHIFT			1
274 #define DA9150_CHG_TIME_MASK			BIT(1)
275 #define DA9150_CHG_TRED_SHIFT			2
276 #define DA9150_CHG_TRED_MASK			BIT(2)
277 #define DA9150_CHG_TJUNC_CLASS_SHIFT		3
278 #define DA9150_CHG_TJUNC_CLASS_MASK		(0x07 << 3)
279 #define DA9150_CHG_TJUNC_CLASS_6		(0x06 << 3)
280 #define DA9150_EBS_STAT_SHIFT			6
281 #define DA9150_EBS_STAT_MASK			BIT(6)
282 #define DA9150_CHG_BAT_REMOVED_SHIFT		7
283 #define DA9150_CHG_BAT_REMOVED_MASK		BIT(7)
284 
285 /* DA9150_FAULT_LOG_A = 0x076 */
286 #define DA9150_TEMP_FAULT_SHIFT			0
287 #define DA9150_TEMP_FAULT_MASK			BIT(0)
288 #define DA9150_VSYS_FAULT_SHIFT			1
289 #define DA9150_VSYS_FAULT_MASK			BIT(1)
290 #define DA9150_START_FAULT_SHIFT		2
291 #define DA9150_START_FAULT_MASK			BIT(2)
292 #define DA9150_EXT_FAULT_SHIFT			3
293 #define DA9150_EXT_FAULT_MASK			BIT(3)
294 #define DA9150_POR_FAULT_SHIFT			4
295 #define DA9150_POR_FAULT_MASK			BIT(4)
296 
297 /* DA9150_FAULT_LOG_B = 0x077 */
298 #define DA9150_VBUS_FAULT_SHIFT			0
299 #define DA9150_VBUS_FAULT_MASK			BIT(0)
300 #define DA9150_OTG_FAULT_SHIFT			1
301 #define DA9150_OTG_FAULT_MASK			BIT(1)
302 
303 /* DA9150_EVENT_E = 0x078 */
304 #define DA9150_E_VBUS_SHIFT			0
305 #define DA9150_E_VBUS_MASK			BIT(0)
306 #define DA9150_E_CHG_SHIFT			1
307 #define DA9150_E_CHG_MASK			BIT(1)
308 #define DA9150_E_TCLASS_SHIFT			2
309 #define DA9150_E_TCLASS_MASK			BIT(2)
310 #define DA9150_E_TJUNC_SHIFT			3
311 #define DA9150_E_TJUNC_MASK			BIT(3)
312 #define DA9150_E_VFAULT_SHIFT			4
313 #define DA9150_E_VFAULT_MASK			BIT(4)
314 #define DA9150_EVENTS_H_SHIFT			5
315 #define DA9150_EVENTS_H_MASK			BIT(5)
316 #define DA9150_EVENTS_G_SHIFT			6
317 #define DA9150_EVENTS_G_MASK			BIT(6)
318 #define DA9150_EVENTS_F_SHIFT			7
319 #define DA9150_EVENTS_F_MASK			BIT(7)
320 
321 /* DA9150_EVENT_F = 0x079 */
322 #define DA9150_E_CONF_SHIFT			0
323 #define DA9150_E_CONF_MASK			BIT(0)
324 #define DA9150_E_DAT_SHIFT			1
325 #define DA9150_E_DAT_MASK			BIT(1)
326 #define DA9150_E_DTYPE_SHIFT			3
327 #define DA9150_E_DTYPE_MASK			BIT(3)
328 #define DA9150_E_ID_SHIFT			4
329 #define DA9150_E_ID_MASK			BIT(4)
330 #define DA9150_E_ADP_SHIFT			5
331 #define DA9150_E_ADP_MASK			BIT(5)
332 #define DA9150_E_SESS_END_SHIFT			6
333 #define DA9150_E_SESS_END_MASK			BIT(6)
334 #define DA9150_E_SESS_VLD_SHIFT			7
335 #define DA9150_E_SESS_VLD_MASK			BIT(7)
336 
337 /* DA9150_EVENT_G = 0x07A */
338 #define DA9150_E_FG_SHIFT			0
339 #define DA9150_E_FG_MASK			BIT(0)
340 #define DA9150_E_GP_SHIFT			1
341 #define DA9150_E_GP_MASK			BIT(1)
342 #define DA9150_E_TBAT_SHIFT			2
343 #define DA9150_E_TBAT_MASK			BIT(2)
344 #define DA9150_E_GPIOA_SHIFT			3
345 #define DA9150_E_GPIOA_MASK			BIT(3)
346 #define DA9150_E_GPIOB_SHIFT			4
347 #define DA9150_E_GPIOB_MASK			BIT(4)
348 #define DA9150_E_GPIOC_SHIFT			5
349 #define DA9150_E_GPIOC_MASK			BIT(5)
350 #define DA9150_E_GPIOD_SHIFT			6
351 #define DA9150_E_GPIOD_MASK			BIT(6)
352 #define DA9150_E_GPADC_SHIFT			7
353 #define DA9150_E_GPADC_MASK			BIT(7)
354 
355 /* DA9150_EVENT_H = 0x07B */
356 #define DA9150_E_WKUP_SHIFT			0
357 #define DA9150_E_WKUP_MASK			BIT(0)
358 
359 /* DA9150_IRQ_MASK_E = 0x07C */
360 #define DA9150_M_VBUS_SHIFT			0
361 #define DA9150_M_VBUS_MASK			BIT(0)
362 #define DA9150_M_CHG_SHIFT			1
363 #define DA9150_M_CHG_MASK			BIT(1)
364 #define DA9150_M_TJUNC_SHIFT			3
365 #define DA9150_M_TJUNC_MASK			BIT(3)
366 #define DA9150_M_VFAULT_SHIFT			4
367 #define DA9150_M_VFAULT_MASK			BIT(4)
368 
369 /* DA9150_IRQ_MASK_F = 0x07D */
370 #define DA9150_M_CONF_SHIFT			0
371 #define DA9150_M_CONF_MASK			BIT(0)
372 #define DA9150_M_DAT_SHIFT			1
373 #define DA9150_M_DAT_MASK			BIT(1)
374 #define DA9150_M_DTYPE_SHIFT			3
375 #define DA9150_M_DTYPE_MASK			BIT(3)
376 #define DA9150_M_ID_SHIFT			4
377 #define DA9150_M_ID_MASK			BIT(4)
378 #define DA9150_M_ADP_SHIFT			5
379 #define DA9150_M_ADP_MASK			BIT(5)
380 #define DA9150_M_SESS_END_SHIFT			6
381 #define DA9150_M_SESS_END_MASK			BIT(6)
382 #define DA9150_M_SESS_VLD_SHIFT			7
383 #define DA9150_M_SESS_VLD_MASK			BIT(7)
384 
385 /* DA9150_IRQ_MASK_G = 0x07E */
386 #define DA9150_M_FG_SHIFT			0
387 #define DA9150_M_FG_MASK			BIT(0)
388 #define DA9150_M_GP_SHIFT			1
389 #define DA9150_M_GP_MASK			BIT(1)
390 #define DA9150_M_TBAT_SHIFT			2
391 #define DA9150_M_TBAT_MASK			BIT(2)
392 #define DA9150_M_GPIOA_SHIFT			3
393 #define DA9150_M_GPIOA_MASK			BIT(3)
394 #define DA9150_M_GPIOB_SHIFT			4
395 #define DA9150_M_GPIOB_MASK			BIT(4)
396 #define DA9150_M_GPIOC_SHIFT			5
397 #define DA9150_M_GPIOC_MASK			BIT(5)
398 #define DA9150_M_GPIOD_SHIFT			6
399 #define DA9150_M_GPIOD_MASK			BIT(6)
400 #define DA9150_M_GPADC_SHIFT			7
401 #define DA9150_M_GPADC_MASK			BIT(7)
402 
403 /* DA9150_IRQ_MASK_H = 0x07F */
404 #define DA9150_M_WKUP_SHIFT			0
405 #define DA9150_M_WKUP_MASK			BIT(0)
406 
407 /* DA9150_PAGE_CON_1 = 0x080 */
408 #define DA9150_PAGE_SHIFT			0
409 #define DA9150_PAGE_MASK			(0x3f << 0)
410 #define DA9150_WRITE_MODE_SHIFT			6
411 #define DA9150_WRITE_MODE_MASK			BIT(6)
412 #define DA9150_REVERT_SHIFT			7
413 #define DA9150_REVERT_MASK			BIT(7)
414 
415 /* DA9150_CONFIG_A = 0x0E0 */
416 #define DA9150_RESET_DUR_SHIFT			0
417 #define DA9150_RESET_DUR_MASK			(0x03 << 0)
418 #define DA9150_RESET_EXT_SHIFT			2
419 #define DA9150_RESET_EXT_MASK			(0x03 << 2)
420 #define DA9150_START_MAX_SHIFT			4
421 #define DA9150_START_MAX_MASK			(0x03 << 4)
422 #define DA9150_PS_WAIT_EN_SHIFT			6
423 #define DA9150_PS_WAIT_EN_MASK			BIT(6)
424 #define DA9150_PS_DISABLE_DIRECT_SHIFT		7
425 #define DA9150_PS_DISABLE_DIRECT_MASK		BIT(7)
426 
427 /* DA9150_CONFIG_B = 0x0E1 */
428 #define DA9150_VFAULT_ADJ_SHIFT			0
429 #define DA9150_VFAULT_ADJ_MASK			(0x0f << 0)
430 #define DA9150_VFAULT_HYST_SHIFT		4
431 #define DA9150_VFAULT_HYST_MASK			(0x07 << 4)
432 #define DA9150_VFAULT_EN_SHIFT			7
433 #define DA9150_VFAULT_EN_MASK			BIT(7)
434 
435 /* DA9150_CONFIG_C = 0x0E2 */
436 #define DA9150_VSYS_MIN_SHIFT			3
437 #define DA9150_VSYS_MIN_MASK			(0x1f << 3)
438 
439 /* DA9150_CONFIG_D = 0x0E3 */
440 #define DA9150_LFOSC_EXT_SHIFT			0
441 #define DA9150_LFOSC_EXT_MASK			BIT(0)
442 #define DA9150_VDD33_DWN_SHIFT			1
443 #define DA9150_VDD33_DWN_MASK			BIT(1)
444 #define DA9150_WKUP_PM_EN_SHIFT			2
445 #define DA9150_WKUP_PM_EN_MASK			BIT(2)
446 #define DA9150_WKUP_CE_SEL_SHIFT		3
447 #define DA9150_WKUP_CE_SEL_MASK			(0x03 << 3)
448 #define DA9150_WKUP_CLK32K_EN_SHIFT		5
449 #define DA9150_WKUP_CLK32K_EN_MASK		BIT(5)
450 #define DA9150_DISABLE_DEL_SHIFT		7
451 #define DA9150_DISABLE_DEL_MASK			BIT(7)
452 
453 /* DA9150_CONFIG_E = 0x0E4 */
454 #define DA9150_PM_SPKSUP_DIS_SHIFT		0
455 #define DA9150_PM_SPKSUP_DIS_MASK		BIT(0)
456 #define DA9150_PM_MERGE_SHIFT			1
457 #define DA9150_PM_MERGE_MASK			BIT(1)
458 #define DA9150_PM_SR_OFF_SHIFT			2
459 #define DA9150_PM_SR_OFF_MASK			BIT(2)
460 #define DA9150_PM_TIMEOUT_EN_SHIFT		3
461 #define DA9150_PM_TIMEOUT_EN_MASK		BIT(3)
462 #define DA9150_PM_DLY_SEL_SHIFT			4
463 #define DA9150_PM_DLY_SEL_MASK			(0x07 << 4)
464 #define DA9150_PM_OUT_DLY_SEL_SHIFT		7
465 #define DA9150_PM_OUT_DLY_SEL_MASK		BIT(7)
466 
467 /* DA9150_CONTROL_A = 0x0E5 */
468 #define DA9150_VDD33_SL_SHIFT			0
469 #define DA9150_VDD33_SL_MASK			BIT(0)
470 #define DA9150_VDD33_LPM_SHIFT			1
471 #define DA9150_VDD33_LPM_MASK			(0x03 << 1)
472 #define DA9150_VDD33_EN_SHIFT			3
473 #define DA9150_VDD33_EN_MASK			BIT(3)
474 #define DA9150_GPI_LPM_SHIFT			6
475 #define DA9150_GPI_LPM_MASK			BIT(6)
476 #define DA9150_PM_IF_LPM_SHIFT			7
477 #define DA9150_PM_IF_LPM_MASK			BIT(7)
478 
479 /* DA9150_CONTROL_B = 0x0E6 */
480 #define DA9150_LPM_SHIFT			0
481 #define DA9150_LPM_MASK				BIT(0)
482 #define DA9150_RESET_SHIFT			1
483 #define DA9150_RESET_MASK			BIT(1)
484 #define DA9150_RESET_USRCONF_EN_SHIFT		2
485 #define DA9150_RESET_USRCONF_EN_MASK		BIT(2)
486 
487 /* DA9150_CONTROL_C = 0x0E7 */
488 #define DA9150_DISABLE_SHIFT			0
489 #define DA9150_DISABLE_MASK			BIT(0)
490 
491 /* DA9150_GPIO_A_B = 0x0E8 */
492 #define DA9150_GPIOA_PIN_SHIFT			0
493 #define DA9150_GPIOA_PIN_MASK			(0x07 << 0)
494 #define DA9150_GPIOA_PIN_GPI			(0x00 << 0)
495 #define DA9150_GPIOA_PIN_GPO_OD			BIT(0)
496 #define DA9150_GPIOA_TYPE_SHIFT			3
497 #define DA9150_GPIOA_TYPE_MASK			BIT(3)
498 #define DA9150_GPIOB_PIN_SHIFT			4
499 #define DA9150_GPIOB_PIN_MASK			(0x07 << 4)
500 #define DA9150_GPIOB_PIN_GPI			(0x00 << 4)
501 #define DA9150_GPIOB_PIN_GPO_OD			BIT(4)
502 #define DA9150_GPIOB_TYPE_SHIFT			7
503 #define DA9150_GPIOB_TYPE_MASK			BIT(7)
504 
505 /* DA9150_GPIO_C_D = 0x0E9 */
506 #define DA9150_GPIOC_PIN_SHIFT			0
507 #define DA9150_GPIOC_PIN_MASK			(0x07 << 0)
508 #define DA9150_GPIOC_PIN_GPI			(0x00 << 0)
509 #define DA9150_GPIOC_PIN_GPO_OD			BIT(0)
510 #define DA9150_GPIOC_TYPE_SHIFT			3
511 #define DA9150_GPIOC_TYPE_MASK			BIT(3)
512 #define DA9150_GPIOD_PIN_SHIFT			4
513 #define DA9150_GPIOD_PIN_MASK			(0x07 << 4)
514 #define DA9150_GPIOD_PIN_GPI			(0x00 << 4)
515 #define DA9150_GPIOD_PIN_GPO_OD			BIT(4)
516 #define DA9150_GPIOD_TYPE_SHIFT			7
517 #define DA9150_GPIOD_TYPE_MASK			BIT(7)
518 
519 /* DA9150_GPIO_MODE_CONT = 0x0EA */
520 #define DA9150_GPIOA_MODE_SHIFT			0
521 #define DA9150_GPIOA_MODE_MASK			BIT(0)
522 #define DA9150_GPIOB_MODE_SHIFT			1
523 #define DA9150_GPIOB_MODE_MASK			BIT(1)
524 #define DA9150_GPIOC_MODE_SHIFT			2
525 #define DA9150_GPIOC_MODE_MASK			BIT(2)
526 #define DA9150_GPIOD_MODE_SHIFT			3
527 #define DA9150_GPIOD_MODE_MASK			BIT(3)
528 #define DA9150_GPIOA_CONT_SHIFT			4
529 #define DA9150_GPIOA_CONT_MASK			BIT(4)
530 #define DA9150_GPIOB_CONT_SHIFT			5
531 #define DA9150_GPIOB_CONT_MASK			BIT(5)
532 #define DA9150_GPIOC_CONT_SHIFT			6
533 #define DA9150_GPIOC_CONT_MASK			BIT(6)
534 #define DA9150_GPIOD_CONT_SHIFT			7
535 #define DA9150_GPIOD_CONT_MASK			BIT(7)
536 
537 /* DA9150_GPIO_CTRL_B = 0x0EB */
538 #define DA9150_WAKE_PIN_SHIFT			0
539 #define DA9150_WAKE_PIN_MASK			(0x03 << 0)
540 #define DA9150_WAKE_MODE_SHIFT			2
541 #define DA9150_WAKE_MODE_MASK			BIT(2)
542 #define DA9150_WAKE_CONT_SHIFT			3
543 #define DA9150_WAKE_CONT_MASK			BIT(3)
544 #define DA9150_WAKE_DLY_SHIFT			4
545 #define DA9150_WAKE_DLY_MASK			BIT(4)
546 
547 /* DA9150_GPIO_CTRL_A = 0x0EC */
548 #define DA9150_GPIOA_ANAEN_SHIFT		0
549 #define DA9150_GPIOA_ANAEN_MASK			BIT(0)
550 #define DA9150_GPIOB_ANAEN_SHIFT		1
551 #define DA9150_GPIOB_ANAEN_MASK			BIT(1)
552 #define DA9150_GPIOC_ANAEN_SHIFT		2
553 #define DA9150_GPIOC_ANAEN_MASK			BIT(2)
554 #define DA9150_GPIOD_ANAEN_SHIFT		3
555 #define DA9150_GPIOD_ANAEN_MASK			BIT(3)
556 #define DA9150_GPIO_ANAEN			0x01
557 #define DA9150_GPIO_ANAEN_MASK			0x0F
558 #define DA9150_CHGLED_PIN_SHIFT			5
559 #define DA9150_CHGLED_PIN_MASK			(0x07 << 5)
560 
561 /* DA9150_GPIO_CTRL_C = 0x0ED */
562 #define DA9150_CHGBL_DUR_SHIFT			0
563 #define DA9150_CHGBL_DUR_MASK			(0x03 << 0)
564 #define DA9150_CHGBL_DBL_SHIFT			2
565 #define DA9150_CHGBL_DBL_MASK			BIT(2)
566 #define DA9150_CHGBL_FRQ_SHIFT			3
567 #define DA9150_CHGBL_FRQ_MASK			(0x03 << 3)
568 #define DA9150_CHGBL_FLKR_SHIFT			5
569 #define DA9150_CHGBL_FLKR_MASK			BIT(5)
570 
571 /* DA9150_GPIO_CFG_A = 0x0EE */
572 #define DA9150_CE_LPM_DEB_SHIFT			0
573 #define DA9150_CE_LPM_DEB_MASK			(0x07 << 0)
574 
575 /* DA9150_GPIO_CFG_B = 0x0EF */
576 #define DA9150_GPIOA_PUPD_SHIFT			0
577 #define DA9150_GPIOA_PUPD_MASK			BIT(0)
578 #define DA9150_GPIOB_PUPD_SHIFT			1
579 #define DA9150_GPIOB_PUPD_MASK			BIT(1)
580 #define DA9150_GPIOC_PUPD_SHIFT			2
581 #define DA9150_GPIOC_PUPD_MASK			BIT(2)
582 #define DA9150_GPIOD_PUPD_SHIFT			3
583 #define DA9150_GPIOD_PUPD_MASK			BIT(3)
584 #define DA9150_GPIO_PUPD_MASK			(0xF << 0)
585 #define DA9150_GPI_DEB_SHIFT			4
586 #define DA9150_GPI_DEB_MASK			(0x07 << 4)
587 #define DA9150_LPM_EN_SHIFT			7
588 #define DA9150_LPM_EN_MASK			BIT(7)
589 
590 /* DA9150_GPIO_CFG_C = 0x0F0 */
591 #define DA9150_GPI_V_SHIFT			0
592 #define DA9150_GPI_V_MASK			BIT(0)
593 #define DA9150_VDDIO_INT_SHIFT			1
594 #define DA9150_VDDIO_INT_MASK			BIT(1)
595 #define DA9150_FAULT_PIN_SHIFT			3
596 #define DA9150_FAULT_PIN_MASK			(0x07 << 3)
597 #define DA9150_FAULT_TYPE_SHIFT			6
598 #define DA9150_FAULT_TYPE_MASK			BIT(6)
599 #define DA9150_NIRQ_PUPD_SHIFT			7
600 #define DA9150_NIRQ_PUPD_MASK			BIT(7)
601 
602 /* DA9150_GPADC_MAN = 0x0F2 */
603 #define DA9150_GPADC_EN_SHIFT			0
604 #define DA9150_GPADC_EN_MASK			BIT(0)
605 #define DA9150_GPADC_MUX_SHIFT			1
606 #define DA9150_GPADC_MUX_MASK			(0x1f << 1)
607 
608 /* DA9150_GPADC_RES_A = 0x0F4 */
609 #define DA9150_GPADC_RES_H_SHIFT		0
610 #define DA9150_GPADC_RES_H_MASK			(0xff << 0)
611 
612 /* DA9150_GPADC_RES_B = 0x0F5 */
613 #define DA9150_GPADC_RUN_SHIFT			0
614 #define DA9150_GPADC_RUN_MASK			BIT(0)
615 #define DA9150_GPADC_RES_L_SHIFT		6
616 #define DA9150_GPADC_RES_L_MASK			(0x03 << 6)
617 #define DA9150_GPADC_RES_L_BITS			2
618 
619 /* DA9150_PAGE_CON_2 = 0x100 */
620 #define DA9150_PAGE_SHIFT			0
621 #define DA9150_PAGE_MASK			(0x3f << 0)
622 #define DA9150_WRITE_MODE_SHIFT			6
623 #define DA9150_WRITE_MODE_MASK			BIT(6)
624 #define DA9150_REVERT_SHIFT			7
625 #define DA9150_REVERT_MASK			BIT(7)
626 
627 /* DA9150_OTP_CONT_SHARED = 0x101 */
628 #define DA9150_PC_DONE_SHIFT			3
629 #define DA9150_PC_DONE_MASK			BIT(3)
630 
631 /* DA9150_INTERFACE_SHARED = 0x105 */
632 #define DA9150_IF_BASE_ADDR_SHIFT		4
633 #define DA9150_IF_BASE_ADDR_MASK		(0x0f << 4)
634 
635 /* DA9150_CONFIG_A_SHARED = 0x106 */
636 #define DA9150_NIRQ_VDD_SHIFT			1
637 #define DA9150_NIRQ_VDD_MASK			BIT(1)
638 #define DA9150_NIRQ_PIN_SHIFT			2
639 #define DA9150_NIRQ_PIN_MASK			BIT(2)
640 #define DA9150_NIRQ_TYPE_SHIFT			3
641 #define DA9150_NIRQ_TYPE_MASK			BIT(3)
642 #define DA9150_PM_IF_V_SHIFT			4
643 #define DA9150_PM_IF_V_MASK			BIT(4)
644 #define DA9150_PM_IF_FMP_SHIFT			5
645 #define DA9150_PM_IF_FMP_MASK			BIT(5)
646 #define DA9150_PM_IF_HSM_SHIFT			6
647 #define DA9150_PM_IF_HSM_MASK			BIT(6)
648 
649 /* DA9150_CONFIG_D_SHARED = 0x109 */
650 #define DA9150_NIRQ_MODE_SHIFT			1
651 #define DA9150_NIRQ_MODE_MASK			BIT(1)
652 
653 /* DA9150_ADETVB_CFG_C = 0x150 */
654 #define DA9150_TADP_RISE_SHIFT			0
655 #define DA9150_TADP_RISE_MASK			(0xff << 0)
656 
657 /* DA9150_ADETD_STAT = 0x151 */
658 #define DA9150_DCD_STAT_SHIFT			0
659 #define DA9150_DCD_STAT_MASK			BIT(0)
660 #define DA9150_PCD_STAT_SHIFT			1
661 #define DA9150_PCD_STAT_MASK			(0x03 << 1)
662 #define DA9150_SCD_STAT_SHIFT			3
663 #define DA9150_SCD_STAT_MASK			(0x03 << 3)
664 #define DA9150_DP_STAT_SHIFT			5
665 #define DA9150_DP_STAT_MASK			BIT(5)
666 #define DA9150_DM_STAT_SHIFT			6
667 #define DA9150_DM_STAT_MASK			BIT(6)
668 
669 /* DA9150_ADET_CMPSTAT = 0x152 */
670 #define DA9150_DP_COMP_SHIFT			1
671 #define DA9150_DP_COMP_MASK			BIT(1)
672 #define DA9150_DM_COMP_SHIFT			2
673 #define DA9150_DM_COMP_MASK			BIT(2)
674 #define DA9150_ADP_SNS_COMP_SHIFT		3
675 #define DA9150_ADP_SNS_COMP_MASK		BIT(3)
676 #define DA9150_ADP_PRB_COMP_SHIFT		4
677 #define DA9150_ADP_PRB_COMP_MASK		BIT(4)
678 #define DA9150_ID_COMP_SHIFT			5
679 #define DA9150_ID_COMP_MASK			BIT(5)
680 
681 /* DA9150_ADET_CTRL_A = 0x153 */
682 #define DA9150_AID_DAT_SHIFT			0
683 #define DA9150_AID_DAT_MASK			BIT(0)
684 #define DA9150_AID_ID_SHIFT			1
685 #define DA9150_AID_ID_MASK			BIT(1)
686 #define DA9150_AID_TRIG_SHIFT			2
687 #define DA9150_AID_TRIG_MASK			BIT(2)
688 
689 /* DA9150_ADETVB_CFG_B = 0x154 */
690 #define DA9150_VB_MODE_SHIFT			0
691 #define DA9150_VB_MODE_MASK			(0x03 << 0)
692 #define DA9150_VB_MODE_VB_SESS			BIT(0)
693 
694 #define DA9150_TADP_PRB_SHIFT			2
695 #define DA9150_TADP_PRB_MASK			BIT(2)
696 #define DA9150_DAT_RPD_EXT_SHIFT		5
697 #define DA9150_DAT_RPD_EXT_MASK			BIT(5)
698 #define DA9150_CONF_RPD_SHIFT			6
699 #define DA9150_CONF_RPD_MASK			BIT(6)
700 #define DA9150_CONF_SRP_SHIFT			7
701 #define DA9150_CONF_SRP_MASK			BIT(7)
702 
703 /* DA9150_ADETVB_CFG_A = 0x155 */
704 #define DA9150_AID_MODE_SHIFT			0
705 #define DA9150_AID_MODE_MASK			(0x03 << 0)
706 #define DA9150_AID_EXT_POL_SHIFT		2
707 #define DA9150_AID_EXT_POL_MASK			BIT(2)
708 
709 /* DA9150_ADETAC_CFG_A = 0x156 */
710 #define DA9150_ISET_CDP_SHIFT			0
711 #define DA9150_ISET_CDP_MASK			(0x1f << 0)
712 #define DA9150_CONF_DBP_SHIFT			5
713 #define DA9150_CONF_DBP_MASK			BIT(5)
714 
715 /* DA9150_ADDETAC_CFG_B = 0x157 */
716 #define DA9150_ISET_DCHG_SHIFT			0
717 #define DA9150_ISET_DCHG_MASK			(0x1f << 0)
718 #define DA9150_CONF_GPIOA_SHIFT			5
719 #define DA9150_CONF_GPIOA_MASK			BIT(5)
720 #define DA9150_CONF_GPIOB_SHIFT			6
721 #define DA9150_CONF_GPIOB_MASK			BIT(6)
722 #define DA9150_AID_VB_SHIFT			7
723 #define DA9150_AID_VB_MASK			BIT(7)
724 
725 /* DA9150_ADETAC_CFG_C = 0x158 */
726 #define DA9150_ISET_DEF_SHIFT			0
727 #define DA9150_ISET_DEF_MASK			(0x1f << 0)
728 #define DA9150_CONF_MODE_SHIFT			5
729 #define DA9150_CONF_MODE_MASK			(0x03 << 5)
730 #define DA9150_AID_CR_DIS_SHIFT			7
731 #define DA9150_AID_CR_DIS_MASK			BIT(7)
732 
733 /* DA9150_ADETAC_CFG_D = 0x159 */
734 #define DA9150_ISET_UNIT_SHIFT			0
735 #define DA9150_ISET_UNIT_MASK			(0x1f << 0)
736 #define DA9150_AID_UNCLAMP_SHIFT		5
737 #define DA9150_AID_UNCLAMP_MASK			BIT(5)
738 
739 /* DA9150_ADETVB_CFG_D = 0x15A */
740 #define DA9150_ID_MODE_SHIFT			0
741 #define DA9150_ID_MODE_MASK			(0x03 << 0)
742 #define DA9150_DAT_MODE_SHIFT			2
743 #define DA9150_DAT_MODE_MASK			(0x0f << 2)
744 #define DA9150_DAT_SWP_SHIFT			6
745 #define DA9150_DAT_SWP_MASK			BIT(6)
746 #define DA9150_DAT_CLAMP_EXT_SHIFT		7
747 #define DA9150_DAT_CLAMP_EXT_MASK		BIT(7)
748 
749 /* DA9150_ADETID_CFG_A = 0x15B */
750 #define DA9150_TID_POLL_SHIFT			0
751 #define DA9150_TID_POLL_MASK			(0x07 << 0)
752 #define DA9150_RID_CONV_SHIFT			3
753 #define DA9150_RID_CONV_MASK			BIT(3)
754 
755 /* DA9150_ADET_RID_PT_CHG_H = 0x15C */
756 #define DA9150_RID_PT_CHG_H_SHIFT		0
757 #define DA9150_RID_PT_CHG_H_MASK		(0xff << 0)
758 
759 /* DA9150_ADET_RID_PT_CHG_L = 0x15D */
760 #define DA9150_RID_PT_CHG_L_SHIFT		6
761 #define DA9150_RID_PT_CHG_L_MASK		(0x03 << 6)
762 
763 /* DA9150_PPR_TCTR_B = 0x160 */
764 #define DA9150_CHG_TCTR_VAL_SHIFT		0
765 #define DA9150_CHG_TCTR_VAL_MASK		(0xff << 0)
766 
767 /* DA9150_PPR_BKCTRL_A = 0x163 */
768 #define DA9150_VBUS_MODE_SHIFT			0
769 #define DA9150_VBUS_MODE_MASK			(0x03 << 0)
770 #define DA9150_VBUS_MODE_CHG			BIT(0)
771 #define DA9150_VBUS_MODE_OTG			(0x02 << 0)
772 #define DA9150_VBUS_LPM_SHIFT			2
773 #define DA9150_VBUS_LPM_MASK			(0x03 << 2)
774 #define DA9150_VBUS_SUSP_SHIFT			4
775 #define DA9150_VBUS_SUSP_MASK			BIT(4)
776 #define DA9150_VBUS_PWM_SHIFT			5
777 #define DA9150_VBUS_PWM_MASK			BIT(5)
778 #define DA9150_VBUS_ISO_SHIFT			6
779 #define DA9150_VBUS_ISO_MASK			BIT(6)
780 #define DA9150_VBUS_LDO_SHIFT			7
781 #define DA9150_VBUS_LDO_MASK			BIT(7)
782 
783 /* DA9150_PPR_BKCFG_A = 0x164 */
784 #define DA9150_VBUS_ISET_SHIFT			0
785 #define DA9150_VBUS_ISET_MASK			(0x1f << 0)
786 #define DA9150_VBUS_IMAX_SHIFT			5
787 #define DA9150_VBUS_IMAX_MASK			BIT(5)
788 #define DA9150_VBUS_IOTG_SHIFT			6
789 #define DA9150_VBUS_IOTG_MASK			(0x03 << 6)
790 
791 /* DA9150_PPR_BKCFG_B = 0x165 */
792 #define DA9150_VBUS_DROP_SHIFT			0
793 #define DA9150_VBUS_DROP_MASK			(0x0f << 0)
794 #define DA9150_VBUS_FAULT_DIS_SHIFT		6
795 #define DA9150_VBUS_FAULT_DIS_MASK		BIT(6)
796 #define DA9150_OTG_FAULT_DIS_SHIFT		7
797 #define DA9150_OTG_FAULT_DIS_MASK		BIT(7)
798 
799 /* DA9150_PPR_CHGCTRL_A = 0x166 */
800 #define DA9150_CHG_EN_SHIFT			0
801 #define DA9150_CHG_EN_MASK			BIT(0)
802 
803 /* DA9150_PPR_CHGCTRL_B = 0x167 */
804 #define DA9150_CHG_VBAT_SHIFT			0
805 #define DA9150_CHG_VBAT_MASK			(0x1f << 0)
806 #define DA9150_CHG_VDROP_SHIFT			6
807 #define DA9150_CHG_VDROP_MASK			(0x03 << 6)
808 
809 /* DA9150_PPR_CHGCTRL_C = 0x168 */
810 #define DA9150_CHG_VFAULT_SHIFT			0
811 #define DA9150_CHG_VFAULT_MASK			(0x0f << 0)
812 #define DA9150_CHG_IPRE_SHIFT			4
813 #define DA9150_CHG_IPRE_MASK			(0x03 << 4)
814 
815 /* DA9150_PPR_TCTR_A = 0x169 */
816 #define DA9150_CHG_TCTR_SHIFT			0
817 #define DA9150_CHG_TCTR_MASK			(0x07 << 0)
818 #define DA9150_CHG_TCTR_MODE_SHIFT		4
819 #define DA9150_CHG_TCTR_MODE_MASK		BIT(4)
820 
821 /* DA9150_PPR_CHGCTRL_D = 0x16A */
822 #define DA9150_CHG_IBAT_SHIFT			0
823 #define DA9150_CHG_IBAT_MASK			(0xff << 0)
824 
825 /* DA9150_PPR_CHGCTRL_E = 0x16B */
826 #define DA9150_CHG_IEND_SHIFT			0
827 #define DA9150_CHG_IEND_MASK			(0xff << 0)
828 
829 /* DA9150_PPR_CHGCTRL_F = 0x16C */
830 #define DA9150_CHG_VCOLD_SHIFT			0
831 #define DA9150_CHG_VCOLD_MASK			(0x1f << 0)
832 #define DA9150_TBAT_TQA_EN_SHIFT		6
833 #define DA9150_TBAT_TQA_EN_MASK			BIT(6)
834 #define DA9150_TBAT_TDP_EN_SHIFT		7
835 #define DA9150_TBAT_TDP_EN_MASK			BIT(7)
836 
837 /* DA9150_PPR_CHGCTRL_G = 0x16D */
838 #define DA9150_CHG_VWARM_SHIFT			0
839 #define DA9150_CHG_VWARM_MASK			(0x1f << 0)
840 
841 /* DA9150_PPR_CHGCTRL_H = 0x16E */
842 #define DA9150_CHG_VHOT_SHIFT			0
843 #define DA9150_CHG_VHOT_MASK			(0x1f << 0)
844 
845 /* DA9150_PPR_CHGCTRL_I = 0x16F */
846 #define DA9150_CHG_ICOLD_SHIFT			0
847 #define DA9150_CHG_ICOLD_MASK			(0xff << 0)
848 
849 /* DA9150_PPR_CHGCTRL_J = 0x170 */
850 #define DA9150_CHG_IWARM_SHIFT			0
851 #define DA9150_CHG_IWARM_MASK			(0xff << 0)
852 
853 /* DA9150_PPR_CHGCTRL_K = 0x171 */
854 #define DA9150_CHG_IHOT_SHIFT			0
855 #define DA9150_CHG_IHOT_MASK			(0xff << 0)
856 
857 /* DA9150_PPR_CHGCTRL_L = 0x172 */
858 #define DA9150_CHG_IBAT_TRED_SHIFT		0
859 #define DA9150_CHG_IBAT_TRED_MASK		(0xff << 0)
860 
861 /* DA9150_PPR_CHGCTRL_M = 0x173 */
862 #define DA9150_CHG_VFLOAT_SHIFT			0
863 #define DA9150_CHG_VFLOAT_MASK			(0x0f << 0)
864 #define DA9150_CHG_LPM_SHIFT			5
865 #define DA9150_CHG_LPM_MASK			BIT(5)
866 #define DA9150_CHG_NBLO_SHIFT			6
867 #define DA9150_CHG_NBLO_MASK			BIT(6)
868 #define DA9150_EBS_EN_SHIFT			7
869 #define DA9150_EBS_EN_MASK			BIT(7)
870 
871 /* DA9150_PPR_THYST_A = 0x174 */
872 #define DA9150_TBAT_T1_SHIFT			0
873 #define DA9150_TBAT_T1_MASK			(0xff << 0)
874 
875 /* DA9150_PPR_THYST_B = 0x175 */
876 #define DA9150_TBAT_T2_SHIFT			0
877 #define DA9150_TBAT_T2_MASK			(0xff << 0)
878 
879 /* DA9150_PPR_THYST_C = 0x176 */
880 #define DA9150_TBAT_T3_SHIFT			0
881 #define DA9150_TBAT_T3_MASK			(0xff << 0)
882 
883 /* DA9150_PPR_THYST_D = 0x177 */
884 #define DA9150_TBAT_T4_SHIFT			0
885 #define DA9150_TBAT_T4_MASK			(0xff << 0)
886 
887 /* DA9150_PPR_THYST_E = 0x178 */
888 #define DA9150_TBAT_T5_SHIFT			0
889 #define DA9150_TBAT_T5_MASK			(0xff << 0)
890 
891 /* DA9150_PPR_THYST_F = 0x179 */
892 #define DA9150_TBAT_H1_SHIFT			0
893 #define DA9150_TBAT_H1_MASK			(0xff << 0)
894 
895 /* DA9150_PPR_THYST_G = 0x17A */
896 #define DA9150_TBAT_H5_SHIFT			0
897 #define DA9150_TBAT_H5_MASK			(0xff << 0)
898 
899 /* DA9150_PAGE_CON_3 = 0x180 */
900 #define DA9150_PAGE_SHIFT			0
901 #define DA9150_PAGE_MASK			(0x3f << 0)
902 #define DA9150_WRITE_MODE_SHIFT			6
903 #define DA9150_WRITE_MODE_MASK			BIT(6)
904 #define DA9150_REVERT_SHIFT			7
905 #define DA9150_REVERT_MASK			BIT(7)
906 
907 /* DA9150_PAGE_CON_4 = 0x200 */
908 #define DA9150_PAGE_SHIFT			0
909 #define DA9150_PAGE_MASK			(0x3f << 0)
910 #define DA9150_WRITE_MODE_SHIFT			6
911 #define DA9150_WRITE_MODE_MASK			BIT(6)
912 #define DA9150_REVERT_SHIFT			7
913 #define DA9150_REVERT_MASK			BIT(7)
914 
915 /* DA9150_PAGE_CON_5 = 0x280 */
916 #define DA9150_PAGE_SHIFT			0
917 #define DA9150_PAGE_MASK			(0x3f << 0)
918 #define DA9150_WRITE_MODE_SHIFT			6
919 #define DA9150_WRITE_MODE_MASK			BIT(6)
920 #define DA9150_REVERT_SHIFT			7
921 #define DA9150_REVERT_MASK			BIT(7)
922 
923 /* DA9150_PAGE_CON_6 = 0x300 */
924 #define DA9150_PAGE_SHIFT			0
925 #define DA9150_PAGE_MASK			(0x3f << 0)
926 #define DA9150_WRITE_MODE_SHIFT			6
927 #define DA9150_WRITE_MODE_MASK			BIT(6)
928 #define DA9150_REVERT_SHIFT			7
929 #define DA9150_REVERT_MASK			BIT(7)
930 
931 /* DA9150_COREBTLD_STAT_A = 0x302 */
932 #define DA9150_BOOTLD_STAT_SHIFT		0
933 #define DA9150_BOOTLD_STAT_MASK			(0x03 << 0)
934 #define DA9150_CORE_LOCKUP_SHIFT		2
935 #define DA9150_CORE_LOCKUP_MASK			BIT(2)
936 
937 /* DA9150_COREBTLD_CTRL_A = 0x303 */
938 #define DA9150_CORE_RESET_SHIFT			0
939 #define DA9150_CORE_RESET_MASK			BIT(0)
940 #define DA9150_CORE_STOP_SHIFT			1
941 #define DA9150_CORE_STOP_MASK			BIT(1)
942 
943 /* DA9150_CORE_CONFIG_A = 0x304 */
944 #define DA9150_CORE_MEMMUX_SHIFT		0
945 #define DA9150_CORE_MEMMUX_MASK			(0x03 << 0)
946 #define DA9150_WDT_AUTO_START_SHIFT		2
947 #define DA9150_WDT_AUTO_START_MASK		BIT(2)
948 #define DA9150_WDT_AUTO_LOCK_SHIFT		3
949 #define DA9150_WDT_AUTO_LOCK_MASK		BIT(3)
950 #define DA9150_WDT_HLT_NO_CLK_SHIFT		4
951 #define DA9150_WDT_HLT_NO_CLK_MASK		BIT(4)
952 
953 /* DA9150_CORE_CONFIG_C = 0x305 */
954 #define DA9150_CORE_SW_SIZE_SHIFT		0
955 #define DA9150_CORE_SW_SIZE_MASK		(0xff << 0)
956 
957 /* DA9150_CORE_CONFIG_B = 0x306 */
958 #define DA9150_BOOTLD_EN_SHIFT			0
959 #define DA9150_BOOTLD_EN_MASK			BIT(0)
960 #define DA9150_CORE_EN_SHIFT			2
961 #define DA9150_CORE_EN_MASK			BIT(2)
962 #define DA9150_CORE_SW_SRC_SHIFT		3
963 #define DA9150_CORE_SW_SRC_MASK			(0x07 << 3)
964 #define DA9150_DEEP_SLEEP_EN_SHIFT		7
965 #define DA9150_DEEP_SLEEP_EN_MASK		BIT(7)
966 
967 /* DA9150_CORE_CFG_DATA_A = 0x307 */
968 #define DA9150_CORE_CFG_DT_A_SHIFT		0
969 #define DA9150_CORE_CFG_DT_A_MASK		(0xff << 0)
970 
971 /* DA9150_CORE_CFG_DATA_B = 0x308 */
972 #define DA9150_CORE_CFG_DT_B_SHIFT		0
973 #define DA9150_CORE_CFG_DT_B_MASK		(0xff << 0)
974 
975 /* DA9150_CORE_CMD_A = 0x309 */
976 #define DA9150_CORE_CMD_SHIFT			0
977 #define DA9150_CORE_CMD_MASK			(0xff << 0)
978 
979 /* DA9150_CORE_DATA_A = 0x30A */
980 #define DA9150_CORE_DATA_0_SHIFT		0
981 #define DA9150_CORE_DATA_0_MASK			(0xff << 0)
982 
983 /* DA9150_CORE_DATA_B = 0x30B */
984 #define DA9150_CORE_DATA_1_SHIFT		0
985 #define DA9150_CORE_DATA_1_MASK			(0xff << 0)
986 
987 /* DA9150_CORE_DATA_C = 0x30C */
988 #define DA9150_CORE_DATA_2_SHIFT		0
989 #define DA9150_CORE_DATA_2_MASK			(0xff << 0)
990 
991 /* DA9150_CORE_DATA_D = 0x30D */
992 #define DA9150_CORE_DATA_3_SHIFT		0
993 #define DA9150_CORE_DATA_3_MASK			(0xff << 0)
994 
995 /* DA9150_CORE2WIRE_STAT_A = 0x310 */
996 #define DA9150_FW_FWDL_ERR_SHIFT		7
997 #define DA9150_FW_FWDL_ERR_MASK			BIT(7)
998 
999 /* DA9150_CORE2WIRE_CTRL_A = 0x311 */
1000 #define DA9150_FW_FWDL_EN_SHIFT			0
1001 #define DA9150_FW_FWDL_EN_MASK			BIT(0)
1002 #define DA9150_FG_QIF_EN_SHIFT			1
1003 #define DA9150_FG_QIF_EN_MASK			BIT(1)
1004 #define DA9150_CORE_BASE_ADDR_SHIFT		4
1005 #define DA9150_CORE_BASE_ADDR_MASK		(0x0f << 4)
1006 
1007 /* DA9150_FW_CTRL_A = 0x312 */
1008 #define DA9150_FW_SEAL_SHIFT			0
1009 #define DA9150_FW_SEAL_MASK			(0xff << 0)
1010 
1011 /* DA9150_FW_CTRL_C = 0x313 */
1012 #define DA9150_FW_FWDL_CRC_SHIFT		0
1013 #define DA9150_FW_FWDL_CRC_MASK			(0xff << 0)
1014 
1015 /* DA9150_FW_CTRL_D = 0x314 */
1016 #define DA9150_FW_FWDL_BASE_SHIFT		0
1017 #define DA9150_FW_FWDL_BASE_MASK		(0x0f << 0)
1018 
1019 /* DA9150_FG_CTRL_A = 0x315 */
1020 #define DA9150_FG_QIF_CODE_SHIFT		0
1021 #define DA9150_FG_QIF_CODE_MASK			(0xff << 0)
1022 
1023 /* DA9150_FG_CTRL_B = 0x316 */
1024 #define DA9150_FG_QIF_VALUE_SHIFT		0
1025 #define DA9150_FG_QIF_VALUE_MASK		(0xff << 0)
1026 
1027 /* DA9150_FW_CTRL_E = 0x317 */
1028 #define DA9150_FW_FWDL_SEG_SHIFT		0
1029 #define DA9150_FW_FWDL_SEG_MASK			(0xff << 0)
1030 
1031 /* DA9150_FW_CTRL_B = 0x318 */
1032 #define DA9150_FW_FWDL_VALUE_SHIFT		0
1033 #define DA9150_FW_FWDL_VALUE_MASK		(0xff << 0)
1034 
1035 /* DA9150_GPADC_CMAN = 0x320 */
1036 #define DA9150_GPADC_CEN_SHIFT			0
1037 #define DA9150_GPADC_CEN_MASK			BIT(0)
1038 #define DA9150_GPADC_CMUX_SHIFT			1
1039 #define DA9150_GPADC_CMUX_MASK			(0x1f << 1)
1040 
1041 /* DA9150_GPADC_CRES_A = 0x322 */
1042 #define DA9150_GPADC_CRES_H_SHIFT		0
1043 #define DA9150_GPADC_CRES_H_MASK		(0xff << 0)
1044 
1045 /* DA9150_GPADC_CRES_B = 0x323 */
1046 #define DA9150_GPADC_CRUN_SHIFT			0
1047 #define DA9150_GPADC_CRUN_MASK			BIT(0)
1048 #define DA9150_GPADC_CRES_L_SHIFT		6
1049 #define DA9150_GPADC_CRES_L_MASK		(0x03 << 6)
1050 
1051 /* DA9150_CC_CFG_A = 0x328 */
1052 #define DA9150_CC_EN_SHIFT			0
1053 #define DA9150_CC_EN_MASK			BIT(0)
1054 #define DA9150_CC_TIMEBASE_SHIFT		1
1055 #define DA9150_CC_TIMEBASE_MASK			(0x03 << 1)
1056 #define DA9150_CC_CFG_SHIFT			5
1057 #define DA9150_CC_CFG_MASK			(0x03 << 5)
1058 #define DA9150_CC_ENDLESS_MODE_SHIFT		7
1059 #define DA9150_CC_ENDLESS_MODE_MASK		BIT(7)
1060 
1061 /* DA9150_CC_CFG_B = 0x329 */
1062 #define DA9150_CC_OPT_SHIFT			0
1063 #define DA9150_CC_OPT_MASK			(0x03 << 0)
1064 #define DA9150_CC_PREAMP_SHIFT			2
1065 #define DA9150_CC_PREAMP_MASK			(0x03 << 2)
1066 
1067 /* DA9150_CC_ICHG_RES_A = 0x32A */
1068 #define DA9150_CC_ICHG_RES_H_SHIFT		0
1069 #define DA9150_CC_ICHG_RES_H_MASK		(0xff << 0)
1070 
1071 /* DA9150_CC_ICHG_RES_B = 0x32B */
1072 #define DA9150_CC_ICHG_RES_L_SHIFT		3
1073 #define DA9150_CC_ICHG_RES_L_MASK		(0x1f << 3)
1074 
1075 /* DA9150_CC_IAVG_RES_A = 0x32C */
1076 #define DA9150_CC_IAVG_RES_H_SHIFT		0
1077 #define DA9150_CC_IAVG_RES_H_MASK		(0xff << 0)
1078 
1079 /* DA9150_CC_IAVG_RES_B = 0x32D */
1080 #define DA9150_CC_IAVG_RES_L_SHIFT		0
1081 #define DA9150_CC_IAVG_RES_L_MASK		(0xff << 0)
1082 
1083 /* DA9150_TAUX_CTRL_A = 0x330 */
1084 #define DA9150_TAUX_EN_SHIFT			0
1085 #define DA9150_TAUX_EN_MASK			BIT(0)
1086 #define DA9150_TAUX_MOD_SHIFT			1
1087 #define DA9150_TAUX_MOD_MASK			BIT(1)
1088 #define DA9150_TAUX_UPDATE_SHIFT		2
1089 #define DA9150_TAUX_UPDATE_MASK			BIT(2)
1090 
1091 /* DA9150_TAUX_RELOAD_H = 0x332 */
1092 #define DA9150_TAUX_RLD_H_SHIFT			0
1093 #define DA9150_TAUX_RLD_H_MASK			(0xff << 0)
1094 
1095 /* DA9150_TAUX_RELOAD_L = 0x333 */
1096 #define DA9150_TAUX_RLD_L_SHIFT			3
1097 #define DA9150_TAUX_RLD_L_MASK			(0x1f << 3)
1098 
1099 /* DA9150_TAUX_VALUE_H = 0x334 */
1100 #define DA9150_TAUX_VAL_H_SHIFT			0
1101 #define DA9150_TAUX_VAL_H_MASK			(0xff << 0)
1102 
1103 /* DA9150_TAUX_VALUE_L = 0x335 */
1104 #define DA9150_TAUX_VAL_L_SHIFT			3
1105 #define DA9150_TAUX_VAL_L_MASK			(0x1f << 3)
1106 
1107 /* DA9150_AUX_DATA_0 = 0x338 */
1108 #define DA9150_AUX_DAT_0_SHIFT			0
1109 #define DA9150_AUX_DAT_0_MASK			(0xff << 0)
1110 
1111 /* DA9150_AUX_DATA_1 = 0x339 */
1112 #define DA9150_AUX_DAT_1_SHIFT			0
1113 #define DA9150_AUX_DAT_1_MASK			(0xff << 0)
1114 
1115 /* DA9150_AUX_DATA_2 = 0x33A */
1116 #define DA9150_AUX_DAT_2_SHIFT			0
1117 #define DA9150_AUX_DAT_2_MASK			(0xff << 0)
1118 
1119 /* DA9150_AUX_DATA_3 = 0x33B */
1120 #define DA9150_AUX_DAT_3_SHIFT			0
1121 #define DA9150_AUX_DAT_3_MASK			(0xff << 0)
1122 
1123 /* DA9150_BIF_CTRL = 0x340 */
1124 #define DA9150_BIF_ISRC_EN_SHIFT		0
1125 #define DA9150_BIF_ISRC_EN_MASK			BIT(0)
1126 
1127 /* DA9150_TBAT_CTRL_A = 0x342 */
1128 #define DA9150_TBAT_EN_SHIFT			0
1129 #define DA9150_TBAT_EN_MASK			BIT(0)
1130 #define DA9150_TBAT_SW1_SHIFT			1
1131 #define DA9150_TBAT_SW1_MASK			BIT(1)
1132 #define DA9150_TBAT_SW2_SHIFT			2
1133 #define DA9150_TBAT_SW2_MASK			BIT(2)
1134 
1135 /* DA9150_TBAT_CTRL_B = 0x343 */
1136 #define DA9150_TBAT_SW_FRC_SHIFT		0
1137 #define DA9150_TBAT_SW_FRC_MASK			BIT(0)
1138 #define DA9150_TBAT_STAT_SW1_SHIFT		1
1139 #define DA9150_TBAT_STAT_SW1_MASK		BIT(1)
1140 #define DA9150_TBAT_STAT_SW2_SHIFT		2
1141 #define DA9150_TBAT_STAT_SW2_MASK		BIT(2)
1142 #define DA9150_TBAT_HIGH_CURR_SHIFT		3
1143 #define DA9150_TBAT_HIGH_CURR_MASK		BIT(3)
1144 
1145 /* DA9150_TBAT_RES_A = 0x344 */
1146 #define DA9150_TBAT_RES_H_SHIFT			0
1147 #define DA9150_TBAT_RES_H_MASK			(0xff << 0)
1148 
1149 /* DA9150_TBAT_RES_B = 0x345 */
1150 #define DA9150_TBAT_RES_DIS_SHIFT		0
1151 #define DA9150_TBAT_RES_DIS_MASK		BIT(0)
1152 #define DA9150_TBAT_RES_L_SHIFT			6
1153 #define DA9150_TBAT_RES_L_MASK			(0x03 << 6)
1154 
1155 #endif /* __DA9150_REGISTERS_H */
1156