1 /* 2 * R8A7790 processor support 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * Copyright (C) 2013 Magnus Damm 6 * Copyright (C) 2012 Renesas Solutions Corp. 7 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; version 2 of the 12 * License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 */ 23 24 #include <linux/kernel.h> 25 26 #include "core.h" 27 #include "sh_pfc.h" 28 29 #define PORT_GP_30(bank, fn, sfx) \ 30 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ 31 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ 32 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ 33 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ 34 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ 35 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ 36 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ 37 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ 38 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ 39 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ 40 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ 41 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ 42 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ 43 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ 44 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx) 45 46 #define CPU_ALL_PORT(fn, sfx) \ 47 PORT_GP_32(0, fn, sfx), \ 48 PORT_GP_30(1, fn, sfx), \ 49 PORT_GP_30(2, fn, sfx), \ 50 PORT_GP_32(3, fn, sfx), \ 51 PORT_GP_32(4, fn, sfx), \ 52 PORT_GP_32(5, fn, sfx) 53 54 enum { 55 PINMUX_RESERVED = 0, 56 57 PINMUX_DATA_BEGIN, 58 GP_ALL(DATA), 59 PINMUX_DATA_END, 60 61 PINMUX_FUNCTION_BEGIN, 62 GP_ALL(FN), 63 64 /* GPSR0 */ 65 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, 66 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, 67 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, 68 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, 69 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, 70 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, 71 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, 72 FN_IP3_14_12, FN_IP3_17_15, 73 74 /* GPSR1 */ 75 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, 76 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, 77 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, 78 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, 79 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, 80 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, 81 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, 82 83 /* GPSR2 */ 84 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, 85 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, 86 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, 87 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, 88 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, 89 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, 90 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, 91 92 /* GPSR3 */ 93 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, 94 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, 95 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, 96 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, 97 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, 98 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, 99 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, 100 101 /* GPSR4 */ 102 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, 103 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, 104 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, 105 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, 106 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, 107 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, 108 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, 109 FN_IP14_15_12, FN_IP14_18_16, 110 111 /* GPSR5 */ 112 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, 113 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, 114 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, 115 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, 116 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, 117 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, 118 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, 119 120 /* IPSR0 */ 121 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, 122 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, 123 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, 124 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B, 125 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4, 126 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, 127 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, 128 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, 129 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, 130 FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, 131 FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, 132 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1, 133 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 134 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, 135 136 /* IPSR1 */ 137 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 138 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, 139 FN_SCIFA1_TXD_C, FN_AVB_TXD2, 140 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, 141 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 142 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, 143 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, 144 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, 145 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, 146 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14, 147 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, 148 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, 149 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, 150 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, 151 FN_A0, FN_PWM3, FN_A1, FN_PWM4, 152 153 /* IPSR2 */ 154 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3, 155 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B, 156 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 157 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, 158 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, 159 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, 160 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, 161 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, 162 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, 163 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, 164 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 165 166 /* IPSR3 */ 167 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, 168 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 169 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, 170 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, 171 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, 172 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, 173 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B, 174 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B, 175 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N, 176 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18, 177 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B, 178 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK, 179 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, 180 181 /* IPSR4 */ 182 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 183 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, 184 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7, 185 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3, 186 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, 187 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6, 188 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N, 189 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, 190 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, 191 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B, 192 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B, 193 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK, 194 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B, 195 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, 196 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 197 198 /* IPSR5 */ 199 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, 200 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, 201 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, 202 FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX, 203 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, 204 FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, 205 FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B, 206 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, 207 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, 208 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, 209 FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, 210 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 211 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, 212 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, 213 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, 214 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, 215 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, 216 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, 217 FN_SSI_WS78_B, 218 219 /* IPSR6 */ 220 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, 221 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 222 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, 223 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, 224 FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 225 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, 226 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, 227 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 228 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B, 229 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, 230 FN_I2C2_SCL_E, FN_ETH_RX_ER, 231 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, 232 FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, 233 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, 234 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, 235 FN_HRX0_E, FN_STP_ISSYNC_0_B, 236 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, 237 FN_RX1_E, FN_ETH_LINK, FN_HTX0_E, 238 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 239 FN_ETH_REF_CLK, FN_HCTS0_N_E, 240 FN_STP_IVCXO27_1_B, FN_HRX0_F, 241 242 /* IPSR7 */ 243 FN_ETH_MDIO, FN_HRTS0_N_E, 244 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, 245 FN_HTX0_F, FN_BPFCLK_G, 246 FN_ETH_TX_EN, FN_SIM0_CLK_C, 247 FN_HRTS0_N_F, FN_ETH_MAGIC, 248 FN_SIM0_RST_C, FN_ETH_TXD0, 249 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, 250 FN_ETH_MDC, FN_STP_ISD_1_B, 251 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, 252 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, 253 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, 254 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, 255 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, 256 FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1, 257 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, 258 FN_ATACS00_N, FN_AVB_RXD1, 259 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 260 261 /* IPSR8 */ 262 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 263 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, 264 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, 265 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, 266 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, 267 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 268 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 269 FN_VI1_CLK, FN_AVB_RX_DV, 270 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, 271 FN_AVB_CRS, FN_VI1_DATA1_VI1_B1, 272 FN_SCIFA1_RXD_D, FN_AVB_MDC, 273 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 274 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, 275 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, 276 FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5, 277 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, 278 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, 279 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 280 281 /* IPSR9 */ 282 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 283 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 284 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 285 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 286 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, 287 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, 288 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, 289 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, 290 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, 291 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, 292 FN_AVB_TX_EN, FN_SD1_CMD, 293 FN_AVB_TX_ER, FN_SCIFB0_SCK_B, 294 FN_SD1_DAT0, FN_AVB_TX_CLK, 295 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, 296 FN_SCIFB0_TXD_B, FN_SD1_DAT2, 297 FN_AVB_COL, FN_SCIFB0_CTS_N_B, 298 FN_SD1_DAT3, FN_AVB_RXD0, 299 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, 300 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, 301 FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B, 302 FN_VI3_CLK_B, 303 304 /* IPSR10 */ 305 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, 306 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, 307 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, 308 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, 309 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, 310 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, 311 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, 312 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, 313 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, 314 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, 315 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 316 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, 317 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, 318 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 319 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, 320 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, 321 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, 322 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, 323 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4, 324 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, 325 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, 326 FN_GLO_I0_B, FN_VI3_DATA6_B, 327 328 /* IPSR11 */ 329 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, 330 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, 331 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 332 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD, 333 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 334 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2, 335 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3, 336 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, 337 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, 338 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, 339 FN_FMIN_E, FN_FMIN_F, 340 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 341 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, 342 FN_I2C2_SDA_B, FN_MLB_DAT, 343 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, 344 FN_SSI_SCK0129, FN_CAN_CLK_B, 345 FN_MOUT0, 346 347 /* IPSR12 */ 348 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 349 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 350 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 351 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, 352 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, 353 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34, 354 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, 355 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0, 356 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 357 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, 358 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 359 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, 360 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 361 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, 362 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK, 363 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, 364 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD, 365 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, 366 FN_CAN_DEBUGOUT4, 367 368 /* IPSR13 */ 369 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, 370 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6, 371 FN_SCIFB1_CTS_N, FN_BPFCLK_D, 372 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, 373 FN_BPFCLK_F, FN_SSI_WS6, 374 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, 375 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6, 376 FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5, 377 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1, 378 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6, 379 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1, 380 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7, 381 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7, 382 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, 383 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, 384 FN_BPFCLK_E, FN_SSI_SDATA7_B, 385 FN_FMIN_G, FN_SSI_SDATA8, 386 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, 387 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9, 388 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, 389 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA, 390 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 391 392 /* IPSR14 */ 393 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, 394 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, 395 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, 396 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C, 397 FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, 398 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, 399 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, 400 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, 401 FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, 402 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, 403 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 404 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, 405 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 406 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, 407 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, 408 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, 409 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, 410 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, 411 FN_HRTS0_N_C, 412 413 /* IPSR15 */ 414 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, 415 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, 416 FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL, 417 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, 418 FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0, 419 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, 420 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, 421 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, 422 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, 423 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, 424 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0, 425 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23, 426 FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0, 427 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1, 428 FN_DU2_DG6, FN_LCDOUT14, 429 430 /* IPSR16 */ 431 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, 432 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 433 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, 434 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 435 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC, 436 FN_TCLK1_B, 437 438 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 439 FN_SEL_SCIF1_4, 440 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 441 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 442 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 443 FN_SEL_SCIFB1_4, 444 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, 445 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, 446 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, 447 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 448 FN_SEL_SOF1_0, FN_SEL_SOF1_1, 449 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 450 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 451 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 452 FN_SEL_VI3_0, FN_SEL_VI3_1, 453 FN_SEL_VI2_0, FN_SEL_VI2_1, 454 FN_SEL_VI1_0, FN_SEL_VI1_1, 455 FN_SEL_VI0_0, FN_SEL_VI0_1, 456 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 457 FN_SEL_LBS_0, FN_SEL_LBS_1, 458 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 459 FN_SEL_SOF3_0, FN_SEL_SOF3_1, 460 FN_SEL_SOF0_0, FN_SEL_SOF0_1, 461 462 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 463 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 464 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, 465 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 466 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 467 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 468 FN_SEL_CAN1_0, FN_SEL_CAN1_1, 469 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, 470 FN_SEL_ADI_0, FN_SEL_ADI_1, 471 FN_SEL_SSP_0, FN_SEL_SSP_1, 472 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, 473 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 474 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, 475 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 476 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 477 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 478 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 479 480 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, 481 FN_SEL_IIC0_0, FN_SEL_IIC0_1, 482 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 483 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, 484 FN_SEL_IIC2_4, 485 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 486 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 487 FN_SEL_I2C2_4, 488 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 489 PINMUX_FUNCTION_END, 490 491 PINMUX_MARK_BEGIN, 492 493 VI1_DATA7_VI1_B7_MARK, 494 495 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, 496 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK, 497 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK, 498 499 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK, 500 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK, 501 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK, 502 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK, 503 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK, 504 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK, 505 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, 506 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, 507 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, 508 IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, 509 I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK, 510 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK, 511 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, 512 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, 513 514 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, 515 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, 516 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, 517 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, 518 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, 519 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, 520 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, 521 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, 522 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK, 523 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK, 524 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK, 525 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK, 526 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK, 527 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK, 528 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK, 529 530 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK, 531 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK, 532 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK, 533 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, 534 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, 535 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, 536 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK, 537 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, 538 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK, 539 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, 540 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, 541 542 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK, 543 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK, 544 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK, 545 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK, 546 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK, 547 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK, 548 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK, 549 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK, 550 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK, 551 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK, 552 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK, 553 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK, 554 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK, 555 556 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK, 557 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK, 558 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK, 559 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK, 560 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK, 561 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK, 562 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK, 563 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK, 564 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK, 565 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK, 566 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK, 567 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK, 568 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK, 569 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK, 570 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK, 571 572 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, 573 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, 574 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, 575 VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK, 576 INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, 577 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, 578 VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK, 579 I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, 580 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, 581 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, 582 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, 583 INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, 584 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, 585 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, 586 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, 587 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, 588 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, 589 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, 590 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, 591 SSI_WS78_B_MARK, 592 593 DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, 594 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, 595 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, 596 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, 597 INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, 598 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, 599 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, 600 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, 601 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK, 602 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, 603 I2C2_SCL_E_MARK, ETH_RX_ER_MARK, 604 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, 605 IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, 606 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, 607 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, 608 HRX0_E_MARK, STP_ISSYNC_0_B_MARK, 609 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, 610 RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK, 611 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, 612 ETH_REF_CLK_MARK, HCTS0_N_E_MARK, 613 STP_IVCXO27_1_B_MARK, HRX0_F_MARK, 614 615 ETH_MDIO_MARK, HRTS0_N_E_MARK, 616 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, 617 HTX0_F_MARK, BPFCLK_G_MARK, 618 ETH_TX_EN_MARK, SIM0_CLK_C_MARK, 619 HRTS0_N_F_MARK, ETH_MAGIC_MARK, 620 SIM0_RST_C_MARK, ETH_TXD0_MARK, 621 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, 622 ETH_MDC_MARK, STP_ISD_1_B_MARK, 623 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, 624 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, 625 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, 626 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, 627 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, 628 PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK, 629 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, 630 ATACS00_N_MARK, AVB_RXD1_MARK, 631 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, 632 633 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, 634 VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, 635 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, 636 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, 637 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, 638 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, 639 VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, 640 VI1_CLK_MARK, AVB_RX_DV_MARK, 641 VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, 642 AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK, 643 SCIFA1_RXD_D_MARK, AVB_MDC_MARK, 644 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, 645 VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, 646 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, 647 AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, 648 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, 649 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, 650 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, 651 652 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK, 653 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK, 654 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, 655 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, 656 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, 657 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK, 658 I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, 659 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, 660 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK, 661 I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, 662 AVB_TX_EN_MARK, SD1_CMD_MARK, 663 AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK, 664 SD1_DAT0_MARK, AVB_TX_CLK_MARK, 665 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, 666 SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, 667 AVB_COL_MARK, SCIFB0_CTS_N_B_MARK, 668 SD1_DAT3_MARK, AVB_RXD0_MARK, 669 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, 670 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, 671 IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK, 672 VI3_CLK_B_MARK, 673 674 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, 675 GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK, 676 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, 677 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, 678 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, 679 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK, 680 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK, 681 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, 682 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, 683 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, 684 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, 685 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, 686 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, 687 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, 688 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, 689 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, 690 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, 691 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK, 692 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK, 693 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK, 694 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK, 695 GLO_I0_B_MARK, VI3_DATA6_B_MARK, 696 697 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK, 698 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK, 699 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK, 700 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK, 701 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK, 702 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK, 703 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK, 704 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, 705 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, 706 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, 707 FMIN_E_MARK, FMIN_F_MARK, 708 MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK, 709 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK, 710 I2C2_SDA_B_MARK, MLB_DAT_MARK, 711 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, 712 SSI_SCK0129_MARK, CAN_CLK_B_MARK, 713 MOUT0_MARK, 714 715 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, 716 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK, 717 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK, 718 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK, 719 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK, 720 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK, 721 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK, 722 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK, 723 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK, 724 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK, 725 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK, 726 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK, 727 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK, 728 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK, 729 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK, 730 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK, 731 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK, 732 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK, 733 CAN_DEBUGOUT4_MARK, 734 735 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, 736 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, 737 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, 738 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, 739 BPFCLK_F_MARK, SSI_WS6_MARK, 740 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, 741 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, 742 FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK, 743 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, 744 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, 745 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, 746 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK, 747 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, 748 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, 749 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, 750 BPFCLK_E_MARK, SSI_SDATA7_B_MARK, 751 FMIN_G_MARK, SSI_SDATA8_MARK, 752 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, 753 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, 754 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, 755 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK, 756 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK, 757 758 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, 759 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, 760 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, 761 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK, 762 I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, 763 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, 764 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, 765 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, 766 LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK, 767 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK, 768 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, 769 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, 770 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, 771 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, 772 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, 773 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, 774 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK, 775 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, 776 HRTS0_N_C_MARK, 777 778 SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, 779 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, 780 TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK, 781 SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK, 782 IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK, 783 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, 784 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, 785 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, 786 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK, 787 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, 788 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, 789 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, 790 HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, 791 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, 792 DU2_DG6_MARK, LCDOUT14_MARK, 793 794 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, 795 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, 796 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, 797 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK, 798 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, 799 TCLK1_B_MARK, 800 801 IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK, 802 IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK, 803 PINMUX_MARK_END, 804 }; 805 806 static const u16 pinmux_data[] = { 807 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 808 809 PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7), 810 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), 811 PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS), 812 PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN), 813 PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC), 814 PINMUX_DATA(AVS1_MARK, FN_AVS1), 815 PINMUX_DATA(AVS2_MARK, FN_AVS2), 816 PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0), 817 PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2), 818 819 PINMUX_IPSR_DATA(IP0_2_0, D0), 820 PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), 821 PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0), 822 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0), 823 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1), 824 PINMUX_IPSR_DATA(IP0_5_3, D1), 825 PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), 826 PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0), 827 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0), 828 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1), 829 PINMUX_IPSR_DATA(IP0_8_6, D2), 830 PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), 831 PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0), 832 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0), 833 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1), 834 PINMUX_IPSR_DATA(IP0_11_9, D3), 835 PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), 836 PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0), 837 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0), 838 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1), 839 PINMUX_IPSR_DATA(IP0_15_12, D4), 840 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), 841 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), 842 PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0), 843 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0), 844 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1), 845 PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1), 846 PINMUX_IPSR_DATA(IP0_19_16, D5), 847 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), 848 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), 849 PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0), 850 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0), 851 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1), 852 PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1), 853 PINMUX_IPSR_DATA(IP0_22_20, D6), 854 PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2), 855 PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0), 856 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0), 857 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1), 858 PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2), 859 PINMUX_IPSR_DATA(IP0_26_23, D7), 860 PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1), 861 PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2), 862 PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0), 863 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0), 864 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1), 865 PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2), 866 PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0), 867 PINMUX_IPSR_DATA(IP0_30_27, D8), 868 PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), 869 PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), 870 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0), 871 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1), 872 PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), 873 874 PINMUX_IPSR_DATA(IP1_3_0, D9), 875 PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), 876 PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1), 877 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0), 878 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1), 879 PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), 880 PINMUX_IPSR_DATA(IP1_7_4, D10), 881 PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), 882 PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2), 883 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0), 884 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1), 885 PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), 886 PINMUX_IPSR_DATA(IP1_11_8, D11), 887 PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), 888 PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3), 889 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0), 890 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1), 891 PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), 892 PINMUX_IPSR_DATA(IP1_14_12, D12), 893 PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), 894 PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4), 895 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), 896 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), 897 PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), 898 PINMUX_IPSR_DATA(IP1_17_15, D13), 899 PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5), 900 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), 901 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), 902 PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), 903 PINMUX_IPSR_DATA(IP1_21_18, D14), 904 PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), 905 PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6), 906 PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1), 907 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0), 908 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), 909 PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), 910 PINMUX_IPSR_DATA(IP1_25_22, D15), 911 PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), 912 PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7), 913 PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1), 914 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0), 915 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), 916 PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), 917 PINMUX_IPSR_DATA(IP1_27_26, A0), 918 PINMUX_IPSR_DATA(IP1_27_26, PWM3), 919 PINMUX_IPSR_DATA(IP1_29_28, A1), 920 PINMUX_IPSR_DATA(IP1_29_28, PWM4), 921 922 PINMUX_IPSR_DATA(IP2_2_0, A2), 923 PINMUX_IPSR_DATA(IP2_2_0, PWM5), 924 PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), 925 PINMUX_IPSR_DATA(IP2_5_3, A3), 926 PINMUX_IPSR_DATA(IP2_5_3, PWM6), 927 PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), 928 PINMUX_IPSR_DATA(IP2_8_6, A4), 929 PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), 930 PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0), 931 PINMUX_IPSR_DATA(IP2_11_9, A5), 932 PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), 933 PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1), 934 PINMUX_IPSR_DATA(IP2_14_12, A6), 935 PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), 936 PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2), 937 PINMUX_IPSR_DATA(IP2_17_15, A7), 938 PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), 939 PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B), 940 PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3), 941 PINMUX_IPSR_DATA(IP2_21_18, A8), 942 PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), 943 PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), 944 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0), 945 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1), 946 PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), 947 PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1), 948 PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), 949 PINMUX_IPSR_DATA(IP2_25_22, A9), 950 PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), 951 PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), 952 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0), 953 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1), 954 PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), 955 PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1), 956 PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), 957 PINMUX_IPSR_DATA(IP2_28_26, A10), 958 PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), 959 PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC), 960 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0), 961 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1), 962 PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), 963 964 PINMUX_IPSR_DATA(IP3_3_0, A11), 965 PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), 966 PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK), 967 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0), 968 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1), 969 PINMUX_IPSR_DATA(IP3_3_0, VI2_G0), 970 PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1), 971 PINMUX_IPSR_DATA(IP3_7_4, A12), 972 PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), 973 PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD), 974 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0), 975 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1), 976 PINMUX_IPSR_DATA(IP3_7_4, VI2_G1), 977 PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1), 978 PINMUX_IPSR_DATA(IP3_11_8, A13), 979 PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), 980 PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2), 981 PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD), 982 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0), 983 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1), 984 PINMUX_IPSR_DATA(IP3_11_8, VI2_G2), 985 PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1), 986 PINMUX_IPSR_DATA(IP3_14_12, A14), 987 PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), 988 PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N), 989 PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1), 990 PINMUX_IPSR_DATA(IP3_17_15, A15), 991 PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), 992 PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N), 993 PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2), 994 PINMUX_IPSR_DATA(IP3_19_18, A16), 995 PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N), 996 PINMUX_IPSR_DATA(IP3_22_20, A17), 997 PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1), 998 PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N), 999 PINMUX_IPSR_DATA(IP3_25_23, A18), 1000 PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1), 1001 PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N), 1002 PINMUX_IPSR_DATA(IP3_28_26, A19), 1003 PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), 1004 PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N), 1005 PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), 1006 PINMUX_IPSR_DATA(IP3_31_29, A20), 1007 PINMUX_IPSR_DATA(IP3_31_29, SPCLK), 1008 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0), 1009 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1), 1010 PINMUX_IPSR_DATA(IP3_31_29, VI2_G4), 1011 1012 PINMUX_IPSR_DATA(IP4_2_0, A21), 1013 PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0), 1014 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0), 1015 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1), 1016 PINMUX_IPSR_DATA(IP4_2_0, VI2_G5), 1017 PINMUX_IPSR_DATA(IP4_5_3, A22), 1018 PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1), 1019 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0), 1020 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1), 1021 PINMUX_IPSR_DATA(IP4_5_3, VI2_G6), 1022 PINMUX_IPSR_DATA(IP4_8_6, A23), 1023 PINMUX_IPSR_DATA(IP4_8_6, IO2), 1024 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0), 1025 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1), 1026 PINMUX_IPSR_DATA(IP4_8_6, VI2_G7), 1027 PINMUX_IPSR_DATA(IP4_11_9, A24), 1028 PINMUX_IPSR_DATA(IP4_11_9, IO3), 1029 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0), 1030 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1), 1031 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0), 1032 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), 1033 PINMUX_IPSR_DATA(IP4_14_12, A25), 1034 PINMUX_IPSR_DATA(IP4_14_12, SSL), 1035 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0), 1036 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1), 1037 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0), 1038 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), 1039 PINMUX_IPSR_DATA(IP4_17_15, CS0_N), 1040 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0), 1041 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1), 1042 PINMUX_IPSR_DATA(IP4_17_15, VI2_G3), 1043 PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), 1044 PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26), 1045 PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN), 1046 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0), 1047 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1), 1048 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0), 1049 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1), 1050 PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N), 1051 PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1), 1052 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0), 1053 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1), 1054 PINMUX_IPSR_DATA(IP4_23_21, VI2_R0), 1055 PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1), 1056 PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), 1057 PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N), 1058 PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK), 1059 PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), 1060 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0), 1061 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), 1062 PINMUX_IPSR_DATA(IP4_26_24, VI2_R1), 1063 PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N), 1064 PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN), 1065 PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), 1066 PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB), 1067 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0), 1068 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1), 1069 PINMUX_IPSR_DATA(IP4_29_27, VI2_R2), 1070 1071 PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N), 1072 PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG), 1073 PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD), 1074 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0), 1075 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1), 1076 PINMUX_IPSR_DATA(IP5_2_0, VI2_R3), 1077 PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N), 1078 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), 1079 PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N), 1080 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), 1081 PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0), 1082 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), 1083 PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N), 1084 PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0), 1085 PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N), 1086 PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0), 1087 PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), 1088 PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N), 1089 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0), 1090 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1), 1091 PINMUX_IPSR_DATA(IP5_9_6, VI2_R4), 1092 PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0), 1093 PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N), 1094 PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0), 1095 PINMUX_IPSR_DATA(IP5_12_10, BS_N), 1096 PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0), 1097 PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1), 1098 PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0), 1099 PINMUX_IPSR_DATA(IP5_12_10, DRACK0), 1100 PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2), 1101 PINMUX_IPSR_DATA(IP5_14_13, RD_N), 1102 PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0), 1103 PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), 1104 PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N), 1105 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0), 1106 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1), 1107 PINMUX_IPSR_DATA(IP5_17_15, VI2_R5), 1108 PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), 1109 PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N), 1110 PINMUX_IPSR_DATA(IP5_20_18, WE0_N), 1111 PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0), 1112 PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0), 1113 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), 1114 PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), 1115 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), 1116 PINMUX_IPSR_DATA(IP5_23_21, WE1_N), 1117 PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0), 1118 PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0), 1119 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0), 1120 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1), 1121 PINMUX_IPSR_DATA(IP5_23_21, VI2_R6), 1122 PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), 1123 PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2), 1124 PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0), 1125 PINMUX_IPSR_DATA(IP5_26_24, IRQ3), 1126 PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N), 1127 PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0), 1128 PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), 1129 PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1), 1130 PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), 1131 PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N), 1132 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), 1133 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), 1134 PINMUX_IPSR_DATA(IP5_29_27, VI2_R7), 1135 PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), 1136 PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), 1137 1138 PINMUX_IPSR_DATA(IP6_2_0, DACK0), 1139 PINMUX_IPSR_DATA(IP6_2_0, IRQ0), 1140 PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N), 1141 PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), 1142 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), 1143 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), 1144 PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), 1145 PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N), 1146 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0), 1147 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), 1148 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), 1149 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), 1150 PINMUX_IPSR_DATA(IP6_8_6, DACK1), 1151 PINMUX_IPSR_DATA(IP6_8_6, IRQ1), 1152 PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N), 1153 PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), 1154 PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), 1155 PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N), 1156 PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), 1157 PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), 1158 PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), 1159 PINMUX_IPSR_DATA(IP6_13_11, DACK2), 1160 PINMUX_IPSR_DATA(IP6_13_11, IRQ2), 1161 PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N), 1162 PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), 1163 PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), 1164 PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), 1165 PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), 1166 PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), 1167 PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), 1168 PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2), 1169 PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), 1170 PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), 1171 PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), 1172 PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), 1173 PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), 1174 PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2), 1175 PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), 1176 PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), 1177 PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), 1178 PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), 1179 PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), 1180 PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2), 1181 PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), 1182 PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4), 1183 PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), 1184 PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4), 1185 PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), 1186 PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), 1187 PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2), 1188 PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), 1189 PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4), 1190 PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), 1191 PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4), 1192 PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), 1193 PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), 1194 PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4), 1195 PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), 1196 PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), 1197 PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), 1198 PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5), 1199 1200 PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), 1201 PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), 1202 PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2), 1203 PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), 1204 PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), 1205 PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5), 1206 PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6), 1207 PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), 1208 PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), 1209 PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), 1210 PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), 1211 PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2), 1212 PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), 1213 PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), 1214 PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), 1215 PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), 1216 PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), 1217 PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), 1218 PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), 1219 PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), 1220 PINMUX_IPSR_DATA(IP7_18_16, PWM0), 1221 PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), 1222 PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), 1223 PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), 1224 PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2), 1225 PINMUX_IPSR_DATA(IP7_21_19, PWM1), 1226 PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), 1227 PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), 1228 PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), 1229 PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2), 1230 PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N), 1231 PINMUX_IPSR_DATA(IP7_24_22, PWM2), 1232 PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0), 1233 PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), 1234 PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N), 1235 PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2), 1236 PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1), 1237 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC), 1238 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C), 1239 PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0), 1240 PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), 1241 PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), 1242 PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), 1243 PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), 1244 PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), 1245 1246 PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), 1247 PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), 1248 PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), 1249 PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), 1250 PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), 1251 PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), 1252 PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), 1253 PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N), 1254 PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5), 1255 PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), 1256 PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N), 1257 PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6), 1258 PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), 1259 PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1), 1260 PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), 1261 PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), 1262 PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), 1263 PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), 1264 PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), 1265 PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0), 1266 PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), 1267 PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), 1268 PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), 1269 PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), 1270 PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), 1271 PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), 1272 PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), 1273 PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), 1274 PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), 1275 PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), 1276 PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), 1277 PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), 1278 PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), 1279 PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), 1280 PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), 1281 PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), 1282 PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), 1283 PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT), 1284 PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), 1285 PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK), 1286 PINMUX_IPSR_DATA(IP8_28, SD0_CLK), 1287 PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), 1288 PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD), 1289 PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), 1290 PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), 1291 1292 PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0), 1293 PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), 1294 PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), 1295 PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1), 1296 PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), 1297 PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), 1298 PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2), 1299 PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), 1300 PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), 1301 PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3), 1302 PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), 1303 PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), 1304 PINMUX_IPSR_DATA(IP9_11_8, SD0_CD), 1305 PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6), 1306 PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), 1307 PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP), 1308 PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0), 1309 PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), 1310 PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1), 1311 PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1), 1312 PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), 1313 PINMUX_IPSR_DATA(IP9_15_12, SD0_WP), 1314 PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7), 1315 PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), 1316 PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN), 1317 PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0), 1318 PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), 1319 PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1), 1320 PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1), 1321 PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), 1322 PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), 1323 PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), 1324 PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), 1325 PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), 1326 PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), 1327 PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), 1328 PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), 1329 PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), 1330 PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), 1331 PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), 1332 PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), 1333 PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), 1334 PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), 1335 PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), 1336 PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), 1337 PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), 1338 PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), 1339 PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), 1340 PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), 1341 PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), 1342 PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP), 1343 PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0), 1344 PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1), 1345 PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3), 1346 PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3), 1347 PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), 1348 PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1), 1349 1350 PINMUX_IPSR_DATA(IP10_3_0, SD1_WP), 1351 PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7), 1352 PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), 1353 PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN), 1354 PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0), 1355 PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1), 1356 PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3), 1357 PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3), 1358 PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1), 1359 PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK), 1360 PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK), 1361 PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0), 1362 PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), 1363 PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), 1364 PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), 1365 PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), 1366 PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD), 1367 PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD), 1368 PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0), 1369 PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), 1370 PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), 1371 PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3), 1372 PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), 1373 PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), 1374 PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), 1375 PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0), 1376 PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0), 1377 PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1), 1378 PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), 1379 PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), 1380 PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3), 1381 PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), 1382 PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1), 1383 PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), 1384 PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1), 1385 PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1), 1386 PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1), 1387 PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), 1388 PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), 1389 PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3), 1390 PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), 1391 PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1), 1392 PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), 1393 PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2), 1394 PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2), 1395 PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1), 1396 PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), 1397 PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3), 1398 PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), 1399 PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1), 1400 PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), 1401 PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3), 1402 PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3), 1403 PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0), 1404 PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), 1405 PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3), 1406 PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), 1407 PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1), 1408 PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), 1409 PINMUX_IPSR_DATA(IP10_29_26, SD2_CD), 1410 PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4), 1411 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), 1412 PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP), 1413 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0), 1414 PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), 1415 PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), 1416 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), 1417 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1), 1418 PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), 1419 1420 PINMUX_IPSR_DATA(IP11_3_0, SD2_WP), 1421 PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5), 1422 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), 1423 PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN), 1424 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0), 1425 PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), 1426 PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), 1427 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), 1428 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1), 1429 PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), 1430 PINMUX_IPSR_DATA(IP11_4, SD3_CLK), 1431 PINMUX_IPSR_DATA(IP11_4, MMC1_CLK), 1432 PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD), 1433 PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD), 1434 PINMUX_IPSR_DATA(IP11_6_5, MTS_N), 1435 PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0), 1436 PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0), 1437 PINMUX_IPSR_DATA(IP11_8_7, STM_N), 1438 PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1), 1439 PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1), 1440 PINMUX_IPSR_DATA(IP11_10_9, MDATA), 1441 PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2), 1442 PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2), 1443 PINMUX_IPSR_DATA(IP11_12_11, SDATA), 1444 PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3), 1445 PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3), 1446 PINMUX_IPSR_DATA(IP11_14_13, SCKZ), 1447 PINMUX_IPSR_DATA(IP11_17_15, SD3_CD), 1448 PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4), 1449 PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), 1450 PINMUX_IPSR_DATA(IP11_17_15, VSP), 1451 PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0), 1452 PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1), 1453 PINMUX_IPSR_DATA(IP11_21_18, SD3_WP), 1454 PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5), 1455 PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0), 1456 PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0), 1457 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2), 1458 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4), 1459 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5), 1460 PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), 1461 PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1), 1462 PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1), 1463 PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG), 1464 PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), 1465 PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2), 1466 PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1), 1467 PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1), 1468 PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), 1469 PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), 1470 PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2), 1471 PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2), 1472 PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129), 1473 PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), 1474 PINMUX_IPSR_DATA(IP11_31_30, MOUT0), 1475 1476 PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129), 1477 PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), 1478 PINMUX_IPSR_DATA(IP12_1_0, MOUT1), 1479 PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0), 1480 PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), 1481 PINMUX_IPSR_DATA(IP12_3_2, MOUT2), 1482 PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1), 1483 PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), 1484 PINMUX_IPSR_DATA(IP12_5_4, MOUT5), 1485 PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2), 1486 PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), 1487 PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1), 1488 PINMUX_IPSR_DATA(IP12_7_6, MOUT6), 1489 PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34), 1490 PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0), 1491 PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), 1492 PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), 1493 PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER), 1494 PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34), 1495 PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), 1496 PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), 1497 PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC), 1498 PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0), 1499 PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3), 1500 PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), 1501 PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), 1502 PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), 1503 PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK), 1504 PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4), 1505 PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0), 1506 PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), 1507 PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), 1508 PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), 1509 PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0), 1510 PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4), 1511 PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0), 1512 PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), 1513 PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), 1514 PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), 1515 PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1), 1516 PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4), 1517 PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), 1518 PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), 1519 PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2), 1520 PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0), 1521 PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), 1522 PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1), 1523 PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC), 1524 PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS), 1525 PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3), 1526 PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0), 1527 PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), 1528 PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1), 1529 PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC), 1530 PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE), 1531 PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4), 1532 1533 PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), 1534 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), 1535 PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1), 1536 PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2), 1537 PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2), 1538 PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5), 1539 PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0), 1540 PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), 1541 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3), 1542 PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3), 1543 PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3), 1544 PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6), 1545 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5), 1546 PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0), 1547 PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), 1548 PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), 1549 PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4), 1550 PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4), 1551 PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7), 1552 PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), 1553 PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3), 1554 PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5), 1555 PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5), 1556 PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8), 1557 PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0), 1558 PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), 1559 PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0), 1560 PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), 1561 PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6), 1562 PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6), 1563 PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9), 1564 PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0), 1565 PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), 1566 PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), 1567 PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N), 1568 PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7), 1569 PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7), 1570 PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10), 1571 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), 1572 PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0), 1573 PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), 1574 PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N), 1575 PINMUX_IPSR_DATA(IP13_22_19, TCLK2), 1576 PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS), 1577 PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11), 1578 PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4), 1579 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), 1580 PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6), 1581 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), 1582 PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0), 1583 PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), 1584 PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), 1585 PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12), 1586 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), 1587 PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9), 1588 PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), 1589 PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), 1590 PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1), 1591 PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), 1592 PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13), 1593 PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA), 1594 PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), 1595 PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14), 1596 1597 PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB), 1598 PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), 1599 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), 1600 PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE), 1601 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), 1602 PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15), 1603 PINMUX_IPSR_DATA(IP14_2_0, REMOCON), 1604 PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), 1605 PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0), 1606 PINMUX_IPSR_DATA(IP14_5_3, SCK0), 1607 PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2), 1608 PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2), 1609 PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10), 1610 PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2), 1611 PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2), 1612 PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), 1613 PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0), 1614 PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0), 1615 PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0), 1616 PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0), 1617 PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), 1618 PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0), 1619 PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0), 1620 PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1), 1621 PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1), 1622 PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), 1623 PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), 1624 PINMUX_IPSR_DATA(IP14_15_12, CTS0_N), 1625 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), 1626 PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3), 1627 PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11), 1628 PINMUX_IPSR_DATA(IP14_15_12, PWM0_B), 1629 PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2), 1630 PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), 1631 PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), 1632 PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), 1633 PINMUX_IPSR_DATA(IP14_18_16, RTS0_N), 1634 PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1), 1635 PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0), 1636 PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8), 1637 PINMUX_IPSR_DATA(IP14_18_16, PWM1_B), 1638 PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), 1639 PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0), 1640 PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0), 1641 PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE), 1642 PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE), 1643 PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), 1644 PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0), 1645 PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0), 1646 PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1), 1647 PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9), 1648 PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), 1649 PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0), 1650 PINMUX_IPSR_DATA(IP14_27_25, CTS1_N), 1651 PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), 1652 PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT), 1653 PINMUX_IPSR_DATA(IP14_27_25, QCLK), 1654 PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), 1655 PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0), 1656 PINMUX_IPSR_DATA(IP14_30_28, RTS1_N), 1657 PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), 1658 PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT), 1659 PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE), 1660 PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), 1661 1662 PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), 1663 PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0), 1664 PINMUX_IPSR_DATA(IP15_2_0, SCK2), 1665 PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), 1666 PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7), 1667 PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15), 1668 PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1), 1669 PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), 1670 PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0), 1671 PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0), 1672 PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), 1673 PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), 1674 PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0), 1675 PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0), 1676 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), 1677 PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0), 1678 PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0), 1679 PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), 1680 PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), 1681 PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0), 1682 PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0), 1683 PINMUX_IPSR_DATA(IP15_11_9, HSCK0), 1684 PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), 1685 PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4), 1686 PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12), 1687 PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2), 1688 PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0), 1689 PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2), 1690 PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18), 1691 PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0), 1692 PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3), 1693 PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19), 1694 PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), 1695 PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9), 1696 PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4), 1697 PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20), 1698 PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), 1699 PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9), 1700 PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5), 1701 PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21), 1702 PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), 1703 PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), 1704 PINMUX_IPSR_DATA(IP15_22_20, ADICLK), 1705 PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6), 1706 PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22), 1707 PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC), 1708 PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0), 1709 PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2), 1710 PINMUX_IPSR_DATA(IP15_25_23, ADIDATA), 1711 PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7), 1712 PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23), 1713 PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1), 1714 PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), 1715 PINMUX_IPSR_DATA(IP15_27_26, ADICHS0), 1716 PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5), 1717 PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13), 1718 PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), 1719 PINMUX_IPSR_DATA(IP15_29_28, ADICHS1), 1720 PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6), 1721 PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14), 1722 1723 PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), 1724 PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT), 1725 PINMUX_IPSR_DATA(IP16_2_0, ADICHS2), 1726 PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP), 1727 PINMUX_IPSR_DATA(IP16_2_0, QPOLA), 1728 PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2), 1729 PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), 1730 PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), 1731 PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), 1732 PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2), 1733 PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP), 1734 PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE), 1735 PINMUX_IPSR_DATA(IP16_5_3, QPOLB), 1736 PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2), 1737 PINMUX_IPSR_DATA(IP16_6, USB1_PWEN), 1738 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D), 1739 PINMUX_IPSR_DATA(IP16_7, USB1_OVC), 1740 PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1), 1741 1742 PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0), 1743 PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0), 1744 PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1), 1745 PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1), 1746 1747 PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0), 1748 PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0), 1749 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1), 1750 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1), 1751 }; 1752 1753 /* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */ 1754 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) 1755 #define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200) 1756 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) 1757 1758 static const struct sh_pfc_pin pinmux_pins[] = { 1759 PINMUX_GPIO_GP_ALL(), 1760 1761 /* Pins not associated with a GPIO port */ 1762 SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15), 1763 SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15), 1764 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15), 1765 SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15), 1766 }; 1767 1768 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1769 static const unsigned int audio_clk_a_pins[] = { 1770 /* CLK A */ 1771 RCAR_GP_PIN(4, 25), 1772 }; 1773 static const unsigned int audio_clk_a_mux[] = { 1774 AUDIO_CLKA_MARK, 1775 }; 1776 static const unsigned int audio_clk_b_pins[] = { 1777 /* CLK B */ 1778 RCAR_GP_PIN(4, 26), 1779 }; 1780 static const unsigned int audio_clk_b_mux[] = { 1781 AUDIO_CLKB_MARK, 1782 }; 1783 static const unsigned int audio_clk_c_pins[] = { 1784 /* CLK C */ 1785 RCAR_GP_PIN(5, 27), 1786 }; 1787 static const unsigned int audio_clk_c_mux[] = { 1788 AUDIO_CLKC_MARK, 1789 }; 1790 static const unsigned int audio_clkout_pins[] = { 1791 /* CLK OUT */ 1792 RCAR_GP_PIN(5, 16), 1793 }; 1794 static const unsigned int audio_clkout_mux[] = { 1795 AUDIO_CLKOUT_MARK, 1796 }; 1797 static const unsigned int audio_clkout_b_pins[] = { 1798 /* CLK OUT B */ 1799 RCAR_GP_PIN(0, 23), 1800 }; 1801 static const unsigned int audio_clkout_b_mux[] = { 1802 AUDIO_CLKOUT_B_MARK, 1803 }; 1804 static const unsigned int audio_clkout_c_pins[] = { 1805 /* CLK OUT C */ 1806 RCAR_GP_PIN(5, 27), 1807 }; 1808 static const unsigned int audio_clkout_c_mux[] = { 1809 AUDIO_CLKOUT_C_MARK, 1810 }; 1811 static const unsigned int audio_clkout_d_pins[] = { 1812 /* CLK OUT D */ 1813 RCAR_GP_PIN(5, 20), 1814 }; 1815 static const unsigned int audio_clkout_d_mux[] = { 1816 AUDIO_CLKOUT_D_MARK, 1817 }; 1818 /* - AVB -------------------------------------------------------------------- */ 1819 static const unsigned int avb_link_pins[] = { 1820 RCAR_GP_PIN(3, 11), 1821 }; 1822 static const unsigned int avb_link_mux[] = { 1823 AVB_LINK_MARK, 1824 }; 1825 static const unsigned int avb_magic_pins[] = { 1826 RCAR_GP_PIN(2, 14), 1827 }; 1828 static const unsigned int avb_magic_mux[] = { 1829 AVB_MAGIC_MARK, 1830 }; 1831 static const unsigned int avb_phy_int_pins[] = { 1832 RCAR_GP_PIN(2, 15), 1833 }; 1834 static const unsigned int avb_phy_int_mux[] = { 1835 AVB_PHY_INT_MARK, 1836 }; 1837 static const unsigned int avb_mdio_pins[] = { 1838 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 1839 }; 1840 static const unsigned int avb_mdio_mux[] = { 1841 AVB_MDC_MARK, AVB_MDIO_MARK, 1842 }; 1843 static const unsigned int avb_mii_pins[] = { 1844 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 1845 RCAR_GP_PIN(0, 11), 1846 1847 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1848 RCAR_GP_PIN(2, 2), 1849 1850 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1851 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10), 1852 RCAR_GP_PIN(3, 12), 1853 }; 1854 static const unsigned int avb_mii_mux[] = { 1855 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1856 AVB_TXD3_MARK, 1857 1858 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1859 AVB_RXD3_MARK, 1860 1861 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1862 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK, 1863 AVB_COL_MARK, 1864 }; 1865 static const unsigned int avb_gmii_pins[] = { 1866 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 1867 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 1868 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 1869 1870 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1871 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 1872 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 1873 1874 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1875 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16), 1876 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), 1877 RCAR_GP_PIN(3, 12), 1878 }; 1879 static const unsigned int avb_gmii_mux[] = { 1880 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1881 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK, 1882 AVB_TXD6_MARK, AVB_TXD7_MARK, 1883 1884 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1885 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, 1886 AVB_RXD6_MARK, AVB_RXD7_MARK, 1887 1888 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1889 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, 1890 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, 1891 AVB_COL_MARK, 1892 }; 1893 /* - DU RGB ----------------------------------------------------------------- */ 1894 static const unsigned int du_rgb666_pins[] = { 1895 /* R[7:2], G[7:2], B[7:2] */ 1896 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), 1897 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), 1898 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), 1899 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 1900 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), 1901 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), 1902 }; 1903 static const unsigned int du_rgb666_mux[] = { 1904 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, 1905 DU2_DR3_MARK, DU2_DR2_MARK, 1906 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, 1907 DU2_DG3_MARK, DU2_DG2_MARK, 1908 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, 1909 DU2_DB3_MARK, DU2_DB2_MARK, 1910 }; 1911 static const unsigned int du_rgb888_pins[] = { 1912 /* R[7:0], G[7:0], B[7:0] */ 1913 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), 1914 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), 1915 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4), 1916 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7), 1917 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1), 1918 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), 1919 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), 1920 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), 1921 }; 1922 static const unsigned int du_rgb888_mux[] = { 1923 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, 1924 DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK, 1925 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, 1926 DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK, 1927 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, 1928 DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK, 1929 }; 1930 static const unsigned int du_clk_out_0_pins[] = { 1931 /* CLKOUT */ 1932 RCAR_GP_PIN(5, 2), 1933 }; 1934 static const unsigned int du_clk_out_0_mux[] = { 1935 DU0_DOTCLKOUT_MARK 1936 }; 1937 static const unsigned int du_clk_out_1_pins[] = { 1938 /* CLKOUT */ 1939 RCAR_GP_PIN(5, 3), 1940 }; 1941 static const unsigned int du_clk_out_1_mux[] = { 1942 DU1_DOTCLKOUT_MARK 1943 }; 1944 static const unsigned int du_sync_0_pins[] = { 1945 /* VSYNC, HSYNC, DISP */ 1946 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0), 1947 }; 1948 static const unsigned int du_sync_0_mux[] = { 1949 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, 1950 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK 1951 }; 1952 static const unsigned int du_sync_1_pins[] = { 1953 /* VSYNC, HSYNC, DISP */ 1954 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16), 1955 }; 1956 static const unsigned int du_sync_1_mux[] = { 1957 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, 1958 DU2_DISP_MARK 1959 }; 1960 static const unsigned int du_cde_pins[] = { 1961 /* CDE */ 1962 RCAR_GP_PIN(5, 17), 1963 }; 1964 static const unsigned int du_cde_mux[] = { 1965 DU2_CDE_MARK, 1966 }; 1967 /* - DU0 -------------------------------------------------------------------- */ 1968 static const unsigned int du0_clk_in_pins[] = { 1969 /* CLKIN */ 1970 RCAR_GP_PIN(5, 26), 1971 }; 1972 static const unsigned int du0_clk_in_mux[] = { 1973 DU_DOTCLKIN0_MARK 1974 }; 1975 /* - DU1 -------------------------------------------------------------------- */ 1976 static const unsigned int du1_clk_in_pins[] = { 1977 /* CLKIN */ 1978 RCAR_GP_PIN(5, 27), 1979 }; 1980 static const unsigned int du1_clk_in_mux[] = { 1981 DU_DOTCLKIN1_MARK, 1982 }; 1983 /* - DU2 -------------------------------------------------------------------- */ 1984 static const unsigned int du2_clk_in_pins[] = { 1985 /* CLKIN */ 1986 RCAR_GP_PIN(5, 28), 1987 }; 1988 static const unsigned int du2_clk_in_mux[] = { 1989 DU_DOTCLKIN2_MARK, 1990 }; 1991 /* - ETH -------------------------------------------------------------------- */ 1992 static const unsigned int eth_link_pins[] = { 1993 /* LINK */ 1994 RCAR_GP_PIN(2, 22), 1995 }; 1996 static const unsigned int eth_link_mux[] = { 1997 ETH_LINK_MARK, 1998 }; 1999 static const unsigned int eth_magic_pins[] = { 2000 /* MAGIC */ 2001 RCAR_GP_PIN(2, 27), 2002 }; 2003 static const unsigned int eth_magic_mux[] = { 2004 ETH_MAGIC_MARK, 2005 }; 2006 static const unsigned int eth_mdio_pins[] = { 2007 /* MDC, MDIO */ 2008 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24), 2009 }; 2010 static const unsigned int eth_mdio_mux[] = { 2011 ETH_MDC_MARK, ETH_MDIO_MARK, 2012 }; 2013 static const unsigned int eth_rmii_pins[] = { 2014 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ 2015 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19), 2016 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25), 2017 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23), 2018 }; 2019 static const unsigned int eth_rmii_mux[] = { 2020 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 2021 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, 2022 }; 2023 /* - HSCIF0 ----------------------------------------------------------------- */ 2024 static const unsigned int hscif0_data_pins[] = { 2025 /* RX, TX */ 2026 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), 2027 }; 2028 static const unsigned int hscif0_data_mux[] = { 2029 HRX0_MARK, HTX0_MARK, 2030 }; 2031 static const unsigned int hscif0_clk_pins[] = { 2032 /* SCK */ 2033 RCAR_GP_PIN(5, 7), 2034 }; 2035 static const unsigned int hscif0_clk_mux[] = { 2036 HSCK0_MARK, 2037 }; 2038 static const unsigned int hscif0_ctrl_pins[] = { 2039 /* RTS, CTS */ 2040 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2041 }; 2042 static const unsigned int hscif0_ctrl_mux[] = { 2043 HRTS0_N_MARK, HCTS0_N_MARK, 2044 }; 2045 static const unsigned int hscif0_data_b_pins[] = { 2046 /* RX, TX */ 2047 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12), 2048 }; 2049 static const unsigned int hscif0_data_b_mux[] = { 2050 HRX0_B_MARK, HTX0_B_MARK, 2051 }; 2052 static const unsigned int hscif0_ctrl_b_pins[] = { 2053 /* RTS, CTS */ 2054 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), 2055 }; 2056 static const unsigned int hscif0_ctrl_b_mux[] = { 2057 HRTS0_N_B_MARK, HCTS0_N_B_MARK, 2058 }; 2059 static const unsigned int hscif0_data_c_pins[] = { 2060 /* RX, TX */ 2061 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), 2062 }; 2063 static const unsigned int hscif0_data_c_mux[] = { 2064 HRX0_C_MARK, HTX0_C_MARK, 2065 }; 2066 static const unsigned int hscif0_ctrl_c_pins[] = { 2067 /* RTS, CTS */ 2068 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7), 2069 }; 2070 static const unsigned int hscif0_ctrl_c_mux[] = { 2071 HRTS0_N_C_MARK, HCTS0_N_C_MARK, 2072 }; 2073 static const unsigned int hscif0_data_d_pins[] = { 2074 /* RX, TX */ 2075 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2076 }; 2077 static const unsigned int hscif0_data_d_mux[] = { 2078 HRX0_D_MARK, HTX0_D_MARK, 2079 }; 2080 static const unsigned int hscif0_ctrl_d_pins[] = { 2081 /* RTS, CTS */ 2082 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), 2083 }; 2084 static const unsigned int hscif0_ctrl_d_mux[] = { 2085 HRTS0_N_D_MARK, HCTS0_N_D_MARK, 2086 }; 2087 static const unsigned int hscif0_data_e_pins[] = { 2088 /* RX, TX */ 2089 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 2090 }; 2091 static const unsigned int hscif0_data_e_mux[] = { 2092 HRX0_E_MARK, HTX0_E_MARK, 2093 }; 2094 static const unsigned int hscif0_ctrl_e_pins[] = { 2095 /* RTS, CTS */ 2096 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23), 2097 }; 2098 static const unsigned int hscif0_ctrl_e_mux[] = { 2099 HRTS0_N_E_MARK, HCTS0_N_E_MARK, 2100 }; 2101 static const unsigned int hscif0_data_f_pins[] = { 2102 /* RX, TX */ 2103 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25), 2104 }; 2105 static const unsigned int hscif0_data_f_mux[] = { 2106 HRX0_F_MARK, HTX0_F_MARK, 2107 }; 2108 static const unsigned int hscif0_ctrl_f_pins[] = { 2109 /* RTS, CTS */ 2110 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24), 2111 }; 2112 static const unsigned int hscif0_ctrl_f_mux[] = { 2113 HRTS0_N_F_MARK, HCTS0_N_F_MARK, 2114 }; 2115 /* - HSCIF1 ----------------------------------------------------------------- */ 2116 static const unsigned int hscif1_data_pins[] = { 2117 /* RX, TX */ 2118 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2119 }; 2120 static const unsigned int hscif1_data_mux[] = { 2121 HRX1_MARK, HTX1_MARK, 2122 }; 2123 static const unsigned int hscif1_clk_pins[] = { 2124 /* SCK */ 2125 RCAR_GP_PIN(4, 27), 2126 }; 2127 static const unsigned int hscif1_clk_mux[] = { 2128 HSCK1_MARK, 2129 }; 2130 static const unsigned int hscif1_ctrl_pins[] = { 2131 /* RTS, CTS */ 2132 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2133 }; 2134 static const unsigned int hscif1_ctrl_mux[] = { 2135 HRTS1_N_MARK, HCTS1_N_MARK, 2136 }; 2137 static const unsigned int hscif1_data_b_pins[] = { 2138 /* RX, TX */ 2139 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18), 2140 }; 2141 static const unsigned int hscif1_data_b_mux[] = { 2142 HRX1_B_MARK, HTX1_B_MARK, 2143 }; 2144 static const unsigned int hscif1_clk_b_pins[] = { 2145 /* SCK */ 2146 RCAR_GP_PIN(1, 28), 2147 }; 2148 static const unsigned int hscif1_clk_b_mux[] = { 2149 HSCK1_B_MARK, 2150 }; 2151 static const unsigned int hscif1_ctrl_b_pins[] = { 2152 /* RTS, CTS */ 2153 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2154 }; 2155 static const unsigned int hscif1_ctrl_b_mux[] = { 2156 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2157 }; 2158 /* - I2C0 ------------------------------------------------------------------- */ 2159 static const unsigned int i2c0_pins[] = { 2160 /* SCL, SDA */ 2161 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15), 2162 }; 2163 static const unsigned int i2c0_mux[] = { 2164 I2C0_SCL_MARK, I2C0_SDA_MARK, 2165 }; 2166 /* - I2C1 ------------------------------------------------------------------- */ 2167 static const unsigned int i2c1_pins[] = { 2168 /* SCL, SDA */ 2169 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 2170 }; 2171 static const unsigned int i2c1_mux[] = { 2172 I2C1_SCL_MARK, I2C1_SDA_MARK, 2173 }; 2174 static const unsigned int i2c1_b_pins[] = { 2175 /* SCL, SDA */ 2176 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2177 }; 2178 static const unsigned int i2c1_b_mux[] = { 2179 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, 2180 }; 2181 static const unsigned int i2c1_c_pins[] = { 2182 /* SCL, SDA */ 2183 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 2184 }; 2185 static const unsigned int i2c1_c_mux[] = { 2186 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, 2187 }; 2188 /* - I2C2 ------------------------------------------------------------------- */ 2189 static const unsigned int i2c2_pins[] = { 2190 /* SCL, SDA */ 2191 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2192 }; 2193 static const unsigned int i2c2_mux[] = { 2194 I2C2_SCL_MARK, I2C2_SDA_MARK, 2195 }; 2196 static const unsigned int i2c2_b_pins[] = { 2197 /* SCL, SDA */ 2198 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 2199 }; 2200 static const unsigned int i2c2_b_mux[] = { 2201 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, 2202 }; 2203 static const unsigned int i2c2_c_pins[] = { 2204 /* SCL, SDA */ 2205 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 2206 }; 2207 static const unsigned int i2c2_c_mux[] = { 2208 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, 2209 }; 2210 static const unsigned int i2c2_d_pins[] = { 2211 /* SCL, SDA */ 2212 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2213 }; 2214 static const unsigned int i2c2_d_mux[] = { 2215 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, 2216 }; 2217 static const unsigned int i2c2_e_pins[] = { 2218 /* SCL, SDA */ 2219 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 2220 }; 2221 static const unsigned int i2c2_e_mux[] = { 2222 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK, 2223 }; 2224 /* - I2C3 ------------------------------------------------------------------- */ 2225 static const unsigned int i2c3_pins[] = { 2226 /* SCL, SDA */ 2227 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15), 2228 }; 2229 static const unsigned int i2c3_mux[] = { 2230 I2C3_SCL_MARK, I2C3_SDA_MARK, 2231 }; 2232 /* - IIC0 (I2C4) ------------------------------------------------------------ */ 2233 static const unsigned int iic0_pins[] = { 2234 /* SCL, SDA */ 2235 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15), 2236 }; 2237 static const unsigned int iic0_mux[] = { 2238 IIC0_SCL_MARK, IIC0_SDA_MARK, 2239 }; 2240 /* - IIC1 (I2C5) ------------------------------------------------------------ */ 2241 static const unsigned int iic1_pins[] = { 2242 /* SCL, SDA */ 2243 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 2244 }; 2245 static const unsigned int iic1_mux[] = { 2246 IIC1_SCL_MARK, IIC1_SDA_MARK, 2247 }; 2248 static const unsigned int iic1_b_pins[] = { 2249 /* SCL, SDA */ 2250 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2251 }; 2252 static const unsigned int iic1_b_mux[] = { 2253 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK, 2254 }; 2255 static const unsigned int iic1_c_pins[] = { 2256 /* SCL, SDA */ 2257 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 2258 }; 2259 static const unsigned int iic1_c_mux[] = { 2260 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK, 2261 }; 2262 /* - IIC2 (I2C6) ------------------------------------------------------------ */ 2263 static const unsigned int iic2_pins[] = { 2264 /* SCL, SDA */ 2265 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2266 }; 2267 static const unsigned int iic2_mux[] = { 2268 IIC2_SCL_MARK, IIC2_SDA_MARK, 2269 }; 2270 static const unsigned int iic2_b_pins[] = { 2271 /* SCL, SDA */ 2272 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 2273 }; 2274 static const unsigned int iic2_b_mux[] = { 2275 IIC2_SCL_B_MARK, IIC2_SDA_B_MARK, 2276 }; 2277 static const unsigned int iic2_c_pins[] = { 2278 /* SCL, SDA */ 2279 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 2280 }; 2281 static const unsigned int iic2_c_mux[] = { 2282 IIC2_SCL_C_MARK, IIC2_SDA_C_MARK, 2283 }; 2284 static const unsigned int iic2_d_pins[] = { 2285 /* SCL, SDA */ 2286 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2287 }; 2288 static const unsigned int iic2_d_mux[] = { 2289 IIC2_SCL_D_MARK, IIC2_SDA_D_MARK, 2290 }; 2291 static const unsigned int iic2_e_pins[] = { 2292 /* SCL, SDA */ 2293 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 2294 }; 2295 static const unsigned int iic2_e_mux[] = { 2296 IIC2_SCL_E_MARK, IIC2_SDA_E_MARK, 2297 }; 2298 /* - IIC3 (I2C7) ------------------------------------------------------------ */ 2299 static const unsigned int iic3_pins[] = { 2300 /* SCL, SDA */ 2301 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15), 2302 }; 2303 static const unsigned int iic3_mux[] = { 2304 IIC3_SCL_MARK, IIC3_SDA_MARK, 2305 }; 2306 /* - INTC ------------------------------------------------------------------- */ 2307 static const unsigned int intc_irq0_pins[] = { 2308 /* IRQ */ 2309 RCAR_GP_PIN(1, 25), 2310 }; 2311 static const unsigned int intc_irq0_mux[] = { 2312 IRQ0_MARK, 2313 }; 2314 static const unsigned int intc_irq1_pins[] = { 2315 /* IRQ */ 2316 RCAR_GP_PIN(1, 27), 2317 }; 2318 static const unsigned int intc_irq1_mux[] = { 2319 IRQ1_MARK, 2320 }; 2321 static const unsigned int intc_irq2_pins[] = { 2322 /* IRQ */ 2323 RCAR_GP_PIN(1, 29), 2324 }; 2325 static const unsigned int intc_irq2_mux[] = { 2326 IRQ2_MARK, 2327 }; 2328 static const unsigned int intc_irq3_pins[] = { 2329 /* IRQ */ 2330 RCAR_GP_PIN(1, 23), 2331 }; 2332 static const unsigned int intc_irq3_mux[] = { 2333 IRQ3_MARK, 2334 }; 2335 /* - MLB+ ------------------------------------------------------------------- */ 2336 static const unsigned int mlb_3pin_pins[] = { 2337 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 2338 }; 2339 static const unsigned int mlb_3pin_mux[] = { 2340 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, 2341 }; 2342 /* - MMCIF0 ----------------------------------------------------------------- */ 2343 static const unsigned int mmc0_data1_pins[] = { 2344 /* D[0] */ 2345 RCAR_GP_PIN(3, 18), 2346 }; 2347 static const unsigned int mmc0_data1_mux[] = { 2348 MMC0_D0_MARK, 2349 }; 2350 static const unsigned int mmc0_data4_pins[] = { 2351 /* D[0:3] */ 2352 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2353 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2354 }; 2355 static const unsigned int mmc0_data4_mux[] = { 2356 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 2357 }; 2358 static const unsigned int mmc0_data8_pins[] = { 2359 /* D[0:7] */ 2360 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2361 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2362 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), 2363 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2364 }; 2365 static const unsigned int mmc0_data8_mux[] = { 2366 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 2367 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, 2368 }; 2369 static const unsigned int mmc0_ctrl_pins[] = { 2370 /* CLK, CMD */ 2371 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), 2372 }; 2373 static const unsigned int mmc0_ctrl_mux[] = { 2374 MMC0_CLK_MARK, MMC0_CMD_MARK, 2375 }; 2376 /* - MMCIF1 ----------------------------------------------------------------- */ 2377 static const unsigned int mmc1_data1_pins[] = { 2378 /* D[0] */ 2379 RCAR_GP_PIN(3, 26), 2380 }; 2381 static const unsigned int mmc1_data1_mux[] = { 2382 MMC1_D0_MARK, 2383 }; 2384 static const unsigned int mmc1_data4_pins[] = { 2385 /* D[0:3] */ 2386 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), 2387 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 2388 }; 2389 static const unsigned int mmc1_data4_mux[] = { 2390 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 2391 }; 2392 static const unsigned int mmc1_data8_pins[] = { 2393 /* D[0:7] */ 2394 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), 2395 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 2396 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), 2397 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2398 }; 2399 static const unsigned int mmc1_data8_mux[] = { 2400 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 2401 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, 2402 }; 2403 static const unsigned int mmc1_ctrl_pins[] = { 2404 /* CLK, CMD */ 2405 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), 2406 }; 2407 static const unsigned int mmc1_ctrl_mux[] = { 2408 MMC1_CLK_MARK, MMC1_CMD_MARK, 2409 }; 2410 /* - MSIOF0 ----------------------------------------------------------------- */ 2411 static const unsigned int msiof0_clk_pins[] = { 2412 /* SCK */ 2413 RCAR_GP_PIN(5, 12), 2414 }; 2415 static const unsigned int msiof0_clk_mux[] = { 2416 MSIOF0_SCK_MARK, 2417 }; 2418 static const unsigned int msiof0_sync_pins[] = { 2419 /* SYNC */ 2420 RCAR_GP_PIN(5, 13), 2421 }; 2422 static const unsigned int msiof0_sync_mux[] = { 2423 MSIOF0_SYNC_MARK, 2424 }; 2425 static const unsigned int msiof0_ss1_pins[] = { 2426 /* SS1 */ 2427 RCAR_GP_PIN(5, 14), 2428 }; 2429 static const unsigned int msiof0_ss1_mux[] = { 2430 MSIOF0_SS1_MARK, 2431 }; 2432 static const unsigned int msiof0_ss2_pins[] = { 2433 /* SS2 */ 2434 RCAR_GP_PIN(5, 16), 2435 }; 2436 static const unsigned int msiof0_ss2_mux[] = { 2437 MSIOF0_SS2_MARK, 2438 }; 2439 static const unsigned int msiof0_rx_pins[] = { 2440 /* RXD */ 2441 RCAR_GP_PIN(5, 17), 2442 }; 2443 static const unsigned int msiof0_rx_mux[] = { 2444 MSIOF0_RXD_MARK, 2445 }; 2446 static const unsigned int msiof0_tx_pins[] = { 2447 /* TXD */ 2448 RCAR_GP_PIN(5, 15), 2449 }; 2450 static const unsigned int msiof0_tx_mux[] = { 2451 MSIOF0_TXD_MARK, 2452 }; 2453 2454 static const unsigned int msiof0_clk_b_pins[] = { 2455 /* SCK */ 2456 RCAR_GP_PIN(1, 23), 2457 }; 2458 static const unsigned int msiof0_clk_b_mux[] = { 2459 MSIOF0_SCK_B_MARK, 2460 }; 2461 static const unsigned int msiof0_ss1_b_pins[] = { 2462 /* SS1 */ 2463 RCAR_GP_PIN(1, 12), 2464 }; 2465 static const unsigned int msiof0_ss1_b_mux[] = { 2466 MSIOF0_SS1_B_MARK, 2467 }; 2468 static const unsigned int msiof0_ss2_b_pins[] = { 2469 /* SS2 */ 2470 RCAR_GP_PIN(1, 10), 2471 }; 2472 static const unsigned int msiof0_ss2_b_mux[] = { 2473 MSIOF0_SS2_B_MARK, 2474 }; 2475 static const unsigned int msiof0_rx_b_pins[] = { 2476 /* RXD */ 2477 RCAR_GP_PIN(1, 29), 2478 }; 2479 static const unsigned int msiof0_rx_b_mux[] = { 2480 MSIOF0_RXD_B_MARK, 2481 }; 2482 static const unsigned int msiof0_tx_b_pins[] = { 2483 /* TXD */ 2484 RCAR_GP_PIN(1, 28), 2485 }; 2486 static const unsigned int msiof0_tx_b_mux[] = { 2487 MSIOF0_TXD_B_MARK, 2488 }; 2489 /* - MSIOF1 ----------------------------------------------------------------- */ 2490 static const unsigned int msiof1_clk_pins[] = { 2491 /* SCK */ 2492 RCAR_GP_PIN(4, 8), 2493 }; 2494 static const unsigned int msiof1_clk_mux[] = { 2495 MSIOF1_SCK_MARK, 2496 }; 2497 static const unsigned int msiof1_sync_pins[] = { 2498 /* SYNC */ 2499 RCAR_GP_PIN(4, 9), 2500 }; 2501 static const unsigned int msiof1_sync_mux[] = { 2502 MSIOF1_SYNC_MARK, 2503 }; 2504 static const unsigned int msiof1_ss1_pins[] = { 2505 /* SS1 */ 2506 RCAR_GP_PIN(4, 10), 2507 }; 2508 static const unsigned int msiof1_ss1_mux[] = { 2509 MSIOF1_SS1_MARK, 2510 }; 2511 static const unsigned int msiof1_ss2_pins[] = { 2512 /* SS2 */ 2513 RCAR_GP_PIN(4, 11), 2514 }; 2515 static const unsigned int msiof1_ss2_mux[] = { 2516 MSIOF1_SS2_MARK, 2517 }; 2518 static const unsigned int msiof1_rx_pins[] = { 2519 /* RXD */ 2520 RCAR_GP_PIN(4, 13), 2521 }; 2522 static const unsigned int msiof1_rx_mux[] = { 2523 MSIOF1_RXD_MARK, 2524 }; 2525 static const unsigned int msiof1_tx_pins[] = { 2526 /* TXD */ 2527 RCAR_GP_PIN(4, 12), 2528 }; 2529 static const unsigned int msiof1_tx_mux[] = { 2530 MSIOF1_TXD_MARK, 2531 }; 2532 2533 static const unsigned int msiof1_clk_b_pins[] = { 2534 /* SCK */ 2535 RCAR_GP_PIN(1, 16), 2536 }; 2537 static const unsigned int msiof1_clk_b_mux[] = { 2538 MSIOF1_SCK_B_MARK, 2539 }; 2540 static const unsigned int msiof1_ss1_b_pins[] = { 2541 /* SS1 */ 2542 RCAR_GP_PIN(0, 18), 2543 }; 2544 static const unsigned int msiof1_ss1_b_mux[] = { 2545 MSIOF1_SS1_B_MARK, 2546 }; 2547 static const unsigned int msiof1_ss2_b_pins[] = { 2548 /* SS2 */ 2549 RCAR_GP_PIN(0, 19), 2550 }; 2551 static const unsigned int msiof1_ss2_b_mux[] = { 2552 MSIOF1_SS2_B_MARK, 2553 }; 2554 static const unsigned int msiof1_rx_b_pins[] = { 2555 /* RXD */ 2556 RCAR_GP_PIN(1, 17), 2557 }; 2558 static const unsigned int msiof1_rx_b_mux[] = { 2559 MSIOF1_RXD_B_MARK, 2560 }; 2561 static const unsigned int msiof1_tx_b_pins[] = { 2562 /* TXD */ 2563 RCAR_GP_PIN(0, 20), 2564 }; 2565 static const unsigned int msiof1_tx_b_mux[] = { 2566 MSIOF1_TXD_B_MARK, 2567 }; 2568 /* - MSIOF2 ----------------------------------------------------------------- */ 2569 static const unsigned int msiof2_clk_pins[] = { 2570 /* SCK */ 2571 RCAR_GP_PIN(0, 27), 2572 }; 2573 static const unsigned int msiof2_clk_mux[] = { 2574 MSIOF2_SCK_MARK, 2575 }; 2576 static const unsigned int msiof2_sync_pins[] = { 2577 /* SYNC */ 2578 RCAR_GP_PIN(0, 26), 2579 }; 2580 static const unsigned int msiof2_sync_mux[] = { 2581 MSIOF2_SYNC_MARK, 2582 }; 2583 static const unsigned int msiof2_ss1_pins[] = { 2584 /* SS1 */ 2585 RCAR_GP_PIN(0, 30), 2586 }; 2587 static const unsigned int msiof2_ss1_mux[] = { 2588 MSIOF2_SS1_MARK, 2589 }; 2590 static const unsigned int msiof2_ss2_pins[] = { 2591 /* SS2 */ 2592 RCAR_GP_PIN(0, 31), 2593 }; 2594 static const unsigned int msiof2_ss2_mux[] = { 2595 MSIOF2_SS2_MARK, 2596 }; 2597 static const unsigned int msiof2_rx_pins[] = { 2598 /* RXD */ 2599 RCAR_GP_PIN(0, 29), 2600 }; 2601 static const unsigned int msiof2_rx_mux[] = { 2602 MSIOF2_RXD_MARK, 2603 }; 2604 static const unsigned int msiof2_tx_pins[] = { 2605 /* TXD */ 2606 RCAR_GP_PIN(0, 28), 2607 }; 2608 static const unsigned int msiof2_tx_mux[] = { 2609 MSIOF2_TXD_MARK, 2610 }; 2611 /* - MSIOF3 ----------------------------------------------------------------- */ 2612 static const unsigned int msiof3_clk_pins[] = { 2613 /* SCK */ 2614 RCAR_GP_PIN(5, 4), 2615 }; 2616 static const unsigned int msiof3_clk_mux[] = { 2617 MSIOF3_SCK_MARK, 2618 }; 2619 static const unsigned int msiof3_sync_pins[] = { 2620 /* SYNC */ 2621 RCAR_GP_PIN(4, 30), 2622 }; 2623 static const unsigned int msiof3_sync_mux[] = { 2624 MSIOF3_SYNC_MARK, 2625 }; 2626 static const unsigned int msiof3_ss1_pins[] = { 2627 /* SS1 */ 2628 RCAR_GP_PIN(4, 31), 2629 }; 2630 static const unsigned int msiof3_ss1_mux[] = { 2631 MSIOF3_SS1_MARK, 2632 }; 2633 static const unsigned int msiof3_ss2_pins[] = { 2634 /* SS2 */ 2635 RCAR_GP_PIN(4, 27), 2636 }; 2637 static const unsigned int msiof3_ss2_mux[] = { 2638 MSIOF3_SS2_MARK, 2639 }; 2640 static const unsigned int msiof3_rx_pins[] = { 2641 /* RXD */ 2642 RCAR_GP_PIN(5, 2), 2643 }; 2644 static const unsigned int msiof3_rx_mux[] = { 2645 MSIOF3_RXD_MARK, 2646 }; 2647 static const unsigned int msiof3_tx_pins[] = { 2648 /* TXD */ 2649 RCAR_GP_PIN(5, 3), 2650 }; 2651 static const unsigned int msiof3_tx_mux[] = { 2652 MSIOF3_TXD_MARK, 2653 }; 2654 2655 static const unsigned int msiof3_clk_b_pins[] = { 2656 /* SCK */ 2657 RCAR_GP_PIN(0, 0), 2658 }; 2659 static const unsigned int msiof3_clk_b_mux[] = { 2660 MSIOF3_SCK_B_MARK, 2661 }; 2662 static const unsigned int msiof3_sync_b_pins[] = { 2663 /* SYNC */ 2664 RCAR_GP_PIN(0, 1), 2665 }; 2666 static const unsigned int msiof3_sync_b_mux[] = { 2667 MSIOF3_SYNC_B_MARK, 2668 }; 2669 static const unsigned int msiof3_rx_b_pins[] = { 2670 /* RXD */ 2671 RCAR_GP_PIN(0, 2), 2672 }; 2673 static const unsigned int msiof3_rx_b_mux[] = { 2674 MSIOF3_RXD_B_MARK, 2675 }; 2676 static const unsigned int msiof3_tx_b_pins[] = { 2677 /* TXD */ 2678 RCAR_GP_PIN(0, 3), 2679 }; 2680 static const unsigned int msiof3_tx_b_mux[] = { 2681 MSIOF3_TXD_B_MARK, 2682 }; 2683 /* - PWM -------------------------------------------------------------------- */ 2684 static const unsigned int pwm0_pins[] = { 2685 RCAR_GP_PIN(5, 29), 2686 }; 2687 static const unsigned int pwm0_mux[] = { 2688 PWM0_MARK, 2689 }; 2690 static const unsigned int pwm0_b_pins[] = { 2691 RCAR_GP_PIN(4, 30), 2692 }; 2693 static const unsigned int pwm0_b_mux[] = { 2694 PWM0_B_MARK, 2695 }; 2696 static const unsigned int pwm1_pins[] = { 2697 RCAR_GP_PIN(5, 30), 2698 }; 2699 static const unsigned int pwm1_mux[] = { 2700 PWM1_MARK, 2701 }; 2702 static const unsigned int pwm1_b_pins[] = { 2703 RCAR_GP_PIN(4, 31), 2704 }; 2705 static const unsigned int pwm1_b_mux[] = { 2706 PWM1_B_MARK, 2707 }; 2708 static const unsigned int pwm2_pins[] = { 2709 RCAR_GP_PIN(5, 31), 2710 }; 2711 static const unsigned int pwm2_mux[] = { 2712 PWM2_MARK, 2713 }; 2714 static const unsigned int pwm3_pins[] = { 2715 RCAR_GP_PIN(0, 16), 2716 }; 2717 static const unsigned int pwm3_mux[] = { 2718 PWM3_MARK, 2719 }; 2720 static const unsigned int pwm4_pins[] = { 2721 RCAR_GP_PIN(0, 17), 2722 }; 2723 static const unsigned int pwm4_mux[] = { 2724 PWM4_MARK, 2725 }; 2726 static const unsigned int pwm5_pins[] = { 2727 RCAR_GP_PIN(0, 18), 2728 }; 2729 static const unsigned int pwm5_mux[] = { 2730 PWM5_MARK, 2731 }; 2732 static const unsigned int pwm6_pins[] = { 2733 RCAR_GP_PIN(0, 19), 2734 }; 2735 static const unsigned int pwm6_mux[] = { 2736 PWM6_MARK, 2737 }; 2738 /* - QSPI ------------------------------------------------------------------- */ 2739 static const unsigned int qspi_ctrl_pins[] = { 2740 /* SPCLK, SSL */ 2741 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), 2742 }; 2743 static const unsigned int qspi_ctrl_mux[] = { 2744 SPCLK_MARK, SSL_MARK, 2745 }; 2746 static const unsigned int qspi_data2_pins[] = { 2747 /* MOSI_IO0, MISO_IO1 */ 2748 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 2749 }; 2750 static const unsigned int qspi_data2_mux[] = { 2751 MOSI_IO0_MARK, MISO_IO1_MARK, 2752 }; 2753 static const unsigned int qspi_data4_pins[] = { 2754 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2755 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 2756 RCAR_GP_PIN(1, 8), 2757 }; 2758 static const unsigned int qspi_data4_mux[] = { 2759 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, 2760 }; 2761 /* - SCIF0 ------------------------------------------------------------------ */ 2762 static const unsigned int scif0_data_pins[] = { 2763 /* RX, TX */ 2764 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2765 }; 2766 static const unsigned int scif0_data_mux[] = { 2767 RX0_MARK, TX0_MARK, 2768 }; 2769 static const unsigned int scif0_clk_pins[] = { 2770 /* SCK */ 2771 RCAR_GP_PIN(4, 27), 2772 }; 2773 static const unsigned int scif0_clk_mux[] = { 2774 SCK0_MARK, 2775 }; 2776 static const unsigned int scif0_ctrl_pins[] = { 2777 /* RTS, CTS */ 2778 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2779 }; 2780 static const unsigned int scif0_ctrl_mux[] = { 2781 RTS0_N_MARK, CTS0_N_MARK, 2782 }; 2783 static const unsigned int scif0_data_b_pins[] = { 2784 /* RX, TX */ 2785 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 2786 }; 2787 static const unsigned int scif0_data_b_mux[] = { 2788 RX0_B_MARK, TX0_B_MARK, 2789 }; 2790 /* - SCIF1 ------------------------------------------------------------------ */ 2791 static const unsigned int scif1_data_pins[] = { 2792 /* RX, TX */ 2793 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), 2794 }; 2795 static const unsigned int scif1_data_mux[] = { 2796 RX1_MARK, TX1_MARK, 2797 }; 2798 static const unsigned int scif1_clk_pins[] = { 2799 /* SCK */ 2800 RCAR_GP_PIN(4, 20), 2801 }; 2802 static const unsigned int scif1_clk_mux[] = { 2803 SCK1_MARK, 2804 }; 2805 static const unsigned int scif1_ctrl_pins[] = { 2806 /* RTS, CTS */ 2807 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), 2808 }; 2809 static const unsigned int scif1_ctrl_mux[] = { 2810 RTS1_N_MARK, CTS1_N_MARK, 2811 }; 2812 static const unsigned int scif1_data_b_pins[] = { 2813 /* RX, TX */ 2814 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2815 }; 2816 static const unsigned int scif1_data_b_mux[] = { 2817 RX1_B_MARK, TX1_B_MARK, 2818 }; 2819 static const unsigned int scif1_data_c_pins[] = { 2820 /* RX, TX */ 2821 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 2822 }; 2823 static const unsigned int scif1_data_c_mux[] = { 2824 RX1_C_MARK, TX1_C_MARK, 2825 }; 2826 static const unsigned int scif1_data_d_pins[] = { 2827 /* RX, TX */ 2828 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2829 }; 2830 static const unsigned int scif1_data_d_mux[] = { 2831 RX1_D_MARK, TX1_D_MARK, 2832 }; 2833 static const unsigned int scif1_clk_d_pins[] = { 2834 /* SCK */ 2835 RCAR_GP_PIN(3, 17), 2836 }; 2837 static const unsigned int scif1_clk_d_mux[] = { 2838 SCK1_D_MARK, 2839 }; 2840 static const unsigned int scif1_data_e_pins[] = { 2841 /* RX, TX */ 2842 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 2843 }; 2844 static const unsigned int scif1_data_e_mux[] = { 2845 RX1_E_MARK, TX1_E_MARK, 2846 }; 2847 static const unsigned int scif1_clk_e_pins[] = { 2848 /* SCK */ 2849 RCAR_GP_PIN(2, 20), 2850 }; 2851 static const unsigned int scif1_clk_e_mux[] = { 2852 SCK1_E_MARK, 2853 }; 2854 /* - SCIF2 ------------------------------------------------------------------ */ 2855 static const unsigned int scif2_data_pins[] = { 2856 /* RX, TX */ 2857 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), 2858 }; 2859 static const unsigned int scif2_data_mux[] = { 2860 RX2_MARK, TX2_MARK, 2861 }; 2862 static const unsigned int scif2_clk_pins[] = { 2863 /* SCK */ 2864 RCAR_GP_PIN(5, 4), 2865 }; 2866 static const unsigned int scif2_clk_mux[] = { 2867 SCK2_MARK, 2868 }; 2869 static const unsigned int scif2_data_b_pins[] = { 2870 /* RX, TX */ 2871 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 2872 }; 2873 static const unsigned int scif2_data_b_mux[] = { 2874 RX2_B_MARK, TX2_B_MARK, 2875 }; 2876 /* - SCIFA0 ----------------------------------------------------------------- */ 2877 static const unsigned int scifa0_data_pins[] = { 2878 /* RXD, TXD */ 2879 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2880 }; 2881 static const unsigned int scifa0_data_mux[] = { 2882 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, 2883 }; 2884 static const unsigned int scifa0_clk_pins[] = { 2885 /* SCK */ 2886 RCAR_GP_PIN(4, 27), 2887 }; 2888 static const unsigned int scifa0_clk_mux[] = { 2889 SCIFA0_SCK_MARK, 2890 }; 2891 static const unsigned int scifa0_ctrl_pins[] = { 2892 /* RTS, CTS */ 2893 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2894 }; 2895 static const unsigned int scifa0_ctrl_mux[] = { 2896 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK, 2897 }; 2898 static const unsigned int scifa0_data_b_pins[] = { 2899 /* RXD, TXD */ 2900 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), 2901 }; 2902 static const unsigned int scifa0_data_b_mux[] = { 2903 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK 2904 }; 2905 static const unsigned int scifa0_clk_b_pins[] = { 2906 /* SCK */ 2907 RCAR_GP_PIN(1, 19), 2908 }; 2909 static const unsigned int scifa0_clk_b_mux[] = { 2910 SCIFA0_SCK_B_MARK, 2911 }; 2912 static const unsigned int scifa0_ctrl_b_pins[] = { 2913 /* RTS, CTS */ 2914 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), 2915 }; 2916 static const unsigned int scifa0_ctrl_b_mux[] = { 2917 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK, 2918 }; 2919 /* - SCIFA1 ----------------------------------------------------------------- */ 2920 static const unsigned int scifa1_data_pins[] = { 2921 /* RXD, TXD */ 2922 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), 2923 }; 2924 static const unsigned int scifa1_data_mux[] = { 2925 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, 2926 }; 2927 static const unsigned int scifa1_clk_pins[] = { 2928 /* SCK */ 2929 RCAR_GP_PIN(4, 20), 2930 }; 2931 static const unsigned int scifa1_clk_mux[] = { 2932 SCIFA1_SCK_MARK, 2933 }; 2934 static const unsigned int scifa1_ctrl_pins[] = { 2935 /* RTS, CTS */ 2936 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), 2937 }; 2938 static const unsigned int scifa1_ctrl_mux[] = { 2939 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK, 2940 }; 2941 static const unsigned int scifa1_data_b_pins[] = { 2942 /* RXD, TXD */ 2943 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21), 2944 }; 2945 static const unsigned int scifa1_data_b_mux[] = { 2946 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, 2947 }; 2948 static const unsigned int scifa1_clk_b_pins[] = { 2949 /* SCK */ 2950 RCAR_GP_PIN(0, 23), 2951 }; 2952 static const unsigned int scifa1_clk_b_mux[] = { 2953 SCIFA1_SCK_B_MARK, 2954 }; 2955 static const unsigned int scifa1_ctrl_b_pins[] = { 2956 /* RTS, CTS */ 2957 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25), 2958 }; 2959 static const unsigned int scifa1_ctrl_b_mux[] = { 2960 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK, 2961 }; 2962 static const unsigned int scifa1_data_c_pins[] = { 2963 /* RXD, TXD */ 2964 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 2965 }; 2966 static const unsigned int scifa1_data_c_mux[] = { 2967 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, 2968 }; 2969 static const unsigned int scifa1_clk_c_pins[] = { 2970 /* SCK */ 2971 RCAR_GP_PIN(0, 8), 2972 }; 2973 static const unsigned int scifa1_clk_c_mux[] = { 2974 SCIFA1_SCK_C_MARK, 2975 }; 2976 static const unsigned int scifa1_ctrl_c_pins[] = { 2977 /* RTS, CTS */ 2978 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), 2979 }; 2980 static const unsigned int scifa1_ctrl_c_mux[] = { 2981 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK, 2982 }; 2983 static const unsigned int scifa1_data_d_pins[] = { 2984 /* RXD, TXD */ 2985 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 2986 }; 2987 static const unsigned int scifa1_data_d_mux[] = { 2988 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK, 2989 }; 2990 static const unsigned int scifa1_clk_d_pins[] = { 2991 /* SCK */ 2992 RCAR_GP_PIN(2, 10), 2993 }; 2994 static const unsigned int scifa1_clk_d_mux[] = { 2995 SCIFA1_SCK_D_MARK, 2996 }; 2997 static const unsigned int scifa1_ctrl_d_pins[] = { 2998 /* RTS, CTS */ 2999 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3000 }; 3001 static const unsigned int scifa1_ctrl_d_mux[] = { 3002 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK, 3003 }; 3004 /* - SCIFA2 ----------------------------------------------------------------- */ 3005 static const unsigned int scifa2_data_pins[] = { 3006 /* RXD, TXD */ 3007 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3008 }; 3009 static const unsigned int scifa2_data_mux[] = { 3010 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, 3011 }; 3012 static const unsigned int scifa2_clk_pins[] = { 3013 /* SCK */ 3014 RCAR_GP_PIN(5, 4), 3015 }; 3016 static const unsigned int scifa2_clk_mux[] = { 3017 SCIFA2_SCK_MARK, 3018 }; 3019 static const unsigned int scifa2_ctrl_pins[] = { 3020 /* RTS, CTS */ 3021 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), 3022 }; 3023 static const unsigned int scifa2_ctrl_mux[] = { 3024 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK, 3025 }; 3026 static const unsigned int scifa2_data_b_pins[] = { 3027 /* RXD, TXD */ 3028 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), 3029 }; 3030 static const unsigned int scifa2_data_b_mux[] = { 3031 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, 3032 }; 3033 static const unsigned int scifa2_data_c_pins[] = { 3034 /* RXD, TXD */ 3035 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), 3036 }; 3037 static const unsigned int scifa2_data_c_mux[] = { 3038 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK, 3039 }; 3040 static const unsigned int scifa2_clk_c_pins[] = { 3041 /* SCK */ 3042 RCAR_GP_PIN(5, 29), 3043 }; 3044 static const unsigned int scifa2_clk_c_mux[] = { 3045 SCIFA2_SCK_C_MARK, 3046 }; 3047 /* - SCIFB0 ----------------------------------------------------------------- */ 3048 static const unsigned int scifb0_data_pins[] = { 3049 /* RXD, TXD */ 3050 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3051 }; 3052 static const unsigned int scifb0_data_mux[] = { 3053 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, 3054 }; 3055 static const unsigned int scifb0_clk_pins[] = { 3056 /* SCK */ 3057 RCAR_GP_PIN(4, 8), 3058 }; 3059 static const unsigned int scifb0_clk_mux[] = { 3060 SCIFB0_SCK_MARK, 3061 }; 3062 static const unsigned int scifb0_ctrl_pins[] = { 3063 /* RTS, CTS */ 3064 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), 3065 }; 3066 static const unsigned int scifb0_ctrl_mux[] = { 3067 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, 3068 }; 3069 static const unsigned int scifb0_data_b_pins[] = { 3070 /* RXD, TXD */ 3071 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3072 }; 3073 static const unsigned int scifb0_data_b_mux[] = { 3074 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, 3075 }; 3076 static const unsigned int scifb0_clk_b_pins[] = { 3077 /* SCK */ 3078 RCAR_GP_PIN(3, 9), 3079 }; 3080 static const unsigned int scifb0_clk_b_mux[] = { 3081 SCIFB0_SCK_B_MARK, 3082 }; 3083 static const unsigned int scifb0_ctrl_b_pins[] = { 3084 /* RTS, CTS */ 3085 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 3086 }; 3087 static const unsigned int scifb0_ctrl_b_mux[] = { 3088 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, 3089 }; 3090 static const unsigned int scifb0_data_c_pins[] = { 3091 /* RXD, TXD */ 3092 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3093 }; 3094 static const unsigned int scifb0_data_c_mux[] = { 3095 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, 3096 }; 3097 /* - SCIFB1 ----------------------------------------------------------------- */ 3098 static const unsigned int scifb1_data_pins[] = { 3099 /* RXD, TXD */ 3100 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3101 }; 3102 static const unsigned int scifb1_data_mux[] = { 3103 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, 3104 }; 3105 static const unsigned int scifb1_clk_pins[] = { 3106 /* SCK */ 3107 RCAR_GP_PIN(4, 14), 3108 }; 3109 static const unsigned int scifb1_clk_mux[] = { 3110 SCIFB1_SCK_MARK, 3111 }; 3112 static const unsigned int scifb1_ctrl_pins[] = { 3113 /* RTS, CTS */ 3114 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), 3115 }; 3116 static const unsigned int scifb1_ctrl_mux[] = { 3117 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, 3118 }; 3119 static const unsigned int scifb1_data_b_pins[] = { 3120 /* RXD, TXD */ 3121 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3122 }; 3123 static const unsigned int scifb1_data_b_mux[] = { 3124 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, 3125 }; 3126 static const unsigned int scifb1_clk_b_pins[] = { 3127 /* SCK */ 3128 RCAR_GP_PIN(3, 1), 3129 }; 3130 static const unsigned int scifb1_clk_b_mux[] = { 3131 SCIFB1_SCK_B_MARK, 3132 }; 3133 static const unsigned int scifb1_ctrl_b_pins[] = { 3134 /* RTS, CTS */ 3135 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4), 3136 }; 3137 static const unsigned int scifb1_ctrl_b_mux[] = { 3138 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK, 3139 }; 3140 static const unsigned int scifb1_data_c_pins[] = { 3141 /* RXD, TXD */ 3142 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3143 }; 3144 static const unsigned int scifb1_data_c_mux[] = { 3145 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, 3146 }; 3147 static const unsigned int scifb1_data_d_pins[] = { 3148 /* RXD, TXD */ 3149 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 3150 }; 3151 static const unsigned int scifb1_data_d_mux[] = { 3152 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, 3153 }; 3154 static const unsigned int scifb1_data_e_pins[] = { 3155 /* RXD, TXD */ 3156 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 3157 }; 3158 static const unsigned int scifb1_data_e_mux[] = { 3159 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK, 3160 }; 3161 static const unsigned int scifb1_clk_e_pins[] = { 3162 /* SCK */ 3163 RCAR_GP_PIN(3, 17), 3164 }; 3165 static const unsigned int scifb1_clk_e_mux[] = { 3166 SCIFB1_SCK_E_MARK, 3167 }; 3168 static const unsigned int scifb1_data_f_pins[] = { 3169 /* RXD, TXD */ 3170 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3171 }; 3172 static const unsigned int scifb1_data_f_mux[] = { 3173 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK, 3174 }; 3175 static const unsigned int scifb1_data_g_pins[] = { 3176 /* RXD, TXD */ 3177 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 3178 }; 3179 static const unsigned int scifb1_data_g_mux[] = { 3180 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK, 3181 }; 3182 static const unsigned int scifb1_clk_g_pins[] = { 3183 /* SCK */ 3184 RCAR_GP_PIN(2, 20), 3185 }; 3186 static const unsigned int scifb1_clk_g_mux[] = { 3187 SCIFB1_SCK_G_MARK, 3188 }; 3189 /* - SCIFB2 ----------------------------------------------------------------- */ 3190 static const unsigned int scifb2_data_pins[] = { 3191 /* RXD, TXD */ 3192 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), 3193 }; 3194 static const unsigned int scifb2_data_mux[] = { 3195 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, 3196 }; 3197 static const unsigned int scifb2_clk_pins[] = { 3198 /* SCK */ 3199 RCAR_GP_PIN(4, 21), 3200 }; 3201 static const unsigned int scifb2_clk_mux[] = { 3202 SCIFB2_SCK_MARK, 3203 }; 3204 static const unsigned int scifb2_ctrl_pins[] = { 3205 /* RTS, CTS */ 3206 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), 3207 }; 3208 static const unsigned int scifb2_ctrl_mux[] = { 3209 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, 3210 }; 3211 static const unsigned int scifb2_data_b_pins[] = { 3212 /* RXD, TXD */ 3213 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30), 3214 }; 3215 static const unsigned int scifb2_data_b_mux[] = { 3216 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, 3217 }; 3218 static const unsigned int scifb2_clk_b_pins[] = { 3219 /* SCK */ 3220 RCAR_GP_PIN(0, 31), 3221 }; 3222 static const unsigned int scifb2_clk_b_mux[] = { 3223 SCIFB2_SCK_B_MARK, 3224 }; 3225 static const unsigned int scifb2_ctrl_b_pins[] = { 3226 /* RTS, CTS */ 3227 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27), 3228 }; 3229 static const unsigned int scifb2_ctrl_b_mux[] = { 3230 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, 3231 }; 3232 static const unsigned int scifb2_data_c_pins[] = { 3233 /* RXD, TXD */ 3234 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3235 }; 3236 static const unsigned int scifb2_data_c_mux[] = { 3237 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, 3238 }; 3239 /* - SDHI0 ------------------------------------------------------------------ */ 3240 static const unsigned int sdhi0_data1_pins[] = { 3241 /* D0 */ 3242 RCAR_GP_PIN(3, 2), 3243 }; 3244 static const unsigned int sdhi0_data1_mux[] = { 3245 SD0_DAT0_MARK, 3246 }; 3247 static const unsigned int sdhi0_data4_pins[] = { 3248 /* D[0:3] */ 3249 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3250 }; 3251 static const unsigned int sdhi0_data4_mux[] = { 3252 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, 3253 }; 3254 static const unsigned int sdhi0_ctrl_pins[] = { 3255 /* CLK, CMD */ 3256 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3257 }; 3258 static const unsigned int sdhi0_ctrl_mux[] = { 3259 SD0_CLK_MARK, SD0_CMD_MARK, 3260 }; 3261 static const unsigned int sdhi0_cd_pins[] = { 3262 /* CD */ 3263 RCAR_GP_PIN(3, 6), 3264 }; 3265 static const unsigned int sdhi0_cd_mux[] = { 3266 SD0_CD_MARK, 3267 }; 3268 static const unsigned int sdhi0_wp_pins[] = { 3269 /* WP */ 3270 RCAR_GP_PIN(3, 7), 3271 }; 3272 static const unsigned int sdhi0_wp_mux[] = { 3273 SD0_WP_MARK, 3274 }; 3275 /* - SDHI1 ------------------------------------------------------------------ */ 3276 static const unsigned int sdhi1_data1_pins[] = { 3277 /* D0 */ 3278 RCAR_GP_PIN(3, 10), 3279 }; 3280 static const unsigned int sdhi1_data1_mux[] = { 3281 SD1_DAT0_MARK, 3282 }; 3283 static const unsigned int sdhi1_data4_pins[] = { 3284 /* D[0:3] */ 3285 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 3286 }; 3287 static const unsigned int sdhi1_data4_mux[] = { 3288 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, 3289 }; 3290 static const unsigned int sdhi1_ctrl_pins[] = { 3291 /* CLK, CMD */ 3292 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3293 }; 3294 static const unsigned int sdhi1_ctrl_mux[] = { 3295 SD1_CLK_MARK, SD1_CMD_MARK, 3296 }; 3297 static const unsigned int sdhi1_cd_pins[] = { 3298 /* CD */ 3299 RCAR_GP_PIN(3, 14), 3300 }; 3301 static const unsigned int sdhi1_cd_mux[] = { 3302 SD1_CD_MARK, 3303 }; 3304 static const unsigned int sdhi1_wp_pins[] = { 3305 /* WP */ 3306 RCAR_GP_PIN(3, 15), 3307 }; 3308 static const unsigned int sdhi1_wp_mux[] = { 3309 SD1_WP_MARK, 3310 }; 3311 /* - SDHI2 ------------------------------------------------------------------ */ 3312 static const unsigned int sdhi2_data1_pins[] = { 3313 /* D0 */ 3314 RCAR_GP_PIN(3, 18), 3315 }; 3316 static const unsigned int sdhi2_data1_mux[] = { 3317 SD2_DAT0_MARK, 3318 }; 3319 static const unsigned int sdhi2_data4_pins[] = { 3320 /* D[0:3] */ 3321 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 3322 }; 3323 static const unsigned int sdhi2_data4_mux[] = { 3324 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, 3325 }; 3326 static const unsigned int sdhi2_ctrl_pins[] = { 3327 /* CLK, CMD */ 3328 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), 3329 }; 3330 static const unsigned int sdhi2_ctrl_mux[] = { 3331 SD2_CLK_MARK, SD2_CMD_MARK, 3332 }; 3333 static const unsigned int sdhi2_cd_pins[] = { 3334 /* CD */ 3335 RCAR_GP_PIN(3, 22), 3336 }; 3337 static const unsigned int sdhi2_cd_mux[] = { 3338 SD2_CD_MARK, 3339 }; 3340 static const unsigned int sdhi2_wp_pins[] = { 3341 /* WP */ 3342 RCAR_GP_PIN(3, 23), 3343 }; 3344 static const unsigned int sdhi2_wp_mux[] = { 3345 SD2_WP_MARK, 3346 }; 3347 /* - SDHI3 ------------------------------------------------------------------ */ 3348 static const unsigned int sdhi3_data1_pins[] = { 3349 /* D0 */ 3350 RCAR_GP_PIN(3, 26), 3351 }; 3352 static const unsigned int sdhi3_data1_mux[] = { 3353 SD3_DAT0_MARK, 3354 }; 3355 static const unsigned int sdhi3_data4_pins[] = { 3356 /* D[0:3] */ 3357 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 3358 }; 3359 static const unsigned int sdhi3_data4_mux[] = { 3360 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, 3361 }; 3362 static const unsigned int sdhi3_ctrl_pins[] = { 3363 /* CLK, CMD */ 3364 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), 3365 }; 3366 static const unsigned int sdhi3_ctrl_mux[] = { 3367 SD3_CLK_MARK, SD3_CMD_MARK, 3368 }; 3369 static const unsigned int sdhi3_cd_pins[] = { 3370 /* CD */ 3371 RCAR_GP_PIN(3, 30), 3372 }; 3373 static const unsigned int sdhi3_cd_mux[] = { 3374 SD3_CD_MARK, 3375 }; 3376 static const unsigned int sdhi3_wp_pins[] = { 3377 /* WP */ 3378 RCAR_GP_PIN(3, 31), 3379 }; 3380 static const unsigned int sdhi3_wp_mux[] = { 3381 SD3_WP_MARK, 3382 }; 3383 /* - SSI -------------------------------------------------------------------- */ 3384 static const unsigned int ssi0_data_pins[] = { 3385 /* SDATA0 */ 3386 RCAR_GP_PIN(4, 5), 3387 }; 3388 static const unsigned int ssi0_data_mux[] = { 3389 SSI_SDATA0_MARK, 3390 }; 3391 static const unsigned int ssi0129_ctrl_pins[] = { 3392 /* SCK, WS */ 3393 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), 3394 }; 3395 static const unsigned int ssi0129_ctrl_mux[] = { 3396 SSI_SCK0129_MARK, SSI_WS0129_MARK, 3397 }; 3398 static const unsigned int ssi1_data_pins[] = { 3399 /* SDATA1 */ 3400 RCAR_GP_PIN(4, 6), 3401 }; 3402 static const unsigned int ssi1_data_mux[] = { 3403 SSI_SDATA1_MARK, 3404 }; 3405 static const unsigned int ssi1_ctrl_pins[] = { 3406 /* SCK, WS */ 3407 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24), 3408 }; 3409 static const unsigned int ssi1_ctrl_mux[] = { 3410 SSI_SCK1_MARK, SSI_WS1_MARK, 3411 }; 3412 static const unsigned int ssi2_data_pins[] = { 3413 /* SDATA2 */ 3414 RCAR_GP_PIN(4, 7), 3415 }; 3416 static const unsigned int ssi2_data_mux[] = { 3417 SSI_SDATA2_MARK, 3418 }; 3419 static const unsigned int ssi2_ctrl_pins[] = { 3420 /* SCK, WS */ 3421 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17), 3422 }; 3423 static const unsigned int ssi2_ctrl_mux[] = { 3424 SSI_SCK2_MARK, SSI_WS2_MARK, 3425 }; 3426 static const unsigned int ssi3_data_pins[] = { 3427 /* SDATA3 */ 3428 RCAR_GP_PIN(4, 10), 3429 }; 3430 static const unsigned int ssi3_data_mux[] = { 3431 SSI_SDATA3_MARK 3432 }; 3433 static const unsigned int ssi34_ctrl_pins[] = { 3434 /* SCK, WS */ 3435 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 3436 }; 3437 static const unsigned int ssi34_ctrl_mux[] = { 3438 SSI_SCK34_MARK, SSI_WS34_MARK, 3439 }; 3440 static const unsigned int ssi4_data_pins[] = { 3441 /* SDATA4 */ 3442 RCAR_GP_PIN(4, 13), 3443 }; 3444 static const unsigned int ssi4_data_mux[] = { 3445 SSI_SDATA4_MARK, 3446 }; 3447 static const unsigned int ssi4_ctrl_pins[] = { 3448 /* SCK, WS */ 3449 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3450 }; 3451 static const unsigned int ssi4_ctrl_mux[] = { 3452 SSI_SCK4_MARK, SSI_WS4_MARK, 3453 }; 3454 static const unsigned int ssi5_pins[] = { 3455 /* SDATA5, SCK, WS */ 3456 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), 3457 }; 3458 static const unsigned int ssi5_mux[] = { 3459 SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK, 3460 }; 3461 static const unsigned int ssi5_b_pins[] = { 3462 /* SDATA5, SCK, WS */ 3463 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3464 }; 3465 static const unsigned int ssi5_b_mux[] = { 3466 SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK 3467 }; 3468 static const unsigned int ssi5_c_pins[] = { 3469 /* SDATA5, SCK, WS */ 3470 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3471 }; 3472 static const unsigned int ssi5_c_mux[] = { 3473 SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK, 3474 }; 3475 static const unsigned int ssi6_pins[] = { 3476 /* SDATA6, SCK, WS */ 3477 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 3478 }; 3479 static const unsigned int ssi6_mux[] = { 3480 SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK, 3481 }; 3482 static const unsigned int ssi6_b_pins[] = { 3483 /* SDATA6, SCK, WS */ 3484 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27), 3485 }; 3486 static const unsigned int ssi6_b_mux[] = { 3487 SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK, 3488 }; 3489 static const unsigned int ssi7_data_pins[] = { 3490 /* SDATA7 */ 3491 RCAR_GP_PIN(4, 22), 3492 }; 3493 static const unsigned int ssi7_data_mux[] = { 3494 SSI_SDATA7_MARK, 3495 }; 3496 static const unsigned int ssi7_b_data_pins[] = { 3497 /* SDATA7 */ 3498 RCAR_GP_PIN(4, 22), 3499 }; 3500 static const unsigned int ssi7_b_data_mux[] = { 3501 SSI_SDATA7_B_MARK, 3502 }; 3503 static const unsigned int ssi7_c_data_pins[] = { 3504 /* SDATA7 */ 3505 RCAR_GP_PIN(1, 26), 3506 }; 3507 static const unsigned int ssi7_c_data_mux[] = { 3508 SSI_SDATA7_C_MARK, 3509 }; 3510 static const unsigned int ssi78_ctrl_pins[] = { 3511 /* SCK, WS */ 3512 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 3513 }; 3514 static const unsigned int ssi78_ctrl_mux[] = { 3515 SSI_SCK78_MARK, SSI_WS78_MARK, 3516 }; 3517 static const unsigned int ssi78_b_ctrl_pins[] = { 3518 /* SCK, WS */ 3519 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24), 3520 }; 3521 static const unsigned int ssi78_b_ctrl_mux[] = { 3522 SSI_SCK78_B_MARK, SSI_WS78_B_MARK, 3523 }; 3524 static const unsigned int ssi78_c_ctrl_pins[] = { 3525 /* SCK, WS */ 3526 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25), 3527 }; 3528 static const unsigned int ssi78_c_ctrl_mux[] = { 3529 SSI_SCK78_C_MARK, SSI_WS78_C_MARK, 3530 }; 3531 static const unsigned int ssi8_data_pins[] = { 3532 /* SDATA8 */ 3533 RCAR_GP_PIN(4, 23), 3534 }; 3535 static const unsigned int ssi8_data_mux[] = { 3536 SSI_SDATA8_MARK, 3537 }; 3538 static const unsigned int ssi8_b_data_pins[] = { 3539 /* SDATA8 */ 3540 RCAR_GP_PIN(4, 23), 3541 }; 3542 static const unsigned int ssi8_b_data_mux[] = { 3543 SSI_SDATA8_B_MARK, 3544 }; 3545 static const unsigned int ssi8_c_data_pins[] = { 3546 /* SDATA8 */ 3547 RCAR_GP_PIN(1, 27), 3548 }; 3549 static const unsigned int ssi8_c_data_mux[] = { 3550 SSI_SDATA8_C_MARK, 3551 }; 3552 static const unsigned int ssi9_data_pins[] = { 3553 /* SDATA9 */ 3554 RCAR_GP_PIN(4, 24), 3555 }; 3556 static const unsigned int ssi9_data_mux[] = { 3557 SSI_SDATA9_MARK, 3558 }; 3559 static const unsigned int ssi9_ctrl_pins[] = { 3560 /* SCK, WS */ 3561 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), 3562 }; 3563 static const unsigned int ssi9_ctrl_mux[] = { 3564 SSI_SCK9_MARK, SSI_WS9_MARK, 3565 }; 3566 /* - TPU0 ------------------------------------------------------------------- */ 3567 static const unsigned int tpu0_to0_pins[] = { 3568 /* TO */ 3569 RCAR_GP_PIN(0, 20), 3570 }; 3571 static const unsigned int tpu0_to0_mux[] = { 3572 TPU0TO0_MARK, 3573 }; 3574 static const unsigned int tpu0_to1_pins[] = { 3575 /* TO */ 3576 RCAR_GP_PIN(0, 21), 3577 }; 3578 static const unsigned int tpu0_to1_mux[] = { 3579 TPU0TO1_MARK, 3580 }; 3581 static const unsigned int tpu0_to2_pins[] = { 3582 /* TO */ 3583 RCAR_GP_PIN(0, 22), 3584 }; 3585 static const unsigned int tpu0_to2_mux[] = { 3586 TPU0TO2_MARK, 3587 }; 3588 static const unsigned int tpu0_to3_pins[] = { 3589 /* TO */ 3590 RCAR_GP_PIN(0, 23), 3591 }; 3592 static const unsigned int tpu0_to3_mux[] = { 3593 TPU0TO3_MARK, 3594 }; 3595 /* - USB0 ------------------------------------------------------------------- */ 3596 static const unsigned int usb0_pins[] = { 3597 /* PWEN, OVC/VBUS */ 3598 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), 3599 }; 3600 static const unsigned int usb0_mux[] = { 3601 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, 3602 }; 3603 static const unsigned int usb0_ovc_vbus_pins[] = { 3604 /* OVC/VBUS */ 3605 RCAR_GP_PIN(5, 19), 3606 }; 3607 static const unsigned int usb0_ovc_vbus_mux[] = { 3608 USB0_OVC_VBUS_MARK, 3609 }; 3610 /* - USB1 ------------------------------------------------------------------- */ 3611 static const unsigned int usb1_pins[] = { 3612 /* PWEN, OVC */ 3613 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), 3614 }; 3615 static const unsigned int usb1_mux[] = { 3616 USB1_PWEN_MARK, USB1_OVC_MARK, 3617 }; 3618 /* - USB2 ------------------------------------------------------------------- */ 3619 static const unsigned int usb2_pins[] = { 3620 /* PWEN, OVC */ 3621 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), 3622 }; 3623 static const unsigned int usb2_mux[] = { 3624 USB2_PWEN_MARK, USB2_OVC_MARK, 3625 }; 3626 /* - VIN0 ------------------------------------------------------------------- */ 3627 static const union vin_data vin0_data_pins = { 3628 .data24 = { 3629 /* B */ 3630 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 3631 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 3632 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 3633 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3634 /* G */ 3635 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 3636 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3637 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3638 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3639 /* R */ 3640 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3641 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3642 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3643 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), 3644 }, 3645 }; 3646 static const union vin_data vin0_data_mux = { 3647 .data24 = { 3648 /* B */ 3649 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 3650 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3651 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3652 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3653 /* G */ 3654 VI0_G0_MARK, VI0_G1_MARK, 3655 VI0_G2_MARK, VI0_G3_MARK, 3656 VI0_G4_MARK, VI0_G5_MARK, 3657 VI0_G6_MARK, VI0_G7_MARK, 3658 /* R */ 3659 VI0_R0_MARK, VI0_R1_MARK, 3660 VI0_R2_MARK, VI0_R3_MARK, 3661 VI0_R4_MARK, VI0_R5_MARK, 3662 VI0_R6_MARK, VI0_R7_MARK, 3663 }, 3664 }; 3665 static const unsigned int vin0_data18_pins[] = { 3666 /* B */ 3667 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 3668 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 3669 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3670 /* G */ 3671 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3672 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3673 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3674 /* R */ 3675 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3676 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3677 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), 3678 }; 3679 static const unsigned int vin0_data18_mux[] = { 3680 /* B */ 3681 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3682 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3683 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3684 /* G */ 3685 VI0_G2_MARK, VI0_G3_MARK, 3686 VI0_G4_MARK, VI0_G5_MARK, 3687 VI0_G6_MARK, VI0_G7_MARK, 3688 /* R */ 3689 VI0_R2_MARK, VI0_R3_MARK, 3690 VI0_R4_MARK, VI0_R5_MARK, 3691 VI0_R6_MARK, VI0_R7_MARK, 3692 }; 3693 static const unsigned int vin0_sync_pins[] = { 3694 RCAR_GP_PIN(0, 12), /* HSYNC */ 3695 RCAR_GP_PIN(0, 13), /* VSYNC */ 3696 }; 3697 static const unsigned int vin0_sync_mux[] = { 3698 VI0_HSYNC_N_MARK, 3699 VI0_VSYNC_N_MARK, 3700 }; 3701 static const unsigned int vin0_field_pins[] = { 3702 RCAR_GP_PIN(0, 15), 3703 }; 3704 static const unsigned int vin0_field_mux[] = { 3705 VI0_FIELD_MARK, 3706 }; 3707 static const unsigned int vin0_clkenb_pins[] = { 3708 RCAR_GP_PIN(0, 14), 3709 }; 3710 static const unsigned int vin0_clkenb_mux[] = { 3711 VI0_CLKENB_MARK, 3712 }; 3713 static const unsigned int vin0_clk_pins[] = { 3714 RCAR_GP_PIN(2, 0), 3715 }; 3716 static const unsigned int vin0_clk_mux[] = { 3717 VI0_CLK_MARK, 3718 }; 3719 /* - VIN1 ------------------------------------------------------------------- */ 3720 static const union vin_data vin1_data_pins = { 3721 .data24 = { 3722 /* B */ 3723 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 3724 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3725 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 3726 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 3727 /* G */ 3728 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 3729 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3730 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), 3731 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), 3732 /* R */ 3733 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 3734 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), 3735 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3736 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), 3737 }, 3738 }; 3739 static const union vin_data vin1_data_mux = { 3740 .data24 = { 3741 /* B */ 3742 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, 3743 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, 3744 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, 3745 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, 3746 /* G */ 3747 VI1_G0_MARK, VI1_G1_MARK, 3748 VI1_G2_MARK, VI1_G3_MARK, 3749 VI1_G4_MARK, VI1_G5_MARK, 3750 VI1_G6_MARK, VI1_G7_MARK, 3751 /* R */ 3752 VI1_R0_MARK, VI1_R1_MARK, 3753 VI1_R2_MARK, VI1_R3_MARK, 3754 VI1_R4_MARK, VI1_R5_MARK, 3755 VI1_R6_MARK, VI1_R7_MARK, 3756 }, 3757 }; 3758 static const unsigned int vin1_data18_pins[] = { 3759 /* B */ 3760 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3761 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 3762 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 3763 /* G */ 3764 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3765 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), 3766 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), 3767 /* R */ 3768 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), 3769 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3770 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), 3771 }; 3772 static const unsigned int vin1_data18_mux[] = { 3773 /* B */ 3774 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, 3775 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, 3776 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, 3777 /* G */ 3778 VI1_G2_MARK, VI1_G3_MARK, 3779 VI1_G4_MARK, VI1_G5_MARK, 3780 VI1_G6_MARK, VI1_G7_MARK, 3781 /* R */ 3782 VI1_R2_MARK, VI1_R3_MARK, 3783 VI1_R4_MARK, VI1_R5_MARK, 3784 VI1_R6_MARK, VI1_R7_MARK, 3785 }; 3786 static const unsigned int vin1_sync_pins[] = { 3787 RCAR_GP_PIN(1, 24), /* HSYNC */ 3788 RCAR_GP_PIN(1, 25), /* VSYNC */ 3789 }; 3790 static const unsigned int vin1_sync_mux[] = { 3791 VI1_HSYNC_N_MARK, 3792 VI1_VSYNC_N_MARK, 3793 }; 3794 static const unsigned int vin1_field_pins[] = { 3795 RCAR_GP_PIN(1, 13), 3796 }; 3797 static const unsigned int vin1_field_mux[] = { 3798 VI1_FIELD_MARK, 3799 }; 3800 static const unsigned int vin1_clkenb_pins[] = { 3801 RCAR_GP_PIN(1, 26), 3802 }; 3803 static const unsigned int vin1_clkenb_mux[] = { 3804 VI1_CLKENB_MARK, 3805 }; 3806 static const unsigned int vin1_clk_pins[] = { 3807 RCAR_GP_PIN(2, 9), 3808 }; 3809 static const unsigned int vin1_clk_mux[] = { 3810 VI1_CLK_MARK, 3811 }; 3812 /* - VIN2 ----------------------------------------------------------------- */ 3813 static const union vin_data vin2_data_pins = { 3814 .data24 = { 3815 /* B */ 3816 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 3817 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3818 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3819 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3820 /* G */ 3821 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 3822 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), 3823 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3824 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3825 /* R */ 3826 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 3827 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 3828 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3829 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), 3830 }, 3831 }; 3832 static const union vin_data vin2_data_mux = { 3833 .data24 = { 3834 /* B */ 3835 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, 3836 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, 3837 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, 3838 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, 3839 /* G */ 3840 VI2_G0_MARK, VI2_G1_MARK, 3841 VI2_G2_MARK, VI2_G3_MARK, 3842 VI2_G4_MARK, VI2_G5_MARK, 3843 VI2_G6_MARK, VI2_G7_MARK, 3844 /* R */ 3845 VI2_R0_MARK, VI2_R1_MARK, 3846 VI2_R2_MARK, VI2_R3_MARK, 3847 VI2_R4_MARK, VI2_R5_MARK, 3848 VI2_R6_MARK, VI2_R7_MARK, 3849 }, 3850 }; 3851 static const unsigned int vin2_data18_pins[] = { 3852 /* B */ 3853 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3854 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3855 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3856 /* G */ 3857 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), 3858 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3859 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3860 /* R */ 3861 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 3862 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3863 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), 3864 }; 3865 static const unsigned int vin2_data18_mux[] = { 3866 /* B */ 3867 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, 3868 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, 3869 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, 3870 /* G */ 3871 VI2_G2_MARK, VI2_G3_MARK, 3872 VI2_G4_MARK, VI2_G5_MARK, 3873 VI2_G6_MARK, VI2_G7_MARK, 3874 /* R */ 3875 VI2_R2_MARK, VI2_R3_MARK, 3876 VI2_R4_MARK, VI2_R5_MARK, 3877 VI2_R6_MARK, VI2_R7_MARK, 3878 }; 3879 static const unsigned int vin2_sync_pins[] = { 3880 RCAR_GP_PIN(1, 16), /* HSYNC */ 3881 RCAR_GP_PIN(1, 21), /* VSYNC */ 3882 }; 3883 static const unsigned int vin2_sync_mux[] = { 3884 VI2_HSYNC_N_MARK, 3885 VI2_VSYNC_N_MARK, 3886 }; 3887 static const unsigned int vin2_field_pins[] = { 3888 RCAR_GP_PIN(1, 9), 3889 }; 3890 static const unsigned int vin2_field_mux[] = { 3891 VI2_FIELD_MARK, 3892 }; 3893 static const unsigned int vin2_clkenb_pins[] = { 3894 RCAR_GP_PIN(1, 8), 3895 }; 3896 static const unsigned int vin2_clkenb_mux[] = { 3897 VI2_CLKENB_MARK, 3898 }; 3899 static const unsigned int vin2_clk_pins[] = { 3900 RCAR_GP_PIN(1, 11), 3901 }; 3902 static const unsigned int vin2_clk_mux[] = { 3903 VI2_CLK_MARK, 3904 }; 3905 /* - VIN3 ----------------------------------------------------------------- */ 3906 static const unsigned int vin3_data8_pins[] = { 3907 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3908 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3909 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3910 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3911 }; 3912 static const unsigned int vin3_data8_mux[] = { 3913 VI3_DATA0_MARK, VI3_DATA1_MARK, 3914 VI3_DATA2_MARK, VI3_DATA3_MARK, 3915 VI3_DATA4_MARK, VI3_DATA5_MARK, 3916 VI3_DATA6_MARK, VI3_DATA7_MARK, 3917 }; 3918 static const unsigned int vin3_sync_pins[] = { 3919 RCAR_GP_PIN(1, 16), /* HSYNC */ 3920 RCAR_GP_PIN(1, 17), /* VSYNC */ 3921 }; 3922 static const unsigned int vin3_sync_mux[] = { 3923 VI3_HSYNC_N_MARK, 3924 VI3_VSYNC_N_MARK, 3925 }; 3926 static const unsigned int vin3_field_pins[] = { 3927 RCAR_GP_PIN(1, 15), 3928 }; 3929 static const unsigned int vin3_field_mux[] = { 3930 VI3_FIELD_MARK, 3931 }; 3932 static const unsigned int vin3_clkenb_pins[] = { 3933 RCAR_GP_PIN(1, 14), 3934 }; 3935 static const unsigned int vin3_clkenb_mux[] = { 3936 VI3_CLKENB_MARK, 3937 }; 3938 static const unsigned int vin3_clk_pins[] = { 3939 RCAR_GP_PIN(1, 23), 3940 }; 3941 static const unsigned int vin3_clk_mux[] = { 3942 VI3_CLK_MARK, 3943 }; 3944 3945 static const struct sh_pfc_pin_group pinmux_groups[] = { 3946 SH_PFC_PIN_GROUP(audio_clk_a), 3947 SH_PFC_PIN_GROUP(audio_clk_b), 3948 SH_PFC_PIN_GROUP(audio_clk_c), 3949 SH_PFC_PIN_GROUP(audio_clkout), 3950 SH_PFC_PIN_GROUP(audio_clkout_b), 3951 SH_PFC_PIN_GROUP(audio_clkout_c), 3952 SH_PFC_PIN_GROUP(audio_clkout_d), 3953 SH_PFC_PIN_GROUP(avb_link), 3954 SH_PFC_PIN_GROUP(avb_magic), 3955 SH_PFC_PIN_GROUP(avb_phy_int), 3956 SH_PFC_PIN_GROUP(avb_mdio), 3957 SH_PFC_PIN_GROUP(avb_mii), 3958 SH_PFC_PIN_GROUP(avb_gmii), 3959 SH_PFC_PIN_GROUP(du_rgb666), 3960 SH_PFC_PIN_GROUP(du_rgb888), 3961 SH_PFC_PIN_GROUP(du_clk_out_0), 3962 SH_PFC_PIN_GROUP(du_clk_out_1), 3963 SH_PFC_PIN_GROUP(du_sync_0), 3964 SH_PFC_PIN_GROUP(du_sync_1), 3965 SH_PFC_PIN_GROUP(du_cde), 3966 SH_PFC_PIN_GROUP(du0_clk_in), 3967 SH_PFC_PIN_GROUP(du1_clk_in), 3968 SH_PFC_PIN_GROUP(du2_clk_in), 3969 SH_PFC_PIN_GROUP(eth_link), 3970 SH_PFC_PIN_GROUP(eth_magic), 3971 SH_PFC_PIN_GROUP(eth_mdio), 3972 SH_PFC_PIN_GROUP(eth_rmii), 3973 SH_PFC_PIN_GROUP(hscif0_data), 3974 SH_PFC_PIN_GROUP(hscif0_clk), 3975 SH_PFC_PIN_GROUP(hscif0_ctrl), 3976 SH_PFC_PIN_GROUP(hscif0_data_b), 3977 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 3978 SH_PFC_PIN_GROUP(hscif0_data_c), 3979 SH_PFC_PIN_GROUP(hscif0_ctrl_c), 3980 SH_PFC_PIN_GROUP(hscif0_data_d), 3981 SH_PFC_PIN_GROUP(hscif0_ctrl_d), 3982 SH_PFC_PIN_GROUP(hscif0_data_e), 3983 SH_PFC_PIN_GROUP(hscif0_ctrl_e), 3984 SH_PFC_PIN_GROUP(hscif0_data_f), 3985 SH_PFC_PIN_GROUP(hscif0_ctrl_f), 3986 SH_PFC_PIN_GROUP(hscif1_data), 3987 SH_PFC_PIN_GROUP(hscif1_clk), 3988 SH_PFC_PIN_GROUP(hscif1_ctrl), 3989 SH_PFC_PIN_GROUP(hscif1_data_b), 3990 SH_PFC_PIN_GROUP(hscif1_clk_b), 3991 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 3992 SH_PFC_PIN_GROUP(i2c0), 3993 SH_PFC_PIN_GROUP(i2c1), 3994 SH_PFC_PIN_GROUP(i2c1_b), 3995 SH_PFC_PIN_GROUP(i2c1_c), 3996 SH_PFC_PIN_GROUP(i2c2), 3997 SH_PFC_PIN_GROUP(i2c2_b), 3998 SH_PFC_PIN_GROUP(i2c2_c), 3999 SH_PFC_PIN_GROUP(i2c2_d), 4000 SH_PFC_PIN_GROUP(i2c2_e), 4001 SH_PFC_PIN_GROUP(i2c3), 4002 SH_PFC_PIN_GROUP(iic0), 4003 SH_PFC_PIN_GROUP(iic1), 4004 SH_PFC_PIN_GROUP(iic1_b), 4005 SH_PFC_PIN_GROUP(iic1_c), 4006 SH_PFC_PIN_GROUP(iic2), 4007 SH_PFC_PIN_GROUP(iic2_b), 4008 SH_PFC_PIN_GROUP(iic2_c), 4009 SH_PFC_PIN_GROUP(iic2_d), 4010 SH_PFC_PIN_GROUP(iic2_e), 4011 SH_PFC_PIN_GROUP(iic3), 4012 SH_PFC_PIN_GROUP(intc_irq0), 4013 SH_PFC_PIN_GROUP(intc_irq1), 4014 SH_PFC_PIN_GROUP(intc_irq2), 4015 SH_PFC_PIN_GROUP(intc_irq3), 4016 SH_PFC_PIN_GROUP(mlb_3pin), 4017 SH_PFC_PIN_GROUP(mmc0_data1), 4018 SH_PFC_PIN_GROUP(mmc0_data4), 4019 SH_PFC_PIN_GROUP(mmc0_data8), 4020 SH_PFC_PIN_GROUP(mmc0_ctrl), 4021 SH_PFC_PIN_GROUP(mmc1_data1), 4022 SH_PFC_PIN_GROUP(mmc1_data4), 4023 SH_PFC_PIN_GROUP(mmc1_data8), 4024 SH_PFC_PIN_GROUP(mmc1_ctrl), 4025 SH_PFC_PIN_GROUP(msiof0_clk), 4026 SH_PFC_PIN_GROUP(msiof0_sync), 4027 SH_PFC_PIN_GROUP(msiof0_ss1), 4028 SH_PFC_PIN_GROUP(msiof0_ss2), 4029 SH_PFC_PIN_GROUP(msiof0_rx), 4030 SH_PFC_PIN_GROUP(msiof0_tx), 4031 SH_PFC_PIN_GROUP(msiof0_clk_b), 4032 SH_PFC_PIN_GROUP(msiof0_ss1_b), 4033 SH_PFC_PIN_GROUP(msiof0_ss2_b), 4034 SH_PFC_PIN_GROUP(msiof0_rx_b), 4035 SH_PFC_PIN_GROUP(msiof0_tx_b), 4036 SH_PFC_PIN_GROUP(msiof1_clk), 4037 SH_PFC_PIN_GROUP(msiof1_sync), 4038 SH_PFC_PIN_GROUP(msiof1_ss1), 4039 SH_PFC_PIN_GROUP(msiof1_ss2), 4040 SH_PFC_PIN_GROUP(msiof1_rx), 4041 SH_PFC_PIN_GROUP(msiof1_tx), 4042 SH_PFC_PIN_GROUP(msiof1_clk_b), 4043 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4044 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4045 SH_PFC_PIN_GROUP(msiof1_rx_b), 4046 SH_PFC_PIN_GROUP(msiof1_tx_b), 4047 SH_PFC_PIN_GROUP(msiof2_clk), 4048 SH_PFC_PIN_GROUP(msiof2_sync), 4049 SH_PFC_PIN_GROUP(msiof2_ss1), 4050 SH_PFC_PIN_GROUP(msiof2_ss2), 4051 SH_PFC_PIN_GROUP(msiof2_rx), 4052 SH_PFC_PIN_GROUP(msiof2_tx), 4053 SH_PFC_PIN_GROUP(msiof3_clk), 4054 SH_PFC_PIN_GROUP(msiof3_sync), 4055 SH_PFC_PIN_GROUP(msiof3_ss1), 4056 SH_PFC_PIN_GROUP(msiof3_ss2), 4057 SH_PFC_PIN_GROUP(msiof3_rx), 4058 SH_PFC_PIN_GROUP(msiof3_tx), 4059 SH_PFC_PIN_GROUP(msiof3_clk_b), 4060 SH_PFC_PIN_GROUP(msiof3_sync_b), 4061 SH_PFC_PIN_GROUP(msiof3_rx_b), 4062 SH_PFC_PIN_GROUP(msiof3_tx_b), 4063 SH_PFC_PIN_GROUP(pwm0), 4064 SH_PFC_PIN_GROUP(pwm0_b), 4065 SH_PFC_PIN_GROUP(pwm1), 4066 SH_PFC_PIN_GROUP(pwm1_b), 4067 SH_PFC_PIN_GROUP(pwm2), 4068 SH_PFC_PIN_GROUP(pwm3), 4069 SH_PFC_PIN_GROUP(pwm4), 4070 SH_PFC_PIN_GROUP(pwm5), 4071 SH_PFC_PIN_GROUP(pwm6), 4072 SH_PFC_PIN_GROUP(qspi_ctrl), 4073 SH_PFC_PIN_GROUP(qspi_data2), 4074 SH_PFC_PIN_GROUP(qspi_data4), 4075 SH_PFC_PIN_GROUP(scif0_data), 4076 SH_PFC_PIN_GROUP(scif0_clk), 4077 SH_PFC_PIN_GROUP(scif0_ctrl), 4078 SH_PFC_PIN_GROUP(scif0_data_b), 4079 SH_PFC_PIN_GROUP(scif1_data), 4080 SH_PFC_PIN_GROUP(scif1_clk), 4081 SH_PFC_PIN_GROUP(scif1_ctrl), 4082 SH_PFC_PIN_GROUP(scif1_data_b), 4083 SH_PFC_PIN_GROUP(scif1_data_c), 4084 SH_PFC_PIN_GROUP(scif1_data_d), 4085 SH_PFC_PIN_GROUP(scif1_clk_d), 4086 SH_PFC_PIN_GROUP(scif1_data_e), 4087 SH_PFC_PIN_GROUP(scif1_clk_e), 4088 SH_PFC_PIN_GROUP(scif2_data), 4089 SH_PFC_PIN_GROUP(scif2_clk), 4090 SH_PFC_PIN_GROUP(scif2_data_b), 4091 SH_PFC_PIN_GROUP(scifa0_data), 4092 SH_PFC_PIN_GROUP(scifa0_clk), 4093 SH_PFC_PIN_GROUP(scifa0_ctrl), 4094 SH_PFC_PIN_GROUP(scifa0_data_b), 4095 SH_PFC_PIN_GROUP(scifa0_clk_b), 4096 SH_PFC_PIN_GROUP(scifa0_ctrl_b), 4097 SH_PFC_PIN_GROUP(scifa1_data), 4098 SH_PFC_PIN_GROUP(scifa1_clk), 4099 SH_PFC_PIN_GROUP(scifa1_ctrl), 4100 SH_PFC_PIN_GROUP(scifa1_data_b), 4101 SH_PFC_PIN_GROUP(scifa1_clk_b), 4102 SH_PFC_PIN_GROUP(scifa1_ctrl_b), 4103 SH_PFC_PIN_GROUP(scifa1_data_c), 4104 SH_PFC_PIN_GROUP(scifa1_clk_c), 4105 SH_PFC_PIN_GROUP(scifa1_ctrl_c), 4106 SH_PFC_PIN_GROUP(scifa1_data_d), 4107 SH_PFC_PIN_GROUP(scifa1_clk_d), 4108 SH_PFC_PIN_GROUP(scifa1_ctrl_d), 4109 SH_PFC_PIN_GROUP(scifa2_data), 4110 SH_PFC_PIN_GROUP(scifa2_clk), 4111 SH_PFC_PIN_GROUP(scifa2_ctrl), 4112 SH_PFC_PIN_GROUP(scifa2_data_b), 4113 SH_PFC_PIN_GROUP(scifa2_data_c), 4114 SH_PFC_PIN_GROUP(scifa2_clk_c), 4115 SH_PFC_PIN_GROUP(scifb0_data), 4116 SH_PFC_PIN_GROUP(scifb0_clk), 4117 SH_PFC_PIN_GROUP(scifb0_ctrl), 4118 SH_PFC_PIN_GROUP(scifb0_data_b), 4119 SH_PFC_PIN_GROUP(scifb0_clk_b), 4120 SH_PFC_PIN_GROUP(scifb0_ctrl_b), 4121 SH_PFC_PIN_GROUP(scifb0_data_c), 4122 SH_PFC_PIN_GROUP(scifb1_data), 4123 SH_PFC_PIN_GROUP(scifb1_clk), 4124 SH_PFC_PIN_GROUP(scifb1_ctrl), 4125 SH_PFC_PIN_GROUP(scifb1_data_b), 4126 SH_PFC_PIN_GROUP(scifb1_clk_b), 4127 SH_PFC_PIN_GROUP(scifb1_ctrl_b), 4128 SH_PFC_PIN_GROUP(scifb1_data_c), 4129 SH_PFC_PIN_GROUP(scifb1_data_d), 4130 SH_PFC_PIN_GROUP(scifb1_data_e), 4131 SH_PFC_PIN_GROUP(scifb1_clk_e), 4132 SH_PFC_PIN_GROUP(scifb1_data_f), 4133 SH_PFC_PIN_GROUP(scifb1_data_g), 4134 SH_PFC_PIN_GROUP(scifb1_clk_g), 4135 SH_PFC_PIN_GROUP(scifb2_data), 4136 SH_PFC_PIN_GROUP(scifb2_clk), 4137 SH_PFC_PIN_GROUP(scifb2_ctrl), 4138 SH_PFC_PIN_GROUP(scifb2_data_b), 4139 SH_PFC_PIN_GROUP(scifb2_clk_b), 4140 SH_PFC_PIN_GROUP(scifb2_ctrl_b), 4141 SH_PFC_PIN_GROUP(scifb2_data_c), 4142 SH_PFC_PIN_GROUP(sdhi0_data1), 4143 SH_PFC_PIN_GROUP(sdhi0_data4), 4144 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4145 SH_PFC_PIN_GROUP(sdhi0_cd), 4146 SH_PFC_PIN_GROUP(sdhi0_wp), 4147 SH_PFC_PIN_GROUP(sdhi1_data1), 4148 SH_PFC_PIN_GROUP(sdhi1_data4), 4149 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4150 SH_PFC_PIN_GROUP(sdhi1_cd), 4151 SH_PFC_PIN_GROUP(sdhi1_wp), 4152 SH_PFC_PIN_GROUP(sdhi2_data1), 4153 SH_PFC_PIN_GROUP(sdhi2_data4), 4154 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4155 SH_PFC_PIN_GROUP(sdhi2_cd), 4156 SH_PFC_PIN_GROUP(sdhi2_wp), 4157 SH_PFC_PIN_GROUP(sdhi3_data1), 4158 SH_PFC_PIN_GROUP(sdhi3_data4), 4159 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4160 SH_PFC_PIN_GROUP(sdhi3_cd), 4161 SH_PFC_PIN_GROUP(sdhi3_wp), 4162 SH_PFC_PIN_GROUP(ssi0_data), 4163 SH_PFC_PIN_GROUP(ssi0129_ctrl), 4164 SH_PFC_PIN_GROUP(ssi1_data), 4165 SH_PFC_PIN_GROUP(ssi1_ctrl), 4166 SH_PFC_PIN_GROUP(ssi2_data), 4167 SH_PFC_PIN_GROUP(ssi2_ctrl), 4168 SH_PFC_PIN_GROUP(ssi3_data), 4169 SH_PFC_PIN_GROUP(ssi34_ctrl), 4170 SH_PFC_PIN_GROUP(ssi4_data), 4171 SH_PFC_PIN_GROUP(ssi4_ctrl), 4172 SH_PFC_PIN_GROUP(ssi5), 4173 SH_PFC_PIN_GROUP(ssi5_b), 4174 SH_PFC_PIN_GROUP(ssi5_c), 4175 SH_PFC_PIN_GROUP(ssi6), 4176 SH_PFC_PIN_GROUP(ssi6_b), 4177 SH_PFC_PIN_GROUP(ssi7_data), 4178 SH_PFC_PIN_GROUP(ssi7_b_data), 4179 SH_PFC_PIN_GROUP(ssi7_c_data), 4180 SH_PFC_PIN_GROUP(ssi78_ctrl), 4181 SH_PFC_PIN_GROUP(ssi78_b_ctrl), 4182 SH_PFC_PIN_GROUP(ssi78_c_ctrl), 4183 SH_PFC_PIN_GROUP(ssi8_data), 4184 SH_PFC_PIN_GROUP(ssi8_b_data), 4185 SH_PFC_PIN_GROUP(ssi8_c_data), 4186 SH_PFC_PIN_GROUP(ssi9_data), 4187 SH_PFC_PIN_GROUP(ssi9_ctrl), 4188 SH_PFC_PIN_GROUP(tpu0_to0), 4189 SH_PFC_PIN_GROUP(tpu0_to1), 4190 SH_PFC_PIN_GROUP(tpu0_to2), 4191 SH_PFC_PIN_GROUP(tpu0_to3), 4192 SH_PFC_PIN_GROUP(usb0), 4193 SH_PFC_PIN_GROUP(usb0_ovc_vbus), 4194 SH_PFC_PIN_GROUP(usb1), 4195 SH_PFC_PIN_GROUP(usb2), 4196 VIN_DATA_PIN_GROUP(vin0_data, 24), 4197 VIN_DATA_PIN_GROUP(vin0_data, 20), 4198 SH_PFC_PIN_GROUP(vin0_data18), 4199 VIN_DATA_PIN_GROUP(vin0_data, 16), 4200 VIN_DATA_PIN_GROUP(vin0_data, 12), 4201 VIN_DATA_PIN_GROUP(vin0_data, 10), 4202 VIN_DATA_PIN_GROUP(vin0_data, 8), 4203 VIN_DATA_PIN_GROUP(vin0_data, 4), 4204 SH_PFC_PIN_GROUP(vin0_sync), 4205 SH_PFC_PIN_GROUP(vin0_field), 4206 SH_PFC_PIN_GROUP(vin0_clkenb), 4207 SH_PFC_PIN_GROUP(vin0_clk), 4208 VIN_DATA_PIN_GROUP(vin1_data, 24), 4209 VIN_DATA_PIN_GROUP(vin1_data, 20), 4210 SH_PFC_PIN_GROUP(vin1_data18), 4211 VIN_DATA_PIN_GROUP(vin1_data, 16), 4212 VIN_DATA_PIN_GROUP(vin1_data, 12), 4213 VIN_DATA_PIN_GROUP(vin1_data, 10), 4214 VIN_DATA_PIN_GROUP(vin1_data, 8), 4215 VIN_DATA_PIN_GROUP(vin1_data, 4), 4216 SH_PFC_PIN_GROUP(vin1_sync), 4217 SH_PFC_PIN_GROUP(vin1_field), 4218 SH_PFC_PIN_GROUP(vin1_clkenb), 4219 SH_PFC_PIN_GROUP(vin1_clk), 4220 VIN_DATA_PIN_GROUP(vin2_data, 24), 4221 SH_PFC_PIN_GROUP(vin2_data18), 4222 VIN_DATA_PIN_GROUP(vin2_data, 16), 4223 VIN_DATA_PIN_GROUP(vin2_data, 8), 4224 VIN_DATA_PIN_GROUP(vin2_data, 4), 4225 SH_PFC_PIN_GROUP(vin2_sync), 4226 SH_PFC_PIN_GROUP(vin2_field), 4227 SH_PFC_PIN_GROUP(vin2_clkenb), 4228 SH_PFC_PIN_GROUP(vin2_clk), 4229 SH_PFC_PIN_GROUP(vin3_data8), 4230 SH_PFC_PIN_GROUP(vin3_sync), 4231 SH_PFC_PIN_GROUP(vin3_field), 4232 SH_PFC_PIN_GROUP(vin3_clkenb), 4233 SH_PFC_PIN_GROUP(vin3_clk), 4234 }; 4235 4236 static const char * const audio_clk_groups[] = { 4237 "audio_clk_a", 4238 "audio_clk_b", 4239 "audio_clk_c", 4240 "audio_clkout", 4241 "audio_clkout_b", 4242 "audio_clkout_c", 4243 "audio_clkout_d", 4244 }; 4245 4246 static const char * const avb_groups[] = { 4247 "avb_link", 4248 "avb_magic", 4249 "avb_phy_int", 4250 "avb_mdio", 4251 "avb_mii", 4252 "avb_gmii", 4253 }; 4254 4255 static const char * const du_groups[] = { 4256 "du_rgb666", 4257 "du_rgb888", 4258 "du_clk_out_0", 4259 "du_clk_out_1", 4260 "du_sync_0", 4261 "du_sync_1", 4262 "du_cde", 4263 }; 4264 4265 static const char * const du0_groups[] = { 4266 "du0_clk_in", 4267 }; 4268 4269 static const char * const du1_groups[] = { 4270 "du1_clk_in", 4271 }; 4272 4273 static const char * const du2_groups[] = { 4274 "du2_clk_in", 4275 }; 4276 4277 static const char * const eth_groups[] = { 4278 "eth_link", 4279 "eth_magic", 4280 "eth_mdio", 4281 "eth_rmii", 4282 }; 4283 4284 static const char * const hscif0_groups[] = { 4285 "hscif0_data", 4286 "hscif0_clk", 4287 "hscif0_ctrl", 4288 "hscif0_data_b", 4289 "hscif0_ctrl_b", 4290 "hscif0_data_c", 4291 "hscif0_ctrl_c", 4292 "hscif0_data_d", 4293 "hscif0_ctrl_d", 4294 "hscif0_data_e", 4295 "hscif0_ctrl_e", 4296 "hscif0_data_f", 4297 "hscif0_ctrl_f", 4298 }; 4299 4300 static const char * const hscif1_groups[] = { 4301 "hscif1_data", 4302 "hscif1_clk", 4303 "hscif1_ctrl", 4304 "hscif1_data_b", 4305 "hscif1_clk_b", 4306 "hscif1_ctrl_b", 4307 }; 4308 4309 static const char * const i2c0_groups[] = { 4310 "i2c0", 4311 }; 4312 4313 static const char * const i2c1_groups[] = { 4314 "i2c1", 4315 "i2c1_b", 4316 "i2c1_c", 4317 }; 4318 4319 static const char * const i2c2_groups[] = { 4320 "i2c2", 4321 "i2c2_b", 4322 "i2c2_c", 4323 "i2c2_d", 4324 "i2c2_e", 4325 }; 4326 4327 static const char * const i2c3_groups[] = { 4328 "i2c3", 4329 }; 4330 4331 static const char * const iic0_groups[] = { 4332 "iic0", 4333 }; 4334 4335 static const char * const iic1_groups[] = { 4336 "iic1", 4337 "iic1_b", 4338 "iic1_c", 4339 }; 4340 4341 static const char * const iic2_groups[] = { 4342 "iic2", 4343 "iic2_b", 4344 "iic2_c", 4345 "iic2_d", 4346 "iic2_e", 4347 }; 4348 4349 static const char * const iic3_groups[] = { 4350 "iic3", 4351 }; 4352 4353 static const char * const intc_groups[] = { 4354 "intc_irq0", 4355 "intc_irq1", 4356 "intc_irq2", 4357 "intc_irq3", 4358 }; 4359 4360 static const char * const mlb_groups[] = { 4361 "mlb_3pin", 4362 }; 4363 4364 static const char * const mmc0_groups[] = { 4365 "mmc0_data1", 4366 "mmc0_data4", 4367 "mmc0_data8", 4368 "mmc0_ctrl", 4369 }; 4370 4371 static const char * const mmc1_groups[] = { 4372 "mmc1_data1", 4373 "mmc1_data4", 4374 "mmc1_data8", 4375 "mmc1_ctrl", 4376 }; 4377 4378 static const char * const msiof0_groups[] = { 4379 "msiof0_clk", 4380 "msiof0_sync", 4381 "msiof0_ss1", 4382 "msiof0_ss2", 4383 "msiof0_rx", 4384 "msiof0_tx", 4385 "msiof0_clk_b", 4386 "msiof0_ss1_b", 4387 "msiof0_ss2_b", 4388 "msiof0_rx_b", 4389 "msiof0_tx_b", 4390 }; 4391 4392 static const char * const msiof1_groups[] = { 4393 "msiof1_clk", 4394 "msiof1_sync", 4395 "msiof1_ss1", 4396 "msiof1_ss2", 4397 "msiof1_rx", 4398 "msiof1_tx", 4399 "msiof1_clk_b", 4400 "msiof1_ss1_b", 4401 "msiof1_ss2_b", 4402 "msiof1_rx_b", 4403 "msiof1_tx_b", 4404 }; 4405 4406 static const char * const msiof2_groups[] = { 4407 "msiof2_clk", 4408 "msiof2_sync", 4409 "msiof2_ss1", 4410 "msiof2_ss2", 4411 "msiof2_rx", 4412 "msiof2_tx", 4413 }; 4414 4415 static const char * const msiof3_groups[] = { 4416 "msiof3_clk", 4417 "msiof3_sync", 4418 "msiof3_ss1", 4419 "msiof3_ss2", 4420 "msiof3_rx", 4421 "msiof3_tx", 4422 "msiof3_clk_b", 4423 "msiof3_sync_b", 4424 "msiof3_rx_b", 4425 "msiof3_tx_b", 4426 }; 4427 4428 static const char * const pwm0_groups[] = { 4429 "pwm0", 4430 "pwm0_b", 4431 }; 4432 4433 static const char * const pwm1_groups[] = { 4434 "pwm1", 4435 "pwm1_b", 4436 }; 4437 4438 static const char * const pwm2_groups[] = { 4439 "pwm2", 4440 }; 4441 4442 static const char * const pwm3_groups[] = { 4443 "pwm3", 4444 }; 4445 4446 static const char * const pwm4_groups[] = { 4447 "pwm4", 4448 }; 4449 4450 static const char * const pwm5_groups[] = { 4451 "pwm5", 4452 }; 4453 4454 static const char * const pwm6_groups[] = { 4455 "pwm6", 4456 }; 4457 4458 static const char * const qspi_groups[] = { 4459 "qspi_ctrl", 4460 "qspi_data2", 4461 "qspi_data4", 4462 }; 4463 4464 static const char * const scif0_groups[] = { 4465 "scif0_data", 4466 "scif0_clk", 4467 "scif0_ctrl", 4468 "scif0_data_b", 4469 }; 4470 4471 static const char * const scif1_groups[] = { 4472 "scif1_data", 4473 "scif1_clk", 4474 "scif1_ctrl", 4475 "scif1_data_b", 4476 "scif1_data_c", 4477 "scif1_data_d", 4478 "scif1_clk_d", 4479 "scif1_data_e", 4480 "scif1_clk_e", 4481 }; 4482 4483 static const char * const scif2_groups[] = { 4484 "scif2_data", 4485 "scif2_clk", 4486 "scif2_data_b", 4487 }; 4488 4489 static const char * const scifa0_groups[] = { 4490 "scifa0_data", 4491 "scifa0_clk", 4492 "scifa0_ctrl", 4493 "scifa0_data_b", 4494 "scifa0_clk_b", 4495 "scifa0_ctrl_b", 4496 }; 4497 4498 static const char * const scifa1_groups[] = { 4499 "scifa1_data", 4500 "scifa1_clk", 4501 "scifa1_ctrl", 4502 "scifa1_data_b", 4503 "scifa1_clk_b", 4504 "scifa1_ctrl_b", 4505 "scifa1_data_c", 4506 "scifa1_clk_c", 4507 "scifa1_ctrl_c", 4508 "scifa1_data_d", 4509 "scifa1_clk_d", 4510 "scifa1_ctrl_d", 4511 }; 4512 4513 static const char * const scifa2_groups[] = { 4514 "scifa2_data", 4515 "scifa2_clk", 4516 "scifa2_ctrl", 4517 "scifa2_data_b", 4518 "scifa2_data_c", 4519 "scifa2_clk_c", 4520 }; 4521 4522 static const char * const scifb0_groups[] = { 4523 "scifb0_data", 4524 "scifb0_clk", 4525 "scifb0_ctrl", 4526 "scifb0_data_b", 4527 "scifb0_clk_b", 4528 "scifb0_ctrl_b", 4529 "scifb0_data_c", 4530 }; 4531 4532 static const char * const scifb1_groups[] = { 4533 "scifb1_data", 4534 "scifb1_clk", 4535 "scifb1_ctrl", 4536 "scifb1_data_b", 4537 "scifb1_clk_b", 4538 "scifb1_ctrl_b", 4539 "scifb1_data_c", 4540 "scifb1_data_d", 4541 "scifb1_data_e", 4542 "scifb1_clk_e", 4543 "scifb1_data_f", 4544 "scifb1_data_g", 4545 "scifb1_clk_g", 4546 }; 4547 4548 static const char * const scifb2_groups[] = { 4549 "scifb2_data", 4550 "scifb2_clk", 4551 "scifb2_ctrl", 4552 "scifb2_data_b", 4553 "scifb2_clk_b", 4554 "scifb2_ctrl_b", 4555 "scifb2_data_c", 4556 }; 4557 4558 static const char * const sdhi0_groups[] = { 4559 "sdhi0_data1", 4560 "sdhi0_data4", 4561 "sdhi0_ctrl", 4562 "sdhi0_cd", 4563 "sdhi0_wp", 4564 }; 4565 4566 static const char * const sdhi1_groups[] = { 4567 "sdhi1_data1", 4568 "sdhi1_data4", 4569 "sdhi1_ctrl", 4570 "sdhi1_cd", 4571 "sdhi1_wp", 4572 }; 4573 4574 static const char * const sdhi2_groups[] = { 4575 "sdhi2_data1", 4576 "sdhi2_data4", 4577 "sdhi2_ctrl", 4578 "sdhi2_cd", 4579 "sdhi2_wp", 4580 }; 4581 4582 static const char * const sdhi3_groups[] = { 4583 "sdhi3_data1", 4584 "sdhi3_data4", 4585 "sdhi3_ctrl", 4586 "sdhi3_cd", 4587 "sdhi3_wp", 4588 }; 4589 4590 static const char * const ssi_groups[] = { 4591 "ssi0_data", 4592 "ssi0129_ctrl", 4593 "ssi1_data", 4594 "ssi1_ctrl", 4595 "ssi2_data", 4596 "ssi2_ctrl", 4597 "ssi3_data", 4598 "ssi34_ctrl", 4599 "ssi4_data", 4600 "ssi4_ctrl", 4601 "ssi5", 4602 "ssi5_b", 4603 "ssi5_c", 4604 "ssi6", 4605 "ssi6_b", 4606 "ssi7_data", 4607 "ssi7_b_data", 4608 "ssi7_c_data", 4609 "ssi78_ctrl", 4610 "ssi78_b_ctrl", 4611 "ssi78_c_ctrl", 4612 "ssi8_data", 4613 "ssi8_b_data", 4614 "ssi8_c_data", 4615 "ssi9_data", 4616 "ssi9_ctrl", 4617 }; 4618 4619 static const char * const tpu0_groups[] = { 4620 "tpu0_to0", 4621 "tpu0_to1", 4622 "tpu0_to2", 4623 "tpu0_to3", 4624 }; 4625 4626 static const char * const usb0_groups[] = { 4627 "usb0", 4628 "usb0_ovc_vbus", 4629 }; 4630 4631 static const char * const usb1_groups[] = { 4632 "usb1", 4633 }; 4634 4635 static const char * const usb2_groups[] = { 4636 "usb2", 4637 }; 4638 4639 static const char * const vin0_groups[] = { 4640 "vin0_data24", 4641 "vin0_data20", 4642 "vin0_data18", 4643 "vin0_data16", 4644 "vin0_data12", 4645 "vin0_data10", 4646 "vin0_data8", 4647 "vin0_data4", 4648 "vin0_sync", 4649 "vin0_field", 4650 "vin0_clkenb", 4651 "vin0_clk", 4652 }; 4653 4654 static const char * const vin1_groups[] = { 4655 "vin1_data24", 4656 "vin1_data20", 4657 "vin1_data18", 4658 "vin1_data16", 4659 "vin1_data12", 4660 "vin1_data10", 4661 "vin1_data8", 4662 "vin1_data4", 4663 "vin1_sync", 4664 "vin1_field", 4665 "vin1_clkenb", 4666 "vin1_clk", 4667 }; 4668 4669 static const char * const vin2_groups[] = { 4670 "vin2_data24", 4671 "vin2_data18", 4672 "vin2_data16", 4673 "vin2_data8", 4674 "vin2_data4", 4675 "vin2_sync", 4676 "vin2_field", 4677 "vin2_clkenb", 4678 "vin2_clk", 4679 }; 4680 4681 static const char * const vin3_groups[] = { 4682 "vin3_data8", 4683 "vin3_sync", 4684 "vin3_field", 4685 "vin3_clkenb", 4686 "vin3_clk", 4687 }; 4688 4689 static const struct sh_pfc_function pinmux_functions[] = { 4690 SH_PFC_FUNCTION(audio_clk), 4691 SH_PFC_FUNCTION(avb), 4692 SH_PFC_FUNCTION(du), 4693 SH_PFC_FUNCTION(du0), 4694 SH_PFC_FUNCTION(du1), 4695 SH_PFC_FUNCTION(du2), 4696 SH_PFC_FUNCTION(eth), 4697 SH_PFC_FUNCTION(hscif0), 4698 SH_PFC_FUNCTION(hscif1), 4699 SH_PFC_FUNCTION(i2c0), 4700 SH_PFC_FUNCTION(i2c1), 4701 SH_PFC_FUNCTION(i2c2), 4702 SH_PFC_FUNCTION(i2c3), 4703 SH_PFC_FUNCTION(iic0), 4704 SH_PFC_FUNCTION(iic1), 4705 SH_PFC_FUNCTION(iic2), 4706 SH_PFC_FUNCTION(iic3), 4707 SH_PFC_FUNCTION(intc), 4708 SH_PFC_FUNCTION(mlb), 4709 SH_PFC_FUNCTION(mmc0), 4710 SH_PFC_FUNCTION(mmc1), 4711 SH_PFC_FUNCTION(msiof0), 4712 SH_PFC_FUNCTION(msiof1), 4713 SH_PFC_FUNCTION(msiof2), 4714 SH_PFC_FUNCTION(msiof3), 4715 SH_PFC_FUNCTION(pwm0), 4716 SH_PFC_FUNCTION(pwm1), 4717 SH_PFC_FUNCTION(pwm2), 4718 SH_PFC_FUNCTION(pwm3), 4719 SH_PFC_FUNCTION(pwm4), 4720 SH_PFC_FUNCTION(pwm5), 4721 SH_PFC_FUNCTION(pwm6), 4722 SH_PFC_FUNCTION(qspi), 4723 SH_PFC_FUNCTION(scif0), 4724 SH_PFC_FUNCTION(scif1), 4725 SH_PFC_FUNCTION(scif2), 4726 SH_PFC_FUNCTION(scifa0), 4727 SH_PFC_FUNCTION(scifa1), 4728 SH_PFC_FUNCTION(scifa2), 4729 SH_PFC_FUNCTION(scifb0), 4730 SH_PFC_FUNCTION(scifb1), 4731 SH_PFC_FUNCTION(scifb2), 4732 SH_PFC_FUNCTION(sdhi0), 4733 SH_PFC_FUNCTION(sdhi1), 4734 SH_PFC_FUNCTION(sdhi2), 4735 SH_PFC_FUNCTION(sdhi3), 4736 SH_PFC_FUNCTION(ssi), 4737 SH_PFC_FUNCTION(tpu0), 4738 SH_PFC_FUNCTION(usb0), 4739 SH_PFC_FUNCTION(usb1), 4740 SH_PFC_FUNCTION(usb2), 4741 SH_PFC_FUNCTION(vin0), 4742 SH_PFC_FUNCTION(vin1), 4743 SH_PFC_FUNCTION(vin2), 4744 SH_PFC_FUNCTION(vin3), 4745 }; 4746 4747 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4748 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 4749 GP_0_31_FN, FN_IP3_17_15, 4750 GP_0_30_FN, FN_IP3_14_12, 4751 GP_0_29_FN, FN_IP3_11_8, 4752 GP_0_28_FN, FN_IP3_7_4, 4753 GP_0_27_FN, FN_IP3_3_0, 4754 GP_0_26_FN, FN_IP2_28_26, 4755 GP_0_25_FN, FN_IP2_25_22, 4756 GP_0_24_FN, FN_IP2_21_18, 4757 GP_0_23_FN, FN_IP2_17_15, 4758 GP_0_22_FN, FN_IP2_14_12, 4759 GP_0_21_FN, FN_IP2_11_9, 4760 GP_0_20_FN, FN_IP2_8_6, 4761 GP_0_19_FN, FN_IP2_5_3, 4762 GP_0_18_FN, FN_IP2_2_0, 4763 GP_0_17_FN, FN_IP1_29_28, 4764 GP_0_16_FN, FN_IP1_27_26, 4765 GP_0_15_FN, FN_IP1_25_22, 4766 GP_0_14_FN, FN_IP1_21_18, 4767 GP_0_13_FN, FN_IP1_17_15, 4768 GP_0_12_FN, FN_IP1_14_12, 4769 GP_0_11_FN, FN_IP1_11_8, 4770 GP_0_10_FN, FN_IP1_7_4, 4771 GP_0_9_FN, FN_IP1_3_0, 4772 GP_0_8_FN, FN_IP0_30_27, 4773 GP_0_7_FN, FN_IP0_26_23, 4774 GP_0_6_FN, FN_IP0_22_20, 4775 GP_0_5_FN, FN_IP0_19_16, 4776 GP_0_4_FN, FN_IP0_15_12, 4777 GP_0_3_FN, FN_IP0_11_9, 4778 GP_0_2_FN, FN_IP0_8_6, 4779 GP_0_1_FN, FN_IP0_5_3, 4780 GP_0_0_FN, FN_IP0_2_0 } 4781 }, 4782 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { 4783 0, 0, 4784 0, 0, 4785 GP_1_29_FN, FN_IP6_13_11, 4786 GP_1_28_FN, FN_IP6_10_9, 4787 GP_1_27_FN, FN_IP6_8_6, 4788 GP_1_26_FN, FN_IP6_5_3, 4789 GP_1_25_FN, FN_IP6_2_0, 4790 GP_1_24_FN, FN_IP5_29_27, 4791 GP_1_23_FN, FN_IP5_26_24, 4792 GP_1_22_FN, FN_IP5_23_21, 4793 GP_1_21_FN, FN_IP5_20_18, 4794 GP_1_20_FN, FN_IP5_17_15, 4795 GP_1_19_FN, FN_IP5_14_13, 4796 GP_1_18_FN, FN_IP5_12_10, 4797 GP_1_17_FN, FN_IP5_9_6, 4798 GP_1_16_FN, FN_IP5_5_3, 4799 GP_1_15_FN, FN_IP5_2_0, 4800 GP_1_14_FN, FN_IP4_29_27, 4801 GP_1_13_FN, FN_IP4_26_24, 4802 GP_1_12_FN, FN_IP4_23_21, 4803 GP_1_11_FN, FN_IP4_20_18, 4804 GP_1_10_FN, FN_IP4_17_15, 4805 GP_1_9_FN, FN_IP4_14_12, 4806 GP_1_8_FN, FN_IP4_11_9, 4807 GP_1_7_FN, FN_IP4_8_6, 4808 GP_1_6_FN, FN_IP4_5_3, 4809 GP_1_5_FN, FN_IP4_2_0, 4810 GP_1_4_FN, FN_IP3_31_29, 4811 GP_1_3_FN, FN_IP3_28_26, 4812 GP_1_2_FN, FN_IP3_25_23, 4813 GP_1_1_FN, FN_IP3_22_20, 4814 GP_1_0_FN, FN_IP3_19_18, } 4815 }, 4816 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { 4817 0, 0, 4818 0, 0, 4819 GP_2_29_FN, FN_IP7_15_13, 4820 GP_2_28_FN, FN_IP7_12_10, 4821 GP_2_27_FN, FN_IP7_9_8, 4822 GP_2_26_FN, FN_IP7_7_6, 4823 GP_2_25_FN, FN_IP7_5_3, 4824 GP_2_24_FN, FN_IP7_2_0, 4825 GP_2_23_FN, FN_IP6_31_29, 4826 GP_2_22_FN, FN_IP6_28_26, 4827 GP_2_21_FN, FN_IP6_25_23, 4828 GP_2_20_FN, FN_IP6_22_20, 4829 GP_2_19_FN, FN_IP6_19_17, 4830 GP_2_18_FN, FN_IP6_16_14, 4831 GP_2_17_FN, FN_VI1_DATA7_VI1_B7, 4832 GP_2_16_FN, FN_IP8_27, 4833 GP_2_15_FN, FN_IP8_26, 4834 GP_2_14_FN, FN_IP8_25_24, 4835 GP_2_13_FN, FN_IP8_23_22, 4836 GP_2_12_FN, FN_IP8_21_20, 4837 GP_2_11_FN, FN_IP8_19_18, 4838 GP_2_10_FN, FN_IP8_17_16, 4839 GP_2_9_FN, FN_IP8_15_14, 4840 GP_2_8_FN, FN_IP8_13_12, 4841 GP_2_7_FN, FN_IP8_11_10, 4842 GP_2_6_FN, FN_IP8_9_8, 4843 GP_2_5_FN, FN_IP8_7_6, 4844 GP_2_4_FN, FN_IP8_5_4, 4845 GP_2_3_FN, FN_IP8_3_2, 4846 GP_2_2_FN, FN_IP8_1_0, 4847 GP_2_1_FN, FN_IP7_30_29, 4848 GP_2_0_FN, FN_IP7_28_27 } 4849 }, 4850 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { 4851 GP_3_31_FN, FN_IP11_21_18, 4852 GP_3_30_FN, FN_IP11_17_15, 4853 GP_3_29_FN, FN_IP11_14_13, 4854 GP_3_28_FN, FN_IP11_12_11, 4855 GP_3_27_FN, FN_IP11_10_9, 4856 GP_3_26_FN, FN_IP11_8_7, 4857 GP_3_25_FN, FN_IP11_6_5, 4858 GP_3_24_FN, FN_IP11_4, 4859 GP_3_23_FN, FN_IP11_3_0, 4860 GP_3_22_FN, FN_IP10_29_26, 4861 GP_3_21_FN, FN_IP10_25_23, 4862 GP_3_20_FN, FN_IP10_22_19, 4863 GP_3_19_FN, FN_IP10_18_15, 4864 GP_3_18_FN, FN_IP10_14_11, 4865 GP_3_17_FN, FN_IP10_10_7, 4866 GP_3_16_FN, FN_IP10_6_4, 4867 GP_3_15_FN, FN_IP10_3_0, 4868 GP_3_14_FN, FN_IP9_31_28, 4869 GP_3_13_FN, FN_IP9_27_26, 4870 GP_3_12_FN, FN_IP9_25_24, 4871 GP_3_11_FN, FN_IP9_23_22, 4872 GP_3_10_FN, FN_IP9_21_20, 4873 GP_3_9_FN, FN_IP9_19_18, 4874 GP_3_8_FN, FN_IP9_17_16, 4875 GP_3_7_FN, FN_IP9_15_12, 4876 GP_3_6_FN, FN_IP9_11_8, 4877 GP_3_5_FN, FN_IP9_7_6, 4878 GP_3_4_FN, FN_IP9_5_4, 4879 GP_3_3_FN, FN_IP9_3_2, 4880 GP_3_2_FN, FN_IP9_1_0, 4881 GP_3_1_FN, FN_IP8_30_29, 4882 GP_3_0_FN, FN_IP8_28 } 4883 }, 4884 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { 4885 GP_4_31_FN, FN_IP14_18_16, 4886 GP_4_30_FN, FN_IP14_15_12, 4887 GP_4_29_FN, FN_IP14_11_9, 4888 GP_4_28_FN, FN_IP14_8_6, 4889 GP_4_27_FN, FN_IP14_5_3, 4890 GP_4_26_FN, FN_IP14_2_0, 4891 GP_4_25_FN, FN_IP13_30_29, 4892 GP_4_24_FN, FN_IP13_28_26, 4893 GP_4_23_FN, FN_IP13_25_23, 4894 GP_4_22_FN, FN_IP13_22_19, 4895 GP_4_21_FN, FN_IP13_18_16, 4896 GP_4_20_FN, FN_IP13_15_13, 4897 GP_4_19_FN, FN_IP13_12_10, 4898 GP_4_18_FN, FN_IP13_9_7, 4899 GP_4_17_FN, FN_IP13_6_3, 4900 GP_4_16_FN, FN_IP13_2_0, 4901 GP_4_15_FN, FN_IP12_30_28, 4902 GP_4_14_FN, FN_IP12_27_25, 4903 GP_4_13_FN, FN_IP12_24_23, 4904 GP_4_12_FN, FN_IP12_22_20, 4905 GP_4_11_FN, FN_IP12_19_17, 4906 GP_4_10_FN, FN_IP12_16_14, 4907 GP_4_9_FN, FN_IP12_13_11, 4908 GP_4_8_FN, FN_IP12_10_8, 4909 GP_4_7_FN, FN_IP12_7_6, 4910 GP_4_6_FN, FN_IP12_5_4, 4911 GP_4_5_FN, FN_IP12_3_2, 4912 GP_4_4_FN, FN_IP12_1_0, 4913 GP_4_3_FN, FN_IP11_31_30, 4914 GP_4_2_FN, FN_IP11_29_27, 4915 GP_4_1_FN, FN_IP11_26_24, 4916 GP_4_0_FN, FN_IP11_23_22 } 4917 }, 4918 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { 4919 GP_5_31_FN, FN_IP7_24_22, 4920 GP_5_30_FN, FN_IP7_21_19, 4921 GP_5_29_FN, FN_IP7_18_16, 4922 GP_5_28_FN, FN_DU_DOTCLKIN2, 4923 GP_5_27_FN, FN_IP7_26_25, 4924 GP_5_26_FN, FN_DU_DOTCLKIN0, 4925 GP_5_25_FN, FN_AVS2, 4926 GP_5_24_FN, FN_AVS1, 4927 GP_5_23_FN, FN_USB2_OVC, 4928 GP_5_22_FN, FN_USB2_PWEN, 4929 GP_5_21_FN, FN_IP16_7, 4930 GP_5_20_FN, FN_IP16_6, 4931 GP_5_19_FN, FN_USB0_OVC_VBUS, 4932 GP_5_18_FN, FN_USB0_PWEN, 4933 GP_5_17_FN, FN_IP16_5_3, 4934 GP_5_16_FN, FN_IP16_2_0, 4935 GP_5_15_FN, FN_IP15_29_28, 4936 GP_5_14_FN, FN_IP15_27_26, 4937 GP_5_13_FN, FN_IP15_25_23, 4938 GP_5_12_FN, FN_IP15_22_20, 4939 GP_5_11_FN, FN_IP15_19_18, 4940 GP_5_10_FN, FN_IP15_17_16, 4941 GP_5_9_FN, FN_IP15_15_14, 4942 GP_5_8_FN, FN_IP15_13_12, 4943 GP_5_7_FN, FN_IP15_11_9, 4944 GP_5_6_FN, FN_IP15_8_6, 4945 GP_5_5_FN, FN_IP15_5_3, 4946 GP_5_4_FN, FN_IP15_2_0, 4947 GP_5_3_FN, FN_IP14_30_28, 4948 GP_5_2_FN, FN_IP14_27_25, 4949 GP_5_1_FN, FN_IP14_24_22, 4950 GP_5_0_FN, FN_IP14_21_19 } 4951 }, 4952 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 4953 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { 4954 /* IP0_31 [1] */ 4955 0, 0, 4956 /* IP0_30_27 [4] */ 4957 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0, 4958 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, 4959 0, 0, 0, 0, 0, 0, 0, 0, 0, 4960 /* IP0_26_23 [4] */ 4961 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, 4962 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, 4963 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0, 4964 /* IP0_22_20 [3] */ 4965 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, 4966 FN_I2C2_SCL_C, 0, 0, 4967 /* IP0_19_16 [4] */ 4968 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, 4969 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, 4970 0, 0, 0, 0, 0, 0, 0, 0, 0, 4971 /* IP0_15_12 [4] */ 4972 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, 4973 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, 4974 0, 0, 0, 0, 0, 0, 0, 0, 0, 4975 /* IP0_11_9 [3] */ 4976 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, 4977 0, 0, 0, 4978 /* IP0_8_6 [3] */ 4979 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B, 4980 0, 0, 0, 4981 /* IP0_5_3 [3] */ 4982 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B, 4983 0, 0, 0, 4984 /* IP0_2_0 [3] */ 4985 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, 4986 0, 0, 0, } 4987 }, 4988 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, 4989 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) { 4990 /* IP1_31_30 [2] */ 4991 0, 0, 0, 0, 4992 /* IP1_29_28 [2] */ 4993 FN_A1, FN_PWM4, 0, 0, 4994 /* IP1_27_26 [2] */ 4995 FN_A0, FN_PWM3, 0, 0, 4996 /* IP1_25_22 [4] */ 4997 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, 4998 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, 4999 0, 0, 0, 0, 0, 0, 0, 0, 0, 5000 /* IP1_21_18 [4] */ 5001 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, 5002 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, 5003 0, 0, 0, 0, 0, 0, 0, 0, 0, 5004 /* IP1_17_15 [3] */ 5005 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, 5006 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, 5007 0, 0, 0, 5008 /* IP1_14_12 [3] */ 5009 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, 5010 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, 5011 0, 0, 5012 /* IP1_11_8 [4] */ 5013 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0, 5014 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, 5015 0, 0, 0, 0, 0, 0, 0, 0, 0, 5016 /* IP1_7_4 [4] */ 5017 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0, 5018 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, 5019 0, 0, 0, 0, 0, 0, 0, 0, 0, 5020 /* IP1_3_0 [4] */ 5021 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0, 5022 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, 5023 0, 0, 0, 0, 0, 0, 0, 0, 0, } 5024 }, 5025 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 5026 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) { 5027 /* IP2_31_29 [3] */ 5028 0, 0, 0, 0, 0, 0, 0, 0, 5029 /* IP2_28_26 [3] */ 5030 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, 5031 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, 5032 /* IP2_25_22 [4] */ 5033 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, 5034 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, 5035 0, 0, 0, 0, 0, 0, 0, 0, 5036 /* IP2_21_18 [4] */ 5037 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, 5038 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, 5039 0, 0, 0, 0, 0, 0, 0, 0, 5040 /* IP2_17_15 [3] */ 5041 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, 5042 0, 0, 0, 0, 5043 /* IP2_14_12 [3] */ 5044 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0, 5045 /* IP2_11_9 [3] */ 5046 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0, 5047 /* IP2_8_6 [3] */ 5048 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0, 5049 /* IP2_5_3 [3] */ 5050 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, 5051 /* IP2_2_0 [3] */ 5052 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, } 5053 }, 5054 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, 5055 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) { 5056 /* IP3_31_29 [3] */ 5057 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, 5058 0, 0, 0, 5059 /* IP3_28_26 [3] */ 5060 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B, 5061 0, 0, 0, 0, 5062 /* IP3_25_23 [3] */ 5063 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0, 5064 /* IP3_22_20 [3] */ 5065 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0, 5066 /* IP3_19_18 [2] */ 5067 FN_A16, FN_ATAWR1_N, 0, 0, 5068 /* IP3_17_15 [3] */ 5069 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2, 5070 0, 0, 0, 0, 5071 /* IP3_14_12 [3] */ 5072 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1, 5073 0, 0, 0, 0, 5074 /* IP3_11_8 [4] */ 5075 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, 5076 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, 5077 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0, 5078 /* IP3_7_4 [4] */ 5079 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, 5080 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, 5081 0, 0, 0, 0, 0, 0, 0, 0, 0, 5082 /* IP3_3_0 [4] */ 5083 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, 5084 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, 5085 0, 0, 0, 0, 0, 0, 0, 0, } 5086 }, 5087 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 5088 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 5089 /* IP4_31_30 [2] */ 5090 0, 0, 0, 0, 5091 /* IP4_29_27 [3] */ 5092 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, 5093 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0, 5094 /* IP4_26_24 [3] */ 5095 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD, 5096 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0, 5097 /* IP4_23_21 [3] */ 5098 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, 5099 FN_HTX0_B, FN_MSIOF0_SS1_B, 0, 5100 /* IP4_20_18 [3] */ 5101 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, 5102 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0, 5103 /* IP4_17_15 [3] */ 5104 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, 5105 0, 0, 0, 5106 /* IP4_14_12 [3] */ 5107 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD, 5108 FN_VI2_FIELD_B, 0, 0, 5109 /* IP4_11_9 [3] */ 5110 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, 5111 FN_VI2_CLKENB_B, 0, 0, 5112 /* IP4_8_6 [3] */ 5113 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0, 5114 /* IP4_5_3 [3] */ 5115 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, 5116 /* IP4_2_0 [3] */ 5117 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, 5118 } 5119 }, 5120 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 5121 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) { 5122 /* IP5_31_30 [2] */ 5123 0, 0, 0, 0, 5124 /* IP5_29_27 [3] */ 5125 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, 5126 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, 5127 /* IP5_26_24 [3] */ 5128 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, 5129 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, 5130 FN_MSIOF0_SCK_B, 0, 5131 /* IP5_23_21 [3] */ 5132 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, 5133 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C, 5134 /* IP5_20_18 [3] */ 5135 FN_WE0_N, FN_IECLK, FN_CAN_CLK, 5136 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, 5137 /* IP5_17_15 [3] */ 5138 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, 5139 FN_INTC_IRQ4_N, 0, 0, 5140 /* IP5_14_13 [2] */ 5141 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, 5142 /* IP5_12_10 [3] */ 5143 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C, 5144 0, 0, 5145 /* IP5_9_6 [4] */ 5146 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, 5147 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, 5148 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0, 5149 /* IP5_5_3 [3] */ 5150 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, 5151 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, 5152 FN_INTC_EN0_N, FN_I2C1_SCL, 5153 /* IP5_2_0 [3] */ 5154 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, 5155 FN_VI2_R3, 0, 0, } 5156 }, 5157 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 5158 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { 5159 /* IP6_31_29 [3] */ 5160 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E, 5161 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, 5162 /* IP6_28_26 [3] */ 5163 FN_ETH_LINK, 0, FN_HTX0_E, 5164 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, 5165 /* IP6_25_23 [3] */ 5166 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B, 5167 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, 5168 /* IP6_22_20 [3] */ 5169 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, 5170 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, 5171 /* IP6_19_17 [3] */ 5172 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B, 5173 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0, 5174 /* IP6_16_14 [3] */ 5175 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B, 5176 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, 5177 FN_I2C2_SCL_E, 0, 5178 /* IP6_13_11 [3] */ 5179 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, 5180 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, 5181 /* IP6_10_9 [2] */ 5182 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, 5183 /* IP6_8_6 [3] */ 5184 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, 5185 FN_SSI_SDATA8_C, 0, 0, 0, 5186 /* IP6_5_3 [3] */ 5187 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, 5188 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, 5189 /* IP6_2_0 [3] */ 5190 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, 5191 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } 5192 }, 5193 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 5194 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { 5195 /* IP7_31 [1] */ 5196 0, 0, 5197 /* IP7_30_29 [2] */ 5198 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0, 5199 /* IP7_28_27 [2] */ 5200 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0, 5201 /* IP7_26_25 [2] */ 5202 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, 5203 /* IP7_24_22 [3] */ 5204 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, 5205 0, 0, 0, 5206 /* IP7_21_19 [3] */ 5207 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, 5208 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, 5209 /* IP7_18_16 [3] */ 5210 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, 5211 FN_GLO_SS_C, 0, 0, 0, 5212 /* IP7_15_13 [3] */ 5213 FN_ETH_MDC, 0, FN_STP_ISD_1_B, 5214 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, 5215 /* IP7_12_10 [3] */ 5216 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, 5217 FN_GLO_SCLK_C, 0, 0, 0, 5218 /* IP7_9_8 [2] */ 5219 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0, 5220 /* IP7_7_6 [2] */ 5221 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F, 5222 /* IP7_5_3 [3] */ 5223 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0, 5224 /* IP7_2_0 [3] */ 5225 FN_ETH_MDIO, 0, FN_HRTS0_N_E, 5226 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } 5227 }, 5228 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 5229 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 5230 2, 2, 2, 2, 2, 2, 2) { 5231 /* IP8_31 [1] */ 5232 0, 0, 5233 /* IP8_30_29 [2] */ 5234 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0, 5235 /* IP8_28 [1] */ 5236 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, 5237 /* IP8_27 [1] */ 5238 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, 5239 /* IP8_26 [1] */ 5240 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, 5241 /* IP8_25_24 [2] */ 5242 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, 5243 FN_AVB_MAGIC, 0, 5244 /* IP8_23_22 [2] */ 5245 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, 5246 /* IP8_21_20 [2] */ 5247 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0, 5248 /* IP8_19_18 [2] */ 5249 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0, 5250 /* IP8_17_16 [2] */ 5251 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0, 5252 /* IP8_15_14 [2] */ 5253 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0, 5254 /* IP8_13_12 [2] */ 5255 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0, 5256 /* IP8_11_10 [2] */ 5257 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0, 5258 /* IP8_9_8 [2] */ 5259 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, 5260 /* IP8_7_6 [2] */ 5261 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0, 5262 /* IP8_5_4 [2] */ 5263 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0, 5264 /* IP8_3_2 [2] */ 5265 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, 5266 /* IP8_1_0 [2] */ 5267 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, } 5268 }, 5269 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 5270 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { 5271 /* IP9_31_28 [4] */ 5272 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, 5273 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, 5274 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, 5275 /* IP9_27_26 [2] */ 5276 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B, 5277 /* IP9_25_24 [2] */ 5278 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B, 5279 /* IP9_23_22 [2] */ 5280 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B, 5281 /* IP9_21_20 [2] */ 5282 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B, 5283 /* IP9_19_18 [2] */ 5284 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B, 5285 /* IP9_17_16 [2] */ 5286 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0, 5287 /* IP9_15_12 [4] */ 5288 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, 5289 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, 5290 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, 5291 /* IP9_11_8 [4] */ 5292 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, 5293 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, 5294 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, 5295 /* IP9_7_6 [2] */ 5296 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, 5297 /* IP9_5_4 [2] */ 5298 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0, 5299 /* IP9_3_2 [2] */ 5300 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, 5301 /* IP9_1_0 [2] */ 5302 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } 5303 }, 5304 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 5305 2, 4, 3, 4, 4, 4, 4, 3, 4) { 5306 /* IP10_31_30 [2] */ 5307 0, 0, 0, 0, 5308 /* IP10_29_26 [4] */ 5309 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, 5310 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, 5311 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0, 5312 /* IP10_25_23 [3] */ 5313 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, 5314 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, 5315 /* IP10_22_19 [4] */ 5316 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0, 5317 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, 5318 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, 5319 /* IP10_18_15 [4] */ 5320 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0, 5321 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, 5322 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, 5323 0, 0, 0, 0, 0, 0, 5324 /* IP10_14_11 [4] */ 5325 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, 5326 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, 5327 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, 5328 0, 0, 0, 0, 0, 0, 0, 5329 /* IP10_10_7 [4] */ 5330 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, 5331 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, 5332 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, 5333 0, 0, 0, 0, 0, 0, 0, 5334 /* IP10_6_4 [3] */ 5335 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, 5336 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, 5337 FN_VI3_DATA0_B, 0, 5338 /* IP10_3_0 [4] */ 5339 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, 5340 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, 5341 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } 5342 }, 5343 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 5344 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) { 5345 /* IP11_31_30 [2] */ 5346 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, 5347 /* IP11_29_27 [3] */ 5348 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, 5349 0, 0, 0, 5350 /* IP11_26_24 [3] */ 5351 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B, 5352 0, 0, 0, 5353 /* IP11_23_22 [2] */ 5354 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0, 5355 /* IP11_21_18 [4] */ 5356 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, 5357 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0, 5358 /* IP11_17_15 [3] */ 5359 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, 5360 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, 5361 /* IP11_14_13 [2] */ 5362 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0, 5363 /* IP11_12_11 [2] */ 5364 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0, 5365 /* IP11_10_9 [2] */ 5366 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0, 5367 /* IP11_8_7 [2] */ 5368 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0, 5369 /* IP11_6_5 [2] */ 5370 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0, 5371 /* IP11_4 [1] */ 5372 FN_SD3_CLK, FN_MMC1_CLK, 5373 /* IP11_3_0 [4] */ 5374 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, 5375 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, 5376 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } 5377 }, 5378 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 5379 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) { 5380 /* IP12_31 [1] */ 5381 0, 0, 5382 /* IP12_30_28 [3] */ 5383 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B, 5384 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, 5385 FN_CAN_DEBUGOUT4, 0, 0, 5386 /* IP12_27_25 [3] */ 5387 FN_SSI_SCK5, FN_SCIFB1_SCK, 5388 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, 5389 FN_CAN_DEBUGOUT3, 0, 0, 5390 /* IP12_24_23 [2] */ 5391 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, 5392 FN_CAN_DEBUGOUT2, 5393 /* IP12_22_20 [3] */ 5394 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, 5395 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0, 5396 /* IP12_19_17 [3] */ 5397 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, 5398 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0, 5399 /* IP12_16_14 [3] */ 5400 FN_SSI_SDATA3, FN_STP_ISCLK_0, 5401 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0, 5402 /* IP12_13_11 [3] */ 5403 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, 5404 FN_CAN_STEP0, 0, 0, 0, 5405 /* IP12_10_8 [3] */ 5406 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, 5407 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0, 5408 /* IP12_7_6 [2] */ 5409 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, 5410 /* IP12_5_4 [2] */ 5411 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0, 5412 /* IP12_3_2 [2] */ 5413 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, 5414 /* IP12_1_0 [2] */ 5415 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, } 5416 }, 5417 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 5418 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) { 5419 /* IP13_31 [1] */ 5420 0, 0, 5421 /* IP13_30_29 [2] */ 5422 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0, 5423 /* IP13_28_26 [3] */ 5424 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, 5425 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0, 5426 /* IP13_25_23 [3] */ 5427 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, 5428 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0, 5429 /* IP13_22_19 [4] */ 5430 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, 5431 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E, 5432 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0, 5433 /* IP13_18_16 [3] */ 5434 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, 5435 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0, 5436 /* IP13_15_13 [3] */ 5437 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK, 5438 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0, 5439 /* IP13_12_10 [3] */ 5440 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5, 5441 FN_CAN_DEBUGOUT8, 0, 0, 5442 /* IP13_9_7 [3] */ 5443 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, 5444 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0, 5445 /* IP13_6_3 [4] */ 5446 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0, 5447 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, 5448 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0, 5449 /* IP13_2_0 [3] */ 5450 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, 5451 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } 5452 }, 5453 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, 5454 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) { 5455 /* IP14_30 [1] */ 5456 0, 0, 5457 /* IP14_30_28 [3] */ 5458 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, 5459 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, 5460 FN_HRTS0_N_C, 0, 5461 /* IP14_27_25 [3] */ 5462 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD, 5463 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0, 5464 /* IP14_24_22 [3] */ 5465 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, 5466 FN_LCDOUT9, 0, 0, 0, 5467 /* IP14_21_19 [3] */ 5468 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, 5469 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, 5470 /* IP14_18_16 [3] */ 5471 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, 5472 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, 5473 /* IP14_15_12 [4] */ 5474 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, 5475 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, 5476 0, 0, 0, 0, 0, 0, 0, 5477 /* IP14_11_9 [3] */ 5478 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, 5479 0, 0, 0, 5480 /* IP14_8_6 [3] */ 5481 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0, 5482 0, 0, 0, 5483 /* IP14_5_3 [3] */ 5484 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, 5485 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C, 5486 /* IP14_2_0 [3] */ 5487 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, 5488 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, 5489 FN_REMOCON, 0, } 5490 }, 5491 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, 5492 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) { 5493 /* IP15_31_30 [2] */ 5494 0, 0, 0, 0, 5495 /* IP15_29_28 [2] */ 5496 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14, 5497 /* IP15_27_26 [2] */ 5498 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13, 5499 /* IP15_25_23 [3] */ 5500 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA, 5501 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0, 5502 /* IP15_22_20 [3] */ 5503 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, 5504 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0, 5505 /* IP15_19_18 [2] */ 5506 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21, 5507 /* IP15_17_16 [2] */ 5508 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20, 5509 /* IP15_15_14 [2] */ 5510 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0, 5511 /* IP15_13_12 [2] */ 5512 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0, 5513 /* IP15_11_9 [3] */ 5514 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, 5515 0, 0, 0, 5516 /* IP15_8_6 [3] */ 5517 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, 5518 FN_IIC2_SDA, FN_I2C2_SDA, 0, 5519 /* IP15_5_3 [3] */ 5520 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16, 5521 FN_IIC2_SCL, FN_I2C2_SCL, 0, 5522 /* IP15_2_0 [3] */ 5523 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, 5524 FN_LCDOUT15, FN_SCIF_CLK_B, 0, } 5525 }, 5526 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, 5527 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) { 5528 /* IP16_31_28 [4] */ 5529 0, 0, 0, 0, 0, 0, 0, 0, 5530 0, 0, 0, 0, 0, 0, 0, 0, 5531 /* IP16_27_24 [4] */ 5532 0, 0, 0, 0, 0, 0, 0, 0, 5533 0, 0, 0, 0, 0, 0, 0, 0, 5534 /* IP16_23_20 [4] */ 5535 0, 0, 0, 0, 0, 0, 0, 0, 5536 0, 0, 0, 0, 0, 0, 0, 0, 5537 /* IP16_19_16 [4] */ 5538 0, 0, 0, 0, 0, 0, 0, 0, 5539 0, 0, 0, 0, 0, 0, 0, 0, 5540 /* IP16_15_12 [4] */ 5541 0, 0, 0, 0, 0, 0, 0, 0, 5542 0, 0, 0, 0, 0, 0, 0, 0, 5543 /* IP16_11_8 [4] */ 5544 0, 0, 0, 0, 0, 0, 0, 0, 5545 0, 0, 0, 0, 0, 0, 0, 0, 5546 /* IP16_7 [1] */ 5547 FN_USB1_OVC, FN_TCLK1_B, 5548 /* IP16_6 [1] */ 5549 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, 5550 /* IP16_5_3 [3] */ 5551 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, 5552 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0, 5553 /* IP16_2_0 [3] */ 5554 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, 5555 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } 5556 }, 5557 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 5558 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 5559 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { 5560 /* SEL_SCIF1 [3] */ 5561 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 5562 FN_SEL_SCIF1_4, 0, 0, 0, 5563 /* SEL_SCIFB [2] */ 5564 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0, 5565 /* SEL_SCIFB2 [2] */ 5566 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0, 5567 /* SEL_SCIFB1 [3] */ 5568 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, 5569 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5, 5570 FN_SEL_SCIFB1_6, 0, 5571 /* SEL_SCIFA1 [2] */ 5572 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 5573 FN_SEL_SCIFA1_3, 5574 /* SEL_SCIF0 [1] */ 5575 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, 5576 /* SEL_SCIFA [1] */ 5577 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 5578 /* SEL_SOF1 [1] */ 5579 FN_SEL_SOF1_0, FN_SEL_SOF1_1, 5580 /* SEL_SSI7 [2] */ 5581 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, 5582 /* SEL_SSI6 [1] */ 5583 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 5584 /* SEL_SSI5 [2] */ 5585 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0, 5586 /* SEL_VI3 [1] */ 5587 FN_SEL_VI3_0, FN_SEL_VI3_1, 5588 /* SEL_VI2 [1] */ 5589 FN_SEL_VI2_0, FN_SEL_VI2_1, 5590 /* SEL_VI1 [1] */ 5591 FN_SEL_VI1_0, FN_SEL_VI1_1, 5592 /* SEL_VI0 [1] */ 5593 FN_SEL_VI0_0, FN_SEL_VI0_1, 5594 /* SEL_TSIF1 [2] */ 5595 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0, 5596 /* RESERVED [1] */ 5597 0, 0, 5598 /* SEL_LBS [1] */ 5599 FN_SEL_LBS_0, FN_SEL_LBS_1, 5600 /* SEL_TSIF0 [2] */ 5601 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 5602 /* SEL_SOF3 [1] */ 5603 FN_SEL_SOF3_0, FN_SEL_SOF3_1, 5604 /* SEL_SOF0 [1] */ 5605 FN_SEL_SOF0_0, FN_SEL_SOF0_1, } 5606 }, 5607 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 5608 3, 1, 1, 1, 2, 1, 2, 1, 2, 5609 1, 1, 1, 3, 3, 2, 3, 2, 2) { 5610 /* RESERVED [3] */ 5611 0, 0, 0, 0, 0, 0, 0, 0, 5612 /* SEL_TMU1 [1] */ 5613 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 5614 /* SEL_HSCIF1 [1] */ 5615 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 5616 /* SEL_SCIFCLK [1] */ 5617 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, 5618 /* SEL_CAN0 [2] */ 5619 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 5620 /* SEL_CANCLK [1] */ 5621 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 5622 /* SEL_SCIFA2 [2] */ 5623 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0, 5624 /* SEL_CAN1 [1] */ 5625 FN_SEL_CAN1_0, FN_SEL_CAN1_1, 5626 /* RESERVED [2] */ 5627 0, 0, 0, 0, 5628 /* SEL_SCIF2 [1] */ 5629 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, 5630 /* SEL_ADI [1] */ 5631 FN_SEL_ADI_0, FN_SEL_ADI_1, 5632 /* SEL_SSP [1] */ 5633 FN_SEL_SSP_0, FN_SEL_SSP_1, 5634 /* SEL_FM [3] */ 5635 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, 5636 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0, 5637 /* SEL_HSCIF0 [3] */ 5638 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 5639 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, 5640 /* SEL_GPS [2] */ 5641 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, 5642 /* RESERVED [3] */ 5643 0, 0, 0, 0, 0, 0, 0, 0, 5644 /* SEL_SIM [2] */ 5645 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, 5646 /* SEL_SSI8 [2] */ 5647 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } 5648 }, 5649 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 5650 1, 1, 2, 4, 4, 2, 2, 5651 4, 2, 3, 2, 3, 2) { 5652 /* SEL_IICDVFS [1] */ 5653 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, 5654 /* SEL_IIC0 [1] */ 5655 FN_SEL_IIC0_0, FN_SEL_IIC0_1, 5656 /* RESERVED [2] */ 5657 0, 0, 0, 0, 5658 /* RESERVED [4] */ 5659 0, 0, 0, 0, 0, 0, 0, 0, 5660 0, 0, 0, 0, 0, 0, 0, 0, 5661 /* RESERVED [4] */ 5662 0, 0, 0, 0, 0, 0, 0, 0, 5663 0, 0, 0, 0, 0, 0, 0, 0, 5664 /* RESERVED [2] */ 5665 0, 0, 0, 0, 5666 /* SEL_IEB [2] */ 5667 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, 5668 /* RESERVED [4] */ 5669 0, 0, 0, 0, 0, 0, 0, 0, 5670 0, 0, 0, 0, 0, 0, 0, 0, 5671 /* RESERVED [2] */ 5672 0, 0, 0, 0, 5673 /* SEL_IIC2 [3] */ 5674 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, 5675 FN_SEL_IIC2_4, 0, 0, 0, 5676 /* SEL_IIC1 [2] */ 5677 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, 5678 /* SEL_I2C2 [3] */ 5679 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 5680 FN_SEL_I2C2_4, 0, 0, 0, 5681 /* SEL_I2C1 [2] */ 5682 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } 5683 }, 5684 { }, 5685 }; 5686 5687 const struct sh_pfc_soc_info r8a7790_pinmux_info = { 5688 .name = "r8a77900_pfc", 5689 .unlock_reg = 0xe6060000, /* PMMR */ 5690 5691 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5692 5693 .pins = pinmux_pins, 5694 .nr_pins = ARRAY_SIZE(pinmux_pins), 5695 .groups = pinmux_groups, 5696 .nr_groups = ARRAY_SIZE(pinmux_groups), 5697 .functions = pinmux_functions, 5698 .nr_functions = ARRAY_SIZE(pinmux_functions), 5699 5700 .cfg_regs = pinmux_config_regs, 5701 5702 .pinmux_data = pinmux_data, 5703 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5704 }; 5705