1 /* 2 * Copyright (C) 2014 Free Electrons 3 * Copyright (C) 2014 Atmel 4 * 5 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef DRM_ATMEL_HLCDC_LAYER_H 21 #define DRM_ATMEL_HLCDC_LAYER_H 22 23 #include <linux/mfd/atmel-hlcdc.h> 24 25 #include <drm/drm_crtc.h> 26 #include <drm/drm_flip_work.h> 27 #include <drm/drmP.h> 28 29 #define ATMEL_HLCDC_LAYER_CHER 0x0 30 #define ATMEL_HLCDC_LAYER_CHDR 0x4 31 #define ATMEL_HLCDC_LAYER_CHSR 0x8 32 #define ATMEL_HLCDC_LAYER_DMA_CHAN BIT(0) 33 #define ATMEL_HLCDC_LAYER_UPDATE BIT(1) 34 #define ATMEL_HLCDC_LAYER_A2Q BIT(2) 35 #define ATMEL_HLCDC_LAYER_RST BIT(8) 36 37 #define ATMEL_HLCDC_LAYER_IER 0xc 38 #define ATMEL_HLCDC_LAYER_IDR 0x10 39 #define ATMEL_HLCDC_LAYER_IMR 0x14 40 #define ATMEL_HLCDC_LAYER_ISR 0x18 41 #define ATMEL_HLCDC_LAYER_DFETCH BIT(0) 42 #define ATMEL_HLCDC_LAYER_LFETCH BIT(1) 43 #define ATMEL_HLCDC_LAYER_DMA_IRQ BIT(2) 44 #define ATMEL_HLCDC_LAYER_DSCR_IRQ BIT(3) 45 #define ATMEL_HLCDC_LAYER_ADD_IRQ BIT(4) 46 #define ATMEL_HLCDC_LAYER_DONE_IRQ BIT(5) 47 #define ATMEL_HLCDC_LAYER_OVR_IRQ BIT(6) 48 49 #define ATMEL_HLCDC_LAYER_PLANE_HEAD(n) (((n) * 0x10) + 0x1c) 50 #define ATMEL_HLCDC_LAYER_PLANE_ADDR(n) (((n) * 0x10) + 0x20) 51 #define ATMEL_HLCDC_LAYER_PLANE_CTRL(n) (((n) * 0x10) + 0x24) 52 #define ATMEL_HLCDC_LAYER_PLANE_NEXT(n) (((n) * 0x10) + 0x28) 53 #define ATMEL_HLCDC_LAYER_CFG(p, c) (((c) * 4) + ((p)->max_planes * 0x10) + 0x1c) 54 55 #define ATMEL_HLCDC_LAYER_DMA_CFG_ID 0 56 #define ATMEL_HLCDC_LAYER_DMA_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, ATMEL_HLCDC_LAYER_DMA_CFG_ID) 57 #define ATMEL_HLCDC_LAYER_DMA_SIF BIT(0) 58 #define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK GENMASK(5, 4) 59 #define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE (0 << 4) 60 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4 (1 << 4) 61 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8 (2 << 4) 62 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 (3 << 4) 63 #define ATMEL_HLCDC_LAYER_DMA_DLBO BIT(8) 64 #define ATMEL_HLCDC_LAYER_DMA_ROTDIS BIT(12) 65 #define ATMEL_HLCDC_LAYER_DMA_LOCKDIS BIT(13) 66 67 #define ATMEL_HLCDC_LAYER_FORMAT_CFG_ID 1 68 #define ATMEL_HLCDC_LAYER_FORMAT_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, ATMEL_HLCDC_LAYER_FORMAT_CFG_ID) 69 #define ATMEL_HLCDC_LAYER_RGB (0 << 0) 70 #define ATMEL_HLCDC_LAYER_CLUT (1 << 0) 71 #define ATMEL_HLCDC_LAYER_YUV (2 << 0) 72 #define ATMEL_HLCDC_RGB_MODE(m) (((m) & 0xf) << 4) 73 #define ATMEL_HLCDC_CLUT_MODE(m) (((m) & 0x3) << 8) 74 #define ATMEL_HLCDC_YUV_MODE(m) (((m) & 0xf) << 12) 75 #define ATMEL_HLCDC_YUV422ROT BIT(16) 76 #define ATMEL_HLCDC_YUV422SWP BIT(17) 77 #define ATMEL_HLCDC_DSCALEOPT BIT(20) 78 79 #define ATMEL_HLCDC_XRGB4444_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(0)) 80 #define ATMEL_HLCDC_ARGB4444_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(1)) 81 #define ATMEL_HLCDC_RGBA4444_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(2)) 82 #define ATMEL_HLCDC_RGB565_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(3)) 83 #define ATMEL_HLCDC_ARGB1555_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(4)) 84 #define ATMEL_HLCDC_XRGB8888_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(9)) 85 #define ATMEL_HLCDC_RGB888_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(10)) 86 #define ATMEL_HLCDC_ARGB8888_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(12)) 87 #define ATMEL_HLCDC_RGBA8888_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(13)) 88 89 #define ATMEL_HLCDC_AYUV_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(0)) 90 #define ATMEL_HLCDC_YUYV_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(1)) 91 #define ATMEL_HLCDC_UYVY_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(2)) 92 #define ATMEL_HLCDC_YVYU_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(3)) 93 #define ATMEL_HLCDC_VYUY_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(4)) 94 #define ATMEL_HLCDC_NV61_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(5)) 95 #define ATMEL_HLCDC_YUV422_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(6)) 96 #define ATMEL_HLCDC_NV21_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(7)) 97 #define ATMEL_HLCDC_YUV420_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(8)) 98 99 #define ATMEL_HLCDC_LAYER_POS_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.pos) 100 #define ATMEL_HLCDC_LAYER_SIZE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.size) 101 #define ATMEL_HLCDC_LAYER_MEMSIZE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.memsize) 102 #define ATMEL_HLCDC_LAYER_XSTRIDE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.xstride) 103 #define ATMEL_HLCDC_LAYER_PSTRIDE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.pstride) 104 #define ATMEL_HLCDC_LAYER_DFLTCOLOR_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.default_color) 105 #define ATMEL_HLCDC_LAYER_CRKEY_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.chroma_key) 106 #define ATMEL_HLCDC_LAYER_CRKEY_MASK_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.chroma_key_mask) 107 108 #define ATMEL_HLCDC_LAYER_GENERAL_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.general_config) 109 #define ATMEL_HLCDC_LAYER_CRKEY BIT(0) 110 #define ATMEL_HLCDC_LAYER_INV BIT(1) 111 #define ATMEL_HLCDC_LAYER_ITER2BL BIT(2) 112 #define ATMEL_HLCDC_LAYER_ITER BIT(3) 113 #define ATMEL_HLCDC_LAYER_REVALPHA BIT(4) 114 #define ATMEL_HLCDC_LAYER_GAEN BIT(5) 115 #define ATMEL_HLCDC_LAYER_LAEN BIT(6) 116 #define ATMEL_HLCDC_LAYER_OVR BIT(7) 117 #define ATMEL_HLCDC_LAYER_DMA BIT(8) 118 #define ATMEL_HLCDC_LAYER_REP BIT(9) 119 #define ATMEL_HLCDC_LAYER_DSTKEY BIT(10) 120 #define ATMEL_HLCDC_LAYER_DISCEN BIT(11) 121 #define ATMEL_HLCDC_LAYER_GA_SHIFT 16 122 #define ATMEL_HLCDC_LAYER_GA_MASK GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT) 123 #define ATMEL_HLCDC_LAYER_GA(x) ((x) << ATMEL_HLCDC_LAYER_GA_SHIFT) 124 125 #define ATMEL_HLCDC_LAYER_CSC_CFG(p, o) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.csc + o) 126 127 #define ATMEL_HLCDC_LAYER_DISC_POS_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.disc_pos) 128 129 #define ATMEL_HLCDC_LAYER_DISC_SIZE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.disc_size) 130 131 #define ATMEL_HLCDC_MAX_PLANES 3 132 133 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED BIT(0) 134 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED BIT(1) 135 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE BIT(2) 136 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN BIT(3) 137 138 /** 139 * Atmel HLCDC Layer registers layout structure 140 * 141 * Each HLCDC layer has its own register organization and a given register 142 * can be placed differently on 2 different layers depending on its 143 * capabilities. 144 * This structure stores common registers layout for a given layer and is 145 * used by HLCDC layer code to choose the appropriate register to write to 146 * or to read from. 147 * 148 * For all fields, a value of zero means "unsupported". 149 * 150 * See Atmel's datasheet for a detailled description of these registers. 151 * 152 * @xstride: xstride registers 153 * @pstride: pstride registers 154 * @pos: position register 155 * @size: displayed size register 156 * @memsize: memory size register 157 * @default_color: default color register 158 * @chroma_key: chroma key register 159 * @chroma_key_mask: chroma key mask register 160 * @general_config: general layer config register 161 * @disc_pos: discard area position register 162 * @disc_size: discard area size register 163 * @csc: color space conversion register 164 */ 165 struct atmel_hlcdc_layer_cfg_layout { 166 int xstride[ATMEL_HLCDC_MAX_PLANES]; 167 int pstride[ATMEL_HLCDC_MAX_PLANES]; 168 int pos; 169 int size; 170 int memsize; 171 int default_color; 172 int chroma_key; 173 int chroma_key_mask; 174 int general_config; 175 int disc_pos; 176 int disc_size; 177 int csc; 178 }; 179 180 /** 181 * Atmel HLCDC framebuffer flip structure 182 * 183 * This structure is allocated when someone asked for a layer update (most 184 * likely a DRM plane update, either primary, overlay or cursor plane) and 185 * released when the layer do not need to reference the framebuffer object 186 * anymore (i.e. the layer was disabled or updated). 187 * 188 * @dscrs: DMA descriptors 189 * @fb: the referenced framebuffer object 190 * @ngems: number of GEM objects referenced by the fb element 191 * @status: fb flip operation status 192 */ 193 struct atmel_hlcdc_layer_fb_flip { 194 struct atmel_hlcdc_dma_channel_dscr *dscrs[ATMEL_HLCDC_MAX_PLANES]; 195 struct drm_flip_task *task; 196 struct drm_framebuffer *fb; 197 int ngems; 198 u32 status; 199 }; 200 201 /** 202 * Atmel HLCDC DMA descriptor structure 203 * 204 * This structure is used by the HLCDC DMA engine to schedule a DMA transfer. 205 * 206 * The structure fields must remain in this specific order, because they're 207 * used by the HLCDC DMA engine, which expect them in this order. 208 * HLCDC DMA descriptors must be aligned on 64 bits. 209 * 210 * @addr: buffer DMA address 211 * @ctrl: DMA transfer options 212 * @next: next DMA descriptor to fetch 213 * @gem_flip: the attached gem_flip operation 214 */ 215 struct atmel_hlcdc_dma_channel_dscr { 216 dma_addr_t addr; 217 u32 ctrl; 218 dma_addr_t next; 219 u32 status; 220 } __aligned(sizeof(u64)); 221 222 /** 223 * Atmel HLCDC layer types 224 */ 225 enum atmel_hlcdc_layer_type { 226 ATMEL_HLCDC_BASE_LAYER, 227 ATMEL_HLCDC_OVERLAY_LAYER, 228 ATMEL_HLCDC_CURSOR_LAYER, 229 ATMEL_HLCDC_PP_LAYER, 230 }; 231 232 /** 233 * Atmel HLCDC Supported formats structure 234 * 235 * This structure list all the formats supported by a given layer. 236 * 237 * @nformats: number of supported formats 238 * @formats: supported formats 239 */ 240 struct atmel_hlcdc_formats { 241 int nformats; 242 uint32_t *formats; 243 }; 244 245 /** 246 * Atmel HLCDC Layer description structure 247 * 248 * This structure describe the capabilities provided by a given layer. 249 * 250 * @name: layer name 251 * @type: layer type 252 * @id: layer id 253 * @regs_offset: offset of the layer registers from the HLCDC registers base 254 * @nconfigs: number of config registers provided by this layer 255 * @formats: supported formats 256 * @layout: config registers layout 257 * @max_width: maximum width supported by this layer (0 means unlimited) 258 * @max_height: maximum height supported by this layer (0 means unlimited) 259 */ 260 struct atmel_hlcdc_layer_desc { 261 const char *name; 262 enum atmel_hlcdc_layer_type type; 263 int id; 264 int regs_offset; 265 int nconfigs; 266 struct atmel_hlcdc_formats *formats; 267 struct atmel_hlcdc_layer_cfg_layout layout; 268 int max_width; 269 int max_height; 270 }; 271 272 /** 273 * Atmel HLCDC Layer Update Slot structure 274 * 275 * This structure stores layer update requests to be applied on next frame. 276 * This is the base structure behind the atomic layer update infrastructure. 277 * 278 * Atomic layer update provides a way to update all layer's parameters 279 * simultaneously. This is needed to avoid incompatible sequential updates 280 * like this one: 281 * 1) update layer format from RGB888 (1 plane/buffer) to YUV422 282 * (2 planes/buffers) 283 * 2) the format update is applied but the DMA channel for the second 284 * plane/buffer is not enabled 285 * 3) enable the DMA channel for the second plane 286 * 287 * @fb_flip: fb_flip object 288 * @updated_configs: bitmask used to record modified configs 289 * @configs: new config values 290 */ 291 struct atmel_hlcdc_layer_update_slot { 292 struct atmel_hlcdc_layer_fb_flip *fb_flip; 293 unsigned long *updated_configs; 294 u32 *configs; 295 }; 296 297 /** 298 * Atmel HLCDC Layer Update structure 299 * 300 * This structure provides a way to queue layer update requests. 301 * 302 * At a given time there is at most: 303 * - one pending update request, which means the update request has been 304 * committed (or validated) and is waiting for the DMA channel(s) to be 305 * available 306 * - one request being prepared, which means someone started a layer update 307 * but has not committed it yet. There cannot be more than one started 308 * request, because the update lock is taken when starting a layer update 309 * and release when committing or rolling back the request. 310 * 311 * @slots: update slots. One is used for pending request and the other one 312 * for started update request 313 * @pending: the pending slot index or -1 if no request is pending 314 * @next: the started update slot index or -1 no update has been started 315 */ 316 struct atmel_hlcdc_layer_update { 317 struct atmel_hlcdc_layer_update_slot slots[2]; 318 int pending; 319 int next; 320 }; 321 322 enum atmel_hlcdc_layer_dma_channel_status { 323 ATMEL_HLCDC_LAYER_DISABLED, 324 ATMEL_HLCDC_LAYER_ENABLED, 325 ATMEL_HLCDC_LAYER_DISABLING, 326 }; 327 328 /** 329 * Atmel HLCDC Layer DMA channel structure 330 * 331 * This structure stores information on the DMA channel associated to a 332 * given layer. 333 * 334 * @status: DMA channel status 335 * @cur: current framebuffer 336 * @queue: next framebuffer 337 * @dscrs: allocated DMA descriptors 338 */ 339 struct atmel_hlcdc_layer_dma_channel { 340 enum atmel_hlcdc_layer_dma_channel_status status; 341 struct atmel_hlcdc_layer_fb_flip *cur; 342 struct atmel_hlcdc_layer_fb_flip *queue; 343 struct atmel_hlcdc_dma_channel_dscr *dscrs; 344 }; 345 346 /** 347 * Atmel HLCDC Layer structure 348 * 349 * This structure stores information on the layer instance. 350 * 351 * @desc: layer description 352 * @max_planes: maximum planes/buffers that can be associated with this layer. 353 * This depends on the supported formats. 354 * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device 355 * @dma: dma channel 356 * @gc: fb flip garbage collector 357 * @update: update handler 358 * @lock: layer lock 359 */ 360 struct atmel_hlcdc_layer { 361 const struct atmel_hlcdc_layer_desc *desc; 362 int max_planes; 363 struct atmel_hlcdc *hlcdc; 364 struct workqueue_struct *wq; 365 struct drm_flip_work gc; 366 struct atmel_hlcdc_layer_dma_channel dma; 367 struct atmel_hlcdc_layer_update update; 368 spinlock_t lock; 369 }; 370 371 void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer); 372 373 int atmel_hlcdc_layer_init(struct drm_device *dev, 374 struct atmel_hlcdc_layer *layer, 375 const struct atmel_hlcdc_layer_desc *desc); 376 377 void atmel_hlcdc_layer_cleanup(struct drm_device *dev, 378 struct atmel_hlcdc_layer *layer); 379 380 void atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer); 381 382 int atmel_hlcdc_layer_update_start(struct atmel_hlcdc_layer *layer); 383 384 void atmel_hlcdc_layer_update_cfg(struct atmel_hlcdc_layer *layer, int cfg, 385 u32 mask, u32 val); 386 387 void atmel_hlcdc_layer_update_set_fb(struct atmel_hlcdc_layer *layer, 388 struct drm_framebuffer *fb, 389 unsigned int *offsets); 390 391 void atmel_hlcdc_layer_update_set_finished(struct atmel_hlcdc_layer *layer, 392 void (*finished)(void *data), 393 void *finished_data); 394 395 void atmel_hlcdc_layer_update_rollback(struct atmel_hlcdc_layer *layer); 396 397 void atmel_hlcdc_layer_update_commit(struct atmel_hlcdc_layer *layer); 398 399 #endif /* DRM_ATMEL_HLCDC_LAYER_H */ 400