1 /* 2 * ARIZONA register definitions 3 * 4 * Copyright 2012 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef _ARIZONA_REGISTERS_H 14 #define _ARIZONA_REGISTERS_H 15 16 /* 17 * Register values. 18 */ 19 #define ARIZONA_SOFTWARE_RESET 0x00 20 #define ARIZONA_DEVICE_REVISION 0x01 21 #define ARIZONA_CTRL_IF_SPI_CFG_1 0x08 22 #define ARIZONA_CTRL_IF_I2C1_CFG_1 0x09 23 #define ARIZONA_CTRL_IF_I2C2_CFG_1 0x0A 24 #define ARIZONA_CTRL_IF_I2C1_CFG_2 0x0B 25 #define ARIZONA_CTRL_IF_I2C2_CFG_2 0x0C 26 #define ARIZONA_CTRL_IF_STATUS_1 0x0D 27 #define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16 28 #define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17 29 #define ARIZONA_WRITE_SEQUENCER_CTRL_2 0x18 30 #define ARIZONA_WRITE_SEQUENCER_CTRL_3 0x19 31 #define ARIZONA_WRITE_SEQUENCER_PROM 0x1A 32 #define ARIZONA_TONE_GENERATOR_1 0x20 33 #define ARIZONA_TONE_GENERATOR_2 0x21 34 #define ARIZONA_TONE_GENERATOR_3 0x22 35 #define ARIZONA_TONE_GENERATOR_4 0x23 36 #define ARIZONA_TONE_GENERATOR_5 0x24 37 #define ARIZONA_PWM_DRIVE_1 0x30 38 #define ARIZONA_PWM_DRIVE_2 0x31 39 #define ARIZONA_PWM_DRIVE_3 0x32 40 #define ARIZONA_WAKE_CONTROL 0x40 41 #define ARIZONA_SEQUENCE_CONTROL 0x41 42 #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1 0x61 43 #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2 0x62 44 #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3 0x63 45 #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4 0x64 46 #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x66 47 #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x67 48 #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x68 49 #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x69 50 #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6A 51 #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6B 52 #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_7 0x6C 53 #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_8 0x6D 54 #define ARIZONA_COMFORT_NOISE_GENERATOR 0x70 55 #define ARIZONA_HAPTICS_CONTROL_1 0x90 56 #define ARIZONA_HAPTICS_CONTROL_2 0x91 57 #define ARIZONA_HAPTICS_PHASE_1_INTENSITY 0x92 58 #define ARIZONA_HAPTICS_PHASE_1_DURATION 0x93 59 #define ARIZONA_HAPTICS_PHASE_2_INTENSITY 0x94 60 #define ARIZONA_HAPTICS_PHASE_2_DURATION 0x95 61 #define ARIZONA_HAPTICS_PHASE_3_INTENSITY 0x96 62 #define ARIZONA_HAPTICS_PHASE_3_DURATION 0x97 63 #define ARIZONA_HAPTICS_STATUS 0x98 64 #define ARIZONA_CLOCK_32K_1 0x100 65 #define ARIZONA_SYSTEM_CLOCK_1 0x101 66 #define ARIZONA_SAMPLE_RATE_1 0x102 67 #define ARIZONA_SAMPLE_RATE_2 0x103 68 #define ARIZONA_SAMPLE_RATE_3 0x104 69 #define ARIZONA_SAMPLE_RATE_1_STATUS 0x10A 70 #define ARIZONA_SAMPLE_RATE_2_STATUS 0x10B 71 #define ARIZONA_SAMPLE_RATE_3_STATUS 0x10C 72 #define ARIZONA_ASYNC_CLOCK_1 0x112 73 #define ARIZONA_ASYNC_SAMPLE_RATE_1 0x113 74 #define ARIZONA_ASYNC_SAMPLE_RATE_2 0x114 75 #define ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS 0x11B 76 #define ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS 0x11C 77 #define ARIZONA_OUTPUT_SYSTEM_CLOCK 0x149 78 #define ARIZONA_OUTPUT_ASYNC_CLOCK 0x14A 79 #define ARIZONA_RATE_ESTIMATOR_1 0x152 80 #define ARIZONA_RATE_ESTIMATOR_2 0x153 81 #define ARIZONA_RATE_ESTIMATOR_3 0x154 82 #define ARIZONA_RATE_ESTIMATOR_4 0x155 83 #define ARIZONA_RATE_ESTIMATOR_5 0x156 84 #define ARIZONA_DYNAMIC_FREQUENCY_SCALING_1 0x161 85 #define ARIZONA_FLL1_CONTROL_1 0x171 86 #define ARIZONA_FLL1_CONTROL_2 0x172 87 #define ARIZONA_FLL1_CONTROL_3 0x173 88 #define ARIZONA_FLL1_CONTROL_4 0x174 89 #define ARIZONA_FLL1_CONTROL_5 0x175 90 #define ARIZONA_FLL1_CONTROL_6 0x176 91 #define ARIZONA_FLL1_LOOP_FILTER_TEST_1 0x177 92 #define ARIZONA_FLL1_NCO_TEST_0 0x178 93 #define ARIZONA_FLL1_CONTROL_7 0x179 94 #define ARIZONA_FLL1_SYNCHRONISER_1 0x181 95 #define ARIZONA_FLL1_SYNCHRONISER_2 0x182 96 #define ARIZONA_FLL1_SYNCHRONISER_3 0x183 97 #define ARIZONA_FLL1_SYNCHRONISER_4 0x184 98 #define ARIZONA_FLL1_SYNCHRONISER_5 0x185 99 #define ARIZONA_FLL1_SYNCHRONISER_6 0x186 100 #define ARIZONA_FLL1_SYNCHRONISER_7 0x187 101 #define ARIZONA_FLL1_SPREAD_SPECTRUM 0x189 102 #define ARIZONA_FLL1_GPIO_CLOCK 0x18A 103 #define ARIZONA_FLL2_CONTROL_1 0x191 104 #define ARIZONA_FLL2_CONTROL_2 0x192 105 #define ARIZONA_FLL2_CONTROL_3 0x193 106 #define ARIZONA_FLL2_CONTROL_4 0x194 107 #define ARIZONA_FLL2_CONTROL_5 0x195 108 #define ARIZONA_FLL2_CONTROL_6 0x196 109 #define ARIZONA_FLL2_LOOP_FILTER_TEST_1 0x197 110 #define ARIZONA_FLL2_NCO_TEST_0 0x198 111 #define ARIZONA_FLL2_CONTROL_7 0x199 112 #define ARIZONA_FLL2_SYNCHRONISER_1 0x1A1 113 #define ARIZONA_FLL2_SYNCHRONISER_2 0x1A2 114 #define ARIZONA_FLL2_SYNCHRONISER_3 0x1A3 115 #define ARIZONA_FLL2_SYNCHRONISER_4 0x1A4 116 #define ARIZONA_FLL2_SYNCHRONISER_5 0x1A5 117 #define ARIZONA_FLL2_SYNCHRONISER_6 0x1A6 118 #define ARIZONA_FLL2_SYNCHRONISER_7 0x1A7 119 #define ARIZONA_FLL2_SPREAD_SPECTRUM 0x1A9 120 #define ARIZONA_FLL2_GPIO_CLOCK 0x1AA 121 #define ARIZONA_MIC_CHARGE_PUMP_1 0x200 122 #define ARIZONA_LDO1_CONTROL_1 0x210 123 #define ARIZONA_LDO1_CONTROL_2 0x212 124 #define ARIZONA_LDO2_CONTROL_1 0x213 125 #define ARIZONA_MIC_BIAS_CTRL_1 0x218 126 #define ARIZONA_MIC_BIAS_CTRL_2 0x219 127 #define ARIZONA_MIC_BIAS_CTRL_3 0x21A 128 #define ARIZONA_HP_CTRL_1L 0x225 129 #define ARIZONA_HP_CTRL_1R 0x226 130 #define ARIZONA_ACCESSORY_DETECT_MODE_1 0x293 131 #define ARIZONA_HEADPHONE_DETECT_1 0x29B 132 #define ARIZONA_HEADPHONE_DETECT_2 0x29C 133 #define ARIZONA_HP_DACVAL 0x29F 134 #define ARIZONA_MICD_CLAMP_CONTROL 0x2A2 135 #define ARIZONA_MIC_DETECT_1 0x2A3 136 #define ARIZONA_MIC_DETECT_2 0x2A4 137 #define ARIZONA_MIC_DETECT_3 0x2A5 138 #define ARIZONA_MIC_DETECT_LEVEL_1 0x2A6 139 #define ARIZONA_MIC_DETECT_LEVEL_2 0x2A7 140 #define ARIZONA_MIC_DETECT_LEVEL_3 0x2A8 141 #define ARIZONA_MIC_DETECT_LEVEL_4 0x2A9 142 #define ARIZONA_MIC_NOISE_MIX_CONTROL_1 0x2C3 143 #define ARIZONA_ISOLATION_CONTROL 0x2CB 144 #define ARIZONA_JACK_DETECT_ANALOGUE 0x2D3 145 #define ARIZONA_INPUT_ENABLES 0x300 146 #define ARIZONA_INPUT_ENABLES_STATUS 0x301 147 #define ARIZONA_INPUT_RATE 0x308 148 #define ARIZONA_INPUT_VOLUME_RAMP 0x309 149 #define ARIZONA_HPF_CONTROL 0x30C 150 #define ARIZONA_IN1L_CONTROL 0x310 151 #define ARIZONA_ADC_DIGITAL_VOLUME_1L 0x311 152 #define ARIZONA_DMIC1L_CONTROL 0x312 153 #define ARIZONA_IN1R_CONTROL 0x314 154 #define ARIZONA_ADC_DIGITAL_VOLUME_1R 0x315 155 #define ARIZONA_DMIC1R_CONTROL 0x316 156 #define ARIZONA_IN2L_CONTROL 0x318 157 #define ARIZONA_ADC_DIGITAL_VOLUME_2L 0x319 158 #define ARIZONA_DMIC2L_CONTROL 0x31A 159 #define ARIZONA_IN2R_CONTROL 0x31C 160 #define ARIZONA_ADC_DIGITAL_VOLUME_2R 0x31D 161 #define ARIZONA_DMIC2R_CONTROL 0x31E 162 #define ARIZONA_IN3L_CONTROL 0x320 163 #define ARIZONA_ADC_DIGITAL_VOLUME_3L 0x321 164 #define ARIZONA_DMIC3L_CONTROL 0x322 165 #define ARIZONA_IN3R_CONTROL 0x324 166 #define ARIZONA_ADC_DIGITAL_VOLUME_3R 0x325 167 #define ARIZONA_DMIC3R_CONTROL 0x326 168 #define ARIZONA_IN4L_CONTROL 0x328 169 #define ARIZONA_ADC_DIGITAL_VOLUME_4L 0x329 170 #define ARIZONA_DMIC4L_CONTROL 0x32A 171 #define ARIZONA_IN4R_CONTROL 0x32C 172 #define ARIZONA_ADC_DIGITAL_VOLUME_4R 0x32D 173 #define ARIZONA_DMIC4R_CONTROL 0x32E 174 #define ARIZONA_OUTPUT_ENABLES_1 0x400 175 #define ARIZONA_OUTPUT_STATUS_1 0x401 176 #define ARIZONA_RAW_OUTPUT_STATUS_1 0x406 177 #define ARIZONA_OUTPUT_RATE_1 0x408 178 #define ARIZONA_OUTPUT_VOLUME_RAMP 0x409 179 #define ARIZONA_OUTPUT_PATH_CONFIG_1L 0x410 180 #define ARIZONA_DAC_DIGITAL_VOLUME_1L 0x411 181 #define ARIZONA_DAC_VOLUME_LIMIT_1L 0x412 182 #define ARIZONA_NOISE_GATE_SELECT_1L 0x413 183 #define ARIZONA_OUTPUT_PATH_CONFIG_1R 0x414 184 #define ARIZONA_DAC_DIGITAL_VOLUME_1R 0x415 185 #define ARIZONA_DAC_VOLUME_LIMIT_1R 0x416 186 #define ARIZONA_NOISE_GATE_SELECT_1R 0x417 187 #define ARIZONA_OUTPUT_PATH_CONFIG_2L 0x418 188 #define ARIZONA_DAC_DIGITAL_VOLUME_2L 0x419 189 #define ARIZONA_DAC_VOLUME_LIMIT_2L 0x41A 190 #define ARIZONA_NOISE_GATE_SELECT_2L 0x41B 191 #define ARIZONA_OUTPUT_PATH_CONFIG_2R 0x41C 192 #define ARIZONA_DAC_DIGITAL_VOLUME_2R 0x41D 193 #define ARIZONA_DAC_VOLUME_LIMIT_2R 0x41E 194 #define ARIZONA_NOISE_GATE_SELECT_2R 0x41F 195 #define ARIZONA_OUTPUT_PATH_CONFIG_3L 0x420 196 #define ARIZONA_DAC_DIGITAL_VOLUME_3L 0x421 197 #define ARIZONA_DAC_VOLUME_LIMIT_3L 0x422 198 #define ARIZONA_NOISE_GATE_SELECT_3L 0x423 199 #define ARIZONA_OUTPUT_PATH_CONFIG_3R 0x424 200 #define ARIZONA_DAC_DIGITAL_VOLUME_3R 0x425 201 #define ARIZONA_DAC_VOLUME_LIMIT_3R 0x426 202 #define ARIZONA_NOISE_GATE_SELECT_3R 0x427 203 #define ARIZONA_OUTPUT_PATH_CONFIG_4L 0x428 204 #define ARIZONA_DAC_DIGITAL_VOLUME_4L 0x429 205 #define ARIZONA_OUT_VOLUME_4L 0x42A 206 #define ARIZONA_NOISE_GATE_SELECT_4L 0x42B 207 #define ARIZONA_OUTPUT_PATH_CONFIG_4R 0x42C 208 #define ARIZONA_DAC_DIGITAL_VOLUME_4R 0x42D 209 #define ARIZONA_OUT_VOLUME_4R 0x42E 210 #define ARIZONA_NOISE_GATE_SELECT_4R 0x42F 211 #define ARIZONA_OUTPUT_PATH_CONFIG_5L 0x430 212 #define ARIZONA_DAC_DIGITAL_VOLUME_5L 0x431 213 #define ARIZONA_DAC_VOLUME_LIMIT_5L 0x432 214 #define ARIZONA_NOISE_GATE_SELECT_5L 0x433 215 #define ARIZONA_OUTPUT_PATH_CONFIG_5R 0x434 216 #define ARIZONA_DAC_DIGITAL_VOLUME_5R 0x435 217 #define ARIZONA_DAC_VOLUME_LIMIT_5R 0x436 218 #define ARIZONA_NOISE_GATE_SELECT_5R 0x437 219 #define ARIZONA_OUTPUT_PATH_CONFIG_6L 0x438 220 #define ARIZONA_DAC_DIGITAL_VOLUME_6L 0x439 221 #define ARIZONA_DAC_VOLUME_LIMIT_6L 0x43A 222 #define ARIZONA_NOISE_GATE_SELECT_6L 0x43B 223 #define ARIZONA_OUTPUT_PATH_CONFIG_6R 0x43C 224 #define ARIZONA_DAC_DIGITAL_VOLUME_6R 0x43D 225 #define ARIZONA_DAC_VOLUME_LIMIT_6R 0x43E 226 #define ARIZONA_NOISE_GATE_SELECT_6R 0x43F 227 #define ARIZONA_DRE_ENABLE 0x440 228 #define ARIZONA_DRE_CONTROL_2 0x442 229 #define ARIZONA_DRE_CONTROL_3 0x443 230 #define ARIZONA_DAC_AEC_CONTROL_1 0x450 231 #define ARIZONA_NOISE_GATE_CONTROL 0x458 232 #define ARIZONA_PDM_SPK1_CTRL_1 0x490 233 #define ARIZONA_PDM_SPK1_CTRL_2 0x491 234 #define ARIZONA_PDM_SPK2_CTRL_1 0x492 235 #define ARIZONA_PDM_SPK2_CTRL_2 0x493 236 #define ARIZONA_HP1_SHORT_CIRCUIT_CTRL 0x4A0 237 #define ARIZONA_HP2_SHORT_CIRCUIT_CTRL 0x4A1 238 #define ARIZONA_HP3_SHORT_CIRCUIT_CTRL 0x4A2 239 #define ARIZONA_SPK_CTRL_2 0x4B5 240 #define ARIZONA_SPK_CTRL_3 0x4B6 241 #define ARIZONA_DAC_COMP_1 0x4DC 242 #define ARIZONA_DAC_COMP_2 0x4DD 243 #define ARIZONA_DAC_COMP_3 0x4DE 244 #define ARIZONA_DAC_COMP_4 0x4DF 245 #define ARIZONA_AIF1_BCLK_CTRL 0x500 246 #define ARIZONA_AIF1_TX_PIN_CTRL 0x501 247 #define ARIZONA_AIF1_RX_PIN_CTRL 0x502 248 #define ARIZONA_AIF1_RATE_CTRL 0x503 249 #define ARIZONA_AIF1_FORMAT 0x504 250 #define ARIZONA_AIF1_TX_BCLK_RATE 0x505 251 #define ARIZONA_AIF1_RX_BCLK_RATE 0x506 252 #define ARIZONA_AIF1_FRAME_CTRL_1 0x507 253 #define ARIZONA_AIF1_FRAME_CTRL_2 0x508 254 #define ARIZONA_AIF1_FRAME_CTRL_3 0x509 255 #define ARIZONA_AIF1_FRAME_CTRL_4 0x50A 256 #define ARIZONA_AIF1_FRAME_CTRL_5 0x50B 257 #define ARIZONA_AIF1_FRAME_CTRL_6 0x50C 258 #define ARIZONA_AIF1_FRAME_CTRL_7 0x50D 259 #define ARIZONA_AIF1_FRAME_CTRL_8 0x50E 260 #define ARIZONA_AIF1_FRAME_CTRL_9 0x50F 261 #define ARIZONA_AIF1_FRAME_CTRL_10 0x510 262 #define ARIZONA_AIF1_FRAME_CTRL_11 0x511 263 #define ARIZONA_AIF1_FRAME_CTRL_12 0x512 264 #define ARIZONA_AIF1_FRAME_CTRL_13 0x513 265 #define ARIZONA_AIF1_FRAME_CTRL_14 0x514 266 #define ARIZONA_AIF1_FRAME_CTRL_15 0x515 267 #define ARIZONA_AIF1_FRAME_CTRL_16 0x516 268 #define ARIZONA_AIF1_FRAME_CTRL_17 0x517 269 #define ARIZONA_AIF1_FRAME_CTRL_18 0x518 270 #define ARIZONA_AIF1_TX_ENABLES 0x519 271 #define ARIZONA_AIF1_RX_ENABLES 0x51A 272 #define ARIZONA_AIF1_FORCE_WRITE 0x51B 273 #define ARIZONA_AIF2_BCLK_CTRL 0x540 274 #define ARIZONA_AIF2_TX_PIN_CTRL 0x541 275 #define ARIZONA_AIF2_RX_PIN_CTRL 0x542 276 #define ARIZONA_AIF2_RATE_CTRL 0x543 277 #define ARIZONA_AIF2_FORMAT 0x544 278 #define ARIZONA_AIF2_TX_BCLK_RATE 0x545 279 #define ARIZONA_AIF2_RX_BCLK_RATE 0x546 280 #define ARIZONA_AIF2_FRAME_CTRL_1 0x547 281 #define ARIZONA_AIF2_FRAME_CTRL_2 0x548 282 #define ARIZONA_AIF2_FRAME_CTRL_3 0x549 283 #define ARIZONA_AIF2_FRAME_CTRL_4 0x54A 284 #define ARIZONA_AIF2_FRAME_CTRL_5 0x54B 285 #define ARIZONA_AIF2_FRAME_CTRL_6 0x54C 286 #define ARIZONA_AIF2_FRAME_CTRL_7 0x54D 287 #define ARIZONA_AIF2_FRAME_CTRL_8 0x54E 288 #define ARIZONA_AIF2_FRAME_CTRL_11 0x551 289 #define ARIZONA_AIF2_FRAME_CTRL_12 0x552 290 #define ARIZONA_AIF2_FRAME_CTRL_13 0x553 291 #define ARIZONA_AIF2_FRAME_CTRL_14 0x554 292 #define ARIZONA_AIF2_FRAME_CTRL_15 0x555 293 #define ARIZONA_AIF2_FRAME_CTRL_16 0x556 294 #define ARIZONA_AIF2_TX_ENABLES 0x559 295 #define ARIZONA_AIF2_RX_ENABLES 0x55A 296 #define ARIZONA_AIF2_FORCE_WRITE 0x55B 297 #define ARIZONA_AIF3_BCLK_CTRL 0x580 298 #define ARIZONA_AIF3_TX_PIN_CTRL 0x581 299 #define ARIZONA_AIF3_RX_PIN_CTRL 0x582 300 #define ARIZONA_AIF3_RATE_CTRL 0x583 301 #define ARIZONA_AIF3_FORMAT 0x584 302 #define ARIZONA_AIF3_TX_BCLK_RATE 0x585 303 #define ARIZONA_AIF3_RX_BCLK_RATE 0x586 304 #define ARIZONA_AIF3_FRAME_CTRL_1 0x587 305 #define ARIZONA_AIF3_FRAME_CTRL_2 0x588 306 #define ARIZONA_AIF3_FRAME_CTRL_3 0x589 307 #define ARIZONA_AIF3_FRAME_CTRL_4 0x58A 308 #define ARIZONA_AIF3_FRAME_CTRL_11 0x591 309 #define ARIZONA_AIF3_FRAME_CTRL_12 0x592 310 #define ARIZONA_AIF3_TX_ENABLES 0x599 311 #define ARIZONA_AIF3_RX_ENABLES 0x59A 312 #define ARIZONA_AIF3_FORCE_WRITE 0x59B 313 #define ARIZONA_SLIMBUS_FRAMER_REF_GEAR 0x5E3 314 #define ARIZONA_SLIMBUS_RATES_1 0x5E5 315 #define ARIZONA_SLIMBUS_RATES_2 0x5E6 316 #define ARIZONA_SLIMBUS_RATES_3 0x5E7 317 #define ARIZONA_SLIMBUS_RATES_4 0x5E8 318 #define ARIZONA_SLIMBUS_RATES_5 0x5E9 319 #define ARIZONA_SLIMBUS_RATES_6 0x5EA 320 #define ARIZONA_SLIMBUS_RATES_7 0x5EB 321 #define ARIZONA_SLIMBUS_RATES_8 0x5EC 322 #define ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE 0x5F5 323 #define ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE 0x5F6 324 #define ARIZONA_SLIMBUS_RX_PORT_STATUS 0x5F7 325 #define ARIZONA_SLIMBUS_TX_PORT_STATUS 0x5F8 326 #define ARIZONA_PWM1MIX_INPUT_1_SOURCE 0x640 327 #define ARIZONA_PWM1MIX_INPUT_1_VOLUME 0x641 328 #define ARIZONA_PWM1MIX_INPUT_2_SOURCE 0x642 329 #define ARIZONA_PWM1MIX_INPUT_2_VOLUME 0x643 330 #define ARIZONA_PWM1MIX_INPUT_3_SOURCE 0x644 331 #define ARIZONA_PWM1MIX_INPUT_3_VOLUME 0x645 332 #define ARIZONA_PWM1MIX_INPUT_4_SOURCE 0x646 333 #define ARIZONA_PWM1MIX_INPUT_4_VOLUME 0x647 334 #define ARIZONA_PWM2MIX_INPUT_1_SOURCE 0x648 335 #define ARIZONA_PWM2MIX_INPUT_1_VOLUME 0x649 336 #define ARIZONA_PWM2MIX_INPUT_2_SOURCE 0x64A 337 #define ARIZONA_PWM2MIX_INPUT_2_VOLUME 0x64B 338 #define ARIZONA_PWM2MIX_INPUT_3_SOURCE 0x64C 339 #define ARIZONA_PWM2MIX_INPUT_3_VOLUME 0x64D 340 #define ARIZONA_PWM2MIX_INPUT_4_SOURCE 0x64E 341 #define ARIZONA_PWM2MIX_INPUT_4_VOLUME 0x64F 342 #define ARIZONA_MICMIX_INPUT_1_SOURCE 0x660 343 #define ARIZONA_MICMIX_INPUT_1_VOLUME 0x661 344 #define ARIZONA_MICMIX_INPUT_2_SOURCE 0x662 345 #define ARIZONA_MICMIX_INPUT_2_VOLUME 0x663 346 #define ARIZONA_MICMIX_INPUT_3_SOURCE 0x664 347 #define ARIZONA_MICMIX_INPUT_3_VOLUME 0x665 348 #define ARIZONA_MICMIX_INPUT_4_SOURCE 0x666 349 #define ARIZONA_MICMIX_INPUT_4_VOLUME 0x667 350 #define ARIZONA_NOISEMIX_INPUT_1_SOURCE 0x668 351 #define ARIZONA_NOISEMIX_INPUT_1_VOLUME 0x669 352 #define ARIZONA_NOISEMIX_INPUT_2_SOURCE 0x66A 353 #define ARIZONA_NOISEMIX_INPUT_2_VOLUME 0x66B 354 #define ARIZONA_NOISEMIX_INPUT_3_SOURCE 0x66C 355 #define ARIZONA_NOISEMIX_INPUT_3_VOLUME 0x66D 356 #define ARIZONA_NOISEMIX_INPUT_4_SOURCE 0x66E 357 #define ARIZONA_NOISEMIX_INPUT_4_VOLUME 0x66F 358 #define ARIZONA_OUT1LMIX_INPUT_1_SOURCE 0x680 359 #define ARIZONA_OUT1LMIX_INPUT_1_VOLUME 0x681 360 #define ARIZONA_OUT1LMIX_INPUT_2_SOURCE 0x682 361 #define ARIZONA_OUT1LMIX_INPUT_2_VOLUME 0x683 362 #define ARIZONA_OUT1LMIX_INPUT_3_SOURCE 0x684 363 #define ARIZONA_OUT1LMIX_INPUT_3_VOLUME 0x685 364 #define ARIZONA_OUT1LMIX_INPUT_4_SOURCE 0x686 365 #define ARIZONA_OUT1LMIX_INPUT_4_VOLUME 0x687 366 #define ARIZONA_OUT1RMIX_INPUT_1_SOURCE 0x688 367 #define ARIZONA_OUT1RMIX_INPUT_1_VOLUME 0x689 368 #define ARIZONA_OUT1RMIX_INPUT_2_SOURCE 0x68A 369 #define ARIZONA_OUT1RMIX_INPUT_2_VOLUME 0x68B 370 #define ARIZONA_OUT1RMIX_INPUT_3_SOURCE 0x68C 371 #define ARIZONA_OUT1RMIX_INPUT_3_VOLUME 0x68D 372 #define ARIZONA_OUT1RMIX_INPUT_4_SOURCE 0x68E 373 #define ARIZONA_OUT1RMIX_INPUT_4_VOLUME 0x68F 374 #define ARIZONA_OUT2LMIX_INPUT_1_SOURCE 0x690 375 #define ARIZONA_OUT2LMIX_INPUT_1_VOLUME 0x691 376 #define ARIZONA_OUT2LMIX_INPUT_2_SOURCE 0x692 377 #define ARIZONA_OUT2LMIX_INPUT_2_VOLUME 0x693 378 #define ARIZONA_OUT2LMIX_INPUT_3_SOURCE 0x694 379 #define ARIZONA_OUT2LMIX_INPUT_3_VOLUME 0x695 380 #define ARIZONA_OUT2LMIX_INPUT_4_SOURCE 0x696 381 #define ARIZONA_OUT2LMIX_INPUT_4_VOLUME 0x697 382 #define ARIZONA_OUT2RMIX_INPUT_1_SOURCE 0x698 383 #define ARIZONA_OUT2RMIX_INPUT_1_VOLUME 0x699 384 #define ARIZONA_OUT2RMIX_INPUT_2_SOURCE 0x69A 385 #define ARIZONA_OUT2RMIX_INPUT_2_VOLUME 0x69B 386 #define ARIZONA_OUT2RMIX_INPUT_3_SOURCE 0x69C 387 #define ARIZONA_OUT2RMIX_INPUT_3_VOLUME 0x69D 388 #define ARIZONA_OUT2RMIX_INPUT_4_SOURCE 0x69E 389 #define ARIZONA_OUT2RMIX_INPUT_4_VOLUME 0x69F 390 #define ARIZONA_OUT3LMIX_INPUT_1_SOURCE 0x6A0 391 #define ARIZONA_OUT3LMIX_INPUT_1_VOLUME 0x6A1 392 #define ARIZONA_OUT3LMIX_INPUT_2_SOURCE 0x6A2 393 #define ARIZONA_OUT3LMIX_INPUT_2_VOLUME 0x6A3 394 #define ARIZONA_OUT3LMIX_INPUT_3_SOURCE 0x6A4 395 #define ARIZONA_OUT3LMIX_INPUT_3_VOLUME 0x6A5 396 #define ARIZONA_OUT3LMIX_INPUT_4_SOURCE 0x6A6 397 #define ARIZONA_OUT3LMIX_INPUT_4_VOLUME 0x6A7 398 #define ARIZONA_OUT3RMIX_INPUT_1_SOURCE 0x6A8 399 #define ARIZONA_OUT3RMIX_INPUT_1_VOLUME 0x6A9 400 #define ARIZONA_OUT3RMIX_INPUT_2_SOURCE 0x6AA 401 #define ARIZONA_OUT3RMIX_INPUT_2_VOLUME 0x6AB 402 #define ARIZONA_OUT3RMIX_INPUT_3_SOURCE 0x6AC 403 #define ARIZONA_OUT3RMIX_INPUT_3_VOLUME 0x6AD 404 #define ARIZONA_OUT3RMIX_INPUT_4_SOURCE 0x6AE 405 #define ARIZONA_OUT3RMIX_INPUT_4_VOLUME 0x6AF 406 #define ARIZONA_OUT4LMIX_INPUT_1_SOURCE 0x6B0 407 #define ARIZONA_OUT4LMIX_INPUT_1_VOLUME 0x6B1 408 #define ARIZONA_OUT4LMIX_INPUT_2_SOURCE 0x6B2 409 #define ARIZONA_OUT4LMIX_INPUT_2_VOLUME 0x6B3 410 #define ARIZONA_OUT4LMIX_INPUT_3_SOURCE 0x6B4 411 #define ARIZONA_OUT4LMIX_INPUT_3_VOLUME 0x6B5 412 #define ARIZONA_OUT4LMIX_INPUT_4_SOURCE 0x6B6 413 #define ARIZONA_OUT4LMIX_INPUT_4_VOLUME 0x6B7 414 #define ARIZONA_OUT4RMIX_INPUT_1_SOURCE 0x6B8 415 #define ARIZONA_OUT4RMIX_INPUT_1_VOLUME 0x6B9 416 #define ARIZONA_OUT4RMIX_INPUT_2_SOURCE 0x6BA 417 #define ARIZONA_OUT4RMIX_INPUT_2_VOLUME 0x6BB 418 #define ARIZONA_OUT4RMIX_INPUT_3_SOURCE 0x6BC 419 #define ARIZONA_OUT4RMIX_INPUT_3_VOLUME 0x6BD 420 #define ARIZONA_OUT4RMIX_INPUT_4_SOURCE 0x6BE 421 #define ARIZONA_OUT4RMIX_INPUT_4_VOLUME 0x6BF 422 #define ARIZONA_OUT5LMIX_INPUT_1_SOURCE 0x6C0 423 #define ARIZONA_OUT5LMIX_INPUT_1_VOLUME 0x6C1 424 #define ARIZONA_OUT5LMIX_INPUT_2_SOURCE 0x6C2 425 #define ARIZONA_OUT5LMIX_INPUT_2_VOLUME 0x6C3 426 #define ARIZONA_OUT5LMIX_INPUT_3_SOURCE 0x6C4 427 #define ARIZONA_OUT5LMIX_INPUT_3_VOLUME 0x6C5 428 #define ARIZONA_OUT5LMIX_INPUT_4_SOURCE 0x6C6 429 #define ARIZONA_OUT5LMIX_INPUT_4_VOLUME 0x6C7 430 #define ARIZONA_OUT5RMIX_INPUT_1_SOURCE 0x6C8 431 #define ARIZONA_OUT5RMIX_INPUT_1_VOLUME 0x6C9 432 #define ARIZONA_OUT5RMIX_INPUT_2_SOURCE 0x6CA 433 #define ARIZONA_OUT5RMIX_INPUT_2_VOLUME 0x6CB 434 #define ARIZONA_OUT5RMIX_INPUT_3_SOURCE 0x6CC 435 #define ARIZONA_OUT5RMIX_INPUT_3_VOLUME 0x6CD 436 #define ARIZONA_OUT5RMIX_INPUT_4_SOURCE 0x6CE 437 #define ARIZONA_OUT5RMIX_INPUT_4_VOLUME 0x6CF 438 #define ARIZONA_OUT6LMIX_INPUT_1_SOURCE 0x6D0 439 #define ARIZONA_OUT6LMIX_INPUT_1_VOLUME 0x6D1 440 #define ARIZONA_OUT6LMIX_INPUT_2_SOURCE 0x6D2 441 #define ARIZONA_OUT6LMIX_INPUT_2_VOLUME 0x6D3 442 #define ARIZONA_OUT6LMIX_INPUT_3_SOURCE 0x6D4 443 #define ARIZONA_OUT6LMIX_INPUT_3_VOLUME 0x6D5 444 #define ARIZONA_OUT6LMIX_INPUT_4_SOURCE 0x6D6 445 #define ARIZONA_OUT6LMIX_INPUT_4_VOLUME 0x6D7 446 #define ARIZONA_OUT6RMIX_INPUT_1_SOURCE 0x6D8 447 #define ARIZONA_OUT6RMIX_INPUT_1_VOLUME 0x6D9 448 #define ARIZONA_OUT6RMIX_INPUT_2_SOURCE 0x6DA 449 #define ARIZONA_OUT6RMIX_INPUT_2_VOLUME 0x6DB 450 #define ARIZONA_OUT6RMIX_INPUT_3_SOURCE 0x6DC 451 #define ARIZONA_OUT6RMIX_INPUT_3_VOLUME 0x6DD 452 #define ARIZONA_OUT6RMIX_INPUT_4_SOURCE 0x6DE 453 #define ARIZONA_OUT6RMIX_INPUT_4_VOLUME 0x6DF 454 #define ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE 0x700 455 #define ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME 0x701 456 #define ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE 0x702 457 #define ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME 0x703 458 #define ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE 0x704 459 #define ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME 0x705 460 #define ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE 0x706 461 #define ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME 0x707 462 #define ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE 0x708 463 #define ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME 0x709 464 #define ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE 0x70A 465 #define ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME 0x70B 466 #define ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE 0x70C 467 #define ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME 0x70D 468 #define ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE 0x70E 469 #define ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME 0x70F 470 #define ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE 0x710 471 #define ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME 0x711 472 #define ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE 0x712 473 #define ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME 0x713 474 #define ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE 0x714 475 #define ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME 0x715 476 #define ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE 0x716 477 #define ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME 0x717 478 #define ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE 0x718 479 #define ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME 0x719 480 #define ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE 0x71A 481 #define ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME 0x71B 482 #define ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE 0x71C 483 #define ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME 0x71D 484 #define ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE 0x71E 485 #define ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME 0x71F 486 #define ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE 0x720 487 #define ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME 0x721 488 #define ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE 0x722 489 #define ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME 0x723 490 #define ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE 0x724 491 #define ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME 0x725 492 #define ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE 0x726 493 #define ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME 0x727 494 #define ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE 0x728 495 #define ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME 0x729 496 #define ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE 0x72A 497 #define ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME 0x72B 498 #define ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE 0x72C 499 #define ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME 0x72D 500 #define ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE 0x72E 501 #define ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME 0x72F 502 #define ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE 0x730 503 #define ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME 0x731 504 #define ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE 0x732 505 #define ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME 0x733 506 #define ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE 0x734 507 #define ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME 0x735 508 #define ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE 0x736 509 #define ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME 0x737 510 #define ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE 0x738 511 #define ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME 0x739 512 #define ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE 0x73A 513 #define ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME 0x73B 514 #define ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE 0x73C 515 #define ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME 0x73D 516 #define ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE 0x73E 517 #define ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME 0x73F 518 #define ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE 0x740 519 #define ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME 0x741 520 #define ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE 0x742 521 #define ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME 0x743 522 #define ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE 0x744 523 #define ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME 0x745 524 #define ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE 0x746 525 #define ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME 0x747 526 #define ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE 0x748 527 #define ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME 0x749 528 #define ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE 0x74A 529 #define ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME 0x74B 530 #define ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE 0x74C 531 #define ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME 0x74D 532 #define ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE 0x74E 533 #define ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME 0x74F 534 #define ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE 0x750 535 #define ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME 0x751 536 #define ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE 0x752 537 #define ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME 0x753 538 #define ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE 0x754 539 #define ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME 0x755 540 #define ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE 0x756 541 #define ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME 0x757 542 #define ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE 0x758 543 #define ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME 0x759 544 #define ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE 0x75A 545 #define ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME 0x75B 546 #define ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE 0x75C 547 #define ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME 0x75D 548 #define ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE 0x75E 549 #define ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME 0x75F 550 #define ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE 0x760 551 #define ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME 0x761 552 #define ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE 0x762 553 #define ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME 0x763 554 #define ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE 0x764 555 #define ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME 0x765 556 #define ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE 0x766 557 #define ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME 0x767 558 #define ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE 0x768 559 #define ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME 0x769 560 #define ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE 0x76A 561 #define ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME 0x76B 562 #define ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE 0x76C 563 #define ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME 0x76D 564 #define ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE 0x76E 565 #define ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME 0x76F 566 #define ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE 0x780 567 #define ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME 0x781 568 #define ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE 0x782 569 #define ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME 0x783 570 #define ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE 0x784 571 #define ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME 0x785 572 #define ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE 0x786 573 #define ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME 0x787 574 #define ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE 0x788 575 #define ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME 0x789 576 #define ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE 0x78A 577 #define ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME 0x78B 578 #define ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE 0x78C 579 #define ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME 0x78D 580 #define ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE 0x78E 581 #define ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME 0x78F 582 #define ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE 0x7C0 583 #define ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME 0x7C1 584 #define ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE 0x7C2 585 #define ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME 0x7C3 586 #define ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE 0x7C4 587 #define ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME 0x7C5 588 #define ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE 0x7C6 589 #define ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME 0x7C7 590 #define ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE 0x7C8 591 #define ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME 0x7C9 592 #define ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE 0x7CA 593 #define ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME 0x7CB 594 #define ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE 0x7CC 595 #define ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME 0x7CD 596 #define ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE 0x7CE 597 #define ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME 0x7CF 598 #define ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE 0x7D0 599 #define ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME 0x7D1 600 #define ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE 0x7D2 601 #define ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME 0x7D3 602 #define ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE 0x7D4 603 #define ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME 0x7D5 604 #define ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE 0x7D6 605 #define ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME 0x7D7 606 #define ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE 0x7D8 607 #define ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME 0x7D9 608 #define ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE 0x7DA 609 #define ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME 0x7DB 610 #define ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE 0x7DC 611 #define ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME 0x7DD 612 #define ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE 0x7DE 613 #define ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME 0x7DF 614 #define ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE 0x7E0 615 #define ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME 0x7E1 616 #define ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE 0x7E2 617 #define ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME 0x7E3 618 #define ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE 0x7E4 619 #define ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME 0x7E5 620 #define ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE 0x7E6 621 #define ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME 0x7E7 622 #define ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE 0x7E8 623 #define ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME 0x7E9 624 #define ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE 0x7EA 625 #define ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME 0x7EB 626 #define ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE 0x7EC 627 #define ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME 0x7ED 628 #define ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE 0x7EE 629 #define ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME 0x7EF 630 #define ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE 0x7F0 631 #define ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME 0x7F1 632 #define ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE 0x7F2 633 #define ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME 0x7F3 634 #define ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE 0x7F4 635 #define ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME 0x7F5 636 #define ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE 0x7F6 637 #define ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME 0x7F7 638 #define ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE 0x7F8 639 #define ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME 0x7F9 640 #define ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE 0x7FA 641 #define ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME 0x7FB 642 #define ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE 0x7FC 643 #define ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME 0x7FD 644 #define ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE 0x7FE 645 #define ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME 0x7FF 646 #define ARIZONA_EQ1MIX_INPUT_1_SOURCE 0x880 647 #define ARIZONA_EQ1MIX_INPUT_1_VOLUME 0x881 648 #define ARIZONA_EQ1MIX_INPUT_2_SOURCE 0x882 649 #define ARIZONA_EQ1MIX_INPUT_2_VOLUME 0x883 650 #define ARIZONA_EQ1MIX_INPUT_3_SOURCE 0x884 651 #define ARIZONA_EQ1MIX_INPUT_3_VOLUME 0x885 652 #define ARIZONA_EQ1MIX_INPUT_4_SOURCE 0x886 653 #define ARIZONA_EQ1MIX_INPUT_4_VOLUME 0x887 654 #define ARIZONA_EQ2MIX_INPUT_1_SOURCE 0x888 655 #define ARIZONA_EQ2MIX_INPUT_1_VOLUME 0x889 656 #define ARIZONA_EQ2MIX_INPUT_2_SOURCE 0x88A 657 #define ARIZONA_EQ2MIX_INPUT_2_VOLUME 0x88B 658 #define ARIZONA_EQ2MIX_INPUT_3_SOURCE 0x88C 659 #define ARIZONA_EQ2MIX_INPUT_3_VOLUME 0x88D 660 #define ARIZONA_EQ2MIX_INPUT_4_SOURCE 0x88E 661 #define ARIZONA_EQ2MIX_INPUT_4_VOLUME 0x88F 662 #define ARIZONA_EQ3MIX_INPUT_1_SOURCE 0x890 663 #define ARIZONA_EQ3MIX_INPUT_1_VOLUME 0x891 664 #define ARIZONA_EQ3MIX_INPUT_2_SOURCE 0x892 665 #define ARIZONA_EQ3MIX_INPUT_2_VOLUME 0x893 666 #define ARIZONA_EQ3MIX_INPUT_3_SOURCE 0x894 667 #define ARIZONA_EQ3MIX_INPUT_3_VOLUME 0x895 668 #define ARIZONA_EQ3MIX_INPUT_4_SOURCE 0x896 669 #define ARIZONA_EQ3MIX_INPUT_4_VOLUME 0x897 670 #define ARIZONA_EQ4MIX_INPUT_1_SOURCE 0x898 671 #define ARIZONA_EQ4MIX_INPUT_1_VOLUME 0x899 672 #define ARIZONA_EQ4MIX_INPUT_2_SOURCE 0x89A 673 #define ARIZONA_EQ4MIX_INPUT_2_VOLUME 0x89B 674 #define ARIZONA_EQ4MIX_INPUT_3_SOURCE 0x89C 675 #define ARIZONA_EQ4MIX_INPUT_3_VOLUME 0x89D 676 #define ARIZONA_EQ4MIX_INPUT_4_SOURCE 0x89E 677 #define ARIZONA_EQ4MIX_INPUT_4_VOLUME 0x89F 678 #define ARIZONA_DRC1LMIX_INPUT_1_SOURCE 0x8C0 679 #define ARIZONA_DRC1LMIX_INPUT_1_VOLUME 0x8C1 680 #define ARIZONA_DRC1LMIX_INPUT_2_SOURCE 0x8C2 681 #define ARIZONA_DRC1LMIX_INPUT_2_VOLUME 0x8C3 682 #define ARIZONA_DRC1LMIX_INPUT_3_SOURCE 0x8C4 683 #define ARIZONA_DRC1LMIX_INPUT_3_VOLUME 0x8C5 684 #define ARIZONA_DRC1LMIX_INPUT_4_SOURCE 0x8C6 685 #define ARIZONA_DRC1LMIX_INPUT_4_VOLUME 0x8C7 686 #define ARIZONA_DRC1RMIX_INPUT_1_SOURCE 0x8C8 687 #define ARIZONA_DRC1RMIX_INPUT_1_VOLUME 0x8C9 688 #define ARIZONA_DRC1RMIX_INPUT_2_SOURCE 0x8CA 689 #define ARIZONA_DRC1RMIX_INPUT_2_VOLUME 0x8CB 690 #define ARIZONA_DRC1RMIX_INPUT_3_SOURCE 0x8CC 691 #define ARIZONA_DRC1RMIX_INPUT_3_VOLUME 0x8CD 692 #define ARIZONA_DRC1RMIX_INPUT_4_SOURCE 0x8CE 693 #define ARIZONA_DRC1RMIX_INPUT_4_VOLUME 0x8CF 694 #define ARIZONA_DRC2LMIX_INPUT_1_SOURCE 0x8D0 695 #define ARIZONA_DRC2LMIX_INPUT_1_VOLUME 0x8D1 696 #define ARIZONA_DRC2LMIX_INPUT_2_SOURCE 0x8D2 697 #define ARIZONA_DRC2LMIX_INPUT_2_VOLUME 0x8D3 698 #define ARIZONA_DRC2LMIX_INPUT_3_SOURCE 0x8D4 699 #define ARIZONA_DRC2LMIX_INPUT_3_VOLUME 0x8D5 700 #define ARIZONA_DRC2LMIX_INPUT_4_SOURCE 0x8D6 701 #define ARIZONA_DRC2LMIX_INPUT_4_VOLUME 0x8D7 702 #define ARIZONA_DRC2RMIX_INPUT_1_SOURCE 0x8D8 703 #define ARIZONA_DRC2RMIX_INPUT_1_VOLUME 0x8D9 704 #define ARIZONA_DRC2RMIX_INPUT_2_SOURCE 0x8DA 705 #define ARIZONA_DRC2RMIX_INPUT_2_VOLUME 0x8DB 706 #define ARIZONA_DRC2RMIX_INPUT_3_SOURCE 0x8DC 707 #define ARIZONA_DRC2RMIX_INPUT_3_VOLUME 0x8DD 708 #define ARIZONA_DRC2RMIX_INPUT_4_SOURCE 0x8DE 709 #define ARIZONA_DRC2RMIX_INPUT_4_VOLUME 0x8DF 710 #define ARIZONA_HPLP1MIX_INPUT_1_SOURCE 0x900 711 #define ARIZONA_HPLP1MIX_INPUT_1_VOLUME 0x901 712 #define ARIZONA_HPLP1MIX_INPUT_2_SOURCE 0x902 713 #define ARIZONA_HPLP1MIX_INPUT_2_VOLUME 0x903 714 #define ARIZONA_HPLP1MIX_INPUT_3_SOURCE 0x904 715 #define ARIZONA_HPLP1MIX_INPUT_3_VOLUME 0x905 716 #define ARIZONA_HPLP1MIX_INPUT_4_SOURCE 0x906 717 #define ARIZONA_HPLP1MIX_INPUT_4_VOLUME 0x907 718 #define ARIZONA_HPLP2MIX_INPUT_1_SOURCE 0x908 719 #define ARIZONA_HPLP2MIX_INPUT_1_VOLUME 0x909 720 #define ARIZONA_HPLP2MIX_INPUT_2_SOURCE 0x90A 721 #define ARIZONA_HPLP2MIX_INPUT_2_VOLUME 0x90B 722 #define ARIZONA_HPLP2MIX_INPUT_3_SOURCE 0x90C 723 #define ARIZONA_HPLP2MIX_INPUT_3_VOLUME 0x90D 724 #define ARIZONA_HPLP2MIX_INPUT_4_SOURCE 0x90E 725 #define ARIZONA_HPLP2MIX_INPUT_4_VOLUME 0x90F 726 #define ARIZONA_HPLP3MIX_INPUT_1_SOURCE 0x910 727 #define ARIZONA_HPLP3MIX_INPUT_1_VOLUME 0x911 728 #define ARIZONA_HPLP3MIX_INPUT_2_SOURCE 0x912 729 #define ARIZONA_HPLP3MIX_INPUT_2_VOLUME 0x913 730 #define ARIZONA_HPLP3MIX_INPUT_3_SOURCE 0x914 731 #define ARIZONA_HPLP3MIX_INPUT_3_VOLUME 0x915 732 #define ARIZONA_HPLP3MIX_INPUT_4_SOURCE 0x916 733 #define ARIZONA_HPLP3MIX_INPUT_4_VOLUME 0x917 734 #define ARIZONA_HPLP4MIX_INPUT_1_SOURCE 0x918 735 #define ARIZONA_HPLP4MIX_INPUT_1_VOLUME 0x919 736 #define ARIZONA_HPLP4MIX_INPUT_2_SOURCE 0x91A 737 #define ARIZONA_HPLP4MIX_INPUT_2_VOLUME 0x91B 738 #define ARIZONA_HPLP4MIX_INPUT_3_SOURCE 0x91C 739 #define ARIZONA_HPLP4MIX_INPUT_3_VOLUME 0x91D 740 #define ARIZONA_HPLP4MIX_INPUT_4_SOURCE 0x91E 741 #define ARIZONA_HPLP4MIX_INPUT_4_VOLUME 0x91F 742 #define ARIZONA_DSP1LMIX_INPUT_1_SOURCE 0x940 743 #define ARIZONA_DSP1LMIX_INPUT_1_VOLUME 0x941 744 #define ARIZONA_DSP1LMIX_INPUT_2_SOURCE 0x942 745 #define ARIZONA_DSP1LMIX_INPUT_2_VOLUME 0x943 746 #define ARIZONA_DSP1LMIX_INPUT_3_SOURCE 0x944 747 #define ARIZONA_DSP1LMIX_INPUT_3_VOLUME 0x945 748 #define ARIZONA_DSP1LMIX_INPUT_4_SOURCE 0x946 749 #define ARIZONA_DSP1LMIX_INPUT_4_VOLUME 0x947 750 #define ARIZONA_DSP1RMIX_INPUT_1_SOURCE 0x948 751 #define ARIZONA_DSP1RMIX_INPUT_1_VOLUME 0x949 752 #define ARIZONA_DSP1RMIX_INPUT_2_SOURCE 0x94A 753 #define ARIZONA_DSP1RMIX_INPUT_2_VOLUME 0x94B 754 #define ARIZONA_DSP1RMIX_INPUT_3_SOURCE 0x94C 755 #define ARIZONA_DSP1RMIX_INPUT_3_VOLUME 0x94D 756 #define ARIZONA_DSP1RMIX_INPUT_4_SOURCE 0x94E 757 #define ARIZONA_DSP1RMIX_INPUT_4_VOLUME 0x94F 758 #define ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE 0x950 759 #define ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE 0x958 760 #define ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE 0x960 761 #define ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE 0x968 762 #define ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE 0x970 763 #define ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE 0x978 764 #define ARIZONA_DSP2LMIX_INPUT_1_SOURCE 0x980 765 #define ARIZONA_DSP2LMIX_INPUT_1_VOLUME 0x981 766 #define ARIZONA_DSP2LMIX_INPUT_2_SOURCE 0x982 767 #define ARIZONA_DSP2LMIX_INPUT_2_VOLUME 0x983 768 #define ARIZONA_DSP2LMIX_INPUT_3_SOURCE 0x984 769 #define ARIZONA_DSP2LMIX_INPUT_3_VOLUME 0x985 770 #define ARIZONA_DSP2LMIX_INPUT_4_SOURCE 0x986 771 #define ARIZONA_DSP2LMIX_INPUT_4_VOLUME 0x987 772 #define ARIZONA_DSP2RMIX_INPUT_1_SOURCE 0x988 773 #define ARIZONA_DSP2RMIX_INPUT_1_VOLUME 0x989 774 #define ARIZONA_DSP2RMIX_INPUT_2_SOURCE 0x98A 775 #define ARIZONA_DSP2RMIX_INPUT_2_VOLUME 0x98B 776 #define ARIZONA_DSP2RMIX_INPUT_3_SOURCE 0x98C 777 #define ARIZONA_DSP2RMIX_INPUT_3_VOLUME 0x98D 778 #define ARIZONA_DSP2RMIX_INPUT_4_SOURCE 0x98E 779 #define ARIZONA_DSP2RMIX_INPUT_4_VOLUME 0x98F 780 #define ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE 0x990 781 #define ARIZONA_DSP2AUX2MIX_INPUT_1_SOURCE 0x998 782 #define ARIZONA_DSP2AUX3MIX_INPUT_1_SOURCE 0x9A0 783 #define ARIZONA_DSP2AUX4MIX_INPUT_1_SOURCE 0x9A8 784 #define ARIZONA_DSP2AUX5MIX_INPUT_1_SOURCE 0x9B0 785 #define ARIZONA_DSP2AUX6MIX_INPUT_1_SOURCE 0x9B8 786 #define ARIZONA_DSP3LMIX_INPUT_1_SOURCE 0x9C0 787 #define ARIZONA_DSP3LMIX_INPUT_1_VOLUME 0x9C1 788 #define ARIZONA_DSP3LMIX_INPUT_2_SOURCE 0x9C2 789 #define ARIZONA_DSP3LMIX_INPUT_2_VOLUME 0x9C3 790 #define ARIZONA_DSP3LMIX_INPUT_3_SOURCE 0x9C4 791 #define ARIZONA_DSP3LMIX_INPUT_3_VOLUME 0x9C5 792 #define ARIZONA_DSP3LMIX_INPUT_4_SOURCE 0x9C6 793 #define ARIZONA_DSP3LMIX_INPUT_4_VOLUME 0x9C7 794 #define ARIZONA_DSP3RMIX_INPUT_1_SOURCE 0x9C8 795 #define ARIZONA_DSP3RMIX_INPUT_1_VOLUME 0x9C9 796 #define ARIZONA_DSP3RMIX_INPUT_2_SOURCE 0x9CA 797 #define ARIZONA_DSP3RMIX_INPUT_2_VOLUME 0x9CB 798 #define ARIZONA_DSP3RMIX_INPUT_3_SOURCE 0x9CC 799 #define ARIZONA_DSP3RMIX_INPUT_3_VOLUME 0x9CD 800 #define ARIZONA_DSP3RMIX_INPUT_4_SOURCE 0x9CE 801 #define ARIZONA_DSP3RMIX_INPUT_4_VOLUME 0x9CF 802 #define ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE 0x9D0 803 #define ARIZONA_DSP3AUX2MIX_INPUT_1_SOURCE 0x9D8 804 #define ARIZONA_DSP3AUX3MIX_INPUT_1_SOURCE 0x9E0 805 #define ARIZONA_DSP3AUX4MIX_INPUT_1_SOURCE 0x9E8 806 #define ARIZONA_DSP3AUX5MIX_INPUT_1_SOURCE 0x9F0 807 #define ARIZONA_DSP3AUX6MIX_INPUT_1_SOURCE 0x9F8 808 #define ARIZONA_DSP4LMIX_INPUT_1_SOURCE 0xA00 809 #define ARIZONA_DSP4LMIX_INPUT_1_VOLUME 0xA01 810 #define ARIZONA_DSP4LMIX_INPUT_2_SOURCE 0xA02 811 #define ARIZONA_DSP4LMIX_INPUT_2_VOLUME 0xA03 812 #define ARIZONA_DSP4LMIX_INPUT_3_SOURCE 0xA04 813 #define ARIZONA_DSP4LMIX_INPUT_3_VOLUME 0xA05 814 #define ARIZONA_DSP4LMIX_INPUT_4_SOURCE 0xA06 815 #define ARIZONA_DSP4LMIX_INPUT_4_VOLUME 0xA07 816 #define ARIZONA_DSP4RMIX_INPUT_1_SOURCE 0xA08 817 #define ARIZONA_DSP4RMIX_INPUT_1_VOLUME 0xA09 818 #define ARIZONA_DSP4RMIX_INPUT_2_SOURCE 0xA0A 819 #define ARIZONA_DSP4RMIX_INPUT_2_VOLUME 0xA0B 820 #define ARIZONA_DSP4RMIX_INPUT_3_SOURCE 0xA0C 821 #define ARIZONA_DSP4RMIX_INPUT_3_VOLUME 0xA0D 822 #define ARIZONA_DSP4RMIX_INPUT_4_SOURCE 0xA0E 823 #define ARIZONA_DSP4RMIX_INPUT_4_VOLUME 0xA0F 824 #define ARIZONA_DSP4AUX1MIX_INPUT_1_SOURCE 0xA10 825 #define ARIZONA_DSP4AUX2MIX_INPUT_1_SOURCE 0xA18 826 #define ARIZONA_DSP4AUX3MIX_INPUT_1_SOURCE 0xA20 827 #define ARIZONA_DSP4AUX4MIX_INPUT_1_SOURCE 0xA28 828 #define ARIZONA_DSP4AUX5MIX_INPUT_1_SOURCE 0xA30 829 #define ARIZONA_DSP4AUX6MIX_INPUT_1_SOURCE 0xA38 830 #define ARIZONA_ASRC1LMIX_INPUT_1_SOURCE 0xA80 831 #define ARIZONA_ASRC1RMIX_INPUT_1_SOURCE 0xA88 832 #define ARIZONA_ASRC2LMIX_INPUT_1_SOURCE 0xA90 833 #define ARIZONA_ASRC2RMIX_INPUT_1_SOURCE 0xA98 834 #define ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE 0xB00 835 #define ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE 0xB08 836 #define ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE 0xB10 837 #define ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE 0xB18 838 #define ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE 0xB20 839 #define ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE 0xB28 840 #define ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30 841 #define ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38 842 #define ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40 843 #define ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48 844 #define ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60 845 #define ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68 846 #define ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30 847 #define ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38 848 #define ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40 849 #define ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48 850 #define ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE 0xB50 851 #define ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE 0xB58 852 #define ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60 853 #define ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68 854 #define ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE 0xB70 855 #define ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE 0xB78 856 #define ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE 0xB80 857 #define ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE 0xB88 858 #define ARIZONA_ISRC3DEC3MIX_INPUT_1_SOURCE 0xB90 859 #define ARIZONA_ISRC3DEC4MIX_INPUT_1_SOURCE 0xB98 860 #define ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE 0xBA0 861 #define ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE 0xBA8 862 #define ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE 0xBB0 863 #define ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE 0xBB8 864 #define ARIZONA_GPIO1_CTRL 0xC00 865 #define ARIZONA_GPIO2_CTRL 0xC01 866 #define ARIZONA_GPIO3_CTRL 0xC02 867 #define ARIZONA_GPIO4_CTRL 0xC03 868 #define ARIZONA_GPIO5_CTRL 0xC04 869 #define ARIZONA_IRQ_CTRL_1 0xC0F 870 #define ARIZONA_GPIO_DEBOUNCE_CONFIG 0xC10 871 #define ARIZONA_MISC_PAD_CTRL_1 0xC20 872 #define ARIZONA_MISC_PAD_CTRL_2 0xC21 873 #define ARIZONA_MISC_PAD_CTRL_3 0xC22 874 #define ARIZONA_MISC_PAD_CTRL_4 0xC23 875 #define ARIZONA_MISC_PAD_CTRL_5 0xC24 876 #define ARIZONA_MISC_PAD_CTRL_6 0xC25 877 #define ARIZONA_MISC_PAD_CTRL_7 0xC30 878 #define ARIZONA_MISC_PAD_CTRL_8 0xC31 879 #define ARIZONA_MISC_PAD_CTRL_9 0xC32 880 #define ARIZONA_MISC_PAD_CTRL_10 0xC33 881 #define ARIZONA_MISC_PAD_CTRL_11 0xC34 882 #define ARIZONA_MISC_PAD_CTRL_12 0xC35 883 #define ARIZONA_MISC_PAD_CTRL_13 0xC36 884 #define ARIZONA_MISC_PAD_CTRL_14 0xC37 885 #define ARIZONA_MISC_PAD_CTRL_15 0xC38 886 #define ARIZONA_MISC_PAD_CTRL_16 0xC39 887 #define ARIZONA_MISC_PAD_CTRL_17 0xC3A 888 #define ARIZONA_MISC_PAD_CTRL_18 0xC3B 889 #define ARIZONA_INTERRUPT_STATUS_1 0xD00 890 #define ARIZONA_INTERRUPT_STATUS_2 0xD01 891 #define ARIZONA_INTERRUPT_STATUS_3 0xD02 892 #define ARIZONA_INTERRUPT_STATUS_4 0xD03 893 #define ARIZONA_INTERRUPT_STATUS_5 0xD04 894 #define ARIZONA_INTERRUPT_STATUS_6 0xD05 895 #define ARIZONA_INTERRUPT_STATUS_1_MASK 0xD08 896 #define ARIZONA_INTERRUPT_STATUS_2_MASK 0xD09 897 #define ARIZONA_INTERRUPT_STATUS_3_MASK 0xD0A 898 #define ARIZONA_INTERRUPT_STATUS_4_MASK 0xD0B 899 #define ARIZONA_INTERRUPT_STATUS_5_MASK 0xD0C 900 #define ARIZONA_INTERRUPT_STATUS_6_MASK 0xD0D 901 #define ARIZONA_INTERRUPT_CONTROL 0xD0F 902 #define ARIZONA_IRQ2_STATUS_1 0xD10 903 #define ARIZONA_IRQ2_STATUS_2 0xD11 904 #define ARIZONA_IRQ2_STATUS_3 0xD12 905 #define ARIZONA_IRQ2_STATUS_4 0xD13 906 #define ARIZONA_IRQ2_STATUS_5 0xD14 907 #define ARIZONA_IRQ2_STATUS_6 0xD15 908 #define ARIZONA_IRQ2_STATUS_1_MASK 0xD18 909 #define ARIZONA_IRQ2_STATUS_2_MASK 0xD19 910 #define ARIZONA_IRQ2_STATUS_3_MASK 0xD1A 911 #define ARIZONA_IRQ2_STATUS_4_MASK 0xD1B 912 #define ARIZONA_IRQ2_STATUS_5_MASK 0xD1C 913 #define ARIZONA_IRQ2_STATUS_6_MASK 0xD1D 914 #define ARIZONA_IRQ2_CONTROL 0xD1F 915 #define ARIZONA_INTERRUPT_RAW_STATUS_2 0xD20 916 #define ARIZONA_INTERRUPT_RAW_STATUS_3 0xD21 917 #define ARIZONA_INTERRUPT_RAW_STATUS_4 0xD22 918 #define ARIZONA_INTERRUPT_RAW_STATUS_5 0xD23 919 #define ARIZONA_INTERRUPT_RAW_STATUS_6 0xD24 920 #define ARIZONA_INTERRUPT_RAW_STATUS_7 0xD25 921 #define ARIZONA_INTERRUPT_RAW_STATUS_8 0xD26 922 #define ARIZONA_INTERRUPT_RAW_STATUS_9 0xD28 923 #define ARIZONA_IRQ_PIN_STATUS 0xD40 924 #define ARIZONA_ADSP2_IRQ0 0xD41 925 #define ARIZONA_AOD_WKUP_AND_TRIG 0xD50 926 #define ARIZONA_AOD_IRQ1 0xD51 927 #define ARIZONA_AOD_IRQ2 0xD52 928 #define ARIZONA_AOD_IRQ_MASK_IRQ1 0xD53 929 #define ARIZONA_AOD_IRQ_MASK_IRQ2 0xD54 930 #define ARIZONA_AOD_IRQ_RAW_STATUS 0xD55 931 #define ARIZONA_JACK_DETECT_DEBOUNCE 0xD56 932 #define ARIZONA_FX_CTRL1 0xE00 933 #define ARIZONA_FX_CTRL2 0xE01 934 #define ARIZONA_EQ1_1 0xE10 935 #define ARIZONA_EQ1_2 0xE11 936 #define ARIZONA_EQ1_3 0xE12 937 #define ARIZONA_EQ1_4 0xE13 938 #define ARIZONA_EQ1_5 0xE14 939 #define ARIZONA_EQ1_6 0xE15 940 #define ARIZONA_EQ1_7 0xE16 941 #define ARIZONA_EQ1_8 0xE17 942 #define ARIZONA_EQ1_9 0xE18 943 #define ARIZONA_EQ1_10 0xE19 944 #define ARIZONA_EQ1_11 0xE1A 945 #define ARIZONA_EQ1_12 0xE1B 946 #define ARIZONA_EQ1_13 0xE1C 947 #define ARIZONA_EQ1_14 0xE1D 948 #define ARIZONA_EQ1_15 0xE1E 949 #define ARIZONA_EQ1_16 0xE1F 950 #define ARIZONA_EQ1_17 0xE20 951 #define ARIZONA_EQ1_18 0xE21 952 #define ARIZONA_EQ1_19 0xE22 953 #define ARIZONA_EQ1_20 0xE23 954 #define ARIZONA_EQ1_21 0xE24 955 #define ARIZONA_EQ2_1 0xE26 956 #define ARIZONA_EQ2_2 0xE27 957 #define ARIZONA_EQ2_3 0xE28 958 #define ARIZONA_EQ2_4 0xE29 959 #define ARIZONA_EQ2_5 0xE2A 960 #define ARIZONA_EQ2_6 0xE2B 961 #define ARIZONA_EQ2_7 0xE2C 962 #define ARIZONA_EQ2_8 0xE2D 963 #define ARIZONA_EQ2_9 0xE2E 964 #define ARIZONA_EQ2_10 0xE2F 965 #define ARIZONA_EQ2_11 0xE30 966 #define ARIZONA_EQ2_12 0xE31 967 #define ARIZONA_EQ2_13 0xE32 968 #define ARIZONA_EQ2_14 0xE33 969 #define ARIZONA_EQ2_15 0xE34 970 #define ARIZONA_EQ2_16 0xE35 971 #define ARIZONA_EQ2_17 0xE36 972 #define ARIZONA_EQ2_18 0xE37 973 #define ARIZONA_EQ2_19 0xE38 974 #define ARIZONA_EQ2_20 0xE39 975 #define ARIZONA_EQ2_21 0xE3A 976 #define ARIZONA_EQ3_1 0xE3C 977 #define ARIZONA_EQ3_2 0xE3D 978 #define ARIZONA_EQ3_3 0xE3E 979 #define ARIZONA_EQ3_4 0xE3F 980 #define ARIZONA_EQ3_5 0xE40 981 #define ARIZONA_EQ3_6 0xE41 982 #define ARIZONA_EQ3_7 0xE42 983 #define ARIZONA_EQ3_8 0xE43 984 #define ARIZONA_EQ3_9 0xE44 985 #define ARIZONA_EQ3_10 0xE45 986 #define ARIZONA_EQ3_11 0xE46 987 #define ARIZONA_EQ3_12 0xE47 988 #define ARIZONA_EQ3_13 0xE48 989 #define ARIZONA_EQ3_14 0xE49 990 #define ARIZONA_EQ3_15 0xE4A 991 #define ARIZONA_EQ3_16 0xE4B 992 #define ARIZONA_EQ3_17 0xE4C 993 #define ARIZONA_EQ3_18 0xE4D 994 #define ARIZONA_EQ3_19 0xE4E 995 #define ARIZONA_EQ3_20 0xE4F 996 #define ARIZONA_EQ3_21 0xE50 997 #define ARIZONA_EQ4_1 0xE52 998 #define ARIZONA_EQ4_2 0xE53 999 #define ARIZONA_EQ4_3 0xE54 1000 #define ARIZONA_EQ4_4 0xE55 1001 #define ARIZONA_EQ4_5 0xE56 1002 #define ARIZONA_EQ4_6 0xE57 1003 #define ARIZONA_EQ4_7 0xE58 1004 #define ARIZONA_EQ4_8 0xE59 1005 #define ARIZONA_EQ4_9 0xE5A 1006 #define ARIZONA_EQ4_10 0xE5B 1007 #define ARIZONA_EQ4_11 0xE5C 1008 #define ARIZONA_EQ4_12 0xE5D 1009 #define ARIZONA_EQ4_13 0xE5E 1010 #define ARIZONA_EQ4_14 0xE5F 1011 #define ARIZONA_EQ4_15 0xE60 1012 #define ARIZONA_EQ4_16 0xE61 1013 #define ARIZONA_EQ4_17 0xE62 1014 #define ARIZONA_EQ4_18 0xE63 1015 #define ARIZONA_EQ4_19 0xE64 1016 #define ARIZONA_EQ4_20 0xE65 1017 #define ARIZONA_EQ4_21 0xE66 1018 #define ARIZONA_DRC1_CTRL1 0xE80 1019 #define ARIZONA_DRC1_CTRL2 0xE81 1020 #define ARIZONA_DRC1_CTRL3 0xE82 1021 #define ARIZONA_DRC1_CTRL4 0xE83 1022 #define ARIZONA_DRC1_CTRL5 0xE84 1023 #define ARIZONA_DRC2_CTRL1 0xE89 1024 #define ARIZONA_DRC2_CTRL2 0xE8A 1025 #define ARIZONA_DRC2_CTRL3 0xE8B 1026 #define ARIZONA_DRC2_CTRL4 0xE8C 1027 #define ARIZONA_DRC2_CTRL5 0xE8D 1028 #define ARIZONA_HPLPF1_1 0xEC0 1029 #define ARIZONA_HPLPF1_2 0xEC1 1030 #define ARIZONA_HPLPF2_1 0xEC4 1031 #define ARIZONA_HPLPF2_2 0xEC5 1032 #define ARIZONA_HPLPF3_1 0xEC8 1033 #define ARIZONA_HPLPF3_2 0xEC9 1034 #define ARIZONA_HPLPF4_1 0xECC 1035 #define ARIZONA_HPLPF4_2 0xECD 1036 #define ARIZONA_ASRC_ENABLE 0xEE0 1037 #define ARIZONA_ASRC_STATUS 0xEE1 1038 #define ARIZONA_ASRC_RATE1 0xEE2 1039 #define ARIZONA_ASRC_RATE2 0xEE3 1040 #define ARIZONA_ISRC_1_CTRL_1 0xEF0 1041 #define ARIZONA_ISRC_1_CTRL_2 0xEF1 1042 #define ARIZONA_ISRC_1_CTRL_3 0xEF2 1043 #define ARIZONA_ISRC_2_CTRL_1 0xEF3 1044 #define ARIZONA_ISRC_2_CTRL_2 0xEF4 1045 #define ARIZONA_ISRC_2_CTRL_3 0xEF5 1046 #define ARIZONA_ISRC_3_CTRL_1 0xEF6 1047 #define ARIZONA_ISRC_3_CTRL_2 0xEF7 1048 #define ARIZONA_ISRC_3_CTRL_3 0xEF8 1049 #define ARIZONA_CLOCK_CONTROL 0xF00 1050 #define ARIZONA_ANC_SRC 0xF01 1051 #define ARIZONA_DSP_STATUS 0xF02 1052 #define ARIZONA_DSP1_CONTROL_1 0x1100 1053 #define ARIZONA_DSP1_CLOCKING_1 0x1101 1054 #define ARIZONA_DSP1_STATUS_1 0x1104 1055 #define ARIZONA_DSP1_STATUS_2 0x1105 1056 #define ARIZONA_DSP1_STATUS_3 0x1106 1057 #define ARIZONA_DSP1_STATUS_4 0x1107 1058 #define ARIZONA_DSP1_WDMA_BUFFER_1 0x1110 1059 #define ARIZONA_DSP1_WDMA_BUFFER_2 0x1111 1060 #define ARIZONA_DSP1_WDMA_BUFFER_3 0x1112 1061 #define ARIZONA_DSP1_WDMA_BUFFER_4 0x1113 1062 #define ARIZONA_DSP1_WDMA_BUFFER_5 0x1114 1063 #define ARIZONA_DSP1_WDMA_BUFFER_6 0x1115 1064 #define ARIZONA_DSP1_WDMA_BUFFER_7 0x1116 1065 #define ARIZONA_DSP1_WDMA_BUFFER_8 0x1117 1066 #define ARIZONA_DSP1_RDMA_BUFFER_1 0x1120 1067 #define ARIZONA_DSP1_RDMA_BUFFER_2 0x1121 1068 #define ARIZONA_DSP1_RDMA_BUFFER_3 0x1122 1069 #define ARIZONA_DSP1_RDMA_BUFFER_4 0x1123 1070 #define ARIZONA_DSP1_RDMA_BUFFER_5 0x1124 1071 #define ARIZONA_DSP1_RDMA_BUFFER_6 0x1125 1072 #define ARIZONA_DSP1_WDMA_CONFIG_1 0x1130 1073 #define ARIZONA_DSP1_WDMA_CONFIG_2 0x1131 1074 #define ARIZONA_DSP1_WDMA_OFFSET_1 0x1132 1075 #define ARIZONA_DSP1_RDMA_CONFIG_1 0x1134 1076 #define ARIZONA_DSP1_RDMA_OFFSET_1 0x1135 1077 #define ARIZONA_DSP1_EXTERNAL_START_SELECT_1 0x1138 1078 #define ARIZONA_DSP1_SCRATCH_0 0x1140 1079 #define ARIZONA_DSP1_SCRATCH_1 0x1141 1080 #define ARIZONA_DSP1_SCRATCH_2 0x1142 1081 #define ARIZONA_DSP1_SCRATCH_3 0x1143 1082 #define ARIZONA_DSP2_CONTROL_1 0x1200 1083 #define ARIZONA_DSP2_CLOCKING_1 0x1201 1084 #define ARIZONA_DSP2_STATUS_1 0x1204 1085 #define ARIZONA_DSP2_STATUS_2 0x1205 1086 #define ARIZONA_DSP2_STATUS_3 0x1206 1087 #define ARIZONA_DSP2_STATUS_4 0x1207 1088 #define ARIZONA_DSP2_WDMA_BUFFER_1 0x1210 1089 #define ARIZONA_DSP2_WDMA_BUFFER_2 0x1211 1090 #define ARIZONA_DSP2_WDMA_BUFFER_3 0x1212 1091 #define ARIZONA_DSP2_WDMA_BUFFER_4 0x1213 1092 #define ARIZONA_DSP2_WDMA_BUFFER_5 0x1214 1093 #define ARIZONA_DSP2_WDMA_BUFFER_6 0x1215 1094 #define ARIZONA_DSP2_WDMA_BUFFER_7 0x1216 1095 #define ARIZONA_DSP2_WDMA_BUFFER_8 0x1217 1096 #define ARIZONA_DSP2_RDMA_BUFFER_1 0x1220 1097 #define ARIZONA_DSP2_RDMA_BUFFER_2 0x1221 1098 #define ARIZONA_DSP2_RDMA_BUFFER_3 0x1222 1099 #define ARIZONA_DSP2_RDMA_BUFFER_4 0x1223 1100 #define ARIZONA_DSP2_RDMA_BUFFER_5 0x1224 1101 #define ARIZONA_DSP2_RDMA_BUFFER_6 0x1225 1102 #define ARIZONA_DSP2_WDMA_CONFIG_1 0x1230 1103 #define ARIZONA_DSP2_WDMA_CONFIG_2 0x1231 1104 #define ARIZONA_DSP2_WDMA_OFFSET_1 0x1232 1105 #define ARIZONA_DSP2_RDMA_CONFIG_1 0x1234 1106 #define ARIZONA_DSP2_RDMA_OFFSET_1 0x1235 1107 #define ARIZONA_DSP2_EXTERNAL_START_SELECT_1 0x1238 1108 #define ARIZONA_DSP2_SCRATCH_0 0x1240 1109 #define ARIZONA_DSP2_SCRATCH_1 0x1241 1110 #define ARIZONA_DSP2_SCRATCH_2 0x1242 1111 #define ARIZONA_DSP2_SCRATCH_3 0x1243 1112 #define ARIZONA_DSP3_CONTROL_1 0x1300 1113 #define ARIZONA_DSP3_CLOCKING_1 0x1301 1114 #define ARIZONA_DSP3_STATUS_1 0x1304 1115 #define ARIZONA_DSP3_STATUS_2 0x1305 1116 #define ARIZONA_DSP3_STATUS_3 0x1306 1117 #define ARIZONA_DSP3_STATUS_4 0x1307 1118 #define ARIZONA_DSP3_WDMA_BUFFER_1 0x1310 1119 #define ARIZONA_DSP3_WDMA_BUFFER_2 0x1311 1120 #define ARIZONA_DSP3_WDMA_BUFFER_3 0x1312 1121 #define ARIZONA_DSP3_WDMA_BUFFER_4 0x1313 1122 #define ARIZONA_DSP3_WDMA_BUFFER_5 0x1314 1123 #define ARIZONA_DSP3_WDMA_BUFFER_6 0x1315 1124 #define ARIZONA_DSP3_WDMA_BUFFER_7 0x1316 1125 #define ARIZONA_DSP3_WDMA_BUFFER_8 0x1317 1126 #define ARIZONA_DSP3_RDMA_BUFFER_1 0x1320 1127 #define ARIZONA_DSP3_RDMA_BUFFER_2 0x1321 1128 #define ARIZONA_DSP3_RDMA_BUFFER_3 0x1322 1129 #define ARIZONA_DSP3_RDMA_BUFFER_4 0x1323 1130 #define ARIZONA_DSP3_RDMA_BUFFER_5 0x1324 1131 #define ARIZONA_DSP3_RDMA_BUFFER_6 0x1325 1132 #define ARIZONA_DSP3_WDMA_CONFIG_1 0x1330 1133 #define ARIZONA_DSP3_WDMA_CONFIG_2 0x1331 1134 #define ARIZONA_DSP3_WDMA_OFFSET_1 0x1332 1135 #define ARIZONA_DSP3_RDMA_CONFIG_1 0x1334 1136 #define ARIZONA_DSP3_RDMA_OFFSET_1 0x1335 1137 #define ARIZONA_DSP3_EXTERNAL_START_SELECT_1 0x1338 1138 #define ARIZONA_DSP3_SCRATCH_0 0x1340 1139 #define ARIZONA_DSP3_SCRATCH_1 0x1341 1140 #define ARIZONA_DSP3_SCRATCH_2 0x1342 1141 #define ARIZONA_DSP3_SCRATCH_3 0x1343 1142 #define ARIZONA_DSP4_CONTROL_1 0x1400 1143 #define ARIZONA_DSP4_CLOCKING_1 0x1401 1144 #define ARIZONA_DSP4_STATUS_1 0x1404 1145 #define ARIZONA_DSP4_STATUS_2 0x1405 1146 #define ARIZONA_DSP4_STATUS_3 0x1406 1147 #define ARIZONA_DSP4_STATUS_4 0x1407 1148 #define ARIZONA_DSP4_WDMA_BUFFER_1 0x1410 1149 #define ARIZONA_DSP4_WDMA_BUFFER_2 0x1411 1150 #define ARIZONA_DSP4_WDMA_BUFFER_3 0x1412 1151 #define ARIZONA_DSP4_WDMA_BUFFER_4 0x1413 1152 #define ARIZONA_DSP4_WDMA_BUFFER_5 0x1414 1153 #define ARIZONA_DSP4_WDMA_BUFFER_6 0x1415 1154 #define ARIZONA_DSP4_WDMA_BUFFER_7 0x1416 1155 #define ARIZONA_DSP4_WDMA_BUFFER_8 0x1417 1156 #define ARIZONA_DSP4_RDMA_BUFFER_1 0x1420 1157 #define ARIZONA_DSP4_RDMA_BUFFER_2 0x1421 1158 #define ARIZONA_DSP4_RDMA_BUFFER_3 0x1422 1159 #define ARIZONA_DSP4_RDMA_BUFFER_4 0x1423 1160 #define ARIZONA_DSP4_RDMA_BUFFER_5 0x1424 1161 #define ARIZONA_DSP4_RDMA_BUFFER_6 0x1425 1162 #define ARIZONA_DSP4_WDMA_CONFIG_1 0x1430 1163 #define ARIZONA_DSP4_WDMA_CONFIG_2 0x1431 1164 #define ARIZONA_DSP4_WDMA_OFFSET_1 0x1432 1165 #define ARIZONA_DSP4_RDMA_CONFIG_1 0x1434 1166 #define ARIZONA_DSP4_RDMA_OFFSET_1 0x1435 1167 #define ARIZONA_DSP4_EXTERNAL_START_SELECT_1 0x1438 1168 #define ARIZONA_DSP4_SCRATCH_0 0x1440 1169 #define ARIZONA_DSP4_SCRATCH_1 0x1441 1170 #define ARIZONA_DSP4_SCRATCH_2 0x1442 1171 #define ARIZONA_DSP4_SCRATCH_3 0x1443 1172 1173 /* 1174 * Field Definitions. 1175 */ 1176 1177 /* 1178 * R0 (0x00) - software reset 1179 */ 1180 #define ARIZONA_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */ 1181 #define ARIZONA_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */ 1182 #define ARIZONA_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */ 1183 1184 /* 1185 * R1 (0x01) - Device Revision 1186 */ 1187 #define ARIZONA_DEVICE_REVISION_MASK 0x00FF /* DEVICE_REVISION - [7:0] */ 1188 #define ARIZONA_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [7:0] */ 1189 #define ARIZONA_DEVICE_REVISION_WIDTH 8 /* DEVICE_REVISION - [7:0] */ 1190 1191 /* 1192 * R8 (0x08) - Ctrl IF SPI CFG 1 1193 */ 1194 #define ARIZONA_SPI_CFG 0x0010 /* SPI_CFG */ 1195 #define ARIZONA_SPI_CFG_MASK 0x0010 /* SPI_CFG */ 1196 #define ARIZONA_SPI_CFG_SHIFT 4 /* SPI_CFG */ 1197 #define ARIZONA_SPI_CFG_WIDTH 1 /* SPI_CFG */ 1198 #define ARIZONA_SPI_4WIRE 0x0008 /* SPI_4WIRE */ 1199 #define ARIZONA_SPI_4WIRE_MASK 0x0008 /* SPI_4WIRE */ 1200 #define ARIZONA_SPI_4WIRE_SHIFT 3 /* SPI_4WIRE */ 1201 #define ARIZONA_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */ 1202 #define ARIZONA_SPI_AUTO_INC_MASK 0x0003 /* SPI_AUTO_INC - [1:0] */ 1203 #define ARIZONA_SPI_AUTO_INC_SHIFT 0 /* SPI_AUTO_INC - [1:0] */ 1204 #define ARIZONA_SPI_AUTO_INC_WIDTH 2 /* SPI_AUTO_INC - [1:0] */ 1205 1206 /* 1207 * R9 (0x09) - Ctrl IF I2C1 CFG 1 1208 */ 1209 #define ARIZONA_I2C1_AUTO_INC_MASK 0x0003 /* I2C1_AUTO_INC - [1:0] */ 1210 #define ARIZONA_I2C1_AUTO_INC_SHIFT 0 /* I2C1_AUTO_INC - [1:0] */ 1211 #define ARIZONA_I2C1_AUTO_INC_WIDTH 2 /* I2C1_AUTO_INC - [1:0] */ 1212 1213 /* 1214 * R13 (0x0D) - Ctrl IF Status 1 1215 */ 1216 #define ARIZONA_I2C1_BUSY 0x0020 /* I2C1_BUSY */ 1217 #define ARIZONA_I2C1_BUSY_MASK 0x0020 /* I2C1_BUSY */ 1218 #define ARIZONA_I2C1_BUSY_SHIFT 5 /* I2C1_BUSY */ 1219 #define ARIZONA_I2C1_BUSY_WIDTH 1 /* I2C1_BUSY */ 1220 #define ARIZONA_SPI_BUSY 0x0010 /* SPI_BUSY */ 1221 #define ARIZONA_SPI_BUSY_MASK 0x0010 /* SPI_BUSY */ 1222 #define ARIZONA_SPI_BUSY_SHIFT 4 /* SPI_BUSY */ 1223 #define ARIZONA_SPI_BUSY_WIDTH 1 /* SPI_BUSY */ 1224 1225 /* 1226 * R22 (0x16) - Write Sequencer Ctrl 0 1227 */ 1228 #define ARIZONA_WSEQ_ABORT 0x0800 /* WSEQ_ABORT */ 1229 #define ARIZONA_WSEQ_ABORT_MASK 0x0800 /* WSEQ_ABORT */ 1230 #define ARIZONA_WSEQ_ABORT_SHIFT 11 /* WSEQ_ABORT */ 1231 #define ARIZONA_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 1232 #define ARIZONA_WSEQ_START 0x0400 /* WSEQ_START */ 1233 #define ARIZONA_WSEQ_START_MASK 0x0400 /* WSEQ_START */ 1234 #define ARIZONA_WSEQ_START_SHIFT 10 /* WSEQ_START */ 1235 #define ARIZONA_WSEQ_START_WIDTH 1 /* WSEQ_START */ 1236 #define ARIZONA_WSEQ_ENA 0x0200 /* WSEQ_ENA */ 1237 #define ARIZONA_WSEQ_ENA_MASK 0x0200 /* WSEQ_ENA */ 1238 #define ARIZONA_WSEQ_ENA_SHIFT 9 /* WSEQ_ENA */ 1239 #define ARIZONA_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 1240 #define ARIZONA_WSEQ_START_INDEX_MASK 0x01FF /* WSEQ_START_INDEX - [8:0] */ 1241 #define ARIZONA_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [8:0] */ 1242 #define ARIZONA_WSEQ_START_INDEX_WIDTH 9 /* WSEQ_START_INDEX - [8:0] */ 1243 1244 /* 1245 * R23 (0x17) - Write Sequencer Ctrl 1 1246 */ 1247 #define ARIZONA_WSEQ_BUSY 0x0200 /* WSEQ_BUSY */ 1248 #define ARIZONA_WSEQ_BUSY_MASK 0x0200 /* WSEQ_BUSY */ 1249 #define ARIZONA_WSEQ_BUSY_SHIFT 9 /* WSEQ_BUSY */ 1250 #define ARIZONA_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 1251 #define ARIZONA_WSEQ_CURRENT_INDEX_MASK 0x01FF /* WSEQ_CURRENT_INDEX - [8:0] */ 1252 #define ARIZONA_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [8:0] */ 1253 #define ARIZONA_WSEQ_CURRENT_INDEX_WIDTH 9 /* WSEQ_CURRENT_INDEX - [8:0] */ 1254 1255 /* 1256 * R24 (0x18) - Write Sequencer Ctrl 2 1257 */ 1258 #define ARIZONA_LOAD_DEFAULTS 0x0002 /* LOAD_DEFAULTS */ 1259 #define ARIZONA_LOAD_DEFAULTS_MASK 0x0002 /* LOAD_DEFAULTS */ 1260 #define ARIZONA_LOAD_DEFAULTS_SHIFT 1 /* LOAD_DEFAULTS */ 1261 #define ARIZONA_LOAD_DEFAULTS_WIDTH 1 /* LOAD_DEFAULTS */ 1262 #define ARIZONA_WSEQ_LOAD_MEM 0x0001 /* WSEQ_LOAD_MEM */ 1263 #define ARIZONA_WSEQ_LOAD_MEM_MASK 0x0001 /* WSEQ_LOAD_MEM */ 1264 #define ARIZONA_WSEQ_LOAD_MEM_SHIFT 0 /* WSEQ_LOAD_MEM */ 1265 #define ARIZONA_WSEQ_LOAD_MEM_WIDTH 1 /* WSEQ_LOAD_MEM */ 1266 1267 /* 1268 * R26 (0x1A) - Write Sequencer PROM 1269 */ 1270 #define ARIZONA_WSEQ_OTP_WRITE 0x0001 /* WSEQ_OTP_WRITE */ 1271 #define ARIZONA_WSEQ_OTP_WRITE_MASK 0x0001 /* WSEQ_OTP_WRITE */ 1272 #define ARIZONA_WSEQ_OTP_WRITE_SHIFT 0 /* WSEQ_OTP_WRITE */ 1273 #define ARIZONA_WSEQ_OTP_WRITE_WIDTH 1 /* WSEQ_OTP_WRITE */ 1274 1275 /* 1276 * R32 (0x20) - Tone Generator 1 1277 */ 1278 #define ARIZONA_TONE_RATE_MASK 0x7800 /* TONE_RATE - [14:11] */ 1279 #define ARIZONA_TONE_RATE_SHIFT 11 /* TONE_RATE - [14:11] */ 1280 #define ARIZONA_TONE_RATE_WIDTH 4 /* TONE_RATE - [14:11] */ 1281 #define ARIZONA_TONE_OFFSET_MASK 0x0300 /* TONE_OFFSET - [9:8] */ 1282 #define ARIZONA_TONE_OFFSET_SHIFT 8 /* TONE_OFFSET - [9:8] */ 1283 #define ARIZONA_TONE_OFFSET_WIDTH 2 /* TONE_OFFSET - [9:8] */ 1284 #define ARIZONA_TONE2_OVD 0x0020 /* TONE2_OVD */ 1285 #define ARIZONA_TONE2_OVD_MASK 0x0020 /* TONE2_OVD */ 1286 #define ARIZONA_TONE2_OVD_SHIFT 5 /* TONE2_OVD */ 1287 #define ARIZONA_TONE2_OVD_WIDTH 1 /* TONE2_OVD */ 1288 #define ARIZONA_TONE1_OVD 0x0010 /* TONE1_OVD */ 1289 #define ARIZONA_TONE1_OVD_MASK 0x0010 /* TONE1_OVD */ 1290 #define ARIZONA_TONE1_OVD_SHIFT 4 /* TONE1_OVD */ 1291 #define ARIZONA_TONE1_OVD_WIDTH 1 /* TONE1_OVD */ 1292 #define ARIZONA_TONE2_ENA 0x0002 /* TONE2_ENA */ 1293 #define ARIZONA_TONE2_ENA_MASK 0x0002 /* TONE2_ENA */ 1294 #define ARIZONA_TONE2_ENA_SHIFT 1 /* TONE2_ENA */ 1295 #define ARIZONA_TONE2_ENA_WIDTH 1 /* TONE2_ENA */ 1296 #define ARIZONA_TONE1_ENA 0x0001 /* TONE1_ENA */ 1297 #define ARIZONA_TONE1_ENA_MASK 0x0001 /* TONE1_ENA */ 1298 #define ARIZONA_TONE1_ENA_SHIFT 0 /* TONE1_ENA */ 1299 #define ARIZONA_TONE1_ENA_WIDTH 1 /* TONE1_ENA */ 1300 1301 /* 1302 * R33 (0x21) - Tone Generator 2 1303 */ 1304 #define ARIZONA_TONE1_LVL_0_MASK 0xFFFF /* TONE1_LVL - [15:0] */ 1305 #define ARIZONA_TONE1_LVL_0_SHIFT 0 /* TONE1_LVL - [15:0] */ 1306 #define ARIZONA_TONE1_LVL_0_WIDTH 16 /* TONE1_LVL - [15:0] */ 1307 1308 /* 1309 * R34 (0x22) - Tone Generator 3 1310 */ 1311 #define ARIZONA_TONE1_LVL_MASK 0x00FF /* TONE1_LVL - [7:0] */ 1312 #define ARIZONA_TONE1_LVL_SHIFT 0 /* TONE1_LVL - [7:0] */ 1313 #define ARIZONA_TONE1_LVL_WIDTH 8 /* TONE1_LVL - [7:0] */ 1314 1315 /* 1316 * R35 (0x23) - Tone Generator 4 1317 */ 1318 #define ARIZONA_TONE2_LVL_0_MASK 0xFFFF /* TONE2_LVL - [15:0] */ 1319 #define ARIZONA_TONE2_LVL_0_SHIFT 0 /* TONE2_LVL - [15:0] */ 1320 #define ARIZONA_TONE2_LVL_0_WIDTH 16 /* TONE2_LVL - [15:0] */ 1321 1322 /* 1323 * R36 (0x24) - Tone Generator 5 1324 */ 1325 #define ARIZONA_TONE2_LVL_MASK 0x00FF /* TONE2_LVL - [7:0] */ 1326 #define ARIZONA_TONE2_LVL_SHIFT 0 /* TONE2_LVL - [7:0] */ 1327 #define ARIZONA_TONE2_LVL_WIDTH 8 /* TONE2_LVL - [7:0] */ 1328 1329 /* 1330 * R48 (0x30) - PWM Drive 1 1331 */ 1332 #define ARIZONA_PWM_RATE_MASK 0x7800 /* PWM_RATE - [14:11] */ 1333 #define ARIZONA_PWM_RATE_SHIFT 11 /* PWM_RATE - [14:11] */ 1334 #define ARIZONA_PWM_RATE_WIDTH 4 /* PWM_RATE - [14:11] */ 1335 #define ARIZONA_PWM_CLK_SEL_MASK 0x0700 /* PWM_CLK_SEL - [10:8] */ 1336 #define ARIZONA_PWM_CLK_SEL_SHIFT 8 /* PWM_CLK_SEL - [10:8] */ 1337 #define ARIZONA_PWM_CLK_SEL_WIDTH 3 /* PWM_CLK_SEL - [10:8] */ 1338 #define ARIZONA_PWM2_OVD 0x0020 /* PWM2_OVD */ 1339 #define ARIZONA_PWM2_OVD_MASK 0x0020 /* PWM2_OVD */ 1340 #define ARIZONA_PWM2_OVD_SHIFT 5 /* PWM2_OVD */ 1341 #define ARIZONA_PWM2_OVD_WIDTH 1 /* PWM2_OVD */ 1342 #define ARIZONA_PWM1_OVD 0x0010 /* PWM1_OVD */ 1343 #define ARIZONA_PWM1_OVD_MASK 0x0010 /* PWM1_OVD */ 1344 #define ARIZONA_PWM1_OVD_SHIFT 4 /* PWM1_OVD */ 1345 #define ARIZONA_PWM1_OVD_WIDTH 1 /* PWM1_OVD */ 1346 #define ARIZONA_PWM2_ENA 0x0002 /* PWM2_ENA */ 1347 #define ARIZONA_PWM2_ENA_MASK 0x0002 /* PWM2_ENA */ 1348 #define ARIZONA_PWM2_ENA_SHIFT 1 /* PWM2_ENA */ 1349 #define ARIZONA_PWM2_ENA_WIDTH 1 /* PWM2_ENA */ 1350 #define ARIZONA_PWM1_ENA 0x0001 /* PWM1_ENA */ 1351 #define ARIZONA_PWM1_ENA_MASK 0x0001 /* PWM1_ENA */ 1352 #define ARIZONA_PWM1_ENA_SHIFT 0 /* PWM1_ENA */ 1353 #define ARIZONA_PWM1_ENA_WIDTH 1 /* PWM1_ENA */ 1354 1355 /* 1356 * R49 (0x31) - PWM Drive 2 1357 */ 1358 #define ARIZONA_PWM1_LVL_MASK 0x03FF /* PWM1_LVL - [9:0] */ 1359 #define ARIZONA_PWM1_LVL_SHIFT 0 /* PWM1_LVL - [9:0] */ 1360 #define ARIZONA_PWM1_LVL_WIDTH 10 /* PWM1_LVL - [9:0] */ 1361 1362 /* 1363 * R50 (0x32) - PWM Drive 3 1364 */ 1365 #define ARIZONA_PWM2_LVL_MASK 0x03FF /* PWM2_LVL - [9:0] */ 1366 #define ARIZONA_PWM2_LVL_SHIFT 0 /* PWM2_LVL - [9:0] */ 1367 #define ARIZONA_PWM2_LVL_WIDTH 10 /* PWM2_LVL - [9:0] */ 1368 1369 /* 1370 * R64 (0x40) - Wake control 1371 */ 1372 #define ARIZONA_WKUP_MICD_CLAMP_FALL 0x0080 /* WKUP_MICD_CLAMP_FALL */ 1373 #define ARIZONA_WKUP_MICD_CLAMP_FALL_MASK 0x0080 /* WKUP_MICD_CLAMP_FALL */ 1374 #define ARIZONA_WKUP_MICD_CLAMP_FALL_SHIFT 7 /* WKUP_MICD_CLAMP_FALL */ 1375 #define ARIZONA_WKUP_MICD_CLAMP_FALL_WIDTH 1 /* WKUP_MICD_CLAMP_FALL */ 1376 #define ARIZONA_WKUP_MICD_CLAMP_RISE 0x0040 /* WKUP_MICD_CLAMP_RISE */ 1377 #define ARIZONA_WKUP_MICD_CLAMP_RISE_MASK 0x0040 /* WKUP_MICD_CLAMP_RISE */ 1378 #define ARIZONA_WKUP_MICD_CLAMP_RISE_SHIFT 6 /* WKUP_MICD_CLAMP_RISE */ 1379 #define ARIZONA_WKUP_MICD_CLAMP_RISE_WIDTH 1 /* WKUP_MICD_CLAMP_RISE */ 1380 #define ARIZONA_WKUP_GP5_FALL 0x0020 /* WKUP_GP5_FALL */ 1381 #define ARIZONA_WKUP_GP5_FALL_MASK 0x0020 /* WKUP_GP5_FALL */ 1382 #define ARIZONA_WKUP_GP5_FALL_SHIFT 5 /* WKUP_GP5_FALL */ 1383 #define ARIZONA_WKUP_GP5_FALL_WIDTH 1 /* WKUP_GP5_FALL */ 1384 #define ARIZONA_WKUP_GP5_RISE 0x0010 /* WKUP_GP5_RISE */ 1385 #define ARIZONA_WKUP_GP5_RISE_MASK 0x0010 /* WKUP_GP5_RISE */ 1386 #define ARIZONA_WKUP_GP5_RISE_SHIFT 4 /* WKUP_GP5_RISE */ 1387 #define ARIZONA_WKUP_GP5_RISE_WIDTH 1 /* WKUP_GP5_RISE */ 1388 #define ARIZONA_WKUP_JD1_FALL 0x0008 /* WKUP_JD1_FALL */ 1389 #define ARIZONA_WKUP_JD1_FALL_MASK 0x0008 /* WKUP_JD1_FALL */ 1390 #define ARIZONA_WKUP_JD1_FALL_SHIFT 3 /* WKUP_JD1_FALL */ 1391 #define ARIZONA_WKUP_JD1_FALL_WIDTH 1 /* WKUP_JD1_FALL */ 1392 #define ARIZONA_WKUP_JD1_RISE 0x0004 /* WKUP_JD1_RISE */ 1393 #define ARIZONA_WKUP_JD1_RISE_MASK 0x0004 /* WKUP_JD1_RISE */ 1394 #define ARIZONA_WKUP_JD1_RISE_SHIFT 2 /* WKUP_JD1_RISE */ 1395 #define ARIZONA_WKUP_JD1_RISE_WIDTH 1 /* WKUP_JD1_RISE */ 1396 #define ARIZONA_WKUP_JD2_FALL 0x0002 /* WKUP_JD2_FALL */ 1397 #define ARIZONA_WKUP_JD2_FALL_MASK 0x0002 /* WKUP_JD2_FALL */ 1398 #define ARIZONA_WKUP_JD2_FALL_SHIFT 1 /* WKUP_JD2_FALL */ 1399 #define ARIZONA_WKUP_JD2_FALL_WIDTH 1 /* WKUP_JD2_FALL */ 1400 #define ARIZONA_WKUP_JD2_RISE 0x0001 /* WKUP_JD2_RISE */ 1401 #define ARIZONA_WKUP_JD2_RISE_MASK 0x0001 /* WKUP_JD2_RISE */ 1402 #define ARIZONA_WKUP_JD2_RISE_SHIFT 0 /* WKUP_JD2_RISE */ 1403 #define ARIZONA_WKUP_JD2_RISE_WIDTH 1 /* WKUP_JD2_RISE */ 1404 1405 /* 1406 * R65 (0x41) - Sequence control 1407 */ 1408 #define ARIZONA_WSEQ_ENA_GP5_FALL 0x0020 /* WSEQ_ENA_GP5_FALL */ 1409 #define ARIZONA_WSEQ_ENA_GP5_FALL_MASK 0x0020 /* WSEQ_ENA_GP5_FALL */ 1410 #define ARIZONA_WSEQ_ENA_GP5_FALL_SHIFT 5 /* WSEQ_ENA_GP5_FALL */ 1411 #define ARIZONA_WSEQ_ENA_GP5_FALL_WIDTH 1 /* WSEQ_ENA_GP5_FALL */ 1412 #define ARIZONA_WSEQ_ENA_GP5_RISE 0x0010 /* WSEQ_ENA_GP5_RISE */ 1413 #define ARIZONA_WSEQ_ENA_GP5_RISE_MASK 0x0010 /* WSEQ_ENA_GP5_RISE */ 1414 #define ARIZONA_WSEQ_ENA_GP5_RISE_SHIFT 4 /* WSEQ_ENA_GP5_RISE */ 1415 #define ARIZONA_WSEQ_ENA_GP5_RISE_WIDTH 1 /* WSEQ_ENA_GP5_RISE */ 1416 #define ARIZONA_WSEQ_ENA_JD1_FALL 0x0008 /* WSEQ_ENA_JD1_FALL */ 1417 #define ARIZONA_WSEQ_ENA_JD1_FALL_MASK 0x0008 /* WSEQ_ENA_JD1_FALL */ 1418 #define ARIZONA_WSEQ_ENA_JD1_FALL_SHIFT 3 /* WSEQ_ENA_JD1_FALL */ 1419 #define ARIZONA_WSEQ_ENA_JD1_FALL_WIDTH 1 /* WSEQ_ENA_JD1_FALL */ 1420 #define ARIZONA_WSEQ_ENA_JD1_RISE 0x0004 /* WSEQ_ENA_JD1_RISE */ 1421 #define ARIZONA_WSEQ_ENA_JD1_RISE_MASK 0x0004 /* WSEQ_ENA_JD1_RISE */ 1422 #define ARIZONA_WSEQ_ENA_JD1_RISE_SHIFT 2 /* WSEQ_ENA_JD1_RISE */ 1423 #define ARIZONA_WSEQ_ENA_JD1_RISE_WIDTH 1 /* WSEQ_ENA_JD1_RISE */ 1424 #define ARIZONA_WSEQ_ENA_JD2_FALL 0x0002 /* WSEQ_ENA_JD2_FALL */ 1425 #define ARIZONA_WSEQ_ENA_JD2_FALL_MASK 0x0002 /* WSEQ_ENA_JD2_FALL */ 1426 #define ARIZONA_WSEQ_ENA_JD2_FALL_SHIFT 1 /* WSEQ_ENA_JD2_FALL */ 1427 #define ARIZONA_WSEQ_ENA_JD2_FALL_WIDTH 1 /* WSEQ_ENA_JD2_FALL */ 1428 #define ARIZONA_WSEQ_ENA_JD2_RISE 0x0001 /* WSEQ_ENA_JD2_RISE */ 1429 #define ARIZONA_WSEQ_ENA_JD2_RISE_MASK 0x0001 /* WSEQ_ENA_JD2_RISE */ 1430 #define ARIZONA_WSEQ_ENA_JD2_RISE_SHIFT 0 /* WSEQ_ENA_JD2_RISE */ 1431 #define ARIZONA_WSEQ_ENA_JD2_RISE_WIDTH 1 /* WSEQ_ENA_JD2_RISE */ 1432 1433 /* 1434 * R97 (0x61) - Sample Rate Sequence Select 1 1435 */ 1436 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */ 1437 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */ 1438 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */ 1439 1440 /* 1441 * R98 (0x62) - Sample Rate Sequence Select 2 1442 */ 1443 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */ 1444 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */ 1445 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */ 1446 1447 /* 1448 * R99 (0x63) - Sample Rate Sequence Select 3 1449 */ 1450 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */ 1451 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */ 1452 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */ 1453 1454 /* 1455 * R100 (0x64) - Sample Rate Sequence Select 4 1456 */ 1457 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */ 1458 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */ 1459 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */ 1460 1461 /* 1462 * R104 (0x68) - Always On Triggers Sequence Select 1 1463 */ 1464 #define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */ 1465 #define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */ 1466 #define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */ 1467 1468 /* 1469 * R105 (0x69) - Always On Triggers Sequence Select 2 1470 */ 1471 #define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */ 1472 #define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */ 1473 #define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */ 1474 1475 /* 1476 * R106 (0x6A) - Always On Triggers Sequence Select 3 1477 */ 1478 #define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */ 1479 #define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */ 1480 #define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */ 1481 1482 /* 1483 * R107 (0x6B) - Always On Triggers Sequence Select 4 1484 */ 1485 #define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */ 1486 #define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */ 1487 #define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */ 1488 1489 /* 1490 * R108 (0x6C) - Always On Triggers Sequence Select 5 1491 */ 1492 #define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */ 1493 #define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */ 1494 #define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */ 1495 1496 /* 1497 * R109 (0x6D) - Always On Triggers Sequence Select 6 1498 */ 1499 #define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */ 1500 #define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */ 1501 #define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */ 1502 1503 /* 1504 * R112 (0x70) - Comfort Noise Generator 1505 */ 1506 #define ARIZONA_NOISE_GEN_RATE_MASK 0x7800 /* NOISE_GEN_RATE - [14:11] */ 1507 #define ARIZONA_NOISE_GEN_RATE_SHIFT 11 /* NOISE_GEN_RATE - [14:11] */ 1508 #define ARIZONA_NOISE_GEN_RATE_WIDTH 4 /* NOISE_GEN_RATE - [14:11] */ 1509 #define ARIZONA_NOISE_GEN_ENA 0x0020 /* NOISE_GEN_ENA */ 1510 #define ARIZONA_NOISE_GEN_ENA_MASK 0x0020 /* NOISE_GEN_ENA */ 1511 #define ARIZONA_NOISE_GEN_ENA_SHIFT 5 /* NOISE_GEN_ENA */ 1512 #define ARIZONA_NOISE_GEN_ENA_WIDTH 1 /* NOISE_GEN_ENA */ 1513 #define ARIZONA_NOISE_GEN_GAIN_MASK 0x001F /* NOISE_GEN_GAIN - [4:0] */ 1514 #define ARIZONA_NOISE_GEN_GAIN_SHIFT 0 /* NOISE_GEN_GAIN - [4:0] */ 1515 #define ARIZONA_NOISE_GEN_GAIN_WIDTH 5 /* NOISE_GEN_GAIN - [4:0] */ 1516 1517 /* 1518 * R144 (0x90) - Haptics Control 1 1519 */ 1520 #define ARIZONA_HAP_RATE_MASK 0x7800 /* HAP_RATE - [14:11] */ 1521 #define ARIZONA_HAP_RATE_SHIFT 11 /* HAP_RATE - [14:11] */ 1522 #define ARIZONA_HAP_RATE_WIDTH 4 /* HAP_RATE - [14:11] */ 1523 #define ARIZONA_ONESHOT_TRIG 0x0010 /* ONESHOT_TRIG */ 1524 #define ARIZONA_ONESHOT_TRIG_MASK 0x0010 /* ONESHOT_TRIG */ 1525 #define ARIZONA_ONESHOT_TRIG_SHIFT 4 /* ONESHOT_TRIG */ 1526 #define ARIZONA_ONESHOT_TRIG_WIDTH 1 /* ONESHOT_TRIG */ 1527 #define ARIZONA_HAP_CTRL_MASK 0x000C /* HAP_CTRL - [3:2] */ 1528 #define ARIZONA_HAP_CTRL_SHIFT 2 /* HAP_CTRL - [3:2] */ 1529 #define ARIZONA_HAP_CTRL_WIDTH 2 /* HAP_CTRL - [3:2] */ 1530 #define ARIZONA_HAP_ACT 0x0002 /* HAP_ACT */ 1531 #define ARIZONA_HAP_ACT_MASK 0x0002 /* HAP_ACT */ 1532 #define ARIZONA_HAP_ACT_SHIFT 1 /* HAP_ACT */ 1533 #define ARIZONA_HAP_ACT_WIDTH 1 /* HAP_ACT */ 1534 1535 /* 1536 * R145 (0x91) - Haptics Control 2 1537 */ 1538 #define ARIZONA_LRA_FREQ_MASK 0x7FFF /* LRA_FREQ - [14:0] */ 1539 #define ARIZONA_LRA_FREQ_SHIFT 0 /* LRA_FREQ - [14:0] */ 1540 #define ARIZONA_LRA_FREQ_WIDTH 15 /* LRA_FREQ - [14:0] */ 1541 1542 /* 1543 * R146 (0x92) - Haptics phase 1 intensity 1544 */ 1545 #define ARIZONA_PHASE1_INTENSITY_MASK 0x00FF /* PHASE1_INTENSITY - [7:0] */ 1546 #define ARIZONA_PHASE1_INTENSITY_SHIFT 0 /* PHASE1_INTENSITY - [7:0] */ 1547 #define ARIZONA_PHASE1_INTENSITY_WIDTH 8 /* PHASE1_INTENSITY - [7:0] */ 1548 1549 /* 1550 * R147 (0x93) - Haptics phase 1 duration 1551 */ 1552 #define ARIZONA_PHASE1_DURATION_MASK 0x01FF /* PHASE1_DURATION - [8:0] */ 1553 #define ARIZONA_PHASE1_DURATION_SHIFT 0 /* PHASE1_DURATION - [8:0] */ 1554 #define ARIZONA_PHASE1_DURATION_WIDTH 9 /* PHASE1_DURATION - [8:0] */ 1555 1556 /* 1557 * R148 (0x94) - Haptics phase 2 intensity 1558 */ 1559 #define ARIZONA_PHASE2_INTENSITY_MASK 0x00FF /* PHASE2_INTENSITY - [7:0] */ 1560 #define ARIZONA_PHASE2_INTENSITY_SHIFT 0 /* PHASE2_INTENSITY - [7:0] */ 1561 #define ARIZONA_PHASE2_INTENSITY_WIDTH 8 /* PHASE2_INTENSITY - [7:0] */ 1562 1563 /* 1564 * R149 (0x95) - Haptics phase 2 duration 1565 */ 1566 #define ARIZONA_PHASE2_DURATION_MASK 0x07FF /* PHASE2_DURATION - [10:0] */ 1567 #define ARIZONA_PHASE2_DURATION_SHIFT 0 /* PHASE2_DURATION - [10:0] */ 1568 #define ARIZONA_PHASE2_DURATION_WIDTH 11 /* PHASE2_DURATION - [10:0] */ 1569 1570 /* 1571 * R150 (0x96) - Haptics phase 3 intensity 1572 */ 1573 #define ARIZONA_PHASE3_INTENSITY_MASK 0x00FF /* PHASE3_INTENSITY - [7:0] */ 1574 #define ARIZONA_PHASE3_INTENSITY_SHIFT 0 /* PHASE3_INTENSITY - [7:0] */ 1575 #define ARIZONA_PHASE3_INTENSITY_WIDTH 8 /* PHASE3_INTENSITY - [7:0] */ 1576 1577 /* 1578 * R151 (0x97) - Haptics phase 3 duration 1579 */ 1580 #define ARIZONA_PHASE3_DURATION_MASK 0x01FF /* PHASE3_DURATION - [8:0] */ 1581 #define ARIZONA_PHASE3_DURATION_SHIFT 0 /* PHASE3_DURATION - [8:0] */ 1582 #define ARIZONA_PHASE3_DURATION_WIDTH 9 /* PHASE3_DURATION - [8:0] */ 1583 1584 /* 1585 * R152 (0x98) - Haptics Status 1586 */ 1587 #define ARIZONA_ONESHOT_STS 0x0001 /* ONESHOT_STS */ 1588 #define ARIZONA_ONESHOT_STS_MASK 0x0001 /* ONESHOT_STS */ 1589 #define ARIZONA_ONESHOT_STS_SHIFT 0 /* ONESHOT_STS */ 1590 #define ARIZONA_ONESHOT_STS_WIDTH 1 /* ONESHOT_STS */ 1591 1592 /* 1593 * R256 (0x100) - Clock 32k 1 1594 */ 1595 #define ARIZONA_CLK_32K_ENA 0x0040 /* CLK_32K_ENA */ 1596 #define ARIZONA_CLK_32K_ENA_MASK 0x0040 /* CLK_32K_ENA */ 1597 #define ARIZONA_CLK_32K_ENA_SHIFT 6 /* CLK_32K_ENA */ 1598 #define ARIZONA_CLK_32K_ENA_WIDTH 1 /* CLK_32K_ENA */ 1599 #define ARIZONA_CLK_32K_SRC_MASK 0x0003 /* CLK_32K_SRC - [1:0] */ 1600 #define ARIZONA_CLK_32K_SRC_SHIFT 0 /* CLK_32K_SRC - [1:0] */ 1601 #define ARIZONA_CLK_32K_SRC_WIDTH 2 /* CLK_32K_SRC - [1:0] */ 1602 1603 /* 1604 * R257 (0x101) - System Clock 1 1605 */ 1606 #define ARIZONA_SYSCLK_FRAC 0x8000 /* SYSCLK_FRAC */ 1607 #define ARIZONA_SYSCLK_FRAC_MASK 0x8000 /* SYSCLK_FRAC */ 1608 #define ARIZONA_SYSCLK_FRAC_SHIFT 15 /* SYSCLK_FRAC */ 1609 #define ARIZONA_SYSCLK_FRAC_WIDTH 1 /* SYSCLK_FRAC */ 1610 #define ARIZONA_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */ 1611 #define ARIZONA_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */ 1612 #define ARIZONA_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */ 1613 #define ARIZONA_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */ 1614 #define ARIZONA_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */ 1615 #define ARIZONA_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */ 1616 #define ARIZONA_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ 1617 #define ARIZONA_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */ 1618 #define ARIZONA_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */ 1619 #define ARIZONA_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */ 1620 1621 /* 1622 * R258 (0x102) - Sample rate 1 1623 */ 1624 #define ARIZONA_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */ 1625 #define ARIZONA_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */ 1626 #define ARIZONA_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */ 1627 1628 /* 1629 * R259 (0x103) - Sample rate 2 1630 */ 1631 #define ARIZONA_SAMPLE_RATE_2_MASK 0x001F /* SAMPLE_RATE_2 - [4:0] */ 1632 #define ARIZONA_SAMPLE_RATE_2_SHIFT 0 /* SAMPLE_RATE_2 - [4:0] */ 1633 #define ARIZONA_SAMPLE_RATE_2_WIDTH 5 /* SAMPLE_RATE_2 - [4:0] */ 1634 1635 /* 1636 * R260 (0x104) - Sample rate 3 1637 */ 1638 #define ARIZONA_SAMPLE_RATE_3_MASK 0x001F /* SAMPLE_RATE_3 - [4:0] */ 1639 #define ARIZONA_SAMPLE_RATE_3_SHIFT 0 /* SAMPLE_RATE_3 - [4:0] */ 1640 #define ARIZONA_SAMPLE_RATE_3_WIDTH 5 /* SAMPLE_RATE_3 - [4:0] */ 1641 1642 /* 1643 * R266 (0x10A) - Sample rate 1 status 1644 */ 1645 #define ARIZONA_SAMPLE_RATE_1_STS_MASK 0x001F /* SAMPLE_RATE_1_STS - [4:0] */ 1646 #define ARIZONA_SAMPLE_RATE_1_STS_SHIFT 0 /* SAMPLE_RATE_1_STS - [4:0] */ 1647 #define ARIZONA_SAMPLE_RATE_1_STS_WIDTH 5 /* SAMPLE_RATE_1_STS - [4:0] */ 1648 1649 /* 1650 * R267 (0x10B) - Sample rate 2 status 1651 */ 1652 #define ARIZONA_SAMPLE_RATE_2_STS_MASK 0x001F /* SAMPLE_RATE_2_STS - [4:0] */ 1653 #define ARIZONA_SAMPLE_RATE_2_STS_SHIFT 0 /* SAMPLE_RATE_2_STS - [4:0] */ 1654 #define ARIZONA_SAMPLE_RATE_2_STS_WIDTH 5 /* SAMPLE_RATE_2_STS - [4:0] */ 1655 1656 /* 1657 * R268 (0x10C) - Sample rate 3 status 1658 */ 1659 #define ARIZONA_SAMPLE_RATE_3_STS_MASK 0x001F /* SAMPLE_RATE_3_STS - [4:0] */ 1660 #define ARIZONA_SAMPLE_RATE_3_STS_SHIFT 0 /* SAMPLE_RATE_3_STS - [4:0] */ 1661 #define ARIZONA_SAMPLE_RATE_3_STS_WIDTH 5 /* SAMPLE_RATE_3_STS - [4:0] */ 1662 1663 /* 1664 * R274 (0x112) - Async clock 1 1665 */ 1666 #define ARIZONA_ASYNC_CLK_FREQ_MASK 0x0700 /* ASYNC_CLK_FREQ - [10:8] */ 1667 #define ARIZONA_ASYNC_CLK_FREQ_SHIFT 8 /* ASYNC_CLK_FREQ - [10:8] */ 1668 #define ARIZONA_ASYNC_CLK_FREQ_WIDTH 3 /* ASYNC_CLK_FREQ - [10:8] */ 1669 #define ARIZONA_ASYNC_CLK_ENA 0x0040 /* ASYNC_CLK_ENA */ 1670 #define ARIZONA_ASYNC_CLK_ENA_MASK 0x0040 /* ASYNC_CLK_ENA */ 1671 #define ARIZONA_ASYNC_CLK_ENA_SHIFT 6 /* ASYNC_CLK_ENA */ 1672 #define ARIZONA_ASYNC_CLK_ENA_WIDTH 1 /* ASYNC_CLK_ENA */ 1673 #define ARIZONA_ASYNC_CLK_SRC_MASK 0x000F /* ASYNC_CLK_SRC - [3:0] */ 1674 #define ARIZONA_ASYNC_CLK_SRC_SHIFT 0 /* ASYNC_CLK_SRC - [3:0] */ 1675 #define ARIZONA_ASYNC_CLK_SRC_WIDTH 4 /* ASYNC_CLK_SRC - [3:0] */ 1676 1677 /* 1678 * R275 (0x113) - Async sample rate 1 1679 */ 1680 #define ARIZONA_ASYNC_SAMPLE_RATE_1_MASK 0x001F /* ASYNC_SAMPLE_RATE_1 - [4:0] */ 1681 #define ARIZONA_ASYNC_SAMPLE_RATE_1_SHIFT 0 /* ASYNC_SAMPLE_RATE_1 - [4:0] */ 1682 #define ARIZONA_ASYNC_SAMPLE_RATE_1_WIDTH 5 /* ASYNC_SAMPLE_RATE_1 - [4:0] */ 1683 1684 /* 1685 * R276 (0x114) - Async sample rate 2 1686 */ 1687 #define ARIZONA_ASYNC_SAMPLE_RATE_2_MASK 0x001F /* ASYNC_SAMPLE_RATE_2 - [4:0] */ 1688 #define ARIZONA_ASYNC_SAMPLE_RATE_2_SHIFT 0 /* ASYNC_SAMPLE_RATE_2 - [4:0] */ 1689 #define ARIZONA_ASYNC_SAMPLE_RATE_2_WIDTH 5 /* ASYNC_SAMPLE_RATE_2 - [4:0] */ 1690 1691 /* 1692 * R283 (0x11B) - Async sample rate 1 status 1693 */ 1694 #define ARIZONA_ASYNC_SAMPLE_RATE_1_STS_MASK 0x001F /* ASYNC_SAMPLE_RATE_1_STS - [4:0] */ 1695 #define ARIZONA_ASYNC_SAMPLE_RATE_1_STS_SHIFT 0 /* ASYNC_SAMPLE_RATE_1_STS - [4:0] */ 1696 #define ARIZONA_ASYNC_SAMPLE_RATE_1_STS_WIDTH 5 /* ASYNC_SAMPLE_RATE_1_STS - [4:0] */ 1697 1698 /* 1699 * R284 (0x11C) - Async sample rate 2 status 1700 */ 1701 #define ARIZONA_ASYNC_SAMPLE_RATE_2_STS_MASK 0x001F /* ASYNC_SAMPLE_RATE_2_STS - [4:0] */ 1702 #define ARIZONA_ASYNC_SAMPLE_RATE_2_STS_SHIFT 0 /* ASYNC_SAMPLE_RATE_2_STS - [4:0] */ 1703 #define ARIZONA_ASYNC_SAMPLE_RATE_2_STS_WIDTH 5 /* ASYNC_SAMPLE_RATE_2_STS - [4:0] */ 1704 1705 /* 1706 * R329 (0x149) - Output system clock 1707 */ 1708 #define ARIZONA_OPCLK_ENA 0x8000 /* OPCLK_ENA */ 1709 #define ARIZONA_OPCLK_ENA_MASK 0x8000 /* OPCLK_ENA */ 1710 #define ARIZONA_OPCLK_ENA_SHIFT 15 /* OPCLK_ENA */ 1711 #define ARIZONA_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ 1712 #define ARIZONA_OPCLK_DIV_MASK 0x00F8 /* OPCLK_DIV - [7:3] */ 1713 #define ARIZONA_OPCLK_DIV_SHIFT 3 /* OPCLK_DIV - [7:3] */ 1714 #define ARIZONA_OPCLK_DIV_WIDTH 5 /* OPCLK_DIV - [7:3] */ 1715 #define ARIZONA_OPCLK_SEL_MASK 0x0007 /* OPCLK_SEL - [2:0] */ 1716 #define ARIZONA_OPCLK_SEL_SHIFT 0 /* OPCLK_SEL - [2:0] */ 1717 #define ARIZONA_OPCLK_SEL_WIDTH 3 /* OPCLK_SEL - [2:0] */ 1718 1719 /* 1720 * R330 (0x14A) - Output async clock 1721 */ 1722 #define ARIZONA_OPCLK_ASYNC_ENA 0x8000 /* OPCLK_ASYNC_ENA */ 1723 #define ARIZONA_OPCLK_ASYNC_ENA_MASK 0x8000 /* OPCLK_ASYNC_ENA */ 1724 #define ARIZONA_OPCLK_ASYNC_ENA_SHIFT 15 /* OPCLK_ASYNC_ENA */ 1725 #define ARIZONA_OPCLK_ASYNC_ENA_WIDTH 1 /* OPCLK_ASYNC_ENA */ 1726 #define ARIZONA_OPCLK_ASYNC_DIV_MASK 0x00F8 /* OPCLK_ASYNC_DIV - [7:3] */ 1727 #define ARIZONA_OPCLK_ASYNC_DIV_SHIFT 3 /* OPCLK_ASYNC_DIV - [7:3] */ 1728 #define ARIZONA_OPCLK_ASYNC_DIV_WIDTH 5 /* OPCLK_ASYNC_DIV - [7:3] */ 1729 #define ARIZONA_OPCLK_ASYNC_SEL_MASK 0x0007 /* OPCLK_ASYNC_SEL - [2:0] */ 1730 #define ARIZONA_OPCLK_ASYNC_SEL_SHIFT 0 /* OPCLK_ASYNC_SEL - [2:0] */ 1731 #define ARIZONA_OPCLK_ASYNC_SEL_WIDTH 3 /* OPCLK_ASYNC_SEL - [2:0] */ 1732 1733 /* 1734 * R338 (0x152) - Rate Estimator 1 1735 */ 1736 #define ARIZONA_TRIG_ON_STARTUP 0x0010 /* TRIG_ON_STARTUP */ 1737 #define ARIZONA_TRIG_ON_STARTUP_MASK 0x0010 /* TRIG_ON_STARTUP */ 1738 #define ARIZONA_TRIG_ON_STARTUP_SHIFT 4 /* TRIG_ON_STARTUP */ 1739 #define ARIZONA_TRIG_ON_STARTUP_WIDTH 1 /* TRIG_ON_STARTUP */ 1740 #define ARIZONA_LRCLK_SRC_MASK 0x000E /* LRCLK_SRC - [3:1] */ 1741 #define ARIZONA_LRCLK_SRC_SHIFT 1 /* LRCLK_SRC - [3:1] */ 1742 #define ARIZONA_LRCLK_SRC_WIDTH 3 /* LRCLK_SRC - [3:1] */ 1743 #define ARIZONA_RATE_EST_ENA 0x0001 /* RATE_EST_ENA */ 1744 #define ARIZONA_RATE_EST_ENA_MASK 0x0001 /* RATE_EST_ENA */ 1745 #define ARIZONA_RATE_EST_ENA_SHIFT 0 /* RATE_EST_ENA */ 1746 #define ARIZONA_RATE_EST_ENA_WIDTH 1 /* RATE_EST_ENA */ 1747 1748 /* 1749 * R339 (0x153) - Rate Estimator 2 1750 */ 1751 #define ARIZONA_SAMPLE_RATE_DETECT_A_MASK 0x001F /* SAMPLE_RATE_DETECT_A - [4:0] */ 1752 #define ARIZONA_SAMPLE_RATE_DETECT_A_SHIFT 0 /* SAMPLE_RATE_DETECT_A - [4:0] */ 1753 #define ARIZONA_SAMPLE_RATE_DETECT_A_WIDTH 5 /* SAMPLE_RATE_DETECT_A - [4:0] */ 1754 1755 /* 1756 * R340 (0x154) - Rate Estimator 3 1757 */ 1758 #define ARIZONA_SAMPLE_RATE_DETECT_B_MASK 0x001F /* SAMPLE_RATE_DETECT_B - [4:0] */ 1759 #define ARIZONA_SAMPLE_RATE_DETECT_B_SHIFT 0 /* SAMPLE_RATE_DETECT_B - [4:0] */ 1760 #define ARIZONA_SAMPLE_RATE_DETECT_B_WIDTH 5 /* SAMPLE_RATE_DETECT_B - [4:0] */ 1761 1762 /* 1763 * R341 (0x155) - Rate Estimator 4 1764 */ 1765 #define ARIZONA_SAMPLE_RATE_DETECT_C_MASK 0x001F /* SAMPLE_RATE_DETECT_C - [4:0] */ 1766 #define ARIZONA_SAMPLE_RATE_DETECT_C_SHIFT 0 /* SAMPLE_RATE_DETECT_C - [4:0] */ 1767 #define ARIZONA_SAMPLE_RATE_DETECT_C_WIDTH 5 /* SAMPLE_RATE_DETECT_C - [4:0] */ 1768 1769 /* 1770 * R342 (0x156) - Rate Estimator 5 1771 */ 1772 #define ARIZONA_SAMPLE_RATE_DETECT_D_MASK 0x001F /* SAMPLE_RATE_DETECT_D - [4:0] */ 1773 #define ARIZONA_SAMPLE_RATE_DETECT_D_SHIFT 0 /* SAMPLE_RATE_DETECT_D - [4:0] */ 1774 #define ARIZONA_SAMPLE_RATE_DETECT_D_WIDTH 5 /* SAMPLE_RATE_DETECT_D - [4:0] */ 1775 1776 /* 1777 * R353 (0x161) - Dynamic Frequency Scaling 1 1778 */ 1779 #define ARIZONA_SUBSYS_MAX_FREQ 0x0001 /* SUBSYS_MAX_FREQ */ 1780 #define ARIZONA_SUBSYS_MAX_FREQ_SHIFT 0 /* SUBSYS_MAX_FREQ */ 1781 #define ARIZONA_SUBSYS_MAX_FREQ_WIDTH 1 /* SUBSYS_MAX_FREQ */ 1782 1783 /* 1784 * R369 (0x171) - FLL1 Control 1 1785 */ 1786 #define ARIZONA_FLL1_FREERUN 0x0002 /* FLL1_FREERUN */ 1787 #define ARIZONA_FLL1_FREERUN_MASK 0x0002 /* FLL1_FREERUN */ 1788 #define ARIZONA_FLL1_FREERUN_SHIFT 1 /* FLL1_FREERUN */ 1789 #define ARIZONA_FLL1_FREERUN_WIDTH 1 /* FLL1_FREERUN */ 1790 #define ARIZONA_FLL1_ENA 0x0001 /* FLL1_ENA */ 1791 #define ARIZONA_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */ 1792 #define ARIZONA_FLL1_ENA_SHIFT 0 /* FLL1_ENA */ 1793 #define ARIZONA_FLL1_ENA_WIDTH 1 /* FLL1_ENA */ 1794 1795 /* 1796 * R370 (0x172) - FLL1 Control 2 1797 */ 1798 #define ARIZONA_FLL1_CTRL_UPD 0x8000 /* FLL1_CTRL_UPD */ 1799 #define ARIZONA_FLL1_CTRL_UPD_MASK 0x8000 /* FLL1_CTRL_UPD */ 1800 #define ARIZONA_FLL1_CTRL_UPD_SHIFT 15 /* FLL1_CTRL_UPD */ 1801 #define ARIZONA_FLL1_CTRL_UPD_WIDTH 1 /* FLL1_CTRL_UPD */ 1802 #define ARIZONA_FLL1_N_MASK 0x03FF /* FLL1_N - [9:0] */ 1803 #define ARIZONA_FLL1_N_SHIFT 0 /* FLL1_N - [9:0] */ 1804 #define ARIZONA_FLL1_N_WIDTH 10 /* FLL1_N - [9:0] */ 1805 1806 /* 1807 * R371 (0x173) - FLL1 Control 3 1808 */ 1809 #define ARIZONA_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */ 1810 #define ARIZONA_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */ 1811 #define ARIZONA_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */ 1812 1813 /* 1814 * R372 (0x174) - FLL1 Control 4 1815 */ 1816 #define ARIZONA_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */ 1817 #define ARIZONA_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */ 1818 #define ARIZONA_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */ 1819 1820 /* 1821 * R373 (0x175) - FLL1 Control 5 1822 */ 1823 #define ARIZONA_FLL1_FRATIO_MASK 0x0F00 /* FLL1_FRATIO - [11:8] */ 1824 #define ARIZONA_FLL1_FRATIO_SHIFT 8 /* FLL1_FRATIO - [11:8] */ 1825 #define ARIZONA_FLL1_FRATIO_WIDTH 4 /* FLL1_FRATIO - [11:8] */ 1826 #define ARIZONA_FLL1_OUTDIV_MASK 0x000E /* FLL1_OUTDIV - [3:1] */ 1827 #define ARIZONA_FLL1_OUTDIV_SHIFT 1 /* FLL1_OUTDIV - [3:1] */ 1828 #define ARIZONA_FLL1_OUTDIV_WIDTH 3 /* FLL1_OUTDIV - [3:1] */ 1829 1830 /* 1831 * R374 (0x176) - FLL1 Control 6 1832 */ 1833 #define ARIZONA_FLL1_CLK_REF_DIV_MASK 0x00C0 /* FLL1_CLK_REF_DIV - [7:6] */ 1834 #define ARIZONA_FLL1_CLK_REF_DIV_SHIFT 6 /* FLL1_CLK_REF_DIV - [7:6] */ 1835 #define ARIZONA_FLL1_CLK_REF_DIV_WIDTH 2 /* FLL1_CLK_REF_DIV - [7:6] */ 1836 #define ARIZONA_FLL1_CLK_REF_SRC_MASK 0x000F /* FLL1_CLK_REF_SRC - [3:0] */ 1837 #define ARIZONA_FLL1_CLK_REF_SRC_SHIFT 0 /* FLL1_CLK_REF_SRC - [3:0] */ 1838 #define ARIZONA_FLL1_CLK_REF_SRC_WIDTH 4 /* FLL1_CLK_REF_SRC - [3:0] */ 1839 1840 /* 1841 * R375 (0x177) - FLL1 Loop Filter Test 1 1842 */ 1843 #define ARIZONA_FLL1_FRC_INTEG_UPD 0x8000 /* FLL1_FRC_INTEG_UPD */ 1844 #define ARIZONA_FLL1_FRC_INTEG_UPD_MASK 0x8000 /* FLL1_FRC_INTEG_UPD */ 1845 #define ARIZONA_FLL1_FRC_INTEG_UPD_SHIFT 15 /* FLL1_FRC_INTEG_UPD */ 1846 #define ARIZONA_FLL1_FRC_INTEG_UPD_WIDTH 1 /* FLL1_FRC_INTEG_UPD */ 1847 #define ARIZONA_FLL1_FRC_INTEG_VAL_MASK 0x0FFF /* FLL1_FRC_INTEG_VAL - [11:0] */ 1848 #define ARIZONA_FLL1_FRC_INTEG_VAL_SHIFT 0 /* FLL1_FRC_INTEG_VAL - [11:0] */ 1849 #define ARIZONA_FLL1_FRC_INTEG_VAL_WIDTH 12 /* FLL1_FRC_INTEG_VAL - [11:0] */ 1850 1851 /* 1852 * R377 (0x179) - FLL1 Control 7 1853 */ 1854 #define ARIZONA_FLL1_GAIN_MASK 0x003c /* FLL1_GAIN */ 1855 #define ARIZONA_FLL1_GAIN_SHIFT 2 /* FLL1_GAIN */ 1856 #define ARIZONA_FLL1_GAIN_WIDTH 4 /* FLL1_GAIN */ 1857 1858 /* 1859 * R385 (0x181) - FLL1 Synchroniser 1 1860 */ 1861 #define ARIZONA_FLL1_SYNC_ENA 0x0001 /* FLL1_SYNC_ENA */ 1862 #define ARIZONA_FLL1_SYNC_ENA_MASK 0x0001 /* FLL1_SYNC_ENA */ 1863 #define ARIZONA_FLL1_SYNC_ENA_SHIFT 0 /* FLL1_SYNC_ENA */ 1864 #define ARIZONA_FLL1_SYNC_ENA_WIDTH 1 /* FLL1_SYNC_ENA */ 1865 1866 /* 1867 * R386 (0x182) - FLL1 Synchroniser 2 1868 */ 1869 #define ARIZONA_FLL1_SYNC_N_MASK 0x03FF /* FLL1_SYNC_N - [9:0] */ 1870 #define ARIZONA_FLL1_SYNC_N_SHIFT 0 /* FLL1_SYNC_N - [9:0] */ 1871 #define ARIZONA_FLL1_SYNC_N_WIDTH 10 /* FLL1_SYNC_N - [9:0] */ 1872 1873 /* 1874 * R387 (0x183) - FLL1 Synchroniser 3 1875 */ 1876 #define ARIZONA_FLL1_SYNC_THETA_MASK 0xFFFF /* FLL1_SYNC_THETA - [15:0] */ 1877 #define ARIZONA_FLL1_SYNC_THETA_SHIFT 0 /* FLL1_SYNC_THETA - [15:0] */ 1878 #define ARIZONA_FLL1_SYNC_THETA_WIDTH 16 /* FLL1_SYNC_THETA - [15:0] */ 1879 1880 /* 1881 * R388 (0x184) - FLL1 Synchroniser 4 1882 */ 1883 #define ARIZONA_FLL1_SYNC_LAMBDA_MASK 0xFFFF /* FLL1_SYNC_LAMBDA - [15:0] */ 1884 #define ARIZONA_FLL1_SYNC_LAMBDA_SHIFT 0 /* FLL1_SYNC_LAMBDA - [15:0] */ 1885 #define ARIZONA_FLL1_SYNC_LAMBDA_WIDTH 16 /* FLL1_SYNC_LAMBDA - [15:0] */ 1886 1887 /* 1888 * R389 (0x185) - FLL1 Synchroniser 5 1889 */ 1890 #define ARIZONA_FLL1_SYNC_FRATIO_MASK 0x0700 /* FLL1_SYNC_FRATIO - [10:8] */ 1891 #define ARIZONA_FLL1_SYNC_FRATIO_SHIFT 8 /* FLL1_SYNC_FRATIO - [10:8] */ 1892 #define ARIZONA_FLL1_SYNC_FRATIO_WIDTH 3 /* FLL1_SYNC_FRATIO - [10:8] */ 1893 1894 /* 1895 * R390 (0x186) - FLL1 Synchroniser 6 1896 */ 1897 #define ARIZONA_FLL1_CLK_SYNC_DIV_MASK 0x00C0 /* FLL1_CLK_SYNC_DIV - [7:6] */ 1898 #define ARIZONA_FLL1_CLK_SYNC_DIV_SHIFT 6 /* FLL1_CLK_SYNC_DIV - [7:6] */ 1899 #define ARIZONA_FLL1_CLK_SYNC_DIV_WIDTH 2 /* FLL1_CLK_SYNC_DIV - [7:6] */ 1900 #define ARIZONA_FLL1_CLK_SYNC_SRC_MASK 0x000F /* FLL1_CLK_SYNC_SRC - [3:0] */ 1901 #define ARIZONA_FLL1_CLK_SYNC_SRC_SHIFT 0 /* FLL1_CLK_SYNC_SRC - [3:0] */ 1902 #define ARIZONA_FLL1_CLK_SYNC_SRC_WIDTH 4 /* FLL1_CLK_SYNC_SRC - [3:0] */ 1903 1904 /* 1905 * R391 (0x187) - FLL1 Synchroniser 7 1906 */ 1907 #define ARIZONA_FLL1_SYNC_GAIN_MASK 0x003c /* FLL1_SYNC_GAIN */ 1908 #define ARIZONA_FLL1_SYNC_GAIN_SHIFT 2 /* FLL1_SYNC_GAIN */ 1909 #define ARIZONA_FLL1_SYNC_GAIN_WIDTH 4 /* FLL1_SYNC_GAIN */ 1910 #define ARIZONA_FLL1_SYNC_BW 0x0001 /* FLL1_SYNC_BW */ 1911 #define ARIZONA_FLL1_SYNC_BW_MASK 0x0001 /* FLL1_SYNC_BW */ 1912 #define ARIZONA_FLL1_SYNC_BW_SHIFT 0 /* FLL1_SYNC_BW */ 1913 #define ARIZONA_FLL1_SYNC_BW_WIDTH 1 /* FLL1_SYNC_BW */ 1914 1915 /* 1916 * R393 (0x189) - FLL1 Spread Spectrum 1917 */ 1918 #define ARIZONA_FLL1_SS_AMPL_MASK 0x0030 /* FLL1_SS_AMPL - [5:4] */ 1919 #define ARIZONA_FLL1_SS_AMPL_SHIFT 4 /* FLL1_SS_AMPL - [5:4] */ 1920 #define ARIZONA_FLL1_SS_AMPL_WIDTH 2 /* FLL1_SS_AMPL - [5:4] */ 1921 #define ARIZONA_FLL1_SS_FREQ_MASK 0x000C /* FLL1_SS_FREQ - [3:2] */ 1922 #define ARIZONA_FLL1_SS_FREQ_SHIFT 2 /* FLL1_SS_FREQ - [3:2] */ 1923 #define ARIZONA_FLL1_SS_FREQ_WIDTH 2 /* FLL1_SS_FREQ - [3:2] */ 1924 #define ARIZONA_FLL1_SS_SEL_MASK 0x0003 /* FLL1_SS_SEL - [1:0] */ 1925 #define ARIZONA_FLL1_SS_SEL_SHIFT 0 /* FLL1_SS_SEL - [1:0] */ 1926 #define ARIZONA_FLL1_SS_SEL_WIDTH 2 /* FLL1_SS_SEL - [1:0] */ 1927 1928 /* 1929 * R394 (0x18A) - FLL1 GPIO Clock 1930 */ 1931 #define ARIZONA_FLL1_GPDIV_MASK 0x00FE /* FLL1_GPDIV - [7:1] */ 1932 #define ARIZONA_FLL1_GPDIV_SHIFT 1 /* FLL1_GPDIV - [7:1] */ 1933 #define ARIZONA_FLL1_GPDIV_WIDTH 7 /* FLL1_GPDIV - [7:1] */ 1934 #define ARIZONA_FLL1_GPDIV_ENA 0x0001 /* FLL1_GPDIV_ENA */ 1935 #define ARIZONA_FLL1_GPDIV_ENA_MASK 0x0001 /* FLL1_GPDIV_ENA */ 1936 #define ARIZONA_FLL1_GPDIV_ENA_SHIFT 0 /* FLL1_GPDIV_ENA */ 1937 #define ARIZONA_FLL1_GPDIV_ENA_WIDTH 1 /* FLL1_GPDIV_ENA */ 1938 1939 /* 1940 * R401 (0x191) - FLL2 Control 1 1941 */ 1942 #define ARIZONA_FLL2_FREERUN 0x0002 /* FLL2_FREERUN */ 1943 #define ARIZONA_FLL2_FREERUN_MASK 0x0002 /* FLL2_FREERUN */ 1944 #define ARIZONA_FLL2_FREERUN_SHIFT 1 /* FLL2_FREERUN */ 1945 #define ARIZONA_FLL2_FREERUN_WIDTH 1 /* FLL2_FREERUN */ 1946 #define ARIZONA_FLL2_ENA 0x0001 /* FLL2_ENA */ 1947 #define ARIZONA_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */ 1948 #define ARIZONA_FLL2_ENA_SHIFT 0 /* FLL2_ENA */ 1949 #define ARIZONA_FLL2_ENA_WIDTH 1 /* FLL2_ENA */ 1950 1951 /* 1952 * R402 (0x192) - FLL2 Control 2 1953 */ 1954 #define ARIZONA_FLL2_CTRL_UPD 0x8000 /* FLL2_CTRL_UPD */ 1955 #define ARIZONA_FLL2_CTRL_UPD_MASK 0x8000 /* FLL2_CTRL_UPD */ 1956 #define ARIZONA_FLL2_CTRL_UPD_SHIFT 15 /* FLL2_CTRL_UPD */ 1957 #define ARIZONA_FLL2_CTRL_UPD_WIDTH 1 /* FLL2_CTRL_UPD */ 1958 #define ARIZONA_FLL2_N_MASK 0x03FF /* FLL2_N - [9:0] */ 1959 #define ARIZONA_FLL2_N_SHIFT 0 /* FLL2_N - [9:0] */ 1960 #define ARIZONA_FLL2_N_WIDTH 10 /* FLL2_N - [9:0] */ 1961 1962 /* 1963 * R403 (0x193) - FLL2 Control 3 1964 */ 1965 #define ARIZONA_FLL2_THETA_MASK 0xFFFF /* FLL2_THETA - [15:0] */ 1966 #define ARIZONA_FLL2_THETA_SHIFT 0 /* FLL2_THETA - [15:0] */ 1967 #define ARIZONA_FLL2_THETA_WIDTH 16 /* FLL2_THETA - [15:0] */ 1968 1969 /* 1970 * R404 (0x194) - FLL2 Control 4 1971 */ 1972 #define ARIZONA_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */ 1973 #define ARIZONA_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */ 1974 #define ARIZONA_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */ 1975 1976 /* 1977 * R405 (0x195) - FLL2 Control 5 1978 */ 1979 #define ARIZONA_FLL2_FRATIO_MASK 0x0700 /* FLL2_FRATIO - [10:8] */ 1980 #define ARIZONA_FLL2_FRATIO_SHIFT 8 /* FLL2_FRATIO - [10:8] */ 1981 #define ARIZONA_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [10:8] */ 1982 #define ARIZONA_FLL2_OUTDIV_MASK 0x000E /* FLL2_OUTDIV - [3:1] */ 1983 #define ARIZONA_FLL2_OUTDIV_SHIFT 1 /* FLL2_OUTDIV - [3:1] */ 1984 #define ARIZONA_FLL2_OUTDIV_WIDTH 3 /* FLL2_OUTDIV - [3:1] */ 1985 1986 /* 1987 * R406 (0x196) - FLL2 Control 6 1988 */ 1989 #define ARIZONA_FLL2_CLK_REF_DIV_MASK 0x00C0 /* FLL2_CLK_REF_DIV - [7:6] */ 1990 #define ARIZONA_FLL2_CLK_REF_DIV_SHIFT 6 /* FLL2_CLK_REF_DIV - [7:6] */ 1991 #define ARIZONA_FLL2_CLK_REF_DIV_WIDTH 2 /* FLL2_CLK_REF_DIV - [7:6] */ 1992 #define ARIZONA_FLL2_CLK_REF_SRC_MASK 0x000F /* FLL2_CLK_REF_SRC - [3:0] */ 1993 #define ARIZONA_FLL2_CLK_REF_SRC_SHIFT 0 /* FLL2_CLK_REF_SRC - [3:0] */ 1994 #define ARIZONA_FLL2_CLK_REF_SRC_WIDTH 4 /* FLL2_CLK_REF_SRC - [3:0] */ 1995 1996 /* 1997 * R407 (0x197) - FLL2 Loop Filter Test 1 1998 */ 1999 #define ARIZONA_FLL2_FRC_INTEG_UPD 0x8000 /* FLL2_FRC_INTEG_UPD */ 2000 #define ARIZONA_FLL2_FRC_INTEG_UPD_MASK 0x8000 /* FLL2_FRC_INTEG_UPD */ 2001 #define ARIZONA_FLL2_FRC_INTEG_UPD_SHIFT 15 /* FLL2_FRC_INTEG_UPD */ 2002 #define ARIZONA_FLL2_FRC_INTEG_UPD_WIDTH 1 /* FLL2_FRC_INTEG_UPD */ 2003 #define ARIZONA_FLL2_FRC_INTEG_VAL_MASK 0x0FFF /* FLL2_FRC_INTEG_VAL - [11:0] */ 2004 #define ARIZONA_FLL2_FRC_INTEG_VAL_SHIFT 0 /* FLL2_FRC_INTEG_VAL - [11:0] */ 2005 #define ARIZONA_FLL2_FRC_INTEG_VAL_WIDTH 12 /* FLL2_FRC_INTEG_VAL - [11:0] */ 2006 2007 /* 2008 * R409 (0x199) - FLL2 Control 7 2009 */ 2010 #define ARIZONA_FLL2_GAIN_MASK 0x003c /* FLL2_GAIN */ 2011 #define ARIZONA_FLL2_GAIN_SHIFT 2 /* FLL2_GAIN */ 2012 #define ARIZONA_FLL2_GAIN_WIDTH 4 /* FLL2_GAIN */ 2013 2014 /* 2015 * R417 (0x1A1) - FLL2 Synchroniser 1 2016 */ 2017 #define ARIZONA_FLL2_SYNC_ENA 0x0001 /* FLL2_SYNC_ENA */ 2018 #define ARIZONA_FLL2_SYNC_ENA_MASK 0x0001 /* FLL2_SYNC_ENA */ 2019 #define ARIZONA_FLL2_SYNC_ENA_SHIFT 0 /* FLL2_SYNC_ENA */ 2020 #define ARIZONA_FLL2_SYNC_ENA_WIDTH 1 /* FLL2_SYNC_ENA */ 2021 2022 /* 2023 * R418 (0x1A2) - FLL2 Synchroniser 2 2024 */ 2025 #define ARIZONA_FLL2_SYNC_N_MASK 0x03FF /* FLL2_SYNC_N - [9:0] */ 2026 #define ARIZONA_FLL2_SYNC_N_SHIFT 0 /* FLL2_SYNC_N - [9:0] */ 2027 #define ARIZONA_FLL2_SYNC_N_WIDTH 10 /* FLL2_SYNC_N - [9:0] */ 2028 2029 /* 2030 * R419 (0x1A3) - FLL2 Synchroniser 3 2031 */ 2032 #define ARIZONA_FLL2_SYNC_THETA_MASK 0xFFFF /* FLL2_SYNC_THETA - [15:0] */ 2033 #define ARIZONA_FLL2_SYNC_THETA_SHIFT 0 /* FLL2_SYNC_THETA - [15:0] */ 2034 #define ARIZONA_FLL2_SYNC_THETA_WIDTH 16 /* FLL2_SYNC_THETA - [15:0] */ 2035 2036 /* 2037 * R420 (0x1A4) - FLL2 Synchroniser 4 2038 */ 2039 #define ARIZONA_FLL2_SYNC_LAMBDA_MASK 0xFFFF /* FLL2_SYNC_LAMBDA - [15:0] */ 2040 #define ARIZONA_FLL2_SYNC_LAMBDA_SHIFT 0 /* FLL2_SYNC_LAMBDA - [15:0] */ 2041 #define ARIZONA_FLL2_SYNC_LAMBDA_WIDTH 16 /* FLL2_SYNC_LAMBDA - [15:0] */ 2042 2043 /* 2044 * R421 (0x1A5) - FLL2 Synchroniser 5 2045 */ 2046 #define ARIZONA_FLL2_SYNC_FRATIO_MASK 0x0700 /* FLL2_SYNC_FRATIO - [10:8] */ 2047 #define ARIZONA_FLL2_SYNC_FRATIO_SHIFT 8 /* FLL2_SYNC_FRATIO - [10:8] */ 2048 #define ARIZONA_FLL2_SYNC_FRATIO_WIDTH 3 /* FLL2_SYNC_FRATIO - [10:8] */ 2049 2050 /* 2051 * R422 (0x1A6) - FLL2 Synchroniser 6 2052 */ 2053 #define ARIZONA_FLL2_CLK_SYNC_DIV_MASK 0x00C0 /* FLL2_CLK_SYNC_DIV - [7:6] */ 2054 #define ARIZONA_FLL2_CLK_SYNC_DIV_SHIFT 6 /* FLL2_CLK_SYNC_DIV - [7:6] */ 2055 #define ARIZONA_FLL2_CLK_SYNC_DIV_WIDTH 2 /* FLL2_CLK_SYNC_DIV - [7:6] */ 2056 #define ARIZONA_FLL2_CLK_SYNC_SRC_MASK 0x000F /* FLL2_CLK_SYNC_SRC - [3:0] */ 2057 #define ARIZONA_FLL2_CLK_SYNC_SRC_SHIFT 0 /* FLL2_CLK_SYNC_SRC - [3:0] */ 2058 #define ARIZONA_FLL2_CLK_SYNC_SRC_WIDTH 4 /* FLL2_CLK_SYNC_SRC - [3:0] */ 2059 2060 /* 2061 * R423 (0x1A7) - FLL2 Synchroniser 7 2062 */ 2063 #define ARIZONA_FLL2_SYNC_GAIN_MASK 0x003c /* FLL2_SYNC_GAIN */ 2064 #define ARIZONA_FLL2_SYNC_GAIN_SHIFT 2 /* FLL2_SYNC_GAIN */ 2065 #define ARIZONA_FLL2_SYNC_GAIN_WIDTH 4 /* FLL2_SYNC_GAIN */ 2066 #define ARIZONA_FLL2_SYNC_BW 0x0001 /* FLL2_SYNC_BW */ 2067 #define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */ 2068 #define ARIZONA_FLL2_SYNC_BW_SHIFT 0 /* FLL2_SYNC_BW */ 2069 #define ARIZONA_FLL2_SYNC_BW_WIDTH 1 /* FLL2_SYNC_BW */ 2070 2071 /* 2072 * R425 (0x1A9) - FLL2 Spread Spectrum 2073 */ 2074 #define ARIZONA_FLL2_SS_AMPL_MASK 0x0030 /* FLL2_SS_AMPL - [5:4] */ 2075 #define ARIZONA_FLL2_SS_AMPL_SHIFT 4 /* FLL2_SS_AMPL - [5:4] */ 2076 #define ARIZONA_FLL2_SS_AMPL_WIDTH 2 /* FLL2_SS_AMPL - [5:4] */ 2077 #define ARIZONA_FLL2_SS_FREQ_MASK 0x000C /* FLL2_SS_FREQ - [3:2] */ 2078 #define ARIZONA_FLL2_SS_FREQ_SHIFT 2 /* FLL2_SS_FREQ - [3:2] */ 2079 #define ARIZONA_FLL2_SS_FREQ_WIDTH 2 /* FLL2_SS_FREQ - [3:2] */ 2080 #define ARIZONA_FLL2_SS_SEL_MASK 0x0003 /* FLL2_SS_SEL - [1:0] */ 2081 #define ARIZONA_FLL2_SS_SEL_SHIFT 0 /* FLL2_SS_SEL - [1:0] */ 2082 #define ARIZONA_FLL2_SS_SEL_WIDTH 2 /* FLL2_SS_SEL - [1:0] */ 2083 2084 /* 2085 * R426 (0x1AA) - FLL2 GPIO Clock 2086 */ 2087 #define ARIZONA_FLL2_GPDIV_MASK 0x00FE /* FLL2_GPDIV - [7:1] */ 2088 #define ARIZONA_FLL2_GPDIV_SHIFT 1 /* FLL2_GPDIV - [7:1] */ 2089 #define ARIZONA_FLL2_GPDIV_WIDTH 7 /* FLL2_GPDIV - [7:1] */ 2090 #define ARIZONA_FLL2_GPDIV_ENA 0x0001 /* FLL2_GPDIV_ENA */ 2091 #define ARIZONA_FLL2_GPDIV_ENA_MASK 0x0001 /* FLL2_GPDIV_ENA */ 2092 #define ARIZONA_FLL2_GPDIV_ENA_SHIFT 0 /* FLL2_GPDIV_ENA */ 2093 #define ARIZONA_FLL2_GPDIV_ENA_WIDTH 1 /* FLL2_GPDIV_ENA */ 2094 2095 /* 2096 * R512 (0x200) - Mic Charge Pump 1 2097 */ 2098 #define ARIZONA_CPMIC_DISCH 0x0004 /* CPMIC_DISCH */ 2099 #define ARIZONA_CPMIC_DISCH_MASK 0x0004 /* CPMIC_DISCH */ 2100 #define ARIZONA_CPMIC_DISCH_SHIFT 2 /* CPMIC_DISCH */ 2101 #define ARIZONA_CPMIC_DISCH_WIDTH 1 /* CPMIC_DISCH */ 2102 #define ARIZONA_CPMIC_BYPASS 0x0002 /* CPMIC_BYPASS */ 2103 #define ARIZONA_CPMIC_BYPASS_MASK 0x0002 /* CPMIC_BYPASS */ 2104 #define ARIZONA_CPMIC_BYPASS_SHIFT 1 /* CPMIC_BYPASS */ 2105 #define ARIZONA_CPMIC_BYPASS_WIDTH 1 /* CPMIC_BYPASS */ 2106 #define ARIZONA_CPMIC_ENA 0x0001 /* CPMIC_ENA */ 2107 #define ARIZONA_CPMIC_ENA_MASK 0x0001 /* CPMIC_ENA */ 2108 #define ARIZONA_CPMIC_ENA_SHIFT 0 /* CPMIC_ENA */ 2109 #define ARIZONA_CPMIC_ENA_WIDTH 1 /* CPMIC_ENA */ 2110 2111 /* 2112 * R528 (0x210) - LDO1 Control 1 2113 */ 2114 #define ARIZONA_LDO1_VSEL_MASK 0x07E0 /* LDO1_VSEL - [10:5] */ 2115 #define ARIZONA_LDO1_VSEL_SHIFT 5 /* LDO1_VSEL - [10:5] */ 2116 #define ARIZONA_LDO1_VSEL_WIDTH 6 /* LDO1_VSEL - [10:5] */ 2117 #define ARIZONA_LDO1_FAST 0x0010 /* LDO1_FAST */ 2118 #define ARIZONA_LDO1_FAST_MASK 0x0010 /* LDO1_FAST */ 2119 #define ARIZONA_LDO1_FAST_SHIFT 4 /* LDO1_FAST */ 2120 #define ARIZONA_LDO1_FAST_WIDTH 1 /* LDO1_FAST */ 2121 #define ARIZONA_LDO1_DISCH 0x0004 /* LDO1_DISCH */ 2122 #define ARIZONA_LDO1_DISCH_MASK 0x0004 /* LDO1_DISCH */ 2123 #define ARIZONA_LDO1_DISCH_SHIFT 2 /* LDO1_DISCH */ 2124 #define ARIZONA_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */ 2125 #define ARIZONA_LDO1_BYPASS 0x0002 /* LDO1_BYPASS */ 2126 #define ARIZONA_LDO1_BYPASS_MASK 0x0002 /* LDO1_BYPASS */ 2127 #define ARIZONA_LDO1_BYPASS_SHIFT 1 /* LDO1_BYPASS */ 2128 #define ARIZONA_LDO1_BYPASS_WIDTH 1 /* LDO1_BYPASS */ 2129 #define ARIZONA_LDO1_ENA 0x0001 /* LDO1_ENA */ 2130 #define ARIZONA_LDO1_ENA_MASK 0x0001 /* LDO1_ENA */ 2131 #define ARIZONA_LDO1_ENA_SHIFT 0 /* LDO1_ENA */ 2132 #define ARIZONA_LDO1_ENA_WIDTH 1 /* LDO1_ENA */ 2133 2134 /* 2135 * R530 (0x212) - LDO1 Control 2 2136 */ 2137 #define ARIZONA_LDO1_HI_PWR 0x0001 /* LDO1_HI_PWR */ 2138 #define ARIZONA_LDO1_HI_PWR_SHIFT 0 /* LDO1_HI_PWR */ 2139 #define ARIZONA_LDO1_HI_PWR_WIDTH 1 /* LDO1_HI_PWR */ 2140 2141 /* 2142 * R531 (0x213) - LDO2 Control 1 2143 */ 2144 #define ARIZONA_LDO2_VSEL_MASK 0x07E0 /* LDO2_VSEL - [10:5] */ 2145 #define ARIZONA_LDO2_VSEL_SHIFT 5 /* LDO2_VSEL - [10:5] */ 2146 #define ARIZONA_LDO2_VSEL_WIDTH 6 /* LDO2_VSEL - [10:5] */ 2147 #define ARIZONA_LDO2_FAST 0x0010 /* LDO2_FAST */ 2148 #define ARIZONA_LDO2_FAST_MASK 0x0010 /* LDO2_FAST */ 2149 #define ARIZONA_LDO2_FAST_SHIFT 4 /* LDO2_FAST */ 2150 #define ARIZONA_LDO2_FAST_WIDTH 1 /* LDO2_FAST */ 2151 #define ARIZONA_LDO2_DISCH 0x0004 /* LDO2_DISCH */ 2152 #define ARIZONA_LDO2_DISCH_MASK 0x0004 /* LDO2_DISCH */ 2153 #define ARIZONA_LDO2_DISCH_SHIFT 2 /* LDO2_DISCH */ 2154 #define ARIZONA_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */ 2155 #define ARIZONA_LDO2_BYPASS 0x0002 /* LDO2_BYPASS */ 2156 #define ARIZONA_LDO2_BYPASS_MASK 0x0002 /* LDO2_BYPASS */ 2157 #define ARIZONA_LDO2_BYPASS_SHIFT 1 /* LDO2_BYPASS */ 2158 #define ARIZONA_LDO2_BYPASS_WIDTH 1 /* LDO2_BYPASS */ 2159 #define ARIZONA_LDO2_ENA 0x0001 /* LDO2_ENA */ 2160 #define ARIZONA_LDO2_ENA_MASK 0x0001 /* LDO2_ENA */ 2161 #define ARIZONA_LDO2_ENA_SHIFT 0 /* LDO2_ENA */ 2162 #define ARIZONA_LDO2_ENA_WIDTH 1 /* LDO2_ENA */ 2163 2164 /* 2165 * R536 (0x218) - Mic Bias Ctrl 1 2166 */ 2167 #define ARIZONA_MICB1_EXT_CAP 0x8000 /* MICB1_EXT_CAP */ 2168 #define ARIZONA_MICB1_EXT_CAP_MASK 0x8000 /* MICB1_EXT_CAP */ 2169 #define ARIZONA_MICB1_EXT_CAP_SHIFT 15 /* MICB1_EXT_CAP */ 2170 #define ARIZONA_MICB1_EXT_CAP_WIDTH 1 /* MICB1_EXT_CAP */ 2171 #define ARIZONA_MICB1_LVL_MASK 0x01E0 /* MICB1_LVL - [8:5] */ 2172 #define ARIZONA_MICB1_LVL_SHIFT 5 /* MICB1_LVL - [8:5] */ 2173 #define ARIZONA_MICB1_LVL_WIDTH 4 /* MICB1_LVL - [8:5] */ 2174 #define ARIZONA_MICB1_FAST 0x0010 /* MICB1_FAST */ 2175 #define ARIZONA_MICB1_FAST_MASK 0x0010 /* MICB1_FAST */ 2176 #define ARIZONA_MICB1_FAST_SHIFT 4 /* MICB1_FAST */ 2177 #define ARIZONA_MICB1_FAST_WIDTH 1 /* MICB1_FAST */ 2178 #define ARIZONA_MICB1_RATE 0x0008 /* MICB1_RATE */ 2179 #define ARIZONA_MICB1_RATE_MASK 0x0008 /* MICB1_RATE */ 2180 #define ARIZONA_MICB1_RATE_SHIFT 3 /* MICB1_RATE */ 2181 #define ARIZONA_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ 2182 #define ARIZONA_MICB1_DISCH 0x0004 /* MICB1_DISCH */ 2183 #define ARIZONA_MICB1_DISCH_MASK 0x0004 /* MICB1_DISCH */ 2184 #define ARIZONA_MICB1_DISCH_SHIFT 2 /* MICB1_DISCH */ 2185 #define ARIZONA_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 2186 #define ARIZONA_MICB1_BYPASS 0x0002 /* MICB1_BYPASS */ 2187 #define ARIZONA_MICB1_BYPASS_MASK 0x0002 /* MICB1_BYPASS */ 2188 #define ARIZONA_MICB1_BYPASS_SHIFT 1 /* MICB1_BYPASS */ 2189 #define ARIZONA_MICB1_BYPASS_WIDTH 1 /* MICB1_BYPASS */ 2190 #define ARIZONA_MICB1_ENA 0x0001 /* MICB1_ENA */ 2191 #define ARIZONA_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */ 2192 #define ARIZONA_MICB1_ENA_SHIFT 0 /* MICB1_ENA */ 2193 #define ARIZONA_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 2194 2195 /* 2196 * R537 (0x219) - Mic Bias Ctrl 2 2197 */ 2198 #define ARIZONA_MICB2_EXT_CAP 0x8000 /* MICB2_EXT_CAP */ 2199 #define ARIZONA_MICB2_EXT_CAP_MASK 0x8000 /* MICB2_EXT_CAP */ 2200 #define ARIZONA_MICB2_EXT_CAP_SHIFT 15 /* MICB2_EXT_CAP */ 2201 #define ARIZONA_MICB2_EXT_CAP_WIDTH 1 /* MICB2_EXT_CAP */ 2202 #define ARIZONA_MICB2_LVL_MASK 0x01E0 /* MICB2_LVL - [8:5] */ 2203 #define ARIZONA_MICB2_LVL_SHIFT 5 /* MICB2_LVL - [8:5] */ 2204 #define ARIZONA_MICB2_LVL_WIDTH 4 /* MICB2_LVL - [8:5] */ 2205 #define ARIZONA_MICB2_FAST 0x0010 /* MICB2_FAST */ 2206 #define ARIZONA_MICB2_FAST_MASK 0x0010 /* MICB2_FAST */ 2207 #define ARIZONA_MICB2_FAST_SHIFT 4 /* MICB2_FAST */ 2208 #define ARIZONA_MICB2_FAST_WIDTH 1 /* MICB2_FAST */ 2209 #define ARIZONA_MICB2_RATE 0x0008 /* MICB2_RATE */ 2210 #define ARIZONA_MICB2_RATE_MASK 0x0008 /* MICB2_RATE */ 2211 #define ARIZONA_MICB2_RATE_SHIFT 3 /* MICB2_RATE */ 2212 #define ARIZONA_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ 2213 #define ARIZONA_MICB2_DISCH 0x0004 /* MICB2_DISCH */ 2214 #define ARIZONA_MICB2_DISCH_MASK 0x0004 /* MICB2_DISCH */ 2215 #define ARIZONA_MICB2_DISCH_SHIFT 2 /* MICB2_DISCH */ 2216 #define ARIZONA_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 2217 #define ARIZONA_MICB2_BYPASS 0x0002 /* MICB2_BYPASS */ 2218 #define ARIZONA_MICB2_BYPASS_MASK 0x0002 /* MICB2_BYPASS */ 2219 #define ARIZONA_MICB2_BYPASS_SHIFT 1 /* MICB2_BYPASS */ 2220 #define ARIZONA_MICB2_BYPASS_WIDTH 1 /* MICB2_BYPASS */ 2221 #define ARIZONA_MICB2_ENA 0x0001 /* MICB2_ENA */ 2222 #define ARIZONA_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */ 2223 #define ARIZONA_MICB2_ENA_SHIFT 0 /* MICB2_ENA */ 2224 #define ARIZONA_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 2225 2226 /* 2227 * R538 (0x21A) - Mic Bias Ctrl 3 2228 */ 2229 #define ARIZONA_MICB3_EXT_CAP 0x8000 /* MICB3_EXT_CAP */ 2230 #define ARIZONA_MICB3_EXT_CAP_MASK 0x8000 /* MICB3_EXT_CAP */ 2231 #define ARIZONA_MICB3_EXT_CAP_SHIFT 15 /* MICB3_EXT_CAP */ 2232 #define ARIZONA_MICB3_EXT_CAP_WIDTH 1 /* MICB3_EXT_CAP */ 2233 #define ARIZONA_MICB3_LVL_MASK 0x01E0 /* MICB3_LVL - [8:5] */ 2234 #define ARIZONA_MICB3_LVL_SHIFT 5 /* MICB3_LVL - [8:5] */ 2235 #define ARIZONA_MICB3_LVL_WIDTH 4 /* MICB3_LVL - [8:5] */ 2236 #define ARIZONA_MICB3_FAST 0x0010 /* MICB3_FAST */ 2237 #define ARIZONA_MICB3_FAST_MASK 0x0010 /* MICB3_FAST */ 2238 #define ARIZONA_MICB3_FAST_SHIFT 4 /* MICB3_FAST */ 2239 #define ARIZONA_MICB3_FAST_WIDTH 1 /* MICB3_FAST */ 2240 #define ARIZONA_MICB3_RATE 0x0008 /* MICB3_RATE */ 2241 #define ARIZONA_MICB3_RATE_MASK 0x0008 /* MICB3_RATE */ 2242 #define ARIZONA_MICB3_RATE_SHIFT 3 /* MICB3_RATE */ 2243 #define ARIZONA_MICB3_RATE_WIDTH 1 /* MICB3_RATE */ 2244 #define ARIZONA_MICB3_DISCH 0x0004 /* MICB3_DISCH */ 2245 #define ARIZONA_MICB3_DISCH_MASK 0x0004 /* MICB3_DISCH */ 2246 #define ARIZONA_MICB3_DISCH_SHIFT 2 /* MICB3_DISCH */ 2247 #define ARIZONA_MICB3_DISCH_WIDTH 1 /* MICB3_DISCH */ 2248 #define ARIZONA_MICB3_BYPASS 0x0002 /* MICB3_BYPASS */ 2249 #define ARIZONA_MICB3_BYPASS_MASK 0x0002 /* MICB3_BYPASS */ 2250 #define ARIZONA_MICB3_BYPASS_SHIFT 1 /* MICB3_BYPASS */ 2251 #define ARIZONA_MICB3_BYPASS_WIDTH 1 /* MICB3_BYPASS */ 2252 #define ARIZONA_MICB3_ENA 0x0001 /* MICB3_ENA */ 2253 #define ARIZONA_MICB3_ENA_MASK 0x0001 /* MICB3_ENA */ 2254 #define ARIZONA_MICB3_ENA_SHIFT 0 /* MICB3_ENA */ 2255 #define ARIZONA_MICB3_ENA_WIDTH 1 /* MICB3_ENA */ 2256 2257 /* 2258 * R549 (0x225) - HP Ctrl 1L 2259 */ 2260 #define ARIZONA_RMV_SHRT_HP1L 0x4000 /* RMV_SHRT_HP1L */ 2261 #define ARIZONA_RMV_SHRT_HP1L_MASK 0x4000 /* RMV_SHRT_HP1L */ 2262 #define ARIZONA_RMV_SHRT_HP1L_SHIFT 14 /* RMV_SHRT_HP1L */ 2263 #define ARIZONA_RMV_SHRT_HP1L_WIDTH 1 /* RMV_SHRT_HP1L */ 2264 #define ARIZONA_HP1L_FLWR 0x0004 /* HP1L_FLWR */ 2265 #define ARIZONA_HP1L_FLWR_MASK 0x0004 /* HP1L_FLWR */ 2266 #define ARIZONA_HP1L_FLWR_SHIFT 2 /* HP1L_FLWR */ 2267 #define ARIZONA_HP1L_FLWR_WIDTH 1 /* HP1L_FLWR */ 2268 #define ARIZONA_HP1L_SHRTI 0x0002 /* HP1L_SHRTI */ 2269 #define ARIZONA_HP1L_SHRTI_MASK 0x0002 /* HP1L_SHRTI */ 2270 #define ARIZONA_HP1L_SHRTI_SHIFT 1 /* HP1L_SHRTI */ 2271 #define ARIZONA_HP1L_SHRTI_WIDTH 1 /* HP1L_SHRTI */ 2272 #define ARIZONA_HP1L_SHRTO 0x0001 /* HP1L_SHRTO */ 2273 #define ARIZONA_HP1L_SHRTO_MASK 0x0001 /* HP1L_SHRTO */ 2274 #define ARIZONA_HP1L_SHRTO_SHIFT 0 /* HP1L_SHRTO */ 2275 #define ARIZONA_HP1L_SHRTO_WIDTH 1 /* HP1L_SHRTO */ 2276 2277 /* 2278 * R550 (0x226) - HP Ctrl 1R 2279 */ 2280 #define ARIZONA_RMV_SHRT_HP1R 0x4000 /* RMV_SHRT_HP1R */ 2281 #define ARIZONA_RMV_SHRT_HP1R_MASK 0x4000 /* RMV_SHRT_HP1R */ 2282 #define ARIZONA_RMV_SHRT_HP1R_SHIFT 14 /* RMV_SHRT_HP1R */ 2283 #define ARIZONA_RMV_SHRT_HP1R_WIDTH 1 /* RMV_SHRT_HP1R */ 2284 #define ARIZONA_HP1R_FLWR 0x0004 /* HP1R_FLWR */ 2285 #define ARIZONA_HP1R_FLWR_MASK 0x0004 /* HP1R_FLWR */ 2286 #define ARIZONA_HP1R_FLWR_SHIFT 2 /* HP1R_FLWR */ 2287 #define ARIZONA_HP1R_FLWR_WIDTH 1 /* HP1R_FLWR */ 2288 #define ARIZONA_HP1R_SHRTI 0x0002 /* HP1R_SHRTI */ 2289 #define ARIZONA_HP1R_SHRTI_MASK 0x0002 /* HP1R_SHRTI */ 2290 #define ARIZONA_HP1R_SHRTI_SHIFT 1 /* HP1R_SHRTI */ 2291 #define ARIZONA_HP1R_SHRTI_WIDTH 1 /* HP1R_SHRTI */ 2292 #define ARIZONA_HP1R_SHRTO 0x0001 /* HP1R_SHRTO */ 2293 #define ARIZONA_HP1R_SHRTO_MASK 0x0001 /* HP1R_SHRTO */ 2294 #define ARIZONA_HP1R_SHRTO_SHIFT 0 /* HP1R_SHRTO */ 2295 #define ARIZONA_HP1R_SHRTO_WIDTH 1 /* HP1R_SHRTO */ 2296 2297 /* 2298 * R659 (0x293) - Accessory Detect Mode 1 2299 */ 2300 #define ARIZONA_ACCDET_SRC 0x2000 /* ACCDET_SRC */ 2301 #define ARIZONA_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */ 2302 #define ARIZONA_ACCDET_SRC_SHIFT 13 /* ACCDET_SRC */ 2303 #define ARIZONA_ACCDET_SRC_WIDTH 1 /* ACCDET_SRC */ 2304 #define ARIZONA_ACCDET_MODE_MASK 0x0003 /* ACCDET_MODE - [1:0] */ 2305 #define ARIZONA_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [1:0] */ 2306 #define ARIZONA_ACCDET_MODE_WIDTH 2 /* ACCDET_MODE - [1:0] */ 2307 2308 /* 2309 * R667 (0x29B) - Headphone Detect 1 2310 */ 2311 #define ARIZONA_HP_IMPEDANCE_RANGE_MASK 0x0600 /* HP_IMPEDANCE_RANGE - [10:9] */ 2312 #define ARIZONA_HP_IMPEDANCE_RANGE_SHIFT 9 /* HP_IMPEDANCE_RANGE - [10:9] */ 2313 #define ARIZONA_HP_IMPEDANCE_RANGE_WIDTH 2 /* HP_IMPEDANCE_RANGE - [10:9] */ 2314 #define ARIZONA_HP_STEP_SIZE 0x0100 /* HP_STEP_SIZE */ 2315 #define ARIZONA_HP_STEP_SIZE_MASK 0x0100 /* HP_STEP_SIZE */ 2316 #define ARIZONA_HP_STEP_SIZE_SHIFT 8 /* HP_STEP_SIZE */ 2317 #define ARIZONA_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */ 2318 #define ARIZONA_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */ 2319 #define ARIZONA_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */ 2320 #define ARIZONA_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */ 2321 #define ARIZONA_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */ 2322 #define ARIZONA_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */ 2323 #define ARIZONA_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */ 2324 #define ARIZONA_HP_IDAC_STEER 0x0004 /* HP_IDAC_STEER */ 2325 #define ARIZONA_HP_IDAC_STEER_MASK 0x0004 /* HP_IDAC_STEER */ 2326 #define ARIZONA_HP_IDAC_STEER_SHIFT 2 /* HP_IDAC_STEER */ 2327 #define ARIZONA_HP_IDAC_STEER_WIDTH 1 /* HP_IDAC_STEER */ 2328 #define ARIZONA_HP_RATE 0x0002 /* HP_RATE */ 2329 #define ARIZONA_HP_RATE_MASK 0x0002 /* HP_RATE */ 2330 #define ARIZONA_HP_RATE_SHIFT 1 /* HP_RATE */ 2331 #define ARIZONA_HP_RATE_WIDTH 1 /* HP_RATE */ 2332 #define ARIZONA_HP_POLL 0x0001 /* HP_POLL */ 2333 #define ARIZONA_HP_POLL_MASK 0x0001 /* HP_POLL */ 2334 #define ARIZONA_HP_POLL_SHIFT 0 /* HP_POLL */ 2335 #define ARIZONA_HP_POLL_WIDTH 1 /* HP_POLL */ 2336 2337 /* 2338 * R668 (0x29C) - Headphone Detect 2 2339 */ 2340 #define ARIZONA_HP_DONE 0x0080 /* HP_DONE */ 2341 #define ARIZONA_HP_DONE_MASK 0x0080 /* HP_DONE */ 2342 #define ARIZONA_HP_DONE_SHIFT 7 /* HP_DONE */ 2343 #define ARIZONA_HP_DONE_WIDTH 1 /* HP_DONE */ 2344 #define ARIZONA_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ 2345 #define ARIZONA_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ 2346 #define ARIZONA_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ 2347 2348 #define ARIZONA_HP_DONE_B 0x8000 /* HP_DONE */ 2349 #define ARIZONA_HP_DONE_B_MASK 0x8000 /* HP_DONE */ 2350 #define ARIZONA_HP_DONE_B_SHIFT 15 /* HP_DONE */ 2351 #define ARIZONA_HP_DONE_B_WIDTH 1 /* HP_DONE */ 2352 #define ARIZONA_HP_LVL_B_MASK 0x7FFF /* HP_LVL - [14:0] */ 2353 #define ARIZONA_HP_LVL_B_SHIFT 0 /* HP_LVL - [14:0] */ 2354 #define ARIZONA_HP_LVL_B_WIDTH 15 /* HP_LVL - [14:0] */ 2355 2356 /* 2357 * R674 (0x2A2) - MICD clamp control 2358 */ 2359 #define ARIZONA_MICD_CLAMP_MODE_MASK 0x000F /* MICD_CLAMP_MODE - [3:0] */ 2360 #define ARIZONA_MICD_CLAMP_MODE_SHIFT 0 /* MICD_CLAMP_MODE - [3:0] */ 2361 #define ARIZONA_MICD_CLAMP_MODE_WIDTH 4 /* MICD_CLAMP_MODE - [3:0] */ 2362 2363 /* 2364 * R675 (0x2A3) - Mic Detect 1 2365 */ 2366 #define ARIZONA_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */ 2367 #define ARIZONA_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */ 2368 #define ARIZONA_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */ 2369 #define ARIZONA_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */ 2370 #define ARIZONA_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */ 2371 #define ARIZONA_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */ 2372 #define ARIZONA_MICD_BIAS_SRC_MASK 0x0030 /* MICD_BIAS_SRC - [5:4] */ 2373 #define ARIZONA_MICD_BIAS_SRC_SHIFT 4 /* MICD_BIAS_SRC - [5:4] */ 2374 #define ARIZONA_MICD_BIAS_SRC_WIDTH 2 /* MICD_BIAS_SRC - [5:4] */ 2375 #define ARIZONA_MICD_DBTIME 0x0002 /* MICD_DBTIME */ 2376 #define ARIZONA_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */ 2377 #define ARIZONA_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */ 2378 #define ARIZONA_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */ 2379 #define ARIZONA_MICD_ENA 0x0001 /* MICD_ENA */ 2380 #define ARIZONA_MICD_ENA_MASK 0x0001 /* MICD_ENA */ 2381 #define ARIZONA_MICD_ENA_SHIFT 0 /* MICD_ENA */ 2382 #define ARIZONA_MICD_ENA_WIDTH 1 /* MICD_ENA */ 2383 2384 /* 2385 * R676 (0x2A4) - Mic Detect 2 2386 */ 2387 #define ARIZONA_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */ 2388 #define ARIZONA_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */ 2389 #define ARIZONA_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */ 2390 2391 /* 2392 * R677 (0x2A5) - Mic Detect 3 2393 */ 2394 #define ARIZONA_MICD_LVL_0 0x0004 /* MICD_LVL - [2] */ 2395 #define ARIZONA_MICD_LVL_1 0x0008 /* MICD_LVL - [3] */ 2396 #define ARIZONA_MICD_LVL_2 0x0010 /* MICD_LVL - [4] */ 2397 #define ARIZONA_MICD_LVL_3 0x0020 /* MICD_LVL - [5] */ 2398 #define ARIZONA_MICD_LVL_4 0x0040 /* MICD_LVL - [6] */ 2399 #define ARIZONA_MICD_LVL_5 0x0080 /* MICD_LVL - [7] */ 2400 #define ARIZONA_MICD_LVL_6 0x0100 /* MICD_LVL - [8] */ 2401 #define ARIZONA_MICD_LVL_7 0x0200 /* MICD_LVL - [9] */ 2402 #define ARIZONA_MICD_LVL_8 0x0400 /* MICD_LVL - [10] */ 2403 #define ARIZONA_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */ 2404 #define ARIZONA_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */ 2405 #define ARIZONA_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */ 2406 #define ARIZONA_MICD_VALID 0x0002 /* MICD_VALID */ 2407 #define ARIZONA_MICD_VALID_MASK 0x0002 /* MICD_VALID */ 2408 #define ARIZONA_MICD_VALID_SHIFT 1 /* MICD_VALID */ 2409 #define ARIZONA_MICD_VALID_WIDTH 1 /* MICD_VALID */ 2410 #define ARIZONA_MICD_STS 0x0001 /* MICD_STS */ 2411 #define ARIZONA_MICD_STS_MASK 0x0001 /* MICD_STS */ 2412 #define ARIZONA_MICD_STS_SHIFT 0 /* MICD_STS */ 2413 #define ARIZONA_MICD_STS_WIDTH 1 /* MICD_STS */ 2414 2415 /* 2416 * R707 (0x2C3) - Mic noise mix control 1 2417 */ 2418 #define ARIZONA_MICMUTE_RATE_MASK 0x7800 /* MICMUTE_RATE - [14:11] */ 2419 #define ARIZONA_MICMUTE_RATE_SHIFT 11 /* MICMUTE_RATE - [14:11] */ 2420 #define ARIZONA_MICMUTE_RATE_WIDTH 4 /* MICMUTE_RATE - [14:11] */ 2421 #define ARIZONA_MICMUTE_MIX_ENA 0x0040 /* MICMUTE_MIX_ENA */ 2422 #define ARIZONA_MICMUTE_MIX_ENA_MASK 0x0040 /* MICMUTE_MIX_ENA */ 2423 #define ARIZONA_MICMUTE_MIX_ENA_SHIFT 6 /* MICMUTE_MIX_ENA */ 2424 #define ARIZONA_MICMUTE_MIX_ENA_WIDTH 1 /* MICMUTE_MIX_ENA */ 2425 2426 /* 2427 * R715 (0x2CB) - Isolation control 2428 */ 2429 #define ARIZONA_ISOLATE_DCVDD1 0x0001 /* ISOLATE_DCVDD1 */ 2430 #define ARIZONA_ISOLATE_DCVDD1_MASK 0x0001 /* ISOLATE_DCVDD1 */ 2431 #define ARIZONA_ISOLATE_DCVDD1_SHIFT 0 /* ISOLATE_DCVDD1 */ 2432 #define ARIZONA_ISOLATE_DCVDD1_WIDTH 1 /* ISOLATE_DCVDD1 */ 2433 2434 /* 2435 * R723 (0x2D3) - Jack detect analogue 2436 */ 2437 #define ARIZONA_JD2_ENA 0x0002 /* JD2_ENA */ 2438 #define ARIZONA_JD2_ENA_MASK 0x0002 /* JD2_ENA */ 2439 #define ARIZONA_JD2_ENA_SHIFT 1 /* JD2_ENA */ 2440 #define ARIZONA_JD2_ENA_WIDTH 1 /* JD2_ENA */ 2441 #define ARIZONA_JD1_ENA 0x0001 /* JD1_ENA */ 2442 #define ARIZONA_JD1_ENA_MASK 0x0001 /* JD1_ENA */ 2443 #define ARIZONA_JD1_ENA_SHIFT 0 /* JD1_ENA */ 2444 #define ARIZONA_JD1_ENA_WIDTH 1 /* JD1_ENA */ 2445 2446 /* 2447 * R768 (0x300) - Input Enables 2448 */ 2449 #define ARIZONA_IN4L_ENA 0x0080 /* IN4L_ENA */ 2450 #define ARIZONA_IN4L_ENA_MASK 0x0080 /* IN4L_ENA */ 2451 #define ARIZONA_IN4L_ENA_SHIFT 7 /* IN4L_ENA */ 2452 #define ARIZONA_IN4L_ENA_WIDTH 1 /* IN4L_ENA */ 2453 #define ARIZONA_IN4R_ENA 0x0040 /* IN4R_ENA */ 2454 #define ARIZONA_IN4R_ENA_MASK 0x0040 /* IN4R_ENA */ 2455 #define ARIZONA_IN4R_ENA_SHIFT 6 /* IN4R_ENA */ 2456 #define ARIZONA_IN4R_ENA_WIDTH 1 /* IN4R_ENA */ 2457 #define ARIZONA_IN3L_ENA 0x0020 /* IN3L_ENA */ 2458 #define ARIZONA_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */ 2459 #define ARIZONA_IN3L_ENA_SHIFT 5 /* IN3L_ENA */ 2460 #define ARIZONA_IN3L_ENA_WIDTH 1 /* IN3L_ENA */ 2461 #define ARIZONA_IN3R_ENA 0x0010 /* IN3R_ENA */ 2462 #define ARIZONA_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */ 2463 #define ARIZONA_IN3R_ENA_SHIFT 4 /* IN3R_ENA */ 2464 #define ARIZONA_IN3R_ENA_WIDTH 1 /* IN3R_ENA */ 2465 #define ARIZONA_IN2L_ENA 0x0008 /* IN2L_ENA */ 2466 #define ARIZONA_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */ 2467 #define ARIZONA_IN2L_ENA_SHIFT 3 /* IN2L_ENA */ 2468 #define ARIZONA_IN2L_ENA_WIDTH 1 /* IN2L_ENA */ 2469 #define ARIZONA_IN2R_ENA 0x0004 /* IN2R_ENA */ 2470 #define ARIZONA_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */ 2471 #define ARIZONA_IN2R_ENA_SHIFT 2 /* IN2R_ENA */ 2472 #define ARIZONA_IN2R_ENA_WIDTH 1 /* IN2R_ENA */ 2473 #define ARIZONA_IN1L_ENA 0x0002 /* IN1L_ENA */ 2474 #define ARIZONA_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */ 2475 #define ARIZONA_IN1L_ENA_SHIFT 1 /* IN1L_ENA */ 2476 #define ARIZONA_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ 2477 #define ARIZONA_IN1R_ENA 0x0001 /* IN1R_ENA */ 2478 #define ARIZONA_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */ 2479 #define ARIZONA_IN1R_ENA_SHIFT 0 /* IN1R_ENA */ 2480 #define ARIZONA_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ 2481 2482 /* 2483 * R776 (0x308) - Input Rate 2484 */ 2485 #define ARIZONA_IN_RATE_MASK 0x7800 /* IN_RATE - [14:11] */ 2486 #define ARIZONA_IN_RATE_SHIFT 11 /* IN_RATE - [14:11] */ 2487 #define ARIZONA_IN_RATE_WIDTH 4 /* IN_RATE - [14:11] */ 2488 2489 /* 2490 * R777 (0x309) - Input Volume Ramp 2491 */ 2492 #define ARIZONA_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */ 2493 #define ARIZONA_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */ 2494 #define ARIZONA_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */ 2495 #define ARIZONA_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */ 2496 #define ARIZONA_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */ 2497 #define ARIZONA_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */ 2498 2499 /* 2500 * R780 (0x30C) - HPF Control 2501 */ 2502 #define ARIZONA_IN_HPF_CUT_MASK 0x0007 /* IN_HPF_CUT [2:0] */ 2503 #define ARIZONA_IN_HPF_CUT_SHIFT 0 /* IN_HPF_CUT [2:0] */ 2504 #define ARIZONA_IN_HPF_CUT_WIDTH 3 /* IN_HPF_CUT [2:0] */ 2505 2506 /* 2507 * R784 (0x310) - IN1L Control 2508 */ 2509 #define ARIZONA_IN1L_HPF_MASK 0x8000 /* IN1L_HPF - [15] */ 2510 #define ARIZONA_IN1L_HPF_SHIFT 15 /* IN1L_HPF - [15] */ 2511 #define ARIZONA_IN1L_HPF_WIDTH 1 /* IN1L_HPF - [15] */ 2512 #define ARIZONA_IN1_OSR_MASK 0x6000 /* IN1_OSR - [14:13] */ 2513 #define ARIZONA_IN1_OSR_SHIFT 13 /* IN1_OSR - [14:13] */ 2514 #define ARIZONA_IN1_OSR_WIDTH 2 /* IN1_OSR - [14:13] */ 2515 #define ARIZONA_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */ 2516 #define ARIZONA_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */ 2517 #define ARIZONA_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */ 2518 #define ARIZONA_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */ 2519 #define ARIZONA_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */ 2520 #define ARIZONA_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */ 2521 #define ARIZONA_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */ 2522 #define ARIZONA_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */ 2523 #define ARIZONA_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */ 2524 2525 /* 2526 * R785 (0x311) - ADC Digital Volume 1L 2527 */ 2528 #define ARIZONA_IN_VU 0x0200 /* IN_VU */ 2529 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ 2530 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ 2531 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */ 2532 #define ARIZONA_IN1L_MUTE 0x0100 /* IN1L_MUTE */ 2533 #define ARIZONA_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */ 2534 #define ARIZONA_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */ 2535 #define ARIZONA_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */ 2536 #define ARIZONA_IN1L_DIG_VOL_MASK 0x00FF /* IN1L_DIG_VOL - [7:0] */ 2537 #define ARIZONA_IN1L_DIG_VOL_SHIFT 0 /* IN1L_DIG_VOL - [7:0] */ 2538 #define ARIZONA_IN1L_DIG_VOL_WIDTH 8 /* IN1L_DIG_VOL - [7:0] */ 2539 2540 /* 2541 * R786 (0x312) - DMIC1L Control 2542 */ 2543 #define ARIZONA_IN1_DMICL_DLY_MASK 0x003F /* IN1_DMICL_DLY - [5:0] */ 2544 #define ARIZONA_IN1_DMICL_DLY_SHIFT 0 /* IN1_DMICL_DLY - [5:0] */ 2545 #define ARIZONA_IN1_DMICL_DLY_WIDTH 6 /* IN1_DMICL_DLY - [5:0] */ 2546 2547 /* 2548 * R788 (0x314) - IN1R Control 2549 */ 2550 #define ARIZONA_IN1R_HPF_MASK 0x8000 /* IN1R_HPF - [15] */ 2551 #define ARIZONA_IN1R_HPF_SHIFT 15 /* IN1R_HPF - [15] */ 2552 #define ARIZONA_IN1R_HPF_WIDTH 1 /* IN1R_HPF - [15] */ 2553 #define ARIZONA_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */ 2554 #define ARIZONA_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */ 2555 #define ARIZONA_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */ 2556 2557 /* 2558 * R789 (0x315) - ADC Digital Volume 1R 2559 */ 2560 #define ARIZONA_IN_VU 0x0200 /* IN_VU */ 2561 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ 2562 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ 2563 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */ 2564 #define ARIZONA_IN1R_MUTE 0x0100 /* IN1R_MUTE */ 2565 #define ARIZONA_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */ 2566 #define ARIZONA_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */ 2567 #define ARIZONA_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */ 2568 #define ARIZONA_IN1R_DIG_VOL_MASK 0x00FF /* IN1R_DIG_VOL - [7:0] */ 2569 #define ARIZONA_IN1R_DIG_VOL_SHIFT 0 /* IN1R_DIG_VOL - [7:0] */ 2570 #define ARIZONA_IN1R_DIG_VOL_WIDTH 8 /* IN1R_DIG_VOL - [7:0] */ 2571 2572 /* 2573 * R790 (0x316) - DMIC1R Control 2574 */ 2575 #define ARIZONA_IN1_DMICR_DLY_MASK 0x003F /* IN1_DMICR_DLY - [5:0] */ 2576 #define ARIZONA_IN1_DMICR_DLY_SHIFT 0 /* IN1_DMICR_DLY - [5:0] */ 2577 #define ARIZONA_IN1_DMICR_DLY_WIDTH 6 /* IN1_DMICR_DLY - [5:0] */ 2578 2579 /* 2580 * R792 (0x318) - IN2L Control 2581 */ 2582 #define ARIZONA_IN2L_HPF_MASK 0x8000 /* IN2L_HPF - [15] */ 2583 #define ARIZONA_IN2L_HPF_SHIFT 15 /* IN2L_HPF - [15] */ 2584 #define ARIZONA_IN2L_HPF_WIDTH 1 /* IN2L_HPF - [15] */ 2585 #define ARIZONA_IN2_OSR_MASK 0x6000 /* IN2_OSR - [14:13] */ 2586 #define ARIZONA_IN2_OSR_SHIFT 13 /* IN2_OSR - [14:13] */ 2587 #define ARIZONA_IN2_OSR_WIDTH 2 /* IN2_OSR - [14:13] */ 2588 #define ARIZONA_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */ 2589 #define ARIZONA_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */ 2590 #define ARIZONA_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */ 2591 #define ARIZONA_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */ 2592 #define ARIZONA_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */ 2593 #define ARIZONA_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */ 2594 #define ARIZONA_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */ 2595 #define ARIZONA_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */ 2596 #define ARIZONA_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */ 2597 2598 /* 2599 * R793 (0x319) - ADC Digital Volume 2L 2600 */ 2601 #define ARIZONA_IN_VU 0x0200 /* IN_VU */ 2602 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ 2603 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ 2604 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */ 2605 #define ARIZONA_IN2L_MUTE 0x0100 /* IN2L_MUTE */ 2606 #define ARIZONA_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */ 2607 #define ARIZONA_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */ 2608 #define ARIZONA_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */ 2609 #define ARIZONA_IN2L_DIG_VOL_MASK 0x00FF /* IN2L_DIG_VOL - [7:0] */ 2610 #define ARIZONA_IN2L_DIG_VOL_SHIFT 0 /* IN2L_DIG_VOL - [7:0] */ 2611 #define ARIZONA_IN2L_DIG_VOL_WIDTH 8 /* IN2L_DIG_VOL - [7:0] */ 2612 2613 /* 2614 * R794 (0x31A) - DMIC2L Control 2615 */ 2616 #define ARIZONA_IN2_DMICL_DLY_MASK 0x003F /* IN2_DMICL_DLY - [5:0] */ 2617 #define ARIZONA_IN2_DMICL_DLY_SHIFT 0 /* IN2_DMICL_DLY - [5:0] */ 2618 #define ARIZONA_IN2_DMICL_DLY_WIDTH 6 /* IN2_DMICL_DLY - [5:0] */ 2619 2620 /* 2621 * R796 (0x31C) - IN2R Control 2622 */ 2623 #define ARIZONA_IN2R_HPF_MASK 0x8000 /* IN2R_HPF - [15] */ 2624 #define ARIZONA_IN2R_HPF_SHIFT 15 /* IN2R_HPF - [15] */ 2625 #define ARIZONA_IN2R_HPF_WIDTH 1 /* IN2R_HPF - [15] */ 2626 #define ARIZONA_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */ 2627 #define ARIZONA_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */ 2628 #define ARIZONA_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */ 2629 2630 /* 2631 * R797 (0x31D) - ADC Digital Volume 2R 2632 */ 2633 #define ARIZONA_IN_VU 0x0200 /* IN_VU */ 2634 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ 2635 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ 2636 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */ 2637 #define ARIZONA_IN2R_MUTE 0x0100 /* IN2R_MUTE */ 2638 #define ARIZONA_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */ 2639 #define ARIZONA_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */ 2640 #define ARIZONA_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */ 2641 #define ARIZONA_IN2R_DIG_VOL_MASK 0x00FF /* IN2R_DIG_VOL - [7:0] */ 2642 #define ARIZONA_IN2R_DIG_VOL_SHIFT 0 /* IN2R_DIG_VOL - [7:0] */ 2643 #define ARIZONA_IN2R_DIG_VOL_WIDTH 8 /* IN2R_DIG_VOL - [7:0] */ 2644 2645 /* 2646 * R798 (0x31E) - DMIC2R Control 2647 */ 2648 #define ARIZONA_IN2_DMICR_DLY_MASK 0x003F /* IN2_DMICR_DLY - [5:0] */ 2649 #define ARIZONA_IN2_DMICR_DLY_SHIFT 0 /* IN2_DMICR_DLY - [5:0] */ 2650 #define ARIZONA_IN2_DMICR_DLY_WIDTH 6 /* IN2_DMICR_DLY - [5:0] */ 2651 2652 /* 2653 * R800 (0x320) - IN3L Control 2654 */ 2655 #define ARIZONA_IN3L_HPF_MASK 0x8000 /* IN3L_HPF - [15] */ 2656 #define ARIZONA_IN3L_HPF_SHIFT 15 /* IN3L_HPF - [15] */ 2657 #define ARIZONA_IN3L_HPF_WIDTH 1 /* IN3L_HPF - [15] */ 2658 #define ARIZONA_IN3_OSR_MASK 0x6000 /* IN3_OSR - [14:13] */ 2659 #define ARIZONA_IN3_OSR_SHIFT 13 /* IN3_OSR - [14:13] */ 2660 #define ARIZONA_IN3_OSR_WIDTH 2 /* IN3_OSR - [14:13] */ 2661 #define ARIZONA_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */ 2662 #define ARIZONA_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */ 2663 #define ARIZONA_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */ 2664 #define ARIZONA_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */ 2665 #define ARIZONA_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */ 2666 #define ARIZONA_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */ 2667 #define ARIZONA_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */ 2668 #define ARIZONA_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */ 2669 #define ARIZONA_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */ 2670 2671 /* 2672 * R801 (0x321) - ADC Digital Volume 3L 2673 */ 2674 #define ARIZONA_IN_VU 0x0200 /* IN_VU */ 2675 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ 2676 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ 2677 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */ 2678 #define ARIZONA_IN3L_MUTE 0x0100 /* IN3L_MUTE */ 2679 #define ARIZONA_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */ 2680 #define ARIZONA_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */ 2681 #define ARIZONA_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */ 2682 #define ARIZONA_IN3L_DIG_VOL_MASK 0x00FF /* IN3L_DIG_VOL - [7:0] */ 2683 #define ARIZONA_IN3L_DIG_VOL_SHIFT 0 /* IN3L_DIG_VOL - [7:0] */ 2684 #define ARIZONA_IN3L_DIG_VOL_WIDTH 8 /* IN3L_DIG_VOL - [7:0] */ 2685 2686 /* 2687 * R802 (0x322) - DMIC3L Control 2688 */ 2689 #define ARIZONA_IN3_DMICL_DLY_MASK 0x003F /* IN3_DMICL_DLY - [5:0] */ 2690 #define ARIZONA_IN3_DMICL_DLY_SHIFT 0 /* IN3_DMICL_DLY - [5:0] */ 2691 #define ARIZONA_IN3_DMICL_DLY_WIDTH 6 /* IN3_DMICL_DLY - [5:0] */ 2692 2693 /* 2694 * R804 (0x324) - IN3R Control 2695 */ 2696 #define ARIZONA_IN3R_HPF_MASK 0x8000 /* IN3R_HPF - [15] */ 2697 #define ARIZONA_IN3R_HPF_SHIFT 15 /* IN3R_HPF - [15] */ 2698 #define ARIZONA_IN3R_HPF_WIDTH 1 /* IN3R_HPF - [15] */ 2699 #define ARIZONA_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */ 2700 #define ARIZONA_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */ 2701 #define ARIZONA_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */ 2702 2703 /* 2704 * R805 (0x325) - ADC Digital Volume 3R 2705 */ 2706 #define ARIZONA_IN_VU 0x0200 /* IN_VU */ 2707 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ 2708 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ 2709 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */ 2710 #define ARIZONA_IN3R_MUTE 0x0100 /* IN3R_MUTE */ 2711 #define ARIZONA_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */ 2712 #define ARIZONA_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */ 2713 #define ARIZONA_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */ 2714 #define ARIZONA_IN3R_DIG_VOL_MASK 0x00FF /* IN3R_DIG_VOL - [7:0] */ 2715 #define ARIZONA_IN3R_DIG_VOL_SHIFT 0 /* IN3R_DIG_VOL - [7:0] */ 2716 #define ARIZONA_IN3R_DIG_VOL_WIDTH 8 /* IN3R_DIG_VOL - [7:0] */ 2717 2718 /* 2719 * R806 (0x326) - DMIC3R Control 2720 */ 2721 #define ARIZONA_IN3_DMICR_DLY_MASK 0x003F /* IN3_DMICR_DLY - [5:0] */ 2722 #define ARIZONA_IN3_DMICR_DLY_SHIFT 0 /* IN3_DMICR_DLY - [5:0] */ 2723 #define ARIZONA_IN3_DMICR_DLY_WIDTH 6 /* IN3_DMICR_DLY - [5:0] */ 2724 2725 /* 2726 * R808 (0x328) - IN4 Control 2727 */ 2728 #define ARIZONA_IN4L_HPF_MASK 0x8000 /* IN4L_HPF - [15] */ 2729 #define ARIZONA_IN4L_HPF_SHIFT 15 /* IN4L_HPF - [15] */ 2730 #define ARIZONA_IN4L_HPF_WIDTH 1 /* IN4L_HPF - [15] */ 2731 #define ARIZONA_IN4_OSR_MASK 0x6000 /* IN4_OSR - [14:13] */ 2732 #define ARIZONA_IN4_OSR_SHIFT 13 /* IN4_OSR - [14:13] */ 2733 #define ARIZONA_IN4_OSR_WIDTH 2 /* IN4_OSR - [14:13] */ 2734 #define ARIZONA_IN4_DMIC_SUP_MASK 0x1800 /* IN4_DMIC_SUP - [12:11] */ 2735 #define ARIZONA_IN4_DMIC_SUP_SHIFT 11 /* IN4_DMIC_SUP - [12:11] */ 2736 #define ARIZONA_IN4_DMIC_SUP_WIDTH 2 /* IN4_DMIC_SUP - [12:11] */ 2737 2738 /* 2739 * R809 (0x329) - ADC Digital Volume 4L 2740 */ 2741 #define ARIZONA_IN_VU 0x0200 /* IN_VU */ 2742 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ 2743 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ 2744 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */ 2745 #define ARIZONA_IN4L_MUTE 0x0100 /* IN4L_MUTE */ 2746 #define ARIZONA_IN4L_MUTE_MASK 0x0100 /* IN4L_MUTE */ 2747 #define ARIZONA_IN4L_MUTE_SHIFT 8 /* IN4L_MUTE */ 2748 #define ARIZONA_IN4L_MUTE_WIDTH 1 /* IN4L_MUTE */ 2749 #define ARIZONA_IN4L_DIG_VOL_MASK 0x00FF /* IN4L_DIG_VOL - [7:0] */ 2750 #define ARIZONA_IN4L_DIG_VOL_SHIFT 0 /* IN4L_DIG_VOL - [7:0] */ 2751 #define ARIZONA_IN4L_DIG_VOL_WIDTH 8 /* IN4L_DIG_VOL - [7:0] */ 2752 2753 /* 2754 * R810 (0x32A) - DMIC4L Control 2755 */ 2756 #define ARIZONA_IN4L_DMIC_DLY_MASK 0x003F /* IN4L_DMIC_DLY - [5:0] */ 2757 #define ARIZONA_IN4L_DMIC_DLY_SHIFT 0 /* IN4L_DMIC_DLY - [5:0] */ 2758 #define ARIZONA_IN4L_DMIC_DLY_WIDTH 6 /* IN4L_DMIC_DLY - [5:0] */ 2759 2760 /* 2761 * R812 (0x32C) - IN4R Control 2762 */ 2763 #define ARIZONA_IN4R_HPF_MASK 0x8000 /* IN4R_HPF - [15] */ 2764 #define ARIZONA_IN4R_HPF_SHIFT 15 /* IN4R_HPF - [15] */ 2765 #define ARIZONA_IN4R_HPF_WIDTH 1 /* IN4R_HPF - [15] */ 2766 2767 /* 2768 * R813 (0x32D) - ADC Digital Volume 4R 2769 */ 2770 #define ARIZONA_IN_VU 0x0200 /* IN_VU */ 2771 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ 2772 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ 2773 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */ 2774 #define ARIZONA_IN4R_MUTE 0x0100 /* IN4R_MUTE */ 2775 #define ARIZONA_IN4R_MUTE_MASK 0x0100 /* IN4R_MUTE */ 2776 #define ARIZONA_IN4R_MUTE_SHIFT 8 /* IN4R_MUTE */ 2777 #define ARIZONA_IN4R_MUTE_WIDTH 1 /* IN4R_MUTE */ 2778 #define ARIZONA_IN4R_DIG_VOL_MASK 0x00FF /* IN4R_DIG_VOL - [7:0] */ 2779 #define ARIZONA_IN4R_DIG_VOL_SHIFT 0 /* IN4R_DIG_VOL - [7:0] */ 2780 #define ARIZONA_IN4R_DIG_VOL_WIDTH 8 /* IN4R_DIG_VOL - [7:0] */ 2781 2782 /* 2783 * R814 (0x32E) - DMIC4R Control 2784 */ 2785 #define ARIZONA_IN4R_DMIC_DLY_MASK 0x003F /* IN4R_DMIC_DLY - [5:0] */ 2786 #define ARIZONA_IN4R_DMIC_DLY_SHIFT 0 /* IN4R_DMIC_DLY - [5:0] */ 2787 #define ARIZONA_IN4R_DMIC_DLY_WIDTH 6 /* IN4R_DMIC_DLY - [5:0] */ 2788 2789 /* 2790 * R1024 (0x400) - Output Enables 1 2791 */ 2792 #define ARIZONA_OUT6L_ENA 0x0800 /* OUT6L_ENA */ 2793 #define ARIZONA_OUT6L_ENA_MASK 0x0800 /* OUT6L_ENA */ 2794 #define ARIZONA_OUT6L_ENA_SHIFT 11 /* OUT6L_ENA */ 2795 #define ARIZONA_OUT6L_ENA_WIDTH 1 /* OUT6L_ENA */ 2796 #define ARIZONA_OUT6R_ENA 0x0400 /* OUT6R_ENA */ 2797 #define ARIZONA_OUT6R_ENA_MASK 0x0400 /* OUT6R_ENA */ 2798 #define ARIZONA_OUT6R_ENA_SHIFT 10 /* OUT6R_ENA */ 2799 #define ARIZONA_OUT6R_ENA_WIDTH 1 /* OUT6R_ENA */ 2800 #define ARIZONA_OUT5L_ENA 0x0200 /* OUT5L_ENA */ 2801 #define ARIZONA_OUT5L_ENA_MASK 0x0200 /* OUT5L_ENA */ 2802 #define ARIZONA_OUT5L_ENA_SHIFT 9 /* OUT5L_ENA */ 2803 #define ARIZONA_OUT5L_ENA_WIDTH 1 /* OUT5L_ENA */ 2804 #define ARIZONA_OUT5R_ENA 0x0100 /* OUT5R_ENA */ 2805 #define ARIZONA_OUT5R_ENA_MASK 0x0100 /* OUT5R_ENA */ 2806 #define ARIZONA_OUT5R_ENA_SHIFT 8 /* OUT5R_ENA */ 2807 #define ARIZONA_OUT5R_ENA_WIDTH 1 /* OUT5R_ENA */ 2808 #define ARIZONA_OUT4L_ENA 0x0080 /* OUT4L_ENA */ 2809 #define ARIZONA_OUT4L_ENA_MASK 0x0080 /* OUT4L_ENA */ 2810 #define ARIZONA_OUT4L_ENA_SHIFT 7 /* OUT4L_ENA */ 2811 #define ARIZONA_OUT4L_ENA_WIDTH 1 /* OUT4L_ENA */ 2812 #define ARIZONA_OUT4R_ENA 0x0040 /* OUT4R_ENA */ 2813 #define ARIZONA_OUT4R_ENA_MASK 0x0040 /* OUT4R_ENA */ 2814 #define ARIZONA_OUT4R_ENA_SHIFT 6 /* OUT4R_ENA */ 2815 #define ARIZONA_OUT4R_ENA_WIDTH 1 /* OUT4R_ENA */ 2816 #define ARIZONA_OUT3L_ENA 0x0020 /* OUT3L_ENA */ 2817 #define ARIZONA_OUT3L_ENA_MASK 0x0020 /* OUT3L_ENA */ 2818 #define ARIZONA_OUT3L_ENA_SHIFT 5 /* OUT3L_ENA */ 2819 #define ARIZONA_OUT3L_ENA_WIDTH 1 /* OUT3L_ENA */ 2820 #define ARIZONA_OUT3R_ENA 0x0010 /* OUT3R_ENA */ 2821 #define ARIZONA_OUT3R_ENA_MASK 0x0010 /* OUT3R_ENA */ 2822 #define ARIZONA_OUT3R_ENA_SHIFT 4 /* OUT3R_ENA */ 2823 #define ARIZONA_OUT3R_ENA_WIDTH 1 /* OUT3R_ENA */ 2824 #define ARIZONA_OUT2L_ENA 0x0008 /* OUT2L_ENA */ 2825 #define ARIZONA_OUT2L_ENA_MASK 0x0008 /* OUT2L_ENA */ 2826 #define ARIZONA_OUT2L_ENA_SHIFT 3 /* OUT2L_ENA */ 2827 #define ARIZONA_OUT2L_ENA_WIDTH 1 /* OUT2L_ENA */ 2828 #define ARIZONA_OUT2R_ENA 0x0004 /* OUT2R_ENA */ 2829 #define ARIZONA_OUT2R_ENA_MASK 0x0004 /* OUT2R_ENA */ 2830 #define ARIZONA_OUT2R_ENA_SHIFT 2 /* OUT2R_ENA */ 2831 #define ARIZONA_OUT2R_ENA_WIDTH 1 /* OUT2R_ENA */ 2832 #define ARIZONA_OUT1L_ENA 0x0002 /* OUT1L_ENA */ 2833 #define ARIZONA_OUT1L_ENA_MASK 0x0002 /* OUT1L_ENA */ 2834 #define ARIZONA_OUT1L_ENA_SHIFT 1 /* OUT1L_ENA */ 2835 #define ARIZONA_OUT1L_ENA_WIDTH 1 /* OUT1L_ENA */ 2836 #define ARIZONA_OUT1R_ENA 0x0001 /* OUT1R_ENA */ 2837 #define ARIZONA_OUT1R_ENA_MASK 0x0001 /* OUT1R_ENA */ 2838 #define ARIZONA_OUT1R_ENA_SHIFT 0 /* OUT1R_ENA */ 2839 #define ARIZONA_OUT1R_ENA_WIDTH 1 /* OUT1R_ENA */ 2840 2841 /* 2842 * R1025 (0x401) - Output Status 1 2843 */ 2844 #define ARIZONA_OUT6L_ENA_STS 0x0800 /* OUT6L_ENA_STS */ 2845 #define ARIZONA_OUT6L_ENA_STS_MASK 0x0800 /* OUT6L_ENA_STS */ 2846 #define ARIZONA_OUT6L_ENA_STS_SHIFT 11 /* OUT6L_ENA_STS */ 2847 #define ARIZONA_OUT6L_ENA_STS_WIDTH 1 /* OUT6L_ENA_STS */ 2848 #define ARIZONA_OUT6R_ENA_STS 0x0400 /* OUT6R_ENA_STS */ 2849 #define ARIZONA_OUT6R_ENA_STS_MASK 0x0400 /* OUT6R_ENA_STS */ 2850 #define ARIZONA_OUT6R_ENA_STS_SHIFT 10 /* OUT6R_ENA_STS */ 2851 #define ARIZONA_OUT6R_ENA_STS_WIDTH 1 /* OUT6R_ENA_STS */ 2852 #define ARIZONA_OUT5L_ENA_STS 0x0200 /* OUT5L_ENA_STS */ 2853 #define ARIZONA_OUT5L_ENA_STS_MASK 0x0200 /* OUT5L_ENA_STS */ 2854 #define ARIZONA_OUT5L_ENA_STS_SHIFT 9 /* OUT5L_ENA_STS */ 2855 #define ARIZONA_OUT5L_ENA_STS_WIDTH 1 /* OUT5L_ENA_STS */ 2856 #define ARIZONA_OUT5R_ENA_STS 0x0100 /* OUT5R_ENA_STS */ 2857 #define ARIZONA_OUT5R_ENA_STS_MASK 0x0100 /* OUT5R_ENA_STS */ 2858 #define ARIZONA_OUT5R_ENA_STS_SHIFT 8 /* OUT5R_ENA_STS */ 2859 #define ARIZONA_OUT5R_ENA_STS_WIDTH 1 /* OUT5R_ENA_STS */ 2860 #define ARIZONA_OUT4L_ENA_STS 0x0080 /* OUT4L_ENA_STS */ 2861 #define ARIZONA_OUT4L_ENA_STS_MASK 0x0080 /* OUT4L_ENA_STS */ 2862 #define ARIZONA_OUT4L_ENA_STS_SHIFT 7 /* OUT4L_ENA_STS */ 2863 #define ARIZONA_OUT4L_ENA_STS_WIDTH 1 /* OUT4L_ENA_STS */ 2864 #define ARIZONA_OUT4R_ENA_STS 0x0040 /* OUT4R_ENA_STS */ 2865 #define ARIZONA_OUT4R_ENA_STS_MASK 0x0040 /* OUT4R_ENA_STS */ 2866 #define ARIZONA_OUT4R_ENA_STS_SHIFT 6 /* OUT4R_ENA_STS */ 2867 #define ARIZONA_OUT4R_ENA_STS_WIDTH 1 /* OUT4R_ENA_STS */ 2868 2869 /* 2870 * R1032 (0x408) - Output Rate 1 2871 */ 2872 #define ARIZONA_OUT_RATE_MASK 0x7800 /* OUT_RATE - [14:11] */ 2873 #define ARIZONA_OUT_RATE_SHIFT 11 /* OUT_RATE - [14:11] */ 2874 #define ARIZONA_OUT_RATE_WIDTH 4 /* OUT_RATE - [14:11] */ 2875 2876 /* 2877 * R1033 (0x409) - Output Volume Ramp 2878 */ 2879 #define ARIZONA_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */ 2880 #define ARIZONA_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */ 2881 #define ARIZONA_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */ 2882 #define ARIZONA_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */ 2883 #define ARIZONA_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */ 2884 #define ARIZONA_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */ 2885 2886 /* 2887 * R1040 (0x410) - Output Path Config 1L 2888 */ 2889 #define ARIZONA_OUT1_LP_MODE 0x8000 /* OUT1_LP_MODE */ 2890 #define ARIZONA_OUT1_LP_MODE_MASK 0x8000 /* OUT1_LP_MODE */ 2891 #define ARIZONA_OUT1_LP_MODE_SHIFT 15 /* OUT1_LP_MODE */ 2892 #define ARIZONA_OUT1_LP_MODE_WIDTH 1 /* OUT1_LP_MODE */ 2893 #define ARIZONA_OUT1_OSR 0x2000 /* OUT1_OSR */ 2894 #define ARIZONA_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */ 2895 #define ARIZONA_OUT1_OSR_SHIFT 13 /* OUT1_OSR */ 2896 #define ARIZONA_OUT1_OSR_WIDTH 1 /* OUT1_OSR */ 2897 #define ARIZONA_OUT1_MONO 0x1000 /* OUT1_MONO */ 2898 #define ARIZONA_OUT1_MONO_MASK 0x1000 /* OUT1_MONO */ 2899 #define ARIZONA_OUT1_MONO_SHIFT 12 /* OUT1_MONO */ 2900 #define ARIZONA_OUT1_MONO_WIDTH 1 /* OUT1_MONO */ 2901 #define ARIZONA_OUT1L_ANC_SRC_MASK 0x0C00 /* OUT1L_ANC_SRC - [11:10] */ 2902 #define ARIZONA_OUT1L_ANC_SRC_SHIFT 10 /* OUT1L_ANC_SRC - [11:10] */ 2903 #define ARIZONA_OUT1L_ANC_SRC_WIDTH 2 /* OUT1L_ANC_SRC - [11:10] */ 2904 #define ARIZONA_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */ 2905 #define ARIZONA_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */ 2906 #define ARIZONA_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */ 2907 2908 /* 2909 * R1041 (0x411) - DAC Digital Volume 1L 2910 */ 2911 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */ 2912 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */ 2913 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */ 2914 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */ 2915 #define ARIZONA_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */ 2916 #define ARIZONA_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */ 2917 #define ARIZONA_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */ 2918 #define ARIZONA_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */ 2919 #define ARIZONA_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */ 2920 #define ARIZONA_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */ 2921 #define ARIZONA_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */ 2922 2923 /* 2924 * R1042 (0x412) - DAC Volume Limit 1L 2925 */ 2926 #define ARIZONA_OUT1L_VOL_LIM_MASK 0x00FF /* OUT1L_VOL_LIM - [7:0] */ 2927 #define ARIZONA_OUT1L_VOL_LIM_SHIFT 0 /* OUT1L_VOL_LIM - [7:0] */ 2928 #define ARIZONA_OUT1L_VOL_LIM_WIDTH 8 /* OUT1L_VOL_LIM - [7:0] */ 2929 2930 /* 2931 * R1043 (0x413) - Noise Gate Select 1L 2932 */ 2933 #define ARIZONA_OUT1L_NGATE_SRC_MASK 0x0FFF /* OUT1L_NGATE_SRC - [11:0] */ 2934 #define ARIZONA_OUT1L_NGATE_SRC_SHIFT 0 /* OUT1L_NGATE_SRC - [11:0] */ 2935 #define ARIZONA_OUT1L_NGATE_SRC_WIDTH 12 /* OUT1L_NGATE_SRC - [11:0] */ 2936 2937 /* 2938 * R1044 (0x414) - Output Path Config 1R 2939 */ 2940 #define ARIZONA_OUT1R_ANC_SRC_MASK 0x0C00 /* OUT1R_ANC_SRC - [11:10] */ 2941 #define ARIZONA_OUT1R_ANC_SRC_SHIFT 10 /* OUT1R_ANC_SRC - [11:10] */ 2942 #define ARIZONA_OUT1R_ANC_SRC_WIDTH 2 /* OUT1R_ANC_SRC - [11:10] */ 2943 #define ARIZONA_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */ 2944 #define ARIZONA_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */ 2945 #define ARIZONA_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */ 2946 2947 /* 2948 * R1045 (0x415) - DAC Digital Volume 1R 2949 */ 2950 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */ 2951 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */ 2952 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */ 2953 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */ 2954 #define ARIZONA_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */ 2955 #define ARIZONA_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */ 2956 #define ARIZONA_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */ 2957 #define ARIZONA_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */ 2958 #define ARIZONA_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */ 2959 #define ARIZONA_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */ 2960 #define ARIZONA_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */ 2961 2962 /* 2963 * R1046 (0x416) - DAC Volume Limit 1R 2964 */ 2965 #define ARIZONA_OUT1R_VOL_LIM_MASK 0x00FF /* OUT1R_VOL_LIM - [7:0] */ 2966 #define ARIZONA_OUT1R_VOL_LIM_SHIFT 0 /* OUT1R_VOL_LIM - [7:0] */ 2967 #define ARIZONA_OUT1R_VOL_LIM_WIDTH 8 /* OUT1R_VOL_LIM - [7:0] */ 2968 2969 /* 2970 * R1047 (0x417) - Noise Gate Select 1R 2971 */ 2972 #define ARIZONA_OUT1R_NGATE_SRC_MASK 0x0FFF /* OUT1R_NGATE_SRC - [11:0] */ 2973 #define ARIZONA_OUT1R_NGATE_SRC_SHIFT 0 /* OUT1R_NGATE_SRC - [11:0] */ 2974 #define ARIZONA_OUT1R_NGATE_SRC_WIDTH 12 /* OUT1R_NGATE_SRC - [11:0] */ 2975 2976 /* 2977 * R1048 (0x418) - Output Path Config 2L 2978 */ 2979 #define ARIZONA_OUT2_LP_MODE 0x8000 /* OUT2_LP_MODE */ 2980 #define ARIZONA_OUT2_LP_MODE_MASK 0x8000 /* OUT2_LP_MODE */ 2981 #define ARIZONA_OUT2_LP_MODE_SHIFT 15 /* OUT2_LP_MODE */ 2982 #define ARIZONA_OUT2_LP_MODE_WIDTH 1 /* OUT2_LP_MODE */ 2983 #define ARIZONA_OUT2_OSR 0x2000 /* OUT2_OSR */ 2984 #define ARIZONA_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */ 2985 #define ARIZONA_OUT2_OSR_SHIFT 13 /* OUT2_OSR */ 2986 #define ARIZONA_OUT2_OSR_WIDTH 1 /* OUT2_OSR */ 2987 #define ARIZONA_OUT2_MONO 0x1000 /* OUT2_MONO */ 2988 #define ARIZONA_OUT2_MONO_MASK 0x1000 /* OUT2_MONO */ 2989 #define ARIZONA_OUT2_MONO_SHIFT 12 /* OUT2_MONO */ 2990 #define ARIZONA_OUT2_MONO_WIDTH 1 /* OUT2_MONO */ 2991 #define ARIZONA_OUT2L_ANC_SRC_MASK 0x0C00 /* OUT2L_ANC_SRC - [11:10] */ 2992 #define ARIZONA_OUT2L_ANC_SRC_SHIFT 10 /* OUT2L_ANC_SRC - [11:10] */ 2993 #define ARIZONA_OUT2L_ANC_SRC_WIDTH 2 /* OUT2L_ANC_SRC - [11:10] */ 2994 #define ARIZONA_OUT2L_PGA_VOL_MASK 0x00FE /* OUT2L_PGA_VOL - [7:1] */ 2995 #define ARIZONA_OUT2L_PGA_VOL_SHIFT 1 /* OUT2L_PGA_VOL - [7:1] */ 2996 #define ARIZONA_OUT2L_PGA_VOL_WIDTH 7 /* OUT2L_PGA_VOL - [7:1] */ 2997 2998 /* 2999 * R1049 (0x419) - DAC Digital Volume 2L 3000 */ 3001 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */ 3002 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */ 3003 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */ 3004 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */ 3005 #define ARIZONA_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */ 3006 #define ARIZONA_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */ 3007 #define ARIZONA_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */ 3008 #define ARIZONA_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */ 3009 #define ARIZONA_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */ 3010 #define ARIZONA_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */ 3011 #define ARIZONA_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */ 3012 3013 /* 3014 * R1050 (0x41A) - DAC Volume Limit 2L 3015 */ 3016 #define ARIZONA_OUT2L_VOL_LIM_MASK 0x00FF /* OUT2L_VOL_LIM - [7:0] */ 3017 #define ARIZONA_OUT2L_VOL_LIM_SHIFT 0 /* OUT2L_VOL_LIM - [7:0] */ 3018 #define ARIZONA_OUT2L_VOL_LIM_WIDTH 8 /* OUT2L_VOL_LIM - [7:0] */ 3019 3020 /* 3021 * R1051 (0x41B) - Noise Gate Select 2L 3022 */ 3023 #define ARIZONA_OUT2L_NGATE_SRC_MASK 0x0FFF /* OUT2L_NGATE_SRC - [11:0] */ 3024 #define ARIZONA_OUT2L_NGATE_SRC_SHIFT 0 /* OUT2L_NGATE_SRC - [11:0] */ 3025 #define ARIZONA_OUT2L_NGATE_SRC_WIDTH 12 /* OUT2L_NGATE_SRC - [11:0] */ 3026 3027 /* 3028 * R1052 (0x41C) - Output Path Config 2R 3029 */ 3030 #define ARIZONA_OUT2R_ANC_SRC_MASK 0x0C00 /* OUT2R_ANC_SRC - [11:10] */ 3031 #define ARIZONA_OUT2R_ANC_SRC_SHIFT 10 /* OUT2R_ANC_SRC - [11:10] */ 3032 #define ARIZONA_OUT2R_ANC_SRC_WIDTH 2 /* OUT2R_ANC_SRC - [11:10] */ 3033 #define ARIZONA_OUT2R_PGA_VOL_MASK 0x00FE /* OUT2R_PGA_VOL - [7:1] */ 3034 #define ARIZONA_OUT2R_PGA_VOL_SHIFT 1 /* OUT2R_PGA_VOL - [7:1] */ 3035 #define ARIZONA_OUT2R_PGA_VOL_WIDTH 7 /* OUT2R_PGA_VOL - [7:1] */ 3036 3037 /* 3038 * R1053 (0x41D) - DAC Digital Volume 2R 3039 */ 3040 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */ 3041 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */ 3042 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */ 3043 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */ 3044 #define ARIZONA_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */ 3045 #define ARIZONA_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */ 3046 #define ARIZONA_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */ 3047 #define ARIZONA_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */ 3048 #define ARIZONA_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */ 3049 #define ARIZONA_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */ 3050 #define ARIZONA_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */ 3051 3052 /* 3053 * R1054 (0x41E) - DAC Volume Limit 2R 3054 */ 3055 #define ARIZONA_OUT2R_VOL_LIM_MASK 0x00FF /* OUT2R_VOL_LIM - [7:0] */ 3056 #define ARIZONA_OUT2R_VOL_LIM_SHIFT 0 /* OUT2R_VOL_LIM - [7:0] */ 3057 #define ARIZONA_OUT2R_VOL_LIM_WIDTH 8 /* OUT2R_VOL_LIM - [7:0] */ 3058 3059 /* 3060 * R1055 (0x41F) - Noise Gate Select 2R 3061 */ 3062 #define ARIZONA_OUT2R_NGATE_SRC_MASK 0x0FFF /* OUT2R_NGATE_SRC - [11:0] */ 3063 #define ARIZONA_OUT2R_NGATE_SRC_SHIFT 0 /* OUT2R_NGATE_SRC - [11:0] */ 3064 #define ARIZONA_OUT2R_NGATE_SRC_WIDTH 12 /* OUT2R_NGATE_SRC - [11:0] */ 3065 3066 /* 3067 * R1056 (0x420) - Output Path Config 3L 3068 */ 3069 #define ARIZONA_OUT3_LP_MODE 0x8000 /* OUT3_LP_MODE */ 3070 #define ARIZONA_OUT3_LP_MODE_MASK 0x8000 /* OUT3_LP_MODE */ 3071 #define ARIZONA_OUT3_LP_MODE_SHIFT 15 /* OUT3_LP_MODE */ 3072 #define ARIZONA_OUT3_LP_MODE_WIDTH 1 /* OUT3_LP_MODE */ 3073 #define ARIZONA_OUT3_OSR 0x2000 /* OUT3_OSR */ 3074 #define ARIZONA_OUT3_OSR_MASK 0x2000 /* OUT3_OSR */ 3075 #define ARIZONA_OUT3_OSR_SHIFT 13 /* OUT3_OSR */ 3076 #define ARIZONA_OUT3_OSR_WIDTH 1 /* OUT3_OSR */ 3077 #define ARIZONA_OUT3_MONO 0x1000 /* OUT3_MONO */ 3078 #define ARIZONA_OUT3_MONO_MASK 0x1000 /* OUT3_MONO */ 3079 #define ARIZONA_OUT3_MONO_SHIFT 12 /* OUT3_MONO */ 3080 #define ARIZONA_OUT3_MONO_WIDTH 1 /* OUT3_MONO */ 3081 #define ARIZONA_OUT3L_ANC_SRC_MASK 0x0C00 /* OUT3L_ANC_SRC - [11:10] */ 3082 #define ARIZONA_OUT3L_ANC_SRC_SHIFT 10 /* OUT3L_ANC_SRC - [11:10] */ 3083 #define ARIZONA_OUT3L_ANC_SRC_WIDTH 2 /* OUT3L_ANC_SRC - [11:10] */ 3084 #define ARIZONA_OUT3L_PGA_VOL_MASK 0x00FE /* OUT3L_PGA_VOL - [7:1] */ 3085 #define ARIZONA_OUT3L_PGA_VOL_SHIFT 1 /* OUT3L_PGA_VOL - [7:1] */ 3086 #define ARIZONA_OUT3L_PGA_VOL_WIDTH 7 /* OUT3L_PGA_VOL - [7:1] */ 3087 3088 /* 3089 * R1057 (0x421) - DAC Digital Volume 3L 3090 */ 3091 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */ 3092 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */ 3093 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */ 3094 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */ 3095 #define ARIZONA_OUT3L_MUTE 0x0100 /* OUT3L_MUTE */ 3096 #define ARIZONA_OUT3L_MUTE_MASK 0x0100 /* OUT3L_MUTE */ 3097 #define ARIZONA_OUT3L_MUTE_SHIFT 8 /* OUT3L_MUTE */ 3098 #define ARIZONA_OUT3L_MUTE_WIDTH 1 /* OUT3L_MUTE */ 3099 #define ARIZONA_OUT3L_VOL_MASK 0x00FF /* OUT3L_VOL - [7:0] */ 3100 #define ARIZONA_OUT3L_VOL_SHIFT 0 /* OUT3L_VOL - [7:0] */ 3101 #define ARIZONA_OUT3L_VOL_WIDTH 8 /* OUT3L_VOL - [7:0] */ 3102 3103 /* 3104 * R1058 (0x422) - DAC Volume Limit 3L 3105 */ 3106 #define ARIZONA_OUT3L_VOL_LIM_MASK 0x00FF /* OUT3L_VOL_LIM - [7:0] */ 3107 #define ARIZONA_OUT3L_VOL_LIM_SHIFT 0 /* OUT3L_VOL_LIM - [7:0] */ 3108 #define ARIZONA_OUT3L_VOL_LIM_WIDTH 8 /* OUT3L_VOL_LIM - [7:0] */ 3109 3110 /* 3111 * R1059 (0x423) - Noise Gate Select 3L 3112 */ 3113 #define ARIZONA_OUT3_NGATE_SRC_MASK 0x0FFF /* OUT3_NGATE_SRC - [11:0] */ 3114 #define ARIZONA_OUT3_NGATE_SRC_SHIFT 0 /* OUT3_NGATE_SRC - [11:0] */ 3115 #define ARIZONA_OUT3_NGATE_SRC_WIDTH 12 /* OUT3_NGATE_SRC - [11:0] */ 3116 3117 /* 3118 * R1060 (0x424) - Output Path Config 3R 3119 */ 3120 #define ARIZONA_OUT3R_PGA_VOL_MASK 0x00FE /* OUT3R_PGA_VOL - [7:1] */ 3121 #define ARIZONA_OUT3R_PGA_VOL_SHIFT 1 /* OUT3R_PGA_VOL - [7:1] */ 3122 #define ARIZONA_OUT3R_PGA_VOL_WIDTH 7 /* OUT3R_PGA_VOL - [7:1] */ 3123 3124 /* 3125 * R1061 (0x425) - DAC Digital Volume 3R 3126 */ 3127 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */ 3128 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */ 3129 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */ 3130 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */ 3131 #define ARIZONA_OUT3R_MUTE 0x0100 /* OUT3R_MUTE */ 3132 #define ARIZONA_OUT3R_MUTE_MASK 0x0100 /* OUT3R_MUTE */ 3133 #define ARIZONA_OUT3R_MUTE_SHIFT 8 /* OUT3R_MUTE */ 3134 #define ARIZONA_OUT3R_MUTE_WIDTH 1 /* OUT3R_MUTE */ 3135 #define ARIZONA_OUT3R_VOL_MASK 0x00FF /* OUT3R_VOL - [7:0] */ 3136 #define ARIZONA_OUT3R_VOL_SHIFT 0 /* OUT3R_VOL - [7:0] */ 3137 #define ARIZONA_OUT3R_VOL_WIDTH 8 /* OUT3R_VOL - [7:0] */ 3138 3139 /* 3140 * R1062 (0x426) - DAC Volume Limit 3R 3141 */ 3142 #define ARIZONA_OUT3R_ANC_SRC_MASK 0x0C00 /* OUT3R_ANC_SRC - [11:10] */ 3143 #define ARIZONA_OUT3R_ANC_SRC_SHIFT 10 /* OUT3R_ANC_SRC - [11:10] */ 3144 #define ARIZONA_OUT3R_ANC_SRC_WIDTH 2 /* OUT3R_ANC_SRC - [11:10] */ 3145 #define ARIZONA_OUT3R_VOL_LIM_MASK 0x00FF /* OUT3R_VOL_LIM - [7:0] */ 3146 #define ARIZONA_OUT3R_VOL_LIM_SHIFT 0 /* OUT3R_VOL_LIM - [7:0] */ 3147 #define ARIZONA_OUT3R_VOL_LIM_WIDTH 8 /* OUT3R_VOL_LIM - [7:0] */ 3148 3149 /* 3150 * R1064 (0x428) - Output Path Config 4L 3151 */ 3152 #define ARIZONA_OUT4_OSR 0x2000 /* OUT4_OSR */ 3153 #define ARIZONA_OUT4_OSR_MASK 0x2000 /* OUT4_OSR */ 3154 #define ARIZONA_OUT4_OSR_SHIFT 13 /* OUT4_OSR */ 3155 #define ARIZONA_OUT4_OSR_WIDTH 1 /* OUT4_OSR */ 3156 #define ARIZONA_OUT4L_ANC_SRC_MASK 0x0C00 /* OUT4L_ANC_SRC - [11:10] */ 3157 #define ARIZONA_OUT4L_ANC_SRC_SHIFT 10 /* OUT4L_ANC_SRC - [11:10] */ 3158 #define ARIZONA_OUT4L_ANC_SRC_WIDTH 2 /* OUT4L_ANC_SRC - [11:10] */ 3159 3160 /* 3161 * R1065 (0x429) - DAC Digital Volume 4L 3162 */ 3163 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */ 3164 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */ 3165 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */ 3166 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */ 3167 #define ARIZONA_OUT4L_MUTE 0x0100 /* OUT4L_MUTE */ 3168 #define ARIZONA_OUT4L_MUTE_MASK 0x0100 /* OUT4L_MUTE */ 3169 #define ARIZONA_OUT4L_MUTE_SHIFT 8 /* OUT4L_MUTE */ 3170 #define ARIZONA_OUT4L_MUTE_WIDTH 1 /* OUT4L_MUTE */ 3171 #define ARIZONA_OUT4L_VOL_MASK 0x00FF /* OUT4L_VOL - [7:0] */ 3172 #define ARIZONA_OUT4L_VOL_SHIFT 0 /* OUT4L_VOL - [7:0] */ 3173 #define ARIZONA_OUT4L_VOL_WIDTH 8 /* OUT4L_VOL - [7:0] */ 3174 3175 /* 3176 * R1066 (0x42A) - Out Volume 4L 3177 */ 3178 #define ARIZONA_OUT4L_VOL_LIM_MASK 0x00FF /* OUT4L_VOL_LIM - [7:0] */ 3179 #define ARIZONA_OUT4L_VOL_LIM_SHIFT 0 /* OUT4L_VOL_LIM - [7:0] */ 3180 #define ARIZONA_OUT4L_VOL_LIM_WIDTH 8 /* OUT4L_VOL_LIM - [7:0] */ 3181 3182 /* 3183 * R1067 (0x42B) - Noise Gate Select 4L 3184 */ 3185 #define ARIZONA_OUT4L_NGATE_SRC_MASK 0x0FFF /* OUT4L_NGATE_SRC - [11:0] */ 3186 #define ARIZONA_OUT4L_NGATE_SRC_SHIFT 0 /* OUT4L_NGATE_SRC - [11:0] */ 3187 #define ARIZONA_OUT4L_NGATE_SRC_WIDTH 12 /* OUT4L_NGATE_SRC - [11:0] */ 3188 3189 /* 3190 * R1068 (0x42C) - Output Path Config 4R 3191 */ 3192 #define ARIZONA_OUT4R_ANC_SRC_MASK 0x0C00 /* OUT4R_ANC_SRC - [11:10] */ 3193 #define ARIZONA_OUT4R_ANC_SRC_SHIFT 10 /* OUT4R_ANC_SRC - [11:10] */ 3194 #define ARIZONA_OUT4R_ANC_SRC_WIDTH 2 /* OUT4R_ANC_SRC - [11:10] */ 3195 3196 /* 3197 * R1069 (0x42D) - DAC Digital Volume 4R 3198 */ 3199 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */ 3200 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */ 3201 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */ 3202 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */ 3203 #define ARIZONA_OUT4R_MUTE 0x0100 /* OUT4R_MUTE */ 3204 #define ARIZONA_OUT4R_MUTE_MASK 0x0100 /* OUT4R_MUTE */ 3205 #define ARIZONA_OUT4R_MUTE_SHIFT 8 /* OUT4R_MUTE */ 3206 #define ARIZONA_OUT4R_MUTE_WIDTH 1 /* OUT4R_MUTE */ 3207 #define ARIZONA_OUT4R_VOL_MASK 0x00FF /* OUT4R_VOL - [7:0] */ 3208 #define ARIZONA_OUT4R_VOL_SHIFT 0 /* OUT4R_VOL - [7:0] */ 3209 #define ARIZONA_OUT4R_VOL_WIDTH 8 /* OUT4R_VOL - [7:0] */ 3210 3211 /* 3212 * R1070 (0x42E) - Out Volume 4R 3213 */ 3214 #define ARIZONA_OUT4R_VOL_LIM_MASK 0x00FF /* OUT4R_VOL_LIM - [7:0] */ 3215 #define ARIZONA_OUT4R_VOL_LIM_SHIFT 0 /* OUT4R_VOL_LIM - [7:0] */ 3216 #define ARIZONA_OUT4R_VOL_LIM_WIDTH 8 /* OUT4R_VOL_LIM - [7:0] */ 3217 3218 /* 3219 * R1071 (0x42F) - Noise Gate Select 4R 3220 */ 3221 #define ARIZONA_OUT4R_NGATE_SRC_MASK 0x0FFF /* OUT4R_NGATE_SRC - [11:0] */ 3222 #define ARIZONA_OUT4R_NGATE_SRC_SHIFT 0 /* OUT4R_NGATE_SRC - [11:0] */ 3223 #define ARIZONA_OUT4R_NGATE_SRC_WIDTH 12 /* OUT4R_NGATE_SRC - [11:0] */ 3224 3225 /* 3226 * R1072 (0x430) - Output Path Config 5L 3227 */ 3228 #define ARIZONA_OUT5_OSR 0x2000 /* OUT5_OSR */ 3229 #define ARIZONA_OUT5_OSR_MASK 0x2000 /* OUT5_OSR */ 3230 #define ARIZONA_OUT5_OSR_SHIFT 13 /* OUT5_OSR */ 3231 #define ARIZONA_OUT5_OSR_WIDTH 1 /* OUT5_OSR */ 3232 #define ARIZONA_OUT5L_ANC_SRC_MASK 0x0C00 /* OUT5L_ANC_SRC - [11:10] */ 3233 #define ARIZONA_OUT5L_ANC_SRC_SHIFT 10 /* OUT5L_ANC_SRC - [11:10] */ 3234 #define ARIZONA_OUT5L_ANC_SRC_WIDTH 2 /* OUT5L_ANC_SRC - [11:10] */ 3235 3236 /* 3237 * R1073 (0x431) - DAC Digital Volume 5L 3238 */ 3239 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */ 3240 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */ 3241 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */ 3242 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */ 3243 #define ARIZONA_OUT5L_MUTE 0x0100 /* OUT5L_MUTE */ 3244 #define ARIZONA_OUT5L_MUTE_MASK 0x0100 /* OUT5L_MUTE */ 3245 #define ARIZONA_OUT5L_MUTE_SHIFT 8 /* OUT5L_MUTE */ 3246 #define ARIZONA_OUT5L_MUTE_WIDTH 1 /* OUT5L_MUTE */ 3247 #define ARIZONA_OUT5L_VOL_MASK 0x00FF /* OUT5L_VOL - [7:0] */ 3248 #define ARIZONA_OUT5L_VOL_SHIFT 0 /* OUT5L_VOL - [7:0] */ 3249 #define ARIZONA_OUT5L_VOL_WIDTH 8 /* OUT5L_VOL - [7:0] */ 3250 3251 /* 3252 * R1074 (0x432) - DAC Volume Limit 5L 3253 */ 3254 #define ARIZONA_OUT5L_VOL_LIM_MASK 0x00FF /* OUT5L_VOL_LIM - [7:0] */ 3255 #define ARIZONA_OUT5L_VOL_LIM_SHIFT 0 /* OUT5L_VOL_LIM - [7:0] */ 3256 #define ARIZONA_OUT5L_VOL_LIM_WIDTH 8 /* OUT5L_VOL_LIM - [7:0] */ 3257 3258 /* 3259 * R1075 (0x433) - Noise Gate Select 5L 3260 */ 3261 #define ARIZONA_OUT5L_NGATE_SRC_MASK 0x0FFF /* OUT5L_NGATE_SRC - [11:0] */ 3262 #define ARIZONA_OUT5L_NGATE_SRC_SHIFT 0 /* OUT5L_NGATE_SRC - [11:0] */ 3263 #define ARIZONA_OUT5L_NGATE_SRC_WIDTH 12 /* OUT5L_NGATE_SRC - [11:0] */ 3264 3265 /* 3266 * R1076 (0x434) - Output Path Config 5R 3267 */ 3268 #define ARIZONA_OUT5R_ANC_SRC_MASK 0x0C00 /* OUT5R_ANC_SRC - [11:10] */ 3269 #define ARIZONA_OUT5R_ANC_SRC_SHIFT 10 /* OUT5R_ANC_SRC - [11:10] */ 3270 #define ARIZONA_OUT5R_ANC_SRC_WIDTH 2 /* OUT5R_ANC_SRC - [11:10] */ 3271 3272 /* 3273 * R1077 (0x435) - DAC Digital Volume 5R 3274 */ 3275 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */ 3276 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */ 3277 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */ 3278 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */ 3279 #define ARIZONA_OUT5R_MUTE 0x0100 /* OUT5R_MUTE */ 3280 #define ARIZONA_OUT5R_MUTE_MASK 0x0100 /* OUT5R_MUTE */ 3281 #define ARIZONA_OUT5R_MUTE_SHIFT 8 /* OUT5R_MUTE */ 3282 #define ARIZONA_OUT5R_MUTE_WIDTH 1 /* OUT5R_MUTE */ 3283 #define ARIZONA_OUT5R_VOL_MASK 0x00FF /* OUT5R_VOL - [7:0] */ 3284 #define ARIZONA_OUT5R_VOL_SHIFT 0 /* OUT5R_VOL - [7:0] */ 3285 #define ARIZONA_OUT5R_VOL_WIDTH 8 /* OUT5R_VOL - [7:0] */ 3286 3287 /* 3288 * R1078 (0x436) - DAC Volume Limit 5R 3289 */ 3290 #define ARIZONA_OUT5R_VOL_LIM_MASK 0x00FF /* OUT5R_VOL_LIM - [7:0] */ 3291 #define ARIZONA_OUT5R_VOL_LIM_SHIFT 0 /* OUT5R_VOL_LIM - [7:0] */ 3292 #define ARIZONA_OUT5R_VOL_LIM_WIDTH 8 /* OUT5R_VOL_LIM - [7:0] */ 3293 3294 /* 3295 * R1079 (0x437) - Noise Gate Select 5R 3296 */ 3297 #define ARIZONA_OUT5R_NGATE_SRC_MASK 0x0FFF /* OUT5R_NGATE_SRC - [11:0] */ 3298 #define ARIZONA_OUT5R_NGATE_SRC_SHIFT 0 /* OUT5R_NGATE_SRC - [11:0] */ 3299 #define ARIZONA_OUT5R_NGATE_SRC_WIDTH 12 /* OUT5R_NGATE_SRC - [11:0] */ 3300 3301 /* 3302 * R1080 (0x438) - Output Path Config 6L 3303 */ 3304 #define ARIZONA_OUT6_OSR 0x2000 /* OUT6_OSR */ 3305 #define ARIZONA_OUT6_OSR_MASK 0x2000 /* OUT6_OSR */ 3306 #define ARIZONA_OUT6_OSR_SHIFT 13 /* OUT6_OSR */ 3307 #define ARIZONA_OUT6_OSR_WIDTH 1 /* OUT6_OSR */ 3308 #define ARIZONA_OUT6L_ANC_SRC_MASK 0x0C00 /* OUT6L_ANC_SRC - [11:10] */ 3309 #define ARIZONA_OUT6L_ANC_SRC_SHIFT 10 /* OUT6L_ANC_SRC - [11:10] */ 3310 #define ARIZONA_OUT6L_ANC_SRC_WIDTH 2 /* OUT6L_ANC_SRC - [11:10] */ 3311 3312 /* 3313 * R1081 (0x439) - DAC Digital Volume 6L 3314 */ 3315 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */ 3316 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */ 3317 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */ 3318 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */ 3319 #define ARIZONA_OUT6L_MUTE 0x0100 /* OUT6L_MUTE */ 3320 #define ARIZONA_OUT6L_MUTE_MASK 0x0100 /* OUT6L_MUTE */ 3321 #define ARIZONA_OUT6L_MUTE_SHIFT 8 /* OUT6L_MUTE */ 3322 #define ARIZONA_OUT6L_MUTE_WIDTH 1 /* OUT6L_MUTE */ 3323 #define ARIZONA_OUT6L_VOL_MASK 0x00FF /* OUT6L_VOL - [7:0] */ 3324 #define ARIZONA_OUT6L_VOL_SHIFT 0 /* OUT6L_VOL - [7:0] */ 3325 #define ARIZONA_OUT6L_VOL_WIDTH 8 /* OUT6L_VOL - [7:0] */ 3326 3327 /* 3328 * R1082 (0x43A) - DAC Volume Limit 6L 3329 */ 3330 #define ARIZONA_OUT6L_VOL_LIM_MASK 0x00FF /* OUT6L_VOL_LIM - [7:0] */ 3331 #define ARIZONA_OUT6L_VOL_LIM_SHIFT 0 /* OUT6L_VOL_LIM - [7:0] */ 3332 #define ARIZONA_OUT6L_VOL_LIM_WIDTH 8 /* OUT6L_VOL_LIM - [7:0] */ 3333 3334 /* 3335 * R1083 (0x43B) - Noise Gate Select 6L 3336 */ 3337 #define ARIZONA_OUT6L_NGATE_SRC_MASK 0x0FFF /* OUT6L_NGATE_SRC - [11:0] */ 3338 #define ARIZONA_OUT6L_NGATE_SRC_SHIFT 0 /* OUT6L_NGATE_SRC - [11:0] */ 3339 #define ARIZONA_OUT6L_NGATE_SRC_WIDTH 12 /* OUT6L_NGATE_SRC - [11:0] */ 3340 3341 /* 3342 * R1084 (0x43C) - Output Path Config 6R 3343 */ 3344 #define ARIZONA_OUT6R_ANC_SRC_MASK 0x0C00 /* OUT6R_ANC_SRC - [11:10] */ 3345 #define ARIZONA_OUT6R_ANC_SRC_SHIFT 10 /* OUT6R_ANC_SRC - [11:10] */ 3346 #define ARIZONA_OUT6R_ANC_SRC_WIDTH 2 /* OUT6R_ANC_SRC - [11:10] */ 3347 3348 /* 3349 * R1085 (0x43D) - DAC Digital Volume 6R 3350 */ 3351 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */ 3352 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */ 3353 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */ 3354 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */ 3355 #define ARIZONA_OUT6R_MUTE 0x0100 /* OUT6R_MUTE */ 3356 #define ARIZONA_OUT6R_MUTE_MASK 0x0100 /* OUT6R_MUTE */ 3357 #define ARIZONA_OUT6R_MUTE_SHIFT 8 /* OUT6R_MUTE */ 3358 #define ARIZONA_OUT6R_MUTE_WIDTH 1 /* OUT6R_MUTE */ 3359 #define ARIZONA_OUT6R_VOL_MASK 0x00FF /* OUT6R_VOL - [7:0] */ 3360 #define ARIZONA_OUT6R_VOL_SHIFT 0 /* OUT6R_VOL - [7:0] */ 3361 #define ARIZONA_OUT6R_VOL_WIDTH 8 /* OUT6R_VOL - [7:0] */ 3362 3363 /* 3364 * R1086 (0x43E) - DAC Volume Limit 6R 3365 */ 3366 #define ARIZONA_OUT6R_VOL_LIM_MASK 0x00FF /* OUT6R_VOL_LIM - [7:0] */ 3367 #define ARIZONA_OUT6R_VOL_LIM_SHIFT 0 /* OUT6R_VOL_LIM - [7:0] */ 3368 #define ARIZONA_OUT6R_VOL_LIM_WIDTH 8 /* OUT6R_VOL_LIM - [7:0] */ 3369 3370 /* 3371 * R1087 (0x43F) - Noise Gate Select 6R 3372 */ 3373 #define ARIZONA_OUT6R_NGATE_SRC_MASK 0x0FFF /* OUT6R_NGATE_SRC - [11:0] */ 3374 #define ARIZONA_OUT6R_NGATE_SRC_SHIFT 0 /* OUT6R_NGATE_SRC - [11:0] */ 3375 #define ARIZONA_OUT6R_NGATE_SRC_WIDTH 12 /* OUT6R_NGATE_SRC - [11:0] */ 3376 3377 /* 3378 * R1088 (0x440) - DRE Enable 3379 */ 3380 #define ARIZONA_DRE3R_ENA 0x0020 /* DRE3R_ENA */ 3381 #define ARIZONA_DRE3R_ENA_MASK 0x0020 /* DRE3R_ENA */ 3382 #define ARIZONA_DRE3R_ENA_SHIFT 5 /* DRE3R_ENA */ 3383 #define ARIZONA_DRE3R_ENA_WIDTH 1 /* DRE3R_ENA */ 3384 #define ARIZONA_DRE3L_ENA 0x0010 /* DRE3L_ENA */ 3385 #define ARIZONA_DRE3L_ENA_MASK 0x0010 /* DRE3L_ENA */ 3386 #define ARIZONA_DRE3L_ENA_SHIFT 4 /* DRE3L_ENA */ 3387 #define ARIZONA_DRE3L_ENA_WIDTH 1 /* DRE3L_ENA */ 3388 #define ARIZONA_DRE2R_ENA 0x0008 /* DRE2R_ENA */ 3389 #define ARIZONA_DRE2R_ENA_MASK 0x0008 /* DRE2R_ENA */ 3390 #define ARIZONA_DRE2R_ENA_SHIFT 3 /* DRE2R_ENA */ 3391 #define ARIZONA_DRE2R_ENA_WIDTH 1 /* DRE2R_ENA */ 3392 #define ARIZONA_DRE2L_ENA 0x0004 /* DRE2L_ENA */ 3393 #define ARIZONA_DRE2L_ENA_MASK 0x0004 /* DRE2L_ENA */ 3394 #define ARIZONA_DRE2L_ENA_SHIFT 2 /* DRE2L_ENA */ 3395 #define ARIZONA_DRE2L_ENA_WIDTH 1 /* DRE2L_ENA */ 3396 #define ARIZONA_DRE1R_ENA 0x0002 /* DRE1R_ENA */ 3397 #define ARIZONA_DRE1R_ENA_MASK 0x0002 /* DRE1R_ENA */ 3398 #define ARIZONA_DRE1R_ENA_SHIFT 1 /* DRE1R_ENA */ 3399 #define ARIZONA_DRE1R_ENA_WIDTH 1 /* DRE1R_ENA */ 3400 #define ARIZONA_DRE1L_ENA 0x0001 /* DRE1L_ENA */ 3401 #define ARIZONA_DRE1L_ENA_MASK 0x0001 /* DRE1L_ENA */ 3402 #define ARIZONA_DRE1L_ENA_SHIFT 0 /* DRE1L_ENA */ 3403 #define ARIZONA_DRE1L_ENA_WIDTH 1 /* DRE1L_ENA */ 3404 3405 /* 3406 * R1090 (0x442) - DRE Control 2 3407 */ 3408 #define ARIZONA_DRE_T_LOW_MASK 0x3F00 /* DRE_T_LOW - [13:8] */ 3409 #define ARIZONA_DRE_T_LOW_SHIFT 8 /* DRE_T_LOW - [13:8] */ 3410 #define ARIZONA_DRE_T_LOW_WIDTH 6 /* DRE_T_LOW - [13:8] */ 3411 3412 /* 3413 * R1091 (0x443) - DRE Control 3 3414 */ 3415 #define ARIZONA_DRE_GAIN_SHIFT_MASK 0xC000 /* DRE_GAIN_SHIFT - [15:14] */ 3416 #define ARIZONA_DRE_GAIN_SHIFT_SHIFT 14 /* DRE_GAIN_SHIFT - [15:14] */ 3417 #define ARIZONA_DRE_GAIN_SHIFT_WIDTH 2 /* DRE_GAIN_SHIFT - [15:14] */ 3418 #define ARIZONA_DRE_LOW_LEVEL_ABS_MASK 0x000F /* LOW_LEVEL_ABS - [3:0] */ 3419 #define ARIZONA_DRE_LOW_LEVEL_ABS_SHIFT 0 /* LOW_LEVEL_ABS - [3:0] */ 3420 #define ARIZONA_DRE_LOW_LEVEL_ABS_WIDTH 4 /* LOW_LEVEL_ABS - [3:0] */ 3421 3422 /* 3423 * R1104 (0x450) - DAC AEC Control 1 3424 */ 3425 #define ARIZONA_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */ 3426 #define ARIZONA_AEC_LOOPBACK_SRC_SHIFT 2 /* AEC_LOOPBACK_SRC - [5:2] */ 3427 #define ARIZONA_AEC_LOOPBACK_SRC_WIDTH 4 /* AEC_LOOPBACK_SRC - [5:2] */ 3428 #define ARIZONA_AEC_ENA_STS 0x0002 /* AEC_ENA_STS */ 3429 #define ARIZONA_AEC_ENA_STS_MASK 0x0002 /* AEC_ENA_STS */ 3430 #define ARIZONA_AEC_ENA_STS_SHIFT 1 /* AEC_ENA_STS */ 3431 #define ARIZONA_AEC_ENA_STS_WIDTH 1 /* AEC_ENA_STS */ 3432 #define ARIZONA_AEC_LOOPBACK_ENA 0x0001 /* AEC_LOOPBACK_ENA */ 3433 #define ARIZONA_AEC_LOOPBACK_ENA_MASK 0x0001 /* AEC_LOOPBACK_ENA */ 3434 #define ARIZONA_AEC_LOOPBACK_ENA_SHIFT 0 /* AEC_LOOPBACK_ENA */ 3435 #define ARIZONA_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */ 3436 3437 /* 3438 * R1112 (0x458) - Noise Gate Control 3439 */ 3440 #define ARIZONA_NGATE_HOLD_MASK 0x0030 /* NGATE_HOLD - [5:4] */ 3441 #define ARIZONA_NGATE_HOLD_SHIFT 4 /* NGATE_HOLD - [5:4] */ 3442 #define ARIZONA_NGATE_HOLD_WIDTH 2 /* NGATE_HOLD - [5:4] */ 3443 #define ARIZONA_NGATE_THR_MASK 0x000E /* NGATE_THR - [3:1] */ 3444 #define ARIZONA_NGATE_THR_SHIFT 1 /* NGATE_THR - [3:1] */ 3445 #define ARIZONA_NGATE_THR_WIDTH 3 /* NGATE_THR - [3:1] */ 3446 #define ARIZONA_NGATE_ENA 0x0001 /* NGATE_ENA */ 3447 #define ARIZONA_NGATE_ENA_MASK 0x0001 /* NGATE_ENA */ 3448 #define ARIZONA_NGATE_ENA_SHIFT 0 /* NGATE_ENA */ 3449 #define ARIZONA_NGATE_ENA_WIDTH 1 /* NGATE_ENA */ 3450 3451 /* 3452 * R1168 (0x490) - PDM SPK1 CTRL 1 3453 */ 3454 #define ARIZONA_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */ 3455 #define ARIZONA_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */ 3456 #define ARIZONA_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */ 3457 #define ARIZONA_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */ 3458 #define ARIZONA_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */ 3459 #define ARIZONA_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */ 3460 #define ARIZONA_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */ 3461 #define ARIZONA_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */ 3462 #define ARIZONA_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */ 3463 #define ARIZONA_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */ 3464 #define ARIZONA_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */ 3465 #define ARIZONA_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */ 3466 #define ARIZONA_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */ 3467 #define ARIZONA_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */ 3468 #define ARIZONA_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */ 3469 3470 /* 3471 * R1169 (0x491) - PDM SPK1 CTRL 2 3472 */ 3473 #define ARIZONA_SPK1_FMT 0x0001 /* SPK1_FMT */ 3474 #define ARIZONA_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */ 3475 #define ARIZONA_SPK1_FMT_SHIFT 0 /* SPK1_FMT */ 3476 #define ARIZONA_SPK1_FMT_WIDTH 1 /* SPK1_FMT */ 3477 3478 /* 3479 * R1170 (0x492) - PDM SPK2 CTRL 1 3480 */ 3481 #define ARIZONA_SPK2R_MUTE 0x2000 /* SPK2R_MUTE */ 3482 #define ARIZONA_SPK2R_MUTE_MASK 0x2000 /* SPK2R_MUTE */ 3483 #define ARIZONA_SPK2R_MUTE_SHIFT 13 /* SPK2R_MUTE */ 3484 #define ARIZONA_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */ 3485 #define ARIZONA_SPK2L_MUTE 0x1000 /* SPK2L_MUTE */ 3486 #define ARIZONA_SPK2L_MUTE_MASK 0x1000 /* SPK2L_MUTE */ 3487 #define ARIZONA_SPK2L_MUTE_SHIFT 12 /* SPK2L_MUTE */ 3488 #define ARIZONA_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */ 3489 #define ARIZONA_SPK2_MUTE_ENDIAN 0x0100 /* SPK2_MUTE_ENDIAN */ 3490 #define ARIZONA_SPK2_MUTE_ENDIAN_MASK 0x0100 /* SPK2_MUTE_ENDIAN */ 3491 #define ARIZONA_SPK2_MUTE_ENDIAN_SHIFT 8 /* SPK2_MUTE_ENDIAN */ 3492 #define ARIZONA_SPK2_MUTE_ENDIAN_WIDTH 1 /* SPK2_MUTE_ENDIAN */ 3493 #define ARIZONA_SPK2_MUTE_SEQ_MASK 0x00FF /* SPK2_MUTE_SEQ - [7:0] */ 3494 #define ARIZONA_SPK2_MUTE_SEQ_SHIFT 0 /* SPK2_MUTE_SEQ - [7:0] */ 3495 #define ARIZONA_SPK2_MUTE_SEQ_WIDTH 8 /* SPK2_MUTE_SEQ - [7:0] */ 3496 3497 /* 3498 * R1171 (0x493) - PDM SPK2 CTRL 2 3499 */ 3500 #define ARIZONA_SPK2_FMT 0x0001 /* SPK2_FMT */ 3501 #define ARIZONA_SPK2_FMT_MASK 0x0001 /* SPK2_FMT */ 3502 #define ARIZONA_SPK2_FMT_SHIFT 0 /* SPK2_FMT */ 3503 #define ARIZONA_SPK2_FMT_WIDTH 1 /* SPK2_FMT */ 3504 3505 /* 3506 * R1184 (0x4A0) - HP1 Short Circuit Ctrl 3507 */ 3508 #define ARIZONA_HP1_SC_ENA 0x1000 /* HP1_SC_ENA */ 3509 #define ARIZONA_HP1_SC_ENA_MASK 0x1000 /* HP1_SC_ENA */ 3510 #define ARIZONA_HP1_SC_ENA_SHIFT 12 /* HP1_SC_ENA */ 3511 #define ARIZONA_HP1_SC_ENA_WIDTH 1 /* HP1_SC_ENA */ 3512 3513 /* 3514 * R1185 (0x4A1) - HP2 Short Circuit Ctrl 3515 */ 3516 #define ARIZONA_HP2_SC_ENA 0x1000 /* HP2_SC_ENA */ 3517 #define ARIZONA_HP2_SC_ENA_MASK 0x1000 /* HP2_SC_ENA */ 3518 #define ARIZONA_HP2_SC_ENA_SHIFT 12 /* HP2_SC_ENA */ 3519 #define ARIZONA_HP2_SC_ENA_WIDTH 1 /* HP2_SC_ENA */ 3520 3521 /* 3522 * R1186 (0x4A2) - HP3 Short Circuit Ctrl 3523 */ 3524 #define ARIZONA_HP3_SC_ENA 0x1000 /* HP3_SC_ENA */ 3525 #define ARIZONA_HP3_SC_ENA_MASK 0x1000 /* HP3_SC_ENA */ 3526 #define ARIZONA_HP3_SC_ENA_SHIFT 12 /* HP3_SC_ENA */ 3527 #define ARIZONA_HP3_SC_ENA_WIDTH 1 /* HP3_SC_ENA */ 3528 3529 /* 3530 * R1244 (0x4DC) - DAC comp 1 3531 */ 3532 #define ARIZONA_OUT_COMP_COEFF_MASK 0xFFFF /* OUT_COMP_COEFF - [15:0] */ 3533 #define ARIZONA_OUT_COMP_COEFF_SHIFT 0 /* OUT_COMP_COEFF - [15:0] */ 3534 #define ARIZONA_OUT_COMP_COEFF_WIDTH 16 /* OUT_COMP_COEFF - [15:0] */ 3535 3536 /* 3537 * R1245 (0x4DD) - DAC comp 2 3538 */ 3539 #define ARIZONA_OUT_COMP_COEFF_1 0x0002 /* OUT_COMP_COEFF */ 3540 #define ARIZONA_OUT_COMP_COEFF_1_MASK 0x0002 /* OUT_COMP_COEFF */ 3541 #define ARIZONA_OUT_COMP_COEFF_1_SHIFT 1 /* OUT_COMP_COEFF */ 3542 #define ARIZONA_OUT_COMP_COEFF_1_WIDTH 1 /* OUT_COMP_COEFF */ 3543 #define ARIZONA_OUT_COMP_COEFF_SEL 0x0001 /* OUT_COMP_COEFF_SEL */ 3544 #define ARIZONA_OUT_COMP_COEFF_SEL_MASK 0x0001 /* OUT_COMP_COEFF_SEL */ 3545 #define ARIZONA_OUT_COMP_COEFF_SEL_SHIFT 0 /* OUT_COMP_COEFF_SEL */ 3546 #define ARIZONA_OUT_COMP_COEFF_SEL_WIDTH 1 /* OUT_COMP_COEFF_SEL */ 3547 3548 /* 3549 * R1246 (0x4DE) - DAC comp 3 3550 */ 3551 #define ARIZONA_AEC_COMP_COEFF_MASK 0xFFFF /* AEC_COMP_COEFF - [15:0] */ 3552 #define ARIZONA_AEC_COMP_COEFF_SHIFT 0 /* AEC_COMP_COEFF - [15:0] */ 3553 #define ARIZONA_AEC_COMP_COEFF_WIDTH 16 /* AEC_COMP_COEFF - [15:0] */ 3554 3555 /* 3556 * R1247 (0x4DF) - DAC comp 4 3557 */ 3558 #define ARIZONA_AEC_COMP_COEFF_1 0x0002 /* AEC_COMP_COEFF */ 3559 #define ARIZONA_AEC_COMP_COEFF_1_MASK 0x0002 /* AEC_COMP_COEFF */ 3560 #define ARIZONA_AEC_COMP_COEFF_1_SHIFT 1 /* AEC_COMP_COEFF */ 3561 #define ARIZONA_AEC_COMP_COEFF_1_WIDTH 1 /* AEC_COMP_COEFF */ 3562 #define ARIZONA_AEC_COMP_COEFF_SEL 0x0001 /* AEC_COMP_COEFF_SEL */ 3563 #define ARIZONA_AEC_COMP_COEFF_SEL_MASK 0x0001 /* AEC_COMP_COEFF_SEL */ 3564 #define ARIZONA_AEC_COMP_COEFF_SEL_SHIFT 0 /* AEC_COMP_COEFF_SEL */ 3565 #define ARIZONA_AEC_COMP_COEFF_SEL_WIDTH 1 /* AEC_COMP_COEFF_SEL */ 3566 3567 /* 3568 * R1280 (0x500) - AIF1 BCLK Ctrl 3569 */ 3570 #define ARIZONA_AIF1_BCLK_INV 0x0080 /* AIF1_BCLK_INV */ 3571 #define ARIZONA_AIF1_BCLK_INV_MASK 0x0080 /* AIF1_BCLK_INV */ 3572 #define ARIZONA_AIF1_BCLK_INV_SHIFT 7 /* AIF1_BCLK_INV */ 3573 #define ARIZONA_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 3574 #define ARIZONA_AIF1_BCLK_FRC 0x0040 /* AIF1_BCLK_FRC */ 3575 #define ARIZONA_AIF1_BCLK_FRC_MASK 0x0040 /* AIF1_BCLK_FRC */ 3576 #define ARIZONA_AIF1_BCLK_FRC_SHIFT 6 /* AIF1_BCLK_FRC */ 3577 #define ARIZONA_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */ 3578 #define ARIZONA_AIF1_BCLK_MSTR 0x0020 /* AIF1_BCLK_MSTR */ 3579 #define ARIZONA_AIF1_BCLK_MSTR_MASK 0x0020 /* AIF1_BCLK_MSTR */ 3580 #define ARIZONA_AIF1_BCLK_MSTR_SHIFT 5 /* AIF1_BCLK_MSTR */ 3581 #define ARIZONA_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */ 3582 #define ARIZONA_AIF1_BCLK_FREQ_MASK 0x001F /* AIF1_BCLK_FREQ - [4:0] */ 3583 #define ARIZONA_AIF1_BCLK_FREQ_SHIFT 0 /* AIF1_BCLK_FREQ - [4:0] */ 3584 #define ARIZONA_AIF1_BCLK_FREQ_WIDTH 5 /* AIF1_BCLK_FREQ - [4:0] */ 3585 3586 /* 3587 * R1281 (0x501) - AIF1 Tx Pin Ctrl 3588 */ 3589 #define ARIZONA_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */ 3590 #define ARIZONA_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */ 3591 #define ARIZONA_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */ 3592 #define ARIZONA_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */ 3593 #define ARIZONA_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */ 3594 #define ARIZONA_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */ 3595 #define ARIZONA_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */ 3596 #define ARIZONA_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */ 3597 #define ARIZONA_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */ 3598 #define ARIZONA_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */ 3599 #define ARIZONA_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */ 3600 #define ARIZONA_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */ 3601 #define ARIZONA_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */ 3602 #define ARIZONA_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */ 3603 #define ARIZONA_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */ 3604 #define ARIZONA_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */ 3605 #define ARIZONA_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */ 3606 #define ARIZONA_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */ 3607 #define ARIZONA_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */ 3608 #define ARIZONA_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */ 3609 3610 /* 3611 * R1282 (0x502) - AIF1 Rx Pin Ctrl 3612 */ 3613 #define ARIZONA_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */ 3614 #define ARIZONA_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */ 3615 #define ARIZONA_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */ 3616 #define ARIZONA_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */ 3617 #define ARIZONA_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */ 3618 #define ARIZONA_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */ 3619 #define ARIZONA_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */ 3620 #define ARIZONA_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */ 3621 #define ARIZONA_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */ 3622 #define ARIZONA_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */ 3623 #define ARIZONA_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */ 3624 #define ARIZONA_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */ 3625 3626 /* 3627 * R1283 (0x503) - AIF1 Rate Ctrl 3628 */ 3629 #define ARIZONA_AIF1_RATE_MASK 0x7800 /* AIF1_RATE - [14:11] */ 3630 #define ARIZONA_AIF1_RATE_SHIFT 11 /* AIF1_RATE - [14:11] */ 3631 #define ARIZONA_AIF1_RATE_WIDTH 4 /* AIF1_RATE - [14:11] */ 3632 #define ARIZONA_AIF1_TRI 0x0040 /* AIF1_TRI */ 3633 #define ARIZONA_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */ 3634 #define ARIZONA_AIF1_TRI_SHIFT 6 /* AIF1_TRI */ 3635 #define ARIZONA_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 3636 3637 /* 3638 * R1284 (0x504) - AIF1 Format 3639 */ 3640 #define ARIZONA_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */ 3641 #define ARIZONA_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */ 3642 #define ARIZONA_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */ 3643 3644 /* 3645 * R1285 (0x505) - AIF1 Tx BCLK Rate 3646 */ 3647 #define ARIZONA_AIF1TX_BCPF_MASK 0x1FFF /* AIF1TX_BCPF - [12:0] */ 3648 #define ARIZONA_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [12:0] */ 3649 #define ARIZONA_AIF1TX_BCPF_WIDTH 13 /* AIF1TX_BCPF - [12:0] */ 3650 3651 /* 3652 * R1286 (0x506) - AIF1 Rx BCLK Rate 3653 */ 3654 #define ARIZONA_AIF1RX_BCPF_MASK 0x1FFF /* AIF1RX_BCPF - [12:0] */ 3655 #define ARIZONA_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [12:0] */ 3656 #define ARIZONA_AIF1RX_BCPF_WIDTH 13 /* AIF1RX_BCPF - [12:0] */ 3657 3658 /* 3659 * R1287 (0x507) - AIF1 Frame Ctrl 1 3660 */ 3661 #define ARIZONA_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */ 3662 #define ARIZONA_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */ 3663 #define ARIZONA_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */ 3664 #define ARIZONA_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */ 3665 #define ARIZONA_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */ 3666 #define ARIZONA_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */ 3667 3668 /* 3669 * R1288 (0x508) - AIF1 Frame Ctrl 2 3670 */ 3671 #define ARIZONA_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */ 3672 #define ARIZONA_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */ 3673 #define ARIZONA_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */ 3674 #define ARIZONA_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */ 3675 #define ARIZONA_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */ 3676 #define ARIZONA_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */ 3677 3678 /* 3679 * R1289 (0x509) - AIF1 Frame Ctrl 3 3680 */ 3681 #define ARIZONA_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */ 3682 #define ARIZONA_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */ 3683 #define ARIZONA_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */ 3684 3685 /* 3686 * R1290 (0x50A) - AIF1 Frame Ctrl 4 3687 */ 3688 #define ARIZONA_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */ 3689 #define ARIZONA_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */ 3690 #define ARIZONA_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */ 3691 3692 /* 3693 * R1291 (0x50B) - AIF1 Frame Ctrl 5 3694 */ 3695 #define ARIZONA_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */ 3696 #define ARIZONA_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */ 3697 #define ARIZONA_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */ 3698 3699 /* 3700 * R1292 (0x50C) - AIF1 Frame Ctrl 6 3701 */ 3702 #define ARIZONA_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */ 3703 #define ARIZONA_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */ 3704 #define ARIZONA_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */ 3705 3706 /* 3707 * R1293 (0x50D) - AIF1 Frame Ctrl 7 3708 */ 3709 #define ARIZONA_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */ 3710 #define ARIZONA_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */ 3711 #define ARIZONA_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */ 3712 3713 /* 3714 * R1294 (0x50E) - AIF1 Frame Ctrl 8 3715 */ 3716 #define ARIZONA_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */ 3717 #define ARIZONA_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */ 3718 #define ARIZONA_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */ 3719 3720 /* 3721 * R1295 (0x50F) - AIF1 Frame Ctrl 9 3722 */ 3723 #define ARIZONA_AIF1TX7_SLOT_MASK 0x003F /* AIF1TX7_SLOT - [5:0] */ 3724 #define ARIZONA_AIF1TX7_SLOT_SHIFT 0 /* AIF1TX7_SLOT - [5:0] */ 3725 #define ARIZONA_AIF1TX7_SLOT_WIDTH 6 /* AIF1TX7_SLOT - [5:0] */ 3726 3727 /* 3728 * R1296 (0x510) - AIF1 Frame Ctrl 10 3729 */ 3730 #define ARIZONA_AIF1TX8_SLOT_MASK 0x003F /* AIF1TX8_SLOT - [5:0] */ 3731 #define ARIZONA_AIF1TX8_SLOT_SHIFT 0 /* AIF1TX8_SLOT - [5:0] */ 3732 #define ARIZONA_AIF1TX8_SLOT_WIDTH 6 /* AIF1TX8_SLOT - [5:0] */ 3733 3734 /* 3735 * R1297 (0x511) - AIF1 Frame Ctrl 11 3736 */ 3737 #define ARIZONA_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */ 3738 #define ARIZONA_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */ 3739 #define ARIZONA_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */ 3740 3741 /* 3742 * R1298 (0x512) - AIF1 Frame Ctrl 12 3743 */ 3744 #define ARIZONA_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */ 3745 #define ARIZONA_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */ 3746 #define ARIZONA_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */ 3747 3748 /* 3749 * R1299 (0x513) - AIF1 Frame Ctrl 13 3750 */ 3751 #define ARIZONA_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */ 3752 #define ARIZONA_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */ 3753 #define ARIZONA_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */ 3754 3755 /* 3756 * R1300 (0x514) - AIF1 Frame Ctrl 14 3757 */ 3758 #define ARIZONA_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */ 3759 #define ARIZONA_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */ 3760 #define ARIZONA_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */ 3761 3762 /* 3763 * R1301 (0x515) - AIF1 Frame Ctrl 15 3764 */ 3765 #define ARIZONA_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */ 3766 #define ARIZONA_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */ 3767 #define ARIZONA_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */ 3768 3769 /* 3770 * R1302 (0x516) - AIF1 Frame Ctrl 16 3771 */ 3772 #define ARIZONA_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */ 3773 #define ARIZONA_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */ 3774 #define ARIZONA_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */ 3775 3776 /* 3777 * R1303 (0x517) - AIF1 Frame Ctrl 17 3778 */ 3779 #define ARIZONA_AIF1RX7_SLOT_MASK 0x003F /* AIF1RX7_SLOT - [5:0] */ 3780 #define ARIZONA_AIF1RX7_SLOT_SHIFT 0 /* AIF1RX7_SLOT - [5:0] */ 3781 #define ARIZONA_AIF1RX7_SLOT_WIDTH 6 /* AIF1RX7_SLOT - [5:0] */ 3782 3783 /* 3784 * R1304 (0x518) - AIF1 Frame Ctrl 18 3785 */ 3786 #define ARIZONA_AIF1RX8_SLOT_MASK 0x003F /* AIF1RX8_SLOT - [5:0] */ 3787 #define ARIZONA_AIF1RX8_SLOT_SHIFT 0 /* AIF1RX8_SLOT - [5:0] */ 3788 #define ARIZONA_AIF1RX8_SLOT_WIDTH 6 /* AIF1RX8_SLOT - [5:0] */ 3789 3790 /* 3791 * R1305 (0x519) - AIF1 Tx Enables 3792 */ 3793 #define ARIZONA_AIF1TX8_ENA 0x0080 /* AIF1TX8_ENA */ 3794 #define ARIZONA_AIF1TX8_ENA_MASK 0x0080 /* AIF1TX8_ENA */ 3795 #define ARIZONA_AIF1TX8_ENA_SHIFT 7 /* AIF1TX8_ENA */ 3796 #define ARIZONA_AIF1TX8_ENA_WIDTH 1 /* AIF1TX8_ENA */ 3797 #define ARIZONA_AIF1TX7_ENA 0x0040 /* AIF1TX7_ENA */ 3798 #define ARIZONA_AIF1TX7_ENA_MASK 0x0040 /* AIF1TX7_ENA */ 3799 #define ARIZONA_AIF1TX7_ENA_SHIFT 6 /* AIF1TX7_ENA */ 3800 #define ARIZONA_AIF1TX7_ENA_WIDTH 1 /* AIF1TX7_ENA */ 3801 #define ARIZONA_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */ 3802 #define ARIZONA_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */ 3803 #define ARIZONA_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */ 3804 #define ARIZONA_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */ 3805 #define ARIZONA_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */ 3806 #define ARIZONA_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */ 3807 #define ARIZONA_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */ 3808 #define ARIZONA_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */ 3809 #define ARIZONA_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */ 3810 #define ARIZONA_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */ 3811 #define ARIZONA_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */ 3812 #define ARIZONA_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */ 3813 #define ARIZONA_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */ 3814 #define ARIZONA_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */ 3815 #define ARIZONA_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */ 3816 #define ARIZONA_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */ 3817 #define ARIZONA_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */ 3818 #define ARIZONA_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */ 3819 #define ARIZONA_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */ 3820 #define ARIZONA_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */ 3821 #define ARIZONA_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */ 3822 #define ARIZONA_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */ 3823 #define ARIZONA_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */ 3824 #define ARIZONA_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */ 3825 3826 /* 3827 * R1306 (0x51A) - AIF1 Rx Enables 3828 */ 3829 #define ARIZONA_AIF1RX8_ENA 0x0080 /* AIF1RX8_ENA */ 3830 #define ARIZONA_AIF1RX8_ENA_MASK 0x0080 /* AIF1RX8_ENA */ 3831 #define ARIZONA_AIF1RX8_ENA_SHIFT 7 /* AIF1RX8_ENA */ 3832 #define ARIZONA_AIF1RX8_ENA_WIDTH 1 /* AIF1RX8_ENA */ 3833 #define ARIZONA_AIF1RX7_ENA 0x0040 /* AIF1RX7_ENA */ 3834 #define ARIZONA_AIF1RX7_ENA_MASK 0x0040 /* AIF1RX7_ENA */ 3835 #define ARIZONA_AIF1RX7_ENA_SHIFT 6 /* AIF1RX7_ENA */ 3836 #define ARIZONA_AIF1RX7_ENA_WIDTH 1 /* AIF1RX7_ENA */ 3837 #define ARIZONA_AIF1RX6_ENA 0x0020 /* AIF1RX6_ENA */ 3838 #define ARIZONA_AIF1RX6_ENA_MASK 0x0020 /* AIF1RX6_ENA */ 3839 #define ARIZONA_AIF1RX6_ENA_SHIFT 5 /* AIF1RX6_ENA */ 3840 #define ARIZONA_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */ 3841 #define ARIZONA_AIF1RX5_ENA 0x0010 /* AIF1RX5_ENA */ 3842 #define ARIZONA_AIF1RX5_ENA_MASK 0x0010 /* AIF1RX5_ENA */ 3843 #define ARIZONA_AIF1RX5_ENA_SHIFT 4 /* AIF1RX5_ENA */ 3844 #define ARIZONA_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */ 3845 #define ARIZONA_AIF1RX4_ENA 0x0008 /* AIF1RX4_ENA */ 3846 #define ARIZONA_AIF1RX4_ENA_MASK 0x0008 /* AIF1RX4_ENA */ 3847 #define ARIZONA_AIF1RX4_ENA_SHIFT 3 /* AIF1RX4_ENA */ 3848 #define ARIZONA_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */ 3849 #define ARIZONA_AIF1RX3_ENA 0x0004 /* AIF1RX3_ENA */ 3850 #define ARIZONA_AIF1RX3_ENA_MASK 0x0004 /* AIF1RX3_ENA */ 3851 #define ARIZONA_AIF1RX3_ENA_SHIFT 2 /* AIF1RX3_ENA */ 3852 #define ARIZONA_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */ 3853 #define ARIZONA_AIF1RX2_ENA 0x0002 /* AIF1RX2_ENA */ 3854 #define ARIZONA_AIF1RX2_ENA_MASK 0x0002 /* AIF1RX2_ENA */ 3855 #define ARIZONA_AIF1RX2_ENA_SHIFT 1 /* AIF1RX2_ENA */ 3856 #define ARIZONA_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */ 3857 #define ARIZONA_AIF1RX1_ENA 0x0001 /* AIF1RX1_ENA */ 3858 #define ARIZONA_AIF1RX1_ENA_MASK 0x0001 /* AIF1RX1_ENA */ 3859 #define ARIZONA_AIF1RX1_ENA_SHIFT 0 /* AIF1RX1_ENA */ 3860 #define ARIZONA_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */ 3861 3862 /* 3863 * R1307 (0x51B) - AIF1 Force Write 3864 */ 3865 #define ARIZONA_AIF1_FRC_WR 0x0001 /* AIF1_FRC_WR */ 3866 #define ARIZONA_AIF1_FRC_WR_MASK 0x0001 /* AIF1_FRC_WR */ 3867 #define ARIZONA_AIF1_FRC_WR_SHIFT 0 /* AIF1_FRC_WR */ 3868 #define ARIZONA_AIF1_FRC_WR_WIDTH 1 /* AIF1_FRC_WR */ 3869 3870 /* 3871 * R1344 (0x540) - AIF2 BCLK Ctrl 3872 */ 3873 #define ARIZONA_AIF2_BCLK_INV 0x0080 /* AIF2_BCLK_INV */ 3874 #define ARIZONA_AIF2_BCLK_INV_MASK 0x0080 /* AIF2_BCLK_INV */ 3875 #define ARIZONA_AIF2_BCLK_INV_SHIFT 7 /* AIF2_BCLK_INV */ 3876 #define ARIZONA_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ 3877 #define ARIZONA_AIF2_BCLK_FRC 0x0040 /* AIF2_BCLK_FRC */ 3878 #define ARIZONA_AIF2_BCLK_FRC_MASK 0x0040 /* AIF2_BCLK_FRC */ 3879 #define ARIZONA_AIF2_BCLK_FRC_SHIFT 6 /* AIF2_BCLK_FRC */ 3880 #define ARIZONA_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */ 3881 #define ARIZONA_AIF2_BCLK_MSTR 0x0020 /* AIF2_BCLK_MSTR */ 3882 #define ARIZONA_AIF2_BCLK_MSTR_MASK 0x0020 /* AIF2_BCLK_MSTR */ 3883 #define ARIZONA_AIF2_BCLK_MSTR_SHIFT 5 /* AIF2_BCLK_MSTR */ 3884 #define ARIZONA_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */ 3885 #define ARIZONA_AIF2_BCLK_FREQ_MASK 0x001F /* AIF2_BCLK_FREQ - [4:0] */ 3886 #define ARIZONA_AIF2_BCLK_FREQ_SHIFT 0 /* AIF2_BCLK_FREQ - [4:0] */ 3887 #define ARIZONA_AIF2_BCLK_FREQ_WIDTH 5 /* AIF2_BCLK_FREQ - [4:0] */ 3888 3889 /* 3890 * R1345 (0x541) - AIF2 Tx Pin Ctrl 3891 */ 3892 #define ARIZONA_AIF2TX_DAT_TRI 0x0020 /* AIF2TX_DAT_TRI */ 3893 #define ARIZONA_AIF2TX_DAT_TRI_MASK 0x0020 /* AIF2TX_DAT_TRI */ 3894 #define ARIZONA_AIF2TX_DAT_TRI_SHIFT 5 /* AIF2TX_DAT_TRI */ 3895 #define ARIZONA_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */ 3896 #define ARIZONA_AIF2TX_LRCLK_SRC 0x0008 /* AIF2TX_LRCLK_SRC */ 3897 #define ARIZONA_AIF2TX_LRCLK_SRC_MASK 0x0008 /* AIF2TX_LRCLK_SRC */ 3898 #define ARIZONA_AIF2TX_LRCLK_SRC_SHIFT 3 /* AIF2TX_LRCLK_SRC */ 3899 #define ARIZONA_AIF2TX_LRCLK_SRC_WIDTH 1 /* AIF2TX_LRCLK_SRC */ 3900 #define ARIZONA_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */ 3901 #define ARIZONA_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */ 3902 #define ARIZONA_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */ 3903 #define ARIZONA_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */ 3904 #define ARIZONA_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */ 3905 #define ARIZONA_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */ 3906 #define ARIZONA_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */ 3907 #define ARIZONA_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */ 3908 #define ARIZONA_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */ 3909 #define ARIZONA_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */ 3910 #define ARIZONA_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */ 3911 #define ARIZONA_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */ 3912 3913 /* 3914 * R1346 (0x542) - AIF2 Rx Pin Ctrl 3915 */ 3916 #define ARIZONA_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */ 3917 #define ARIZONA_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */ 3918 #define ARIZONA_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */ 3919 #define ARIZONA_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */ 3920 #define ARIZONA_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */ 3921 #define ARIZONA_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */ 3922 #define ARIZONA_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */ 3923 #define ARIZONA_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */ 3924 #define ARIZONA_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */ 3925 #define ARIZONA_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */ 3926 #define ARIZONA_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */ 3927 #define ARIZONA_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */ 3928 3929 /* 3930 * R1347 (0x543) - AIF2 Rate Ctrl 3931 */ 3932 #define ARIZONA_AIF2_RATE_MASK 0x7800 /* AIF2_RATE - [14:11] */ 3933 #define ARIZONA_AIF2_RATE_SHIFT 11 /* AIF2_RATE - [14:11] */ 3934 #define ARIZONA_AIF2_RATE_WIDTH 4 /* AIF2_RATE - [14:11] */ 3935 #define ARIZONA_AIF2_TRI 0x0040 /* AIF2_TRI */ 3936 #define ARIZONA_AIF2_TRI_MASK 0x0040 /* AIF2_TRI */ 3937 #define ARIZONA_AIF2_TRI_SHIFT 6 /* AIF2_TRI */ 3938 #define ARIZONA_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ 3939 3940 /* 3941 * R1348 (0x544) - AIF2 Format 3942 */ 3943 #define ARIZONA_AIF2_FMT_MASK 0x0007 /* AIF2_FMT - [2:0] */ 3944 #define ARIZONA_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [2:0] */ 3945 #define ARIZONA_AIF2_FMT_WIDTH 3 /* AIF2_FMT - [2:0] */ 3946 3947 /* 3948 * R1349 (0x545) - AIF2 Tx BCLK Rate 3949 */ 3950 #define ARIZONA_AIF2TX_BCPF_MASK 0x1FFF /* AIF2TX_BCPF - [12:0] */ 3951 #define ARIZONA_AIF2TX_BCPF_SHIFT 0 /* AIF2TX_BCPF - [12:0] */ 3952 #define ARIZONA_AIF2TX_BCPF_WIDTH 13 /* AIF2TX_BCPF - [12:0] */ 3953 3954 /* 3955 * R1350 (0x546) - AIF2 Rx BCLK Rate 3956 */ 3957 #define ARIZONA_AIF2RX_BCPF_MASK 0x1FFF /* AIF2RX_BCPF - [12:0] */ 3958 #define ARIZONA_AIF2RX_BCPF_SHIFT 0 /* AIF2RX_BCPF - [12:0] */ 3959 #define ARIZONA_AIF2RX_BCPF_WIDTH 13 /* AIF2RX_BCPF - [12:0] */ 3960 3961 /* 3962 * R1351 (0x547) - AIF2 Frame Ctrl 1 3963 */ 3964 #define ARIZONA_AIF2TX_WL_MASK 0x3F00 /* AIF2TX_WL - [13:8] */ 3965 #define ARIZONA_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [13:8] */ 3966 #define ARIZONA_AIF2TX_WL_WIDTH 6 /* AIF2TX_WL - [13:8] */ 3967 #define ARIZONA_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */ 3968 #define ARIZONA_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */ 3969 #define ARIZONA_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */ 3970 3971 /* 3972 * R1352 (0x548) - AIF2 Frame Ctrl 2 3973 */ 3974 #define ARIZONA_AIF2RX_WL_MASK 0x3F00 /* AIF2RX_WL - [13:8] */ 3975 #define ARIZONA_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [13:8] */ 3976 #define ARIZONA_AIF2RX_WL_WIDTH 6 /* AIF2RX_WL - [13:8] */ 3977 #define ARIZONA_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */ 3978 #define ARIZONA_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */ 3979 #define ARIZONA_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */ 3980 3981 /* 3982 * R1353 (0x549) - AIF2 Frame Ctrl 3 3983 */ 3984 #define ARIZONA_AIF2TX1_SLOT_MASK 0x003F /* AIF2TX1_SLOT - [5:0] */ 3985 #define ARIZONA_AIF2TX1_SLOT_SHIFT 0 /* AIF2TX1_SLOT - [5:0] */ 3986 #define ARIZONA_AIF2TX1_SLOT_WIDTH 6 /* AIF2TX1_SLOT - [5:0] */ 3987 3988 /* 3989 * R1354 (0x54A) - AIF2 Frame Ctrl 4 3990 */ 3991 #define ARIZONA_AIF2TX2_SLOT_MASK 0x003F /* AIF2TX2_SLOT - [5:0] */ 3992 #define ARIZONA_AIF2TX2_SLOT_SHIFT 0 /* AIF2TX2_SLOT - [5:0] */ 3993 #define ARIZONA_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */ 3994 3995 /* 3996 * R1355 (0x54B) - AIF2 Frame Ctrl 5 3997 */ 3998 #define ARIZONA_AIF2TX3_SLOT_MASK 0x003F /* AIF2TX3_SLOT - [5:0] */ 3999 #define ARIZONA_AIF2TX3_SLOT_SHIFT 0 /* AIF2TX3_SLOT - [5:0] */ 4000 #define ARIZONA_AIF2TX3_SLOT_WIDTH 6 /* AIF2TX3_SLOT - [5:0] */ 4001 4002 /* 4003 * R1356 (0x54C) - AIF2 Frame Ctrl 6 4004 */ 4005 #define ARIZONA_AIF2TX4_SLOT_MASK 0x003F /* AIF2TX4_SLOT - [5:0] */ 4006 #define ARIZONA_AIF2TX4_SLOT_SHIFT 0 /* AIF2TX4_SLOT - [5:0] */ 4007 #define ARIZONA_AIF2TX4_SLOT_WIDTH 6 /* AIF2TX4_SLOT - [5:0] */ 4008 4009 4010 /* 4011 * R1357 (0x54D) - AIF2 Frame Ctrl 7 4012 */ 4013 #define ARIZONA_AIF2TX5_SLOT_MASK 0x003F /* AIF2TX5_SLOT - [5:0] */ 4014 #define ARIZONA_AIF2TX5_SLOT_SHIFT 0 /* AIF2TX5_SLOT - [5:0] */ 4015 #define ARIZONA_AIF2TX5_SLOT_WIDTH 6 /* AIF2TX5_SLOT - [5:0] */ 4016 4017 /* 4018 * R1358 (0x54E) - AIF2 Frame Ctrl 8 4019 */ 4020 #define ARIZONA_AIF2TX6_SLOT_MASK 0x003F /* AIF2TX6_SLOT - [5:0] */ 4021 #define ARIZONA_AIF2TX6_SLOT_SHIFT 0 /* AIF2TX6_SLOT - [5:0] */ 4022 #define ARIZONA_AIF2TX6_SLOT_WIDTH 6 /* AIF2TX6_SLOT - [5:0] */ 4023 4024 /* 4025 * R1361 (0x551) - AIF2 Frame Ctrl 11 4026 */ 4027 #define ARIZONA_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */ 4028 #define ARIZONA_AIF2RX1_SLOT_SHIFT 0 /* AIF2RX1_SLOT - [5:0] */ 4029 #define ARIZONA_AIF2RX1_SLOT_WIDTH 6 /* AIF2RX1_SLOT - [5:0] */ 4030 4031 /* 4032 * R1362 (0x552) - AIF2 Frame Ctrl 12 4033 */ 4034 #define ARIZONA_AIF2RX2_SLOT_MASK 0x003F /* AIF2RX2_SLOT - [5:0] */ 4035 #define ARIZONA_AIF2RX2_SLOT_SHIFT 0 /* AIF2RX2_SLOT - [5:0] */ 4036 #define ARIZONA_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */ 4037 4038 /* 4039 * R1363 (0x553) - AIF2 Frame Ctrl 13 4040 */ 4041 #define ARIZONA_AIF2RX3_SLOT_MASK 0x003F /* AIF2RX3_SLOT - [5:0] */ 4042 #define ARIZONA_AIF2RX3_SLOT_SHIFT 0 /* AIF2RX3_SLOT - [5:0] */ 4043 #define ARIZONA_AIF2RX3_SLOT_WIDTH 6 /* AIF2RX3_SLOT - [5:0] */ 4044 4045 /* 4046 * R1364 (0x554) - AIF2 Frame Ctrl 14 4047 */ 4048 #define ARIZONA_AIF2RX4_SLOT_MASK 0x003F /* AIF2RX4_SLOT - [5:0] */ 4049 #define ARIZONA_AIF2RX4_SLOT_SHIFT 0 /* AIF2RX4_SLOT - [5:0] */ 4050 #define ARIZONA_AIF2RX4_SLOT_WIDTH 6 /* AIF2RX4_SLOT - [5:0] */ 4051 4052 /* 4053 * R1365 (0x555) - AIF2 Frame Ctrl 15 4054 */ 4055 #define ARIZONA_AIF2RX5_SLOT_MASK 0x003F /* AIF2RX5_SLOT - [5:0] */ 4056 #define ARIZONA_AIF2RX5_SLOT_SHIFT 0 /* AIF2RX5_SLOT - [5:0] */ 4057 #define ARIZONA_AIF2RX5_SLOT_WIDTH 6 /* AIF2RX5_SLOT - [5:0] */ 4058 4059 /* 4060 * R1366 (0x556) - AIF2 Frame Ctrl 16 4061 */ 4062 #define ARIZONA_AIF2RX6_SLOT_MASK 0x003F /* AIF2RX6_SLOT - [5:0] */ 4063 #define ARIZONA_AIF2RX6_SLOT_SHIFT 0 /* AIF2RX6_SLOT - [5:0] */ 4064 #define ARIZONA_AIF2RX6_SLOT_WIDTH 6 /* AIF2RX6_SLOT - [5:0] */ 4065 4066 /* 4067 * R1369 (0x559) - AIF2 Tx Enables 4068 */ 4069 #define ARIZONA_AIF2TX6_ENA 0x0020 /* AIF2TX6_ENA */ 4070 #define ARIZONA_AIF2TX6_ENA_MASK 0x0020 /* AIF2TX6_ENA */ 4071 #define ARIZONA_AIF2TX6_ENA_SHIFT 5 /* AIF2TX6_ENA */ 4072 #define ARIZONA_AIF2TX6_ENA_WIDTH 1 /* AIF2TX6_ENA */ 4073 #define ARIZONA_AIF2TX5_ENA 0x0010 /* AIF2TX5_ENA */ 4074 #define ARIZONA_AIF2TX5_ENA_MASK 0x0010 /* AIF2TX5_ENA */ 4075 #define ARIZONA_AIF2TX5_ENA_SHIFT 4 /* AIF2TX5_ENA */ 4076 #define ARIZONA_AIF2TX5_ENA_WIDTH 1 /* AIF2TX5_ENA */ 4077 #define ARIZONA_AIF2TX4_ENA 0x0008 /* AIF2TX4_ENA */ 4078 #define ARIZONA_AIF2TX4_ENA_MASK 0x0008 /* AIF2TX4_ENA */ 4079 #define ARIZONA_AIF2TX4_ENA_SHIFT 3 /* AIF2TX4_ENA */ 4080 #define ARIZONA_AIF2TX4_ENA_WIDTH 1 /* AIF2TX4_ENA */ 4081 #define ARIZONA_AIF2TX3_ENA 0x0004 /* AIF2TX3_ENA */ 4082 #define ARIZONA_AIF2TX3_ENA_MASK 0x0004 /* AIF2TX3_ENA */ 4083 #define ARIZONA_AIF2TX3_ENA_SHIFT 2 /* AIF2TX3_ENA */ 4084 #define ARIZONA_AIF2TX3_ENA_WIDTH 1 /* AIF2TX3_ENA */ 4085 #define ARIZONA_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */ 4086 #define ARIZONA_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */ 4087 #define ARIZONA_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */ 4088 #define ARIZONA_AIF2TX2_ENA_WIDTH 1 /* AIF2TX2_ENA */ 4089 #define ARIZONA_AIF2TX1_ENA 0x0001 /* AIF2TX1_ENA */ 4090 #define ARIZONA_AIF2TX1_ENA_MASK 0x0001 /* AIF2TX1_ENA */ 4091 #define ARIZONA_AIF2TX1_ENA_SHIFT 0 /* AIF2TX1_ENA */ 4092 #define ARIZONA_AIF2TX1_ENA_WIDTH 1 /* AIF2TX1_ENA */ 4093 4094 /* 4095 * R1370 (0x55A) - AIF2 Rx Enables 4096 */ 4097 #define ARIZONA_AIF2RX6_ENA 0x0020 /* AIF2RX6_ENA */ 4098 #define ARIZONA_AIF2RX6_ENA_MASK 0x0020 /* AIF2RX6_ENA */ 4099 #define ARIZONA_AIF2RX6_ENA_SHIFT 5 /* AIF2RX6_ENA */ 4100 #define ARIZONA_AIF2RX6_ENA_WIDTH 1 /* AIF2RX6_ENA */ 4101 #define ARIZONA_AIF2RX5_ENA 0x0010 /* AIF2RX5_ENA */ 4102 #define ARIZONA_AIF2RX5_ENA_MASK 0x0010 /* AIF2RX5_ENA */ 4103 #define ARIZONA_AIF2RX5_ENA_SHIFT 4 /* AIF2RX5_ENA */ 4104 #define ARIZONA_AIF2RX5_ENA_WIDTH 1 /* AIF2RX5_ENA */ 4105 #define ARIZONA_AIF2RX4_ENA 0x0008 /* AIF2RX4_ENA */ 4106 #define ARIZONA_AIF2RX4_ENA_MASK 0x0008 /* AIF2RX4_ENA */ 4107 #define ARIZONA_AIF2RX4_ENA_SHIFT 3 /* AIF2RX4_ENA */ 4108 #define ARIZONA_AIF2RX4_ENA_WIDTH 1 /* AIF2RX4_ENA */ 4109 #define ARIZONA_AIF2RX3_ENA 0x0004 /* AIF2RX3_ENA */ 4110 #define ARIZONA_AIF2RX3_ENA_MASK 0x0004 /* AIF2RX3_ENA */ 4111 #define ARIZONA_AIF2RX3_ENA_SHIFT 2 /* AIF2RX3_ENA */ 4112 #define ARIZONA_AIF2RX3_ENA_WIDTH 1 /* AIF2RX3_ENA */ 4113 #define ARIZONA_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */ 4114 #define ARIZONA_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */ 4115 #define ARIZONA_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */ 4116 #define ARIZONA_AIF2RX2_ENA_WIDTH 1 /* AIF2RX2_ENA */ 4117 #define ARIZONA_AIF2RX1_ENA 0x0001 /* AIF2RX1_ENA */ 4118 #define ARIZONA_AIF2RX1_ENA_MASK 0x0001 /* AIF2RX1_ENA */ 4119 #define ARIZONA_AIF2RX1_ENA_SHIFT 0 /* AIF2RX1_ENA */ 4120 #define ARIZONA_AIF2RX1_ENA_WIDTH 1 /* AIF2RX1_ENA */ 4121 4122 /* 4123 * R1371 (0x55B) - AIF2 Force Write 4124 */ 4125 #define ARIZONA_AIF2_FRC_WR 0x0001 /* AIF2_FRC_WR */ 4126 #define ARIZONA_AIF2_FRC_WR_MASK 0x0001 /* AIF2_FRC_WR */ 4127 #define ARIZONA_AIF2_FRC_WR_SHIFT 0 /* AIF2_FRC_WR */ 4128 #define ARIZONA_AIF2_FRC_WR_WIDTH 1 /* AIF2_FRC_WR */ 4129 4130 /* 4131 * R1408 (0x580) - AIF3 BCLK Ctrl 4132 */ 4133 #define ARIZONA_AIF3_BCLK_INV 0x0080 /* AIF3_BCLK_INV */ 4134 #define ARIZONA_AIF3_BCLK_INV_MASK 0x0080 /* AIF3_BCLK_INV */ 4135 #define ARIZONA_AIF3_BCLK_INV_SHIFT 7 /* AIF3_BCLK_INV */ 4136 #define ARIZONA_AIF3_BCLK_INV_WIDTH 1 /* AIF3_BCLK_INV */ 4137 #define ARIZONA_AIF3_BCLK_FRC 0x0040 /* AIF3_BCLK_FRC */ 4138 #define ARIZONA_AIF3_BCLK_FRC_MASK 0x0040 /* AIF3_BCLK_FRC */ 4139 #define ARIZONA_AIF3_BCLK_FRC_SHIFT 6 /* AIF3_BCLK_FRC */ 4140 #define ARIZONA_AIF3_BCLK_FRC_WIDTH 1 /* AIF3_BCLK_FRC */ 4141 #define ARIZONA_AIF3_BCLK_MSTR 0x0020 /* AIF3_BCLK_MSTR */ 4142 #define ARIZONA_AIF3_BCLK_MSTR_MASK 0x0020 /* AIF3_BCLK_MSTR */ 4143 #define ARIZONA_AIF3_BCLK_MSTR_SHIFT 5 /* AIF3_BCLK_MSTR */ 4144 #define ARIZONA_AIF3_BCLK_MSTR_WIDTH 1 /* AIF3_BCLK_MSTR */ 4145 #define ARIZONA_AIF3_BCLK_FREQ_MASK 0x001F /* AIF3_BCLK_FREQ - [4:0] */ 4146 #define ARIZONA_AIF3_BCLK_FREQ_SHIFT 0 /* AIF3_BCLK_FREQ - [4:0] */ 4147 #define ARIZONA_AIF3_BCLK_FREQ_WIDTH 5 /* AIF3_BCLK_FREQ - [4:0] */ 4148 4149 /* 4150 * R1409 (0x581) - AIF3 Tx Pin Ctrl 4151 */ 4152 #define ARIZONA_AIF3TX_DAT_TRI 0x0020 /* AIF3TX_DAT_TRI */ 4153 #define ARIZONA_AIF3TX_DAT_TRI_MASK 0x0020 /* AIF3TX_DAT_TRI */ 4154 #define ARIZONA_AIF3TX_DAT_TRI_SHIFT 5 /* AIF3TX_DAT_TRI */ 4155 #define ARIZONA_AIF3TX_DAT_TRI_WIDTH 1 /* AIF3TX_DAT_TRI */ 4156 #define ARIZONA_AIF3TX_LRCLK_SRC 0x0008 /* AIF3TX_LRCLK_SRC */ 4157 #define ARIZONA_AIF3TX_LRCLK_SRC_MASK 0x0008 /* AIF3TX_LRCLK_SRC */ 4158 #define ARIZONA_AIF3TX_LRCLK_SRC_SHIFT 3 /* AIF3TX_LRCLK_SRC */ 4159 #define ARIZONA_AIF3TX_LRCLK_SRC_WIDTH 1 /* AIF3TX_LRCLK_SRC */ 4160 #define ARIZONA_AIF3TX_LRCLK_INV 0x0004 /* AIF3TX_LRCLK_INV */ 4161 #define ARIZONA_AIF3TX_LRCLK_INV_MASK 0x0004 /* AIF3TX_LRCLK_INV */ 4162 #define ARIZONA_AIF3TX_LRCLK_INV_SHIFT 2 /* AIF3TX_LRCLK_INV */ 4163 #define ARIZONA_AIF3TX_LRCLK_INV_WIDTH 1 /* AIF3TX_LRCLK_INV */ 4164 #define ARIZONA_AIF3TX_LRCLK_FRC 0x0002 /* AIF3TX_LRCLK_FRC */ 4165 #define ARIZONA_AIF3TX_LRCLK_FRC_MASK 0x0002 /* AIF3TX_LRCLK_FRC */ 4166 #define ARIZONA_AIF3TX_LRCLK_FRC_SHIFT 1 /* AIF3TX_LRCLK_FRC */ 4167 #define ARIZONA_AIF3TX_LRCLK_FRC_WIDTH 1 /* AIF3TX_LRCLK_FRC */ 4168 #define ARIZONA_AIF3TX_LRCLK_MSTR 0x0001 /* AIF3TX_LRCLK_MSTR */ 4169 #define ARIZONA_AIF3TX_LRCLK_MSTR_MASK 0x0001 /* AIF3TX_LRCLK_MSTR */ 4170 #define ARIZONA_AIF3TX_LRCLK_MSTR_SHIFT 0 /* AIF3TX_LRCLK_MSTR */ 4171 #define ARIZONA_AIF3TX_LRCLK_MSTR_WIDTH 1 /* AIF3TX_LRCLK_MSTR */ 4172 4173 /* 4174 * R1410 (0x582) - AIF3 Rx Pin Ctrl 4175 */ 4176 #define ARIZONA_AIF3RX_LRCLK_INV 0x0004 /* AIF3RX_LRCLK_INV */ 4177 #define ARIZONA_AIF3RX_LRCLK_INV_MASK 0x0004 /* AIF3RX_LRCLK_INV */ 4178 #define ARIZONA_AIF3RX_LRCLK_INV_SHIFT 2 /* AIF3RX_LRCLK_INV */ 4179 #define ARIZONA_AIF3RX_LRCLK_INV_WIDTH 1 /* AIF3RX_LRCLK_INV */ 4180 #define ARIZONA_AIF3RX_LRCLK_FRC 0x0002 /* AIF3RX_LRCLK_FRC */ 4181 #define ARIZONA_AIF3RX_LRCLK_FRC_MASK 0x0002 /* AIF3RX_LRCLK_FRC */ 4182 #define ARIZONA_AIF3RX_LRCLK_FRC_SHIFT 1 /* AIF3RX_LRCLK_FRC */ 4183 #define ARIZONA_AIF3RX_LRCLK_FRC_WIDTH 1 /* AIF3RX_LRCLK_FRC */ 4184 #define ARIZONA_AIF3RX_LRCLK_MSTR 0x0001 /* AIF3RX_LRCLK_MSTR */ 4185 #define ARIZONA_AIF3RX_LRCLK_MSTR_MASK 0x0001 /* AIF3RX_LRCLK_MSTR */ 4186 #define ARIZONA_AIF3RX_LRCLK_MSTR_SHIFT 0 /* AIF3RX_LRCLK_MSTR */ 4187 #define ARIZONA_AIF3RX_LRCLK_MSTR_WIDTH 1 /* AIF3RX_LRCLK_MSTR */ 4188 4189 /* 4190 * R1411 (0x583) - AIF3 Rate Ctrl 4191 */ 4192 #define ARIZONA_AIF3_RATE_MASK 0x7800 /* AIF3_RATE - [14:11] */ 4193 #define ARIZONA_AIF3_RATE_SHIFT 11 /* AIF3_RATE - [14:11] */ 4194 #define ARIZONA_AIF3_RATE_WIDTH 4 /* AIF3_RATE - [14:11] */ 4195 #define ARIZONA_AIF3_TRI 0x0040 /* AIF3_TRI */ 4196 #define ARIZONA_AIF3_TRI_MASK 0x0040 /* AIF3_TRI */ 4197 #define ARIZONA_AIF3_TRI_SHIFT 6 /* AIF3_TRI */ 4198 #define ARIZONA_AIF3_TRI_WIDTH 1 /* AIF3_TRI */ 4199 4200 /* 4201 * R1412 (0x584) - AIF3 Format 4202 */ 4203 #define ARIZONA_AIF3_FMT_MASK 0x0007 /* AIF3_FMT - [2:0] */ 4204 #define ARIZONA_AIF3_FMT_SHIFT 0 /* AIF3_FMT - [2:0] */ 4205 #define ARIZONA_AIF3_FMT_WIDTH 3 /* AIF3_FMT - [2:0] */ 4206 4207 /* 4208 * R1413 (0x585) - AIF3 Tx BCLK Rate 4209 */ 4210 #define ARIZONA_AIF3TX_BCPF_MASK 0x1FFF /* AIF3TX_BCPF - [12:0] */ 4211 #define ARIZONA_AIF3TX_BCPF_SHIFT 0 /* AIF3TX_BCPF - [12:0] */ 4212 #define ARIZONA_AIF3TX_BCPF_WIDTH 13 /* AIF3TX_BCPF - [12:0] */ 4213 4214 /* 4215 * R1414 (0x586) - AIF3 Rx BCLK Rate 4216 */ 4217 #define ARIZONA_AIF3RX_BCPF_MASK 0x1FFF /* AIF3RX_BCPF - [12:0] */ 4218 #define ARIZONA_AIF3RX_BCPF_SHIFT 0 /* AIF3RX_BCPF - [12:0] */ 4219 #define ARIZONA_AIF3RX_BCPF_WIDTH 13 /* AIF3RX_BCPF - [12:0] */ 4220 4221 /* 4222 * R1415 (0x587) - AIF3 Frame Ctrl 1 4223 */ 4224 #define ARIZONA_AIF3TX_WL_MASK 0x3F00 /* AIF3TX_WL - [13:8] */ 4225 #define ARIZONA_AIF3TX_WL_SHIFT 8 /* AIF3TX_WL - [13:8] */ 4226 #define ARIZONA_AIF3TX_WL_WIDTH 6 /* AIF3TX_WL - [13:8] */ 4227 #define ARIZONA_AIF3TX_SLOT_LEN_MASK 0x00FF /* AIF3TX_SLOT_LEN - [7:0] */ 4228 #define ARIZONA_AIF3TX_SLOT_LEN_SHIFT 0 /* AIF3TX_SLOT_LEN - [7:0] */ 4229 #define ARIZONA_AIF3TX_SLOT_LEN_WIDTH 8 /* AIF3TX_SLOT_LEN - [7:0] */ 4230 4231 /* 4232 * R1416 (0x588) - AIF3 Frame Ctrl 2 4233 */ 4234 #define ARIZONA_AIF3RX_WL_MASK 0x3F00 /* AIF3RX_WL - [13:8] */ 4235 #define ARIZONA_AIF3RX_WL_SHIFT 8 /* AIF3RX_WL - [13:8] */ 4236 #define ARIZONA_AIF3RX_WL_WIDTH 6 /* AIF3RX_WL - [13:8] */ 4237 #define ARIZONA_AIF3RX_SLOT_LEN_MASK 0x00FF /* AIF3RX_SLOT_LEN - [7:0] */ 4238 #define ARIZONA_AIF3RX_SLOT_LEN_SHIFT 0 /* AIF3RX_SLOT_LEN - [7:0] */ 4239 #define ARIZONA_AIF3RX_SLOT_LEN_WIDTH 8 /* AIF3RX_SLOT_LEN - [7:0] */ 4240 4241 /* 4242 * R1417 (0x589) - AIF3 Frame Ctrl 3 4243 */ 4244 #define ARIZONA_AIF3TX1_SLOT_MASK 0x003F /* AIF3TX1_SLOT - [5:0] */ 4245 #define ARIZONA_AIF3TX1_SLOT_SHIFT 0 /* AIF3TX1_SLOT - [5:0] */ 4246 #define ARIZONA_AIF3TX1_SLOT_WIDTH 6 /* AIF3TX1_SLOT - [5:0] */ 4247 4248 /* 4249 * R1418 (0x58A) - AIF3 Frame Ctrl 4 4250 */ 4251 #define ARIZONA_AIF3TX2_SLOT_MASK 0x003F /* AIF3TX2_SLOT - [5:0] */ 4252 #define ARIZONA_AIF3TX2_SLOT_SHIFT 0 /* AIF3TX2_SLOT - [5:0] */ 4253 #define ARIZONA_AIF3TX2_SLOT_WIDTH 6 /* AIF3TX2_SLOT - [5:0] */ 4254 4255 /* 4256 * R1425 (0x591) - AIF3 Frame Ctrl 11 4257 */ 4258 #define ARIZONA_AIF3RX1_SLOT_MASK 0x003F /* AIF3RX1_SLOT - [5:0] */ 4259 #define ARIZONA_AIF3RX1_SLOT_SHIFT 0 /* AIF3RX1_SLOT - [5:0] */ 4260 #define ARIZONA_AIF3RX1_SLOT_WIDTH 6 /* AIF3RX1_SLOT - [5:0] */ 4261 4262 /* 4263 * R1426 (0x592) - AIF3 Frame Ctrl 12 4264 */ 4265 #define ARIZONA_AIF3RX2_SLOT_MASK 0x003F /* AIF3RX2_SLOT - [5:0] */ 4266 #define ARIZONA_AIF3RX2_SLOT_SHIFT 0 /* AIF3RX2_SLOT - [5:0] */ 4267 #define ARIZONA_AIF3RX2_SLOT_WIDTH 6 /* AIF3RX2_SLOT - [5:0] */ 4268 4269 /* 4270 * R1433 (0x599) - AIF3 Tx Enables 4271 */ 4272 #define ARIZONA_AIF3TX2_ENA 0x0002 /* AIF3TX2_ENA */ 4273 #define ARIZONA_AIF3TX2_ENA_MASK 0x0002 /* AIF3TX2_ENA */ 4274 #define ARIZONA_AIF3TX2_ENA_SHIFT 1 /* AIF3TX2_ENA */ 4275 #define ARIZONA_AIF3TX2_ENA_WIDTH 1 /* AIF3TX2_ENA */ 4276 #define ARIZONA_AIF3TX1_ENA 0x0001 /* AIF3TX1_ENA */ 4277 #define ARIZONA_AIF3TX1_ENA_MASK 0x0001 /* AIF3TX1_ENA */ 4278 #define ARIZONA_AIF3TX1_ENA_SHIFT 0 /* AIF3TX1_ENA */ 4279 #define ARIZONA_AIF3TX1_ENA_WIDTH 1 /* AIF3TX1_ENA */ 4280 4281 /* 4282 * R1434 (0x59A) - AIF3 Rx Enables 4283 */ 4284 #define ARIZONA_AIF3RX2_ENA 0x0002 /* AIF3RX2_ENA */ 4285 #define ARIZONA_AIF3RX2_ENA_MASK 0x0002 /* AIF3RX2_ENA */ 4286 #define ARIZONA_AIF3RX2_ENA_SHIFT 1 /* AIF3RX2_ENA */ 4287 #define ARIZONA_AIF3RX2_ENA_WIDTH 1 /* AIF3RX2_ENA */ 4288 #define ARIZONA_AIF3RX1_ENA 0x0001 /* AIF3RX1_ENA */ 4289 #define ARIZONA_AIF3RX1_ENA_MASK 0x0001 /* AIF3RX1_ENA */ 4290 #define ARIZONA_AIF3RX1_ENA_SHIFT 0 /* AIF3RX1_ENA */ 4291 #define ARIZONA_AIF3RX1_ENA_WIDTH 1 /* AIF3RX1_ENA */ 4292 4293 /* 4294 * R1435 (0x59B) - AIF3 Force Write 4295 */ 4296 #define ARIZONA_AIF3_FRC_WR 0x0001 /* AIF3_FRC_WR */ 4297 #define ARIZONA_AIF3_FRC_WR_MASK 0x0001 /* AIF3_FRC_WR */ 4298 #define ARIZONA_AIF3_FRC_WR_SHIFT 0 /* AIF3_FRC_WR */ 4299 #define ARIZONA_AIF3_FRC_WR_WIDTH 1 /* AIF3_FRC_WR */ 4300 4301 /* 4302 * R1507 (0x5E3) - SLIMbus Framer Ref Gear 4303 */ 4304 #define ARIZONA_SLIMCLK_SRC 0x0010 /* SLIMCLK_SRC */ 4305 #define ARIZONA_SLIMCLK_SRC_MASK 0x0010 /* SLIMCLK_SRC */ 4306 #define ARIZONA_SLIMCLK_SRC_SHIFT 4 /* SLIMCLK_SRC */ 4307 #define ARIZONA_SLIMCLK_SRC_WIDTH 1 /* SLIMCLK_SRC */ 4308 #define ARIZONA_FRAMER_REF_GEAR_MASK 0x000F /* FRAMER_REF_GEAR - [3:0] */ 4309 #define ARIZONA_FRAMER_REF_GEAR_SHIFT 0 /* FRAMER_REF_GEAR - [3:0] */ 4310 #define ARIZONA_FRAMER_REF_GEAR_WIDTH 4 /* FRAMER_REF_GEAR - [3:0] */ 4311 4312 /* 4313 * R1509 (0x5E5) - SLIMbus Rates 1 4314 */ 4315 #define ARIZONA_SLIMRX2_RATE_MASK 0x7800 /* SLIMRX2_RATE - [14:11] */ 4316 #define ARIZONA_SLIMRX2_RATE_SHIFT 11 /* SLIMRX2_RATE - [14:11] */ 4317 #define ARIZONA_SLIMRX2_RATE_WIDTH 4 /* SLIMRX2_RATE - [14:11] */ 4318 #define ARIZONA_SLIMRX1_RATE_MASK 0x0078 /* SLIMRX1_RATE - [6:3] */ 4319 #define ARIZONA_SLIMRX1_RATE_SHIFT 3 /* SLIMRX1_RATE - [6:3] */ 4320 #define ARIZONA_SLIMRX1_RATE_WIDTH 4 /* SLIMRX1_RATE - [6:3] */ 4321 4322 /* 4323 * R1510 (0x5E6) - SLIMbus Rates 2 4324 */ 4325 #define ARIZONA_SLIMRX4_RATE_MASK 0x7800 /* SLIMRX4_RATE - [14:11] */ 4326 #define ARIZONA_SLIMRX4_RATE_SHIFT 11 /* SLIMRX4_RATE - [14:11] */ 4327 #define ARIZONA_SLIMRX4_RATE_WIDTH 4 /* SLIMRX4_RATE - [14:11] */ 4328 #define ARIZONA_SLIMRX3_RATE_MASK 0x0078 /* SLIMRX3_RATE - [6:3] */ 4329 #define ARIZONA_SLIMRX3_RATE_SHIFT 3 /* SLIMRX3_RATE - [6:3] */ 4330 #define ARIZONA_SLIMRX3_RATE_WIDTH 4 /* SLIMRX3_RATE - [6:3] */ 4331 4332 /* 4333 * R1511 (0x5E7) - SLIMbus Rates 3 4334 */ 4335 #define ARIZONA_SLIMRX6_RATE_MASK 0x7800 /* SLIMRX6_RATE - [14:11] */ 4336 #define ARIZONA_SLIMRX6_RATE_SHIFT 11 /* SLIMRX6_RATE - [14:11] */ 4337 #define ARIZONA_SLIMRX6_RATE_WIDTH 4 /* SLIMRX6_RATE - [14:11] */ 4338 #define ARIZONA_SLIMRX5_RATE_MASK 0x0078 /* SLIMRX5_RATE - [6:3] */ 4339 #define ARIZONA_SLIMRX5_RATE_SHIFT 3 /* SLIMRX5_RATE - [6:3] */ 4340 #define ARIZONA_SLIMRX5_RATE_WIDTH 4 /* SLIMRX5_RATE - [6:3] */ 4341 4342 /* 4343 * R1512 (0x5E8) - SLIMbus Rates 4 4344 */ 4345 #define ARIZONA_SLIMRX8_RATE_MASK 0x7800 /* SLIMRX8_RATE - [14:11] */ 4346 #define ARIZONA_SLIMRX8_RATE_SHIFT 11 /* SLIMRX8_RATE - [14:11] */ 4347 #define ARIZONA_SLIMRX8_RATE_WIDTH 4 /* SLIMRX8_RATE - [14:11] */ 4348 #define ARIZONA_SLIMRX7_RATE_MASK 0x0078 /* SLIMRX7_RATE - [6:3] */ 4349 #define ARIZONA_SLIMRX7_RATE_SHIFT 3 /* SLIMRX7_RATE - [6:3] */ 4350 #define ARIZONA_SLIMRX7_RATE_WIDTH 4 /* SLIMRX7_RATE - [6:3] */ 4351 4352 /* 4353 * R1513 (0x5E9) - SLIMbus Rates 5 4354 */ 4355 #define ARIZONA_SLIMTX2_RATE_MASK 0x7800 /* SLIMTX2_RATE - [14:11] */ 4356 #define ARIZONA_SLIMTX2_RATE_SHIFT 11 /* SLIMTX2_RATE - [14:11] */ 4357 #define ARIZONA_SLIMTX2_RATE_WIDTH 4 /* SLIMTX2_RATE - [14:11] */ 4358 #define ARIZONA_SLIMTX1_RATE_MASK 0x0078 /* SLIMTX1_RATE - [6:3] */ 4359 #define ARIZONA_SLIMTX1_RATE_SHIFT 3 /* SLIMTX1_RATE - [6:3] */ 4360 #define ARIZONA_SLIMTX1_RATE_WIDTH 4 /* SLIMTX1_RATE - [6:3] */ 4361 4362 /* 4363 * R1514 (0x5EA) - SLIMbus Rates 6 4364 */ 4365 #define ARIZONA_SLIMTX4_RATE_MASK 0x7800 /* SLIMTX4_RATE - [14:11] */ 4366 #define ARIZONA_SLIMTX4_RATE_SHIFT 11 /* SLIMTX4_RATE - [14:11] */ 4367 #define ARIZONA_SLIMTX4_RATE_WIDTH 4 /* SLIMTX4_RATE - [14:11] */ 4368 #define ARIZONA_SLIMTX3_RATE_MASK 0x0078 /* SLIMTX3_RATE - [6:3] */ 4369 #define ARIZONA_SLIMTX3_RATE_SHIFT 3 /* SLIMTX3_RATE - [6:3] */ 4370 #define ARIZONA_SLIMTX3_RATE_WIDTH 4 /* SLIMTX3_RATE - [6:3] */ 4371 4372 /* 4373 * R1515 (0x5EB) - SLIMbus Rates 7 4374 */ 4375 #define ARIZONA_SLIMTX6_RATE_MASK 0x7800 /* SLIMTX6_RATE - [14:11] */ 4376 #define ARIZONA_SLIMTX6_RATE_SHIFT 11 /* SLIMTX6_RATE - [14:11] */ 4377 #define ARIZONA_SLIMTX6_RATE_WIDTH 4 /* SLIMTX6_RATE - [14:11] */ 4378 #define ARIZONA_SLIMTX5_RATE_MASK 0x0078 /* SLIMTX5_RATE - [6:3] */ 4379 #define ARIZONA_SLIMTX5_RATE_SHIFT 3 /* SLIMTX5_RATE - [6:3] */ 4380 #define ARIZONA_SLIMTX5_RATE_WIDTH 4 /* SLIMTX5_RATE - [6:3] */ 4381 4382 /* 4383 * R1516 (0x5EC) - SLIMbus Rates 8 4384 */ 4385 #define ARIZONA_SLIMTX8_RATE_MASK 0x7800 /* SLIMTX8_RATE - [14:11] */ 4386 #define ARIZONA_SLIMTX8_RATE_SHIFT 11 /* SLIMTX8_RATE - [14:11] */ 4387 #define ARIZONA_SLIMTX8_RATE_WIDTH 4 /* SLIMTX8_RATE - [14:11] */ 4388 #define ARIZONA_SLIMTX7_RATE_MASK 0x0078 /* SLIMTX7_RATE - [6:3] */ 4389 #define ARIZONA_SLIMTX7_RATE_SHIFT 3 /* SLIMTX7_RATE - [6:3] */ 4390 #define ARIZONA_SLIMTX7_RATE_WIDTH 4 /* SLIMTX7_RATE - [6:3] */ 4391 4392 /* 4393 * R1525 (0x5F5) - SLIMbus RX Channel Enable 4394 */ 4395 #define ARIZONA_SLIMRX8_ENA 0x0080 /* SLIMRX8_ENA */ 4396 #define ARIZONA_SLIMRX8_ENA_MASK 0x0080 /* SLIMRX8_ENA */ 4397 #define ARIZONA_SLIMRX8_ENA_SHIFT 7 /* SLIMRX8_ENA */ 4398 #define ARIZONA_SLIMRX8_ENA_WIDTH 1 /* SLIMRX8_ENA */ 4399 #define ARIZONA_SLIMRX7_ENA 0x0040 /* SLIMRX7_ENA */ 4400 #define ARIZONA_SLIMRX7_ENA_MASK 0x0040 /* SLIMRX7_ENA */ 4401 #define ARIZONA_SLIMRX7_ENA_SHIFT 6 /* SLIMRX7_ENA */ 4402 #define ARIZONA_SLIMRX7_ENA_WIDTH 1 /* SLIMRX7_ENA */ 4403 #define ARIZONA_SLIMRX6_ENA 0x0020 /* SLIMRX6_ENA */ 4404 #define ARIZONA_SLIMRX6_ENA_MASK 0x0020 /* SLIMRX6_ENA */ 4405 #define ARIZONA_SLIMRX6_ENA_SHIFT 5 /* SLIMRX6_ENA */ 4406 #define ARIZONA_SLIMRX6_ENA_WIDTH 1 /* SLIMRX6_ENA */ 4407 #define ARIZONA_SLIMRX5_ENA 0x0010 /* SLIMRX5_ENA */ 4408 #define ARIZONA_SLIMRX5_ENA_MASK 0x0010 /* SLIMRX5_ENA */ 4409 #define ARIZONA_SLIMRX5_ENA_SHIFT 4 /* SLIMRX5_ENA */ 4410 #define ARIZONA_SLIMRX5_ENA_WIDTH 1 /* SLIMRX5_ENA */ 4411 #define ARIZONA_SLIMRX4_ENA 0x0008 /* SLIMRX4_ENA */ 4412 #define ARIZONA_SLIMRX4_ENA_MASK 0x0008 /* SLIMRX4_ENA */ 4413 #define ARIZONA_SLIMRX4_ENA_SHIFT 3 /* SLIMRX4_ENA */ 4414 #define ARIZONA_SLIMRX4_ENA_WIDTH 1 /* SLIMRX4_ENA */ 4415 #define ARIZONA_SLIMRX3_ENA 0x0004 /* SLIMRX3_ENA */ 4416 #define ARIZONA_SLIMRX3_ENA_MASK 0x0004 /* SLIMRX3_ENA */ 4417 #define ARIZONA_SLIMRX3_ENA_SHIFT 2 /* SLIMRX3_ENA */ 4418 #define ARIZONA_SLIMRX3_ENA_WIDTH 1 /* SLIMRX3_ENA */ 4419 #define ARIZONA_SLIMRX2_ENA 0x0002 /* SLIMRX2_ENA */ 4420 #define ARIZONA_SLIMRX2_ENA_MASK 0x0002 /* SLIMRX2_ENA */ 4421 #define ARIZONA_SLIMRX2_ENA_SHIFT 1 /* SLIMRX2_ENA */ 4422 #define ARIZONA_SLIMRX2_ENA_WIDTH 1 /* SLIMRX2_ENA */ 4423 #define ARIZONA_SLIMRX1_ENA 0x0001 /* SLIMRX1_ENA */ 4424 #define ARIZONA_SLIMRX1_ENA_MASK 0x0001 /* SLIMRX1_ENA */ 4425 #define ARIZONA_SLIMRX1_ENA_SHIFT 0 /* SLIMRX1_ENA */ 4426 #define ARIZONA_SLIMRX1_ENA_WIDTH 1 /* SLIMRX1_ENA */ 4427 4428 /* 4429 * R1526 (0x5F6) - SLIMbus TX Channel Enable 4430 */ 4431 #define ARIZONA_SLIMTX8_ENA 0x0080 /* SLIMTX8_ENA */ 4432 #define ARIZONA_SLIMTX8_ENA_MASK 0x0080 /* SLIMTX8_ENA */ 4433 #define ARIZONA_SLIMTX8_ENA_SHIFT 7 /* SLIMTX8_ENA */ 4434 #define ARIZONA_SLIMTX8_ENA_WIDTH 1 /* SLIMTX8_ENA */ 4435 #define ARIZONA_SLIMTX7_ENA 0x0040 /* SLIMTX7_ENA */ 4436 #define ARIZONA_SLIMTX7_ENA_MASK 0x0040 /* SLIMTX7_ENA */ 4437 #define ARIZONA_SLIMTX7_ENA_SHIFT 6 /* SLIMTX7_ENA */ 4438 #define ARIZONA_SLIMTX7_ENA_WIDTH 1 /* SLIMTX7_ENA */ 4439 #define ARIZONA_SLIMTX6_ENA 0x0020 /* SLIMTX6_ENA */ 4440 #define ARIZONA_SLIMTX6_ENA_MASK 0x0020 /* SLIMTX6_ENA */ 4441 #define ARIZONA_SLIMTX6_ENA_SHIFT 5 /* SLIMTX6_ENA */ 4442 #define ARIZONA_SLIMTX6_ENA_WIDTH 1 /* SLIMTX6_ENA */ 4443 #define ARIZONA_SLIMTX5_ENA 0x0010 /* SLIMTX5_ENA */ 4444 #define ARIZONA_SLIMTX5_ENA_MASK 0x0010 /* SLIMTX5_ENA */ 4445 #define ARIZONA_SLIMTX5_ENA_SHIFT 4 /* SLIMTX5_ENA */ 4446 #define ARIZONA_SLIMTX5_ENA_WIDTH 1 /* SLIMTX5_ENA */ 4447 #define ARIZONA_SLIMTX4_ENA 0x0008 /* SLIMTX4_ENA */ 4448 #define ARIZONA_SLIMTX4_ENA_MASK 0x0008 /* SLIMTX4_ENA */ 4449 #define ARIZONA_SLIMTX4_ENA_SHIFT 3 /* SLIMTX4_ENA */ 4450 #define ARIZONA_SLIMTX4_ENA_WIDTH 1 /* SLIMTX4_ENA */ 4451 #define ARIZONA_SLIMTX3_ENA 0x0004 /* SLIMTX3_ENA */ 4452 #define ARIZONA_SLIMTX3_ENA_MASK 0x0004 /* SLIMTX3_ENA */ 4453 #define ARIZONA_SLIMTX3_ENA_SHIFT 2 /* SLIMTX3_ENA */ 4454 #define ARIZONA_SLIMTX3_ENA_WIDTH 1 /* SLIMTX3_ENA */ 4455 #define ARIZONA_SLIMTX2_ENA 0x0002 /* SLIMTX2_ENA */ 4456 #define ARIZONA_SLIMTX2_ENA_MASK 0x0002 /* SLIMTX2_ENA */ 4457 #define ARIZONA_SLIMTX2_ENA_SHIFT 1 /* SLIMTX2_ENA */ 4458 #define ARIZONA_SLIMTX2_ENA_WIDTH 1 /* SLIMTX2_ENA */ 4459 #define ARIZONA_SLIMTX1_ENA 0x0001 /* SLIMTX1_ENA */ 4460 #define ARIZONA_SLIMTX1_ENA_MASK 0x0001 /* SLIMTX1_ENA */ 4461 #define ARIZONA_SLIMTX1_ENA_SHIFT 0 /* SLIMTX1_ENA */ 4462 #define ARIZONA_SLIMTX1_ENA_WIDTH 1 /* SLIMTX1_ENA */ 4463 4464 /* 4465 * R1527 (0x5F7) - SLIMbus RX Port Status 4466 */ 4467 #define ARIZONA_SLIMRX8_PORT_STS 0x0080 /* SLIMRX8_PORT_STS */ 4468 #define ARIZONA_SLIMRX8_PORT_STS_MASK 0x0080 /* SLIMRX8_PORT_STS */ 4469 #define ARIZONA_SLIMRX8_PORT_STS_SHIFT 7 /* SLIMRX8_PORT_STS */ 4470 #define ARIZONA_SLIMRX8_PORT_STS_WIDTH 1 /* SLIMRX8_PORT_STS */ 4471 #define ARIZONA_SLIMRX7_PORT_STS 0x0040 /* SLIMRX7_PORT_STS */ 4472 #define ARIZONA_SLIMRX7_PORT_STS_MASK 0x0040 /* SLIMRX7_PORT_STS */ 4473 #define ARIZONA_SLIMRX7_PORT_STS_SHIFT 6 /* SLIMRX7_PORT_STS */ 4474 #define ARIZONA_SLIMRX7_PORT_STS_WIDTH 1 /* SLIMRX7_PORT_STS */ 4475 #define ARIZONA_SLIMRX6_PORT_STS 0x0020 /* SLIMRX6_PORT_STS */ 4476 #define ARIZONA_SLIMRX6_PORT_STS_MASK 0x0020 /* SLIMRX6_PORT_STS */ 4477 #define ARIZONA_SLIMRX6_PORT_STS_SHIFT 5 /* SLIMRX6_PORT_STS */ 4478 #define ARIZONA_SLIMRX6_PORT_STS_WIDTH 1 /* SLIMRX6_PORT_STS */ 4479 #define ARIZONA_SLIMRX5_PORT_STS 0x0010 /* SLIMRX5_PORT_STS */ 4480 #define ARIZONA_SLIMRX5_PORT_STS_MASK 0x0010 /* SLIMRX5_PORT_STS */ 4481 #define ARIZONA_SLIMRX5_PORT_STS_SHIFT 4 /* SLIMRX5_PORT_STS */ 4482 #define ARIZONA_SLIMRX5_PORT_STS_WIDTH 1 /* SLIMRX5_PORT_STS */ 4483 #define ARIZONA_SLIMRX4_PORT_STS 0x0008 /* SLIMRX4_PORT_STS */ 4484 #define ARIZONA_SLIMRX4_PORT_STS_MASK 0x0008 /* SLIMRX4_PORT_STS */ 4485 #define ARIZONA_SLIMRX4_PORT_STS_SHIFT 3 /* SLIMRX4_PORT_STS */ 4486 #define ARIZONA_SLIMRX4_PORT_STS_WIDTH 1 /* SLIMRX4_PORT_STS */ 4487 #define ARIZONA_SLIMRX3_PORT_STS 0x0004 /* SLIMRX3_PORT_STS */ 4488 #define ARIZONA_SLIMRX3_PORT_STS_MASK 0x0004 /* SLIMRX3_PORT_STS */ 4489 #define ARIZONA_SLIMRX3_PORT_STS_SHIFT 2 /* SLIMRX3_PORT_STS */ 4490 #define ARIZONA_SLIMRX3_PORT_STS_WIDTH 1 /* SLIMRX3_PORT_STS */ 4491 #define ARIZONA_SLIMRX2_PORT_STS 0x0002 /* SLIMRX2_PORT_STS */ 4492 #define ARIZONA_SLIMRX2_PORT_STS_MASK 0x0002 /* SLIMRX2_PORT_STS */ 4493 #define ARIZONA_SLIMRX2_PORT_STS_SHIFT 1 /* SLIMRX2_PORT_STS */ 4494 #define ARIZONA_SLIMRX2_PORT_STS_WIDTH 1 /* SLIMRX2_PORT_STS */ 4495 #define ARIZONA_SLIMRX1_PORT_STS 0x0001 /* SLIMRX1_PORT_STS */ 4496 #define ARIZONA_SLIMRX1_PORT_STS_MASK 0x0001 /* SLIMRX1_PORT_STS */ 4497 #define ARIZONA_SLIMRX1_PORT_STS_SHIFT 0 /* SLIMRX1_PORT_STS */ 4498 #define ARIZONA_SLIMRX1_PORT_STS_WIDTH 1 /* SLIMRX1_PORT_STS */ 4499 4500 /* 4501 * R1528 (0x5F8) - SLIMbus TX Port Status 4502 */ 4503 #define ARIZONA_SLIMTX8_PORT_STS 0x0080 /* SLIMTX8_PORT_STS */ 4504 #define ARIZONA_SLIMTX8_PORT_STS_MASK 0x0080 /* SLIMTX8_PORT_STS */ 4505 #define ARIZONA_SLIMTX8_PORT_STS_SHIFT 7 /* SLIMTX8_PORT_STS */ 4506 #define ARIZONA_SLIMTX8_PORT_STS_WIDTH 1 /* SLIMTX8_PORT_STS */ 4507 #define ARIZONA_SLIMTX7_PORT_STS 0x0040 /* SLIMTX7_PORT_STS */ 4508 #define ARIZONA_SLIMTX7_PORT_STS_MASK 0x0040 /* SLIMTX7_PORT_STS */ 4509 #define ARIZONA_SLIMTX7_PORT_STS_SHIFT 6 /* SLIMTX7_PORT_STS */ 4510 #define ARIZONA_SLIMTX7_PORT_STS_WIDTH 1 /* SLIMTX7_PORT_STS */ 4511 #define ARIZONA_SLIMTX6_PORT_STS 0x0020 /* SLIMTX6_PORT_STS */ 4512 #define ARIZONA_SLIMTX6_PORT_STS_MASK 0x0020 /* SLIMTX6_PORT_STS */ 4513 #define ARIZONA_SLIMTX6_PORT_STS_SHIFT 5 /* SLIMTX6_PORT_STS */ 4514 #define ARIZONA_SLIMTX6_PORT_STS_WIDTH 1 /* SLIMTX6_PORT_STS */ 4515 #define ARIZONA_SLIMTX5_PORT_STS 0x0010 /* SLIMTX5_PORT_STS */ 4516 #define ARIZONA_SLIMTX5_PORT_STS_MASK 0x0010 /* SLIMTX5_PORT_STS */ 4517 #define ARIZONA_SLIMTX5_PORT_STS_SHIFT 4 /* SLIMTX5_PORT_STS */ 4518 #define ARIZONA_SLIMTX5_PORT_STS_WIDTH 1 /* SLIMTX5_PORT_STS */ 4519 #define ARIZONA_SLIMTX4_PORT_STS 0x0008 /* SLIMTX4_PORT_STS */ 4520 #define ARIZONA_SLIMTX4_PORT_STS_MASK 0x0008 /* SLIMTX4_PORT_STS */ 4521 #define ARIZONA_SLIMTX4_PORT_STS_SHIFT 3 /* SLIMTX4_PORT_STS */ 4522 #define ARIZONA_SLIMTX4_PORT_STS_WIDTH 1 /* SLIMTX4_PORT_STS */ 4523 #define ARIZONA_SLIMTX3_PORT_STS 0x0004 /* SLIMTX3_PORT_STS */ 4524 #define ARIZONA_SLIMTX3_PORT_STS_MASK 0x0004 /* SLIMTX3_PORT_STS */ 4525 #define ARIZONA_SLIMTX3_PORT_STS_SHIFT 2 /* SLIMTX3_PORT_STS */ 4526 #define ARIZONA_SLIMTX3_PORT_STS_WIDTH 1 /* SLIMTX3_PORT_STS */ 4527 #define ARIZONA_SLIMTX2_PORT_STS 0x0002 /* SLIMTX2_PORT_STS */ 4528 #define ARIZONA_SLIMTX2_PORT_STS_MASK 0x0002 /* SLIMTX2_PORT_STS */ 4529 #define ARIZONA_SLIMTX2_PORT_STS_SHIFT 1 /* SLIMTX2_PORT_STS */ 4530 #define ARIZONA_SLIMTX2_PORT_STS_WIDTH 1 /* SLIMTX2_PORT_STS */ 4531 #define ARIZONA_SLIMTX1_PORT_STS 0x0001 /* SLIMTX1_PORT_STS */ 4532 #define ARIZONA_SLIMTX1_PORT_STS_MASK 0x0001 /* SLIMTX1_PORT_STS */ 4533 #define ARIZONA_SLIMTX1_PORT_STS_SHIFT 0 /* SLIMTX1_PORT_STS */ 4534 #define ARIZONA_SLIMTX1_PORT_STS_WIDTH 1 /* SLIMTX1_PORT_STS */ 4535 4536 /* 4537 * R3087 (0xC0F) - IRQ CTRL 1 4538 */ 4539 #define ARIZONA_IRQ_POL 0x0400 /* IRQ_POL */ 4540 #define ARIZONA_IRQ_POL_MASK 0x0400 /* IRQ_POL */ 4541 #define ARIZONA_IRQ_POL_SHIFT 10 /* IRQ_POL */ 4542 #define ARIZONA_IRQ_POL_WIDTH 1 /* IRQ_POL */ 4543 #define ARIZONA_IRQ_OP_CFG 0x0200 /* IRQ_OP_CFG */ 4544 #define ARIZONA_IRQ_OP_CFG_MASK 0x0200 /* IRQ_OP_CFG */ 4545 #define ARIZONA_IRQ_OP_CFG_SHIFT 9 /* IRQ_OP_CFG */ 4546 #define ARIZONA_IRQ_OP_CFG_WIDTH 1 /* IRQ_OP_CFG */ 4547 4548 /* 4549 * R3088 (0xC10) - GPIO Debounce Config 4550 */ 4551 #define ARIZONA_GP_DBTIME_MASK 0xF000 /* GP_DBTIME - [15:12] */ 4552 #define ARIZONA_GP_DBTIME_SHIFT 12 /* GP_DBTIME - [15:12] */ 4553 #define ARIZONA_GP_DBTIME_WIDTH 4 /* GP_DBTIME - [15:12] */ 4554 4555 /* 4556 * R3104 (0xC20) - Misc Pad Ctrl 1 4557 */ 4558 #define ARIZONA_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */ 4559 #define ARIZONA_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */ 4560 #define ARIZONA_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */ 4561 #define ARIZONA_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 4562 #define ARIZONA_MCLK2_PD 0x2000 /* MCLK2_PD */ 4563 #define ARIZONA_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */ 4564 #define ARIZONA_MCLK2_PD_SHIFT 13 /* MCLK2_PD */ 4565 #define ARIZONA_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ 4566 #define ARIZONA_RSTB_PU 0x0002 /* RSTB_PU */ 4567 #define ARIZONA_RSTB_PU_MASK 0x0002 /* RSTB_PU */ 4568 #define ARIZONA_RSTB_PU_SHIFT 1 /* RSTB_PU */ 4569 #define ARIZONA_RSTB_PU_WIDTH 1 /* RSTB_PU */ 4570 4571 /* 4572 * R3105 (0xC21) - Misc Pad Ctrl 2 4573 */ 4574 #define ARIZONA_MCLK1_PD 0x1000 /* MCLK1_PD */ 4575 #define ARIZONA_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */ 4576 #define ARIZONA_MCLK1_PD_SHIFT 12 /* MCLK1_PD */ 4577 #define ARIZONA_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 4578 #define ARIZONA_MICD_PD 0x0100 /* MICD_PD */ 4579 #define ARIZONA_MICD_PD_MASK 0x0100 /* MICD_PD */ 4580 #define ARIZONA_MICD_PD_SHIFT 8 /* MICD_PD */ 4581 #define ARIZONA_MICD_PD_WIDTH 1 /* MICD_PD */ 4582 #define ARIZONA_ADDR_PD 0x0001 /* ADDR_PD */ 4583 #define ARIZONA_ADDR_PD_MASK 0x0001 /* ADDR_PD */ 4584 #define ARIZONA_ADDR_PD_SHIFT 0 /* ADDR_PD */ 4585 #define ARIZONA_ADDR_PD_WIDTH 1 /* ADDR_PD */ 4586 4587 /* 4588 * R3106 (0xC22) - Misc Pad Ctrl 3 4589 */ 4590 #define ARIZONA_DMICDAT4_PD 0x0008 /* DMICDAT4_PD */ 4591 #define ARIZONA_DMICDAT4_PD_MASK 0x0008 /* DMICDAT4_PD */ 4592 #define ARIZONA_DMICDAT4_PD_SHIFT 3 /* DMICDAT4_PD */ 4593 #define ARIZONA_DMICDAT4_PD_WIDTH 1 /* DMICDAT4_PD */ 4594 #define ARIZONA_DMICDAT3_PD 0x0004 /* DMICDAT3_PD */ 4595 #define ARIZONA_DMICDAT3_PD_MASK 0x0004 /* DMICDAT3_PD */ 4596 #define ARIZONA_DMICDAT3_PD_SHIFT 2 /* DMICDAT3_PD */ 4597 #define ARIZONA_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */ 4598 #define ARIZONA_DMICDAT2_PD 0x0002 /* DMICDAT2_PD */ 4599 #define ARIZONA_DMICDAT2_PD_MASK 0x0002 /* DMICDAT2_PD */ 4600 #define ARIZONA_DMICDAT2_PD_SHIFT 1 /* DMICDAT2_PD */ 4601 #define ARIZONA_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 4602 #define ARIZONA_DMICDAT1_PD 0x0001 /* DMICDAT1_PD */ 4603 #define ARIZONA_DMICDAT1_PD_MASK 0x0001 /* DMICDAT1_PD */ 4604 #define ARIZONA_DMICDAT1_PD_SHIFT 0 /* DMICDAT1_PD */ 4605 #define ARIZONA_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 4606 4607 /* 4608 * R3107 (0xC23) - Misc Pad Ctrl 4 4609 */ 4610 #define ARIZONA_AIF1RXLRCLK_PU 0x0020 /* AIF1RXLRCLK_PU */ 4611 #define ARIZONA_AIF1RXLRCLK_PU_MASK 0x0020 /* AIF1RXLRCLK_PU */ 4612 #define ARIZONA_AIF1RXLRCLK_PU_SHIFT 5 /* AIF1RXLRCLK_PU */ 4613 #define ARIZONA_AIF1RXLRCLK_PU_WIDTH 1 /* AIF1RXLRCLK_PU */ 4614 #define ARIZONA_AIF1RXLRCLK_PD 0x0010 /* AIF1RXLRCLK_PD */ 4615 #define ARIZONA_AIF1RXLRCLK_PD_MASK 0x0010 /* AIF1RXLRCLK_PD */ 4616 #define ARIZONA_AIF1RXLRCLK_PD_SHIFT 4 /* AIF1RXLRCLK_PD */ 4617 #define ARIZONA_AIF1RXLRCLK_PD_WIDTH 1 /* AIF1RXLRCLK_PD */ 4618 #define ARIZONA_AIF1BCLK_PU 0x0008 /* AIF1BCLK_PU */ 4619 #define ARIZONA_AIF1BCLK_PU_MASK 0x0008 /* AIF1BCLK_PU */ 4620 #define ARIZONA_AIF1BCLK_PU_SHIFT 3 /* AIF1BCLK_PU */ 4621 #define ARIZONA_AIF1BCLK_PU_WIDTH 1 /* AIF1BCLK_PU */ 4622 #define ARIZONA_AIF1BCLK_PD 0x0004 /* AIF1BCLK_PD */ 4623 #define ARIZONA_AIF1BCLK_PD_MASK 0x0004 /* AIF1BCLK_PD */ 4624 #define ARIZONA_AIF1BCLK_PD_SHIFT 2 /* AIF1BCLK_PD */ 4625 #define ARIZONA_AIF1BCLK_PD_WIDTH 1 /* AIF1BCLK_PD */ 4626 #define ARIZONA_AIF1RXDAT_PU 0x0002 /* AIF1RXDAT_PU */ 4627 #define ARIZONA_AIF1RXDAT_PU_MASK 0x0002 /* AIF1RXDAT_PU */ 4628 #define ARIZONA_AIF1RXDAT_PU_SHIFT 1 /* AIF1RXDAT_PU */ 4629 #define ARIZONA_AIF1RXDAT_PU_WIDTH 1 /* AIF1RXDAT_PU */ 4630 #define ARIZONA_AIF1RXDAT_PD 0x0001 /* AIF1RXDAT_PD */ 4631 #define ARIZONA_AIF1RXDAT_PD_MASK 0x0001 /* AIF1RXDAT_PD */ 4632 #define ARIZONA_AIF1RXDAT_PD_SHIFT 0 /* AIF1RXDAT_PD */ 4633 #define ARIZONA_AIF1RXDAT_PD_WIDTH 1 /* AIF1RXDAT_PD */ 4634 4635 /* 4636 * R3108 (0xC24) - Misc Pad Ctrl 5 4637 */ 4638 #define ARIZONA_AIF2RXLRCLK_PU 0x0020 /* AIF2RXLRCLK_PU */ 4639 #define ARIZONA_AIF2RXLRCLK_PU_MASK 0x0020 /* AIF2RXLRCLK_PU */ 4640 #define ARIZONA_AIF2RXLRCLK_PU_SHIFT 5 /* AIF2RXLRCLK_PU */ 4641 #define ARIZONA_AIF2RXLRCLK_PU_WIDTH 1 /* AIF2RXLRCLK_PU */ 4642 #define ARIZONA_AIF2RXLRCLK_PD 0x0010 /* AIF2RXLRCLK_PD */ 4643 #define ARIZONA_AIF2RXLRCLK_PD_MASK 0x0010 /* AIF2RXLRCLK_PD */ 4644 #define ARIZONA_AIF2RXLRCLK_PD_SHIFT 4 /* AIF2RXLRCLK_PD */ 4645 #define ARIZONA_AIF2RXLRCLK_PD_WIDTH 1 /* AIF2RXLRCLK_PD */ 4646 #define ARIZONA_AIF2BCLK_PU 0x0008 /* AIF2BCLK_PU */ 4647 #define ARIZONA_AIF2BCLK_PU_MASK 0x0008 /* AIF2BCLK_PU */ 4648 #define ARIZONA_AIF2BCLK_PU_SHIFT 3 /* AIF2BCLK_PU */ 4649 #define ARIZONA_AIF2BCLK_PU_WIDTH 1 /* AIF2BCLK_PU */ 4650 #define ARIZONA_AIF2BCLK_PD 0x0004 /* AIF2BCLK_PD */ 4651 #define ARIZONA_AIF2BCLK_PD_MASK 0x0004 /* AIF2BCLK_PD */ 4652 #define ARIZONA_AIF2BCLK_PD_SHIFT 2 /* AIF2BCLK_PD */ 4653 #define ARIZONA_AIF2BCLK_PD_WIDTH 1 /* AIF2BCLK_PD */ 4654 #define ARIZONA_AIF2RXDAT_PU 0x0002 /* AIF2RXDAT_PU */ 4655 #define ARIZONA_AIF2RXDAT_PU_MASK 0x0002 /* AIF2RXDAT_PU */ 4656 #define ARIZONA_AIF2RXDAT_PU_SHIFT 1 /* AIF2RXDAT_PU */ 4657 #define ARIZONA_AIF2RXDAT_PU_WIDTH 1 /* AIF2RXDAT_PU */ 4658 #define ARIZONA_AIF2RXDAT_PD 0x0001 /* AIF2RXDAT_PD */ 4659 #define ARIZONA_AIF2RXDAT_PD_MASK 0x0001 /* AIF2RXDAT_PD */ 4660 #define ARIZONA_AIF2RXDAT_PD_SHIFT 0 /* AIF2RXDAT_PD */ 4661 #define ARIZONA_AIF2RXDAT_PD_WIDTH 1 /* AIF2RXDAT_PD */ 4662 4663 /* 4664 * R3109 (0xC25) - Misc Pad Ctrl 6 4665 */ 4666 #define ARIZONA_AIF3RXLRCLK_PU 0x0020 /* AIF3RXLRCLK_PU */ 4667 #define ARIZONA_AIF3RXLRCLK_PU_MASK 0x0020 /* AIF3RXLRCLK_PU */ 4668 #define ARIZONA_AIF3RXLRCLK_PU_SHIFT 5 /* AIF3RXLRCLK_PU */ 4669 #define ARIZONA_AIF3RXLRCLK_PU_WIDTH 1 /* AIF3RXLRCLK_PU */ 4670 #define ARIZONA_AIF3RXLRCLK_PD 0x0010 /* AIF3RXLRCLK_PD */ 4671 #define ARIZONA_AIF3RXLRCLK_PD_MASK 0x0010 /* AIF3RXLRCLK_PD */ 4672 #define ARIZONA_AIF3RXLRCLK_PD_SHIFT 4 /* AIF3RXLRCLK_PD */ 4673 #define ARIZONA_AIF3RXLRCLK_PD_WIDTH 1 /* AIF3RXLRCLK_PD */ 4674 #define ARIZONA_AIF3BCLK_PU 0x0008 /* AIF3BCLK_PU */ 4675 #define ARIZONA_AIF3BCLK_PU_MASK 0x0008 /* AIF3BCLK_PU */ 4676 #define ARIZONA_AIF3BCLK_PU_SHIFT 3 /* AIF3BCLK_PU */ 4677 #define ARIZONA_AIF3BCLK_PU_WIDTH 1 /* AIF3BCLK_PU */ 4678 #define ARIZONA_AIF3BCLK_PD 0x0004 /* AIF3BCLK_PD */ 4679 #define ARIZONA_AIF3BCLK_PD_MASK 0x0004 /* AIF3BCLK_PD */ 4680 #define ARIZONA_AIF3BCLK_PD_SHIFT 2 /* AIF3BCLK_PD */ 4681 #define ARIZONA_AIF3BCLK_PD_WIDTH 1 /* AIF3BCLK_PD */ 4682 #define ARIZONA_AIF3RXDAT_PU 0x0002 /* AIF3RXDAT_PU */ 4683 #define ARIZONA_AIF3RXDAT_PU_MASK 0x0002 /* AIF3RXDAT_PU */ 4684 #define ARIZONA_AIF3RXDAT_PU_SHIFT 1 /* AIF3RXDAT_PU */ 4685 #define ARIZONA_AIF3RXDAT_PU_WIDTH 1 /* AIF3RXDAT_PU */ 4686 #define ARIZONA_AIF3RXDAT_PD 0x0001 /* AIF3RXDAT_PD */ 4687 #define ARIZONA_AIF3RXDAT_PD_MASK 0x0001 /* AIF3RXDAT_PD */ 4688 #define ARIZONA_AIF3RXDAT_PD_SHIFT 0 /* AIF3RXDAT_PD */ 4689 #define ARIZONA_AIF3RXDAT_PD_WIDTH 1 /* AIF3RXDAT_PD */ 4690 4691 /* 4692 * R3328 (0xD00) - Interrupt Status 1 4693 */ 4694 #define ARIZONA_GP4_EINT1 0x0008 /* GP4_EINT1 */ 4695 #define ARIZONA_GP4_EINT1_MASK 0x0008 /* GP4_EINT1 */ 4696 #define ARIZONA_GP4_EINT1_SHIFT 3 /* GP4_EINT1 */ 4697 #define ARIZONA_GP4_EINT1_WIDTH 1 /* GP4_EINT1 */ 4698 #define ARIZONA_GP3_EINT1 0x0004 /* GP3_EINT1 */ 4699 #define ARIZONA_GP3_EINT1_MASK 0x0004 /* GP3_EINT1 */ 4700 #define ARIZONA_GP3_EINT1_SHIFT 2 /* GP3_EINT1 */ 4701 #define ARIZONA_GP3_EINT1_WIDTH 1 /* GP3_EINT1 */ 4702 #define ARIZONA_GP2_EINT1 0x0002 /* GP2_EINT1 */ 4703 #define ARIZONA_GP2_EINT1_MASK 0x0002 /* GP2_EINT1 */ 4704 #define ARIZONA_GP2_EINT1_SHIFT 1 /* GP2_EINT1 */ 4705 #define ARIZONA_GP2_EINT1_WIDTH 1 /* GP2_EINT1 */ 4706 #define ARIZONA_GP1_EINT1 0x0001 /* GP1_EINT1 */ 4707 #define ARIZONA_GP1_EINT1_MASK 0x0001 /* GP1_EINT1 */ 4708 #define ARIZONA_GP1_EINT1_SHIFT 0 /* GP1_EINT1 */ 4709 #define ARIZONA_GP1_EINT1_WIDTH 1 /* GP1_EINT1 */ 4710 4711 /* 4712 * R3329 (0xD01) - Interrupt Status 2 4713 */ 4714 #define ARIZONA_DSP4_RAM_RDY_EINT1 0x0800 /* DSP4_RAM_RDY_EINT1 */ 4715 #define ARIZONA_DSP4_RAM_RDY_EINT1_MASK 0x0800 /* DSP4_RAM_RDY_EINT1 */ 4716 #define ARIZONA_DSP4_RAM_RDY_EINT1_SHIFT 11 /* DSP4_RAM_RDY_EINT1 */ 4717 #define ARIZONA_DSP4_RAM_RDY_EINT1_WIDTH 1 /* DSP4_RAM_RDY_EINT1 */ 4718 #define ARIZONA_DSP3_RAM_RDY_EINT1 0x0400 /* DSP3_RAM_RDY_EINT1 */ 4719 #define ARIZONA_DSP3_RAM_RDY_EINT1_MASK 0x0400 /* DSP3_RAM_RDY_EINT1 */ 4720 #define ARIZONA_DSP3_RAM_RDY_EINT1_SHIFT 10 /* DSP3_RAM_RDY_EINT1 */ 4721 #define ARIZONA_DSP3_RAM_RDY_EINT1_WIDTH 1 /* DSP3_RAM_RDY_EINT1 */ 4722 #define ARIZONA_DSP2_RAM_RDY_EINT1 0x0200 /* DSP2_RAM_RDY_EINT1 */ 4723 #define ARIZONA_DSP2_RAM_RDY_EINT1_MASK 0x0200 /* DSP2_RAM_RDY_EINT1 */ 4724 #define ARIZONA_DSP2_RAM_RDY_EINT1_SHIFT 9 /* DSP2_RAM_RDY_EINT1 */ 4725 #define ARIZONA_DSP2_RAM_RDY_EINT1_WIDTH 1 /* DSP2_RAM_RDY_EINT1 */ 4726 #define ARIZONA_DSP1_RAM_RDY_EINT1 0x0100 /* DSP1_RAM_RDY_EINT1 */ 4727 #define ARIZONA_DSP1_RAM_RDY_EINT1_MASK 0x0100 /* DSP1_RAM_RDY_EINT1 */ 4728 #define ARIZONA_DSP1_RAM_RDY_EINT1_SHIFT 8 /* DSP1_RAM_RDY_EINT1 */ 4729 #define ARIZONA_DSP1_RAM_RDY_EINT1_WIDTH 1 /* DSP1_RAM_RDY_EINT1 */ 4730 #define ARIZONA_DSP_IRQ8_EINT1 0x0080 /* DSP_IRQ8_EINT1 */ 4731 #define ARIZONA_DSP_IRQ8_EINT1_MASK 0x0080 /* DSP_IRQ8_EINT1 */ 4732 #define ARIZONA_DSP_IRQ8_EINT1_SHIFT 7 /* DSP_IRQ8_EINT1 */ 4733 #define ARIZONA_DSP_IRQ8_EINT1_WIDTH 1 /* DSP_IRQ8_EINT1 */ 4734 #define ARIZONA_DSP_IRQ7_EINT1 0x0040 /* DSP_IRQ7_EINT1 */ 4735 #define ARIZONA_DSP_IRQ7_EINT1_MASK 0x0040 /* DSP_IRQ7_EINT1 */ 4736 #define ARIZONA_DSP_IRQ7_EINT1_SHIFT 6 /* DSP_IRQ7_EINT1 */ 4737 #define ARIZONA_DSP_IRQ7_EINT1_WIDTH 1 /* DSP_IRQ7_EINT1 */ 4738 #define ARIZONA_DSP_IRQ6_EINT1 0x0020 /* DSP_IRQ6_EINT1 */ 4739 #define ARIZONA_DSP_IRQ6_EINT1_MASK 0x0020 /* DSP_IRQ6_EINT1 */ 4740 #define ARIZONA_DSP_IRQ6_EINT1_SHIFT 5 /* DSP_IRQ6_EINT1 */ 4741 #define ARIZONA_DSP_IRQ6_EINT1_WIDTH 1 /* DSP_IRQ6_EINT1 */ 4742 #define ARIZONA_DSP_IRQ5_EINT1 0x0010 /* DSP_IRQ5_EINT1 */ 4743 #define ARIZONA_DSP_IRQ5_EINT1_MASK 0x0010 /* DSP_IRQ5_EINT1 */ 4744 #define ARIZONA_DSP_IRQ5_EINT1_SHIFT 4 /* DSP_IRQ5_EINT1 */ 4745 #define ARIZONA_DSP_IRQ5_EINT1_WIDTH 1 /* DSP_IRQ5_EINT1 */ 4746 #define ARIZONA_DSP_IRQ4_EINT1 0x0008 /* DSP_IRQ4_EINT1 */ 4747 #define ARIZONA_DSP_IRQ4_EINT1_MASK 0x0008 /* DSP_IRQ4_EINT1 */ 4748 #define ARIZONA_DSP_IRQ4_EINT1_SHIFT 3 /* DSP_IRQ4_EINT1 */ 4749 #define ARIZONA_DSP_IRQ4_EINT1_WIDTH 1 /* DSP_IRQ4_EINT1 */ 4750 #define ARIZONA_DSP_IRQ3_EINT1 0x0004 /* DSP_IRQ3_EINT1 */ 4751 #define ARIZONA_DSP_IRQ3_EINT1_MASK 0x0004 /* DSP_IRQ3_EINT1 */ 4752 #define ARIZONA_DSP_IRQ3_EINT1_SHIFT 2 /* DSP_IRQ3_EINT1 */ 4753 #define ARIZONA_DSP_IRQ3_EINT1_WIDTH 1 /* DSP_IRQ3_EINT1 */ 4754 #define ARIZONA_DSP_IRQ2_EINT1 0x0002 /* DSP_IRQ2_EINT1 */ 4755 #define ARIZONA_DSP_IRQ2_EINT1_MASK 0x0002 /* DSP_IRQ2_EINT1 */ 4756 #define ARIZONA_DSP_IRQ2_EINT1_SHIFT 1 /* DSP_IRQ2_EINT1 */ 4757 #define ARIZONA_DSP_IRQ2_EINT1_WIDTH 1 /* DSP_IRQ2_EINT1 */ 4758 #define ARIZONA_DSP_IRQ1_EINT1 0x0001 /* DSP_IRQ1_EINT1 */ 4759 #define ARIZONA_DSP_IRQ1_EINT1_MASK 0x0001 /* DSP_IRQ1_EINT1 */ 4760 #define ARIZONA_DSP_IRQ1_EINT1_SHIFT 0 /* DSP_IRQ1_EINT1 */ 4761 #define ARIZONA_DSP_IRQ1_EINT1_WIDTH 1 /* DSP_IRQ1_EINT1 */ 4762 4763 /* 4764 * R3330 (0xD02) - Interrupt Status 3 4765 */ 4766 #define ARIZONA_SPK_OVERHEAT_WARN_EINT1 0x8000 /* SPK_OVERHEAT_WARN_EINT1 */ 4767 #define ARIZONA_SPK_OVERHEAT_WARN_EINT1_MASK 0x8000 /* SPK_OVERHEAD_WARN_EINT1 */ 4768 #define ARIZONA_SPK_OVERHEAT_WARN_EINT1_SHIFT 15 /* SPK_OVERHEAT_WARN_EINT1 */ 4769 #define ARIZONA_SPK_OVERHEAT_WARN_EINT1_WIDTH 1 /* SPK_OVERHEAT_WARN_EINT1 */ 4770 #define ARIZONA_SPK_OVERHEAT_EINT1 0x4000 /* SPK_OVERHEAT_EINT1 */ 4771 #define ARIZONA_SPK_OVERHEAT_EINT1_MASK 0x4000 /* SPK_OVERHEAT_EINT1 */ 4772 #define ARIZONA_SPK_OVERHEAT_EINT1_SHIFT 14 /* SPK_OVERHEAT_EINT1 */ 4773 #define ARIZONA_SPK_OVERHEAT_EINT1_WIDTH 1 /* SPK_OVERHEAT_EINT1 */ 4774 #define ARIZONA_HPDET_EINT1 0x2000 /* HPDET_EINT1 */ 4775 #define ARIZONA_HPDET_EINT1_MASK 0x2000 /* HPDET_EINT1 */ 4776 #define ARIZONA_HPDET_EINT1_SHIFT 13 /* HPDET_EINT1 */ 4777 #define ARIZONA_HPDET_EINT1_WIDTH 1 /* HPDET_EINT1 */ 4778 #define ARIZONA_MICDET_EINT1 0x1000 /* MICDET_EINT1 */ 4779 #define ARIZONA_MICDET_EINT1_MASK 0x1000 /* MICDET_EINT1 */ 4780 #define ARIZONA_MICDET_EINT1_SHIFT 12 /* MICDET_EINT1 */ 4781 #define ARIZONA_MICDET_EINT1_WIDTH 1 /* MICDET_EINT1 */ 4782 #define ARIZONA_WSEQ_DONE_EINT1 0x0800 /* WSEQ_DONE_EINT1 */ 4783 #define ARIZONA_WSEQ_DONE_EINT1_MASK 0x0800 /* WSEQ_DONE_EINT1 */ 4784 #define ARIZONA_WSEQ_DONE_EINT1_SHIFT 11 /* WSEQ_DONE_EINT1 */ 4785 #define ARIZONA_WSEQ_DONE_EINT1_WIDTH 1 /* WSEQ_DONE_EINT1 */ 4786 #define ARIZONA_DRC2_SIG_DET_EINT1 0x0400 /* DRC2_SIG_DET_EINT1 */ 4787 #define ARIZONA_DRC2_SIG_DET_EINT1_MASK 0x0400 /* DRC2_SIG_DET_EINT1 */ 4788 #define ARIZONA_DRC2_SIG_DET_EINT1_SHIFT 10 /* DRC2_SIG_DET_EINT1 */ 4789 #define ARIZONA_DRC2_SIG_DET_EINT1_WIDTH 1 /* DRC2_SIG_DET_EINT1 */ 4790 #define ARIZONA_DRC1_SIG_DET_EINT1 0x0200 /* DRC1_SIG_DET_EINT1 */ 4791 #define ARIZONA_DRC1_SIG_DET_EINT1_MASK 0x0200 /* DRC1_SIG_DET_EINT1 */ 4792 #define ARIZONA_DRC1_SIG_DET_EINT1_SHIFT 9 /* DRC1_SIG_DET_EINT1 */ 4793 #define ARIZONA_DRC1_SIG_DET_EINT1_WIDTH 1 /* DRC1_SIG_DET_EINT1 */ 4794 #define ARIZONA_ASRC2_LOCK_EINT1 0x0100 /* ASRC2_LOCK_EINT1 */ 4795 #define ARIZONA_ASRC2_LOCK_EINT1_MASK 0x0100 /* ASRC2_LOCK_EINT1 */ 4796 #define ARIZONA_ASRC2_LOCK_EINT1_SHIFT 8 /* ASRC2_LOCK_EINT1 */ 4797 #define ARIZONA_ASRC2_LOCK_EINT1_WIDTH 1 /* ASRC2_LOCK_EINT1 */ 4798 #define ARIZONA_ASRC1_LOCK_EINT1 0x0080 /* ASRC1_LOCK_EINT1 */ 4799 #define ARIZONA_ASRC1_LOCK_EINT1_MASK 0x0080 /* ASRC1_LOCK_EINT1 */ 4800 #define ARIZONA_ASRC1_LOCK_EINT1_SHIFT 7 /* ASRC1_LOCK_EINT1 */ 4801 #define ARIZONA_ASRC1_LOCK_EINT1_WIDTH 1 /* ASRC1_LOCK_EINT1 */ 4802 #define ARIZONA_UNDERCLOCKED_EINT1 0x0040 /* UNDERCLOCKED_EINT1 */ 4803 #define ARIZONA_UNDERCLOCKED_EINT1_MASK 0x0040 /* UNDERCLOCKED_EINT1 */ 4804 #define ARIZONA_UNDERCLOCKED_EINT1_SHIFT 6 /* UNDERCLOCKED_EINT1 */ 4805 #define ARIZONA_UNDERCLOCKED_EINT1_WIDTH 1 /* UNDERCLOCKED_EINT1 */ 4806 #define ARIZONA_OVERCLOCKED_EINT1 0x0020 /* OVERCLOCKED_EINT1 */ 4807 #define ARIZONA_OVERCLOCKED_EINT1_MASK 0x0020 /* OVERCLOCKED_EINT1 */ 4808 #define ARIZONA_OVERCLOCKED_EINT1_SHIFT 5 /* OVERCLOCKED_EINT1 */ 4809 #define ARIZONA_OVERCLOCKED_EINT1_WIDTH 1 /* OVERCLOCKED_EINT1 */ 4810 #define ARIZONA_FLL2_LOCK_EINT1 0x0008 /* FLL2_LOCK_EINT1 */ 4811 #define ARIZONA_FLL2_LOCK_EINT1_MASK 0x0008 /* FLL2_LOCK_EINT1 */ 4812 #define ARIZONA_FLL2_LOCK_EINT1_SHIFT 3 /* FLL2_LOCK_EINT1 */ 4813 #define ARIZONA_FLL2_LOCK_EINT1_WIDTH 1 /* FLL2_LOCK_EINT1 */ 4814 #define ARIZONA_FLL1_LOCK_EINT1 0x0004 /* FLL1_LOCK_EINT1 */ 4815 #define ARIZONA_FLL1_LOCK_EINT1_MASK 0x0004 /* FLL1_LOCK_EINT1 */ 4816 #define ARIZONA_FLL1_LOCK_EINT1_SHIFT 2 /* FLL1_LOCK_EINT1 */ 4817 #define ARIZONA_FLL1_LOCK_EINT1_WIDTH 1 /* FLL1_LOCK_EINT1 */ 4818 #define ARIZONA_CLKGEN_ERR_EINT1 0x0002 /* CLKGEN_ERR_EINT1 */ 4819 #define ARIZONA_CLKGEN_ERR_EINT1_MASK 0x0002 /* CLKGEN_ERR_EINT1 */ 4820 #define ARIZONA_CLKGEN_ERR_EINT1_SHIFT 1 /* CLKGEN_ERR_EINT1 */ 4821 #define ARIZONA_CLKGEN_ERR_EINT1_WIDTH 1 /* CLKGEN_ERR_EINT1 */ 4822 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1 0x0001 /* CLKGEN_ERR_ASYNC_EINT1 */ 4823 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT1 */ 4824 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT1 */ 4825 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT1 */ 4826 4827 /* 4828 * R3331 (0xD03) - Interrupt Status 4 4829 */ 4830 #define ARIZONA_ASRC_CFG_ERR_EINT1 0x8000 /* ASRC_CFG_ERR_EINT1 */ 4831 #define ARIZONA_ASRC_CFG_ERR_EINT1_MASK 0x8000 /* ASRC_CFG_ERR_EINT1 */ 4832 #define ARIZONA_ASRC_CFG_ERR_EINT1_SHIFT 15 /* ASRC_CFG_ERR_EINT1 */ 4833 #define ARIZONA_ASRC_CFG_ERR_EINT1_WIDTH 1 /* ASRC_CFG_ERR_EINT1 */ 4834 #define ARIZONA_AIF3_ERR_EINT1 0x4000 /* AIF3_ERR_EINT1 */ 4835 #define ARIZONA_AIF3_ERR_EINT1_MASK 0x4000 /* AIF3_ERR_EINT1 */ 4836 #define ARIZONA_AIF3_ERR_EINT1_SHIFT 14 /* AIF3_ERR_EINT1 */ 4837 #define ARIZONA_AIF3_ERR_EINT1_WIDTH 1 /* AIF3_ERR_EINT1 */ 4838 #define ARIZONA_AIF2_ERR_EINT1 0x2000 /* AIF2_ERR_EINT1 */ 4839 #define ARIZONA_AIF2_ERR_EINT1_MASK 0x2000 /* AIF2_ERR_EINT1 */ 4840 #define ARIZONA_AIF2_ERR_EINT1_SHIFT 13 /* AIF2_ERR_EINT1 */ 4841 #define ARIZONA_AIF2_ERR_EINT1_WIDTH 1 /* AIF2_ERR_EINT1 */ 4842 #define ARIZONA_AIF1_ERR_EINT1 0x1000 /* AIF1_ERR_EINT1 */ 4843 #define ARIZONA_AIF1_ERR_EINT1_MASK 0x1000 /* AIF1_ERR_EINT1 */ 4844 #define ARIZONA_AIF1_ERR_EINT1_SHIFT 12 /* AIF1_ERR_EINT1 */ 4845 #define ARIZONA_AIF1_ERR_EINT1_WIDTH 1 /* AIF1_ERR_EINT1 */ 4846 #define ARIZONA_CTRLIF_ERR_EINT1 0x0800 /* CTRLIF_ERR_EINT1 */ 4847 #define ARIZONA_CTRLIF_ERR_EINT1_MASK 0x0800 /* CTRLIF_ERR_EINT1 */ 4848 #define ARIZONA_CTRLIF_ERR_EINT1_SHIFT 11 /* CTRLIF_ERR_EINT1 */ 4849 #define ARIZONA_CTRLIF_ERR_EINT1_WIDTH 1 /* CTRLIF_ERR_EINT1 */ 4850 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 0x0400 /* MIXER_DROPPED_SAMPLE_EINT1 */ 4851 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_EINT1 */ 4852 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 10 /* MIXER_DROPPED_SAMPLE_EINT1 */ 4853 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT1 */ 4854 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 0x0200 /* ASYNC_CLK_ENA_LOW_EINT1 */ 4855 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_EINT1 */ 4856 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 9 /* ASYNC_CLK_ENA_LOW_EINT1 */ 4857 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT1 */ 4858 #define ARIZONA_SYSCLK_ENA_LOW_EINT1 0x0100 /* SYSCLK_ENA_LOW_EINT1 */ 4859 #define ARIZONA_SYSCLK_ENA_LOW_EINT1_MASK 0x0100 /* SYSCLK_ENA_LOW_EINT1 */ 4860 #define ARIZONA_SYSCLK_ENA_LOW_EINT1_SHIFT 8 /* SYSCLK_ENA_LOW_EINT1 */ 4861 #define ARIZONA_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* SYSCLK_ENA_LOW_EINT1 */ 4862 #define ARIZONA_ISRC1_CFG_ERR_EINT1 0x0080 /* ISRC1_CFG_ERR_EINT1 */ 4863 #define ARIZONA_ISRC1_CFG_ERR_EINT1_MASK 0x0080 /* ISRC1_CFG_ERR_EINT1 */ 4864 #define ARIZONA_ISRC1_CFG_ERR_EINT1_SHIFT 7 /* ISRC1_CFG_ERR_EINT1 */ 4865 #define ARIZONA_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* ISRC1_CFG_ERR_EINT1 */ 4866 #define ARIZONA_ISRC2_CFG_ERR_EINT1 0x0040 /* ISRC2_CFG_ERR_EINT1 */ 4867 #define ARIZONA_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* ISRC2_CFG_ERR_EINT1 */ 4868 #define ARIZONA_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* ISRC2_CFG_ERR_EINT1 */ 4869 #define ARIZONA_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* ISRC2_CFG_ERR_EINT1 */ 4870 #define ARIZONA_HP3R_DONE_EINT1 0x0020 /* HP3R_DONE_EINT1 */ 4871 #define ARIZONA_HP3R_DONE_EINT1_MASK 0x0020 /* HP3R_DONE_EINT1 */ 4872 #define ARIZONA_HP3R_DONE_EINT1_SHIFT 5 /* HP3R_DONE_EINT1 */ 4873 #define ARIZONA_HP3R_DONE_EINT1_WIDTH 1 /* HP3R_DONE_EINT1 */ 4874 #define ARIZONA_HP3L_DONE_EINT1 0x0010 /* HP3L_DONE_EINT1 */ 4875 #define ARIZONA_HP3L_DONE_EINT1_MASK 0x0010 /* HP3L_DONE_EINT1 */ 4876 #define ARIZONA_HP3L_DONE_EINT1_SHIFT 4 /* HP3L_DONE_EINT1 */ 4877 #define ARIZONA_HP3L_DONE_EINT1_WIDTH 1 /* HP3L_DONE_EINT1 */ 4878 #define ARIZONA_HP2R_DONE_EINT1 0x0008 /* HP2R_DONE_EINT1 */ 4879 #define ARIZONA_HP2R_DONE_EINT1_MASK 0x0008 /* HP2R_DONE_EINT1 */ 4880 #define ARIZONA_HP2R_DONE_EINT1_SHIFT 3 /* HP2R_DONE_EINT1 */ 4881 #define ARIZONA_HP2R_DONE_EINT1_WIDTH 1 /* HP2R_DONE_EINT1 */ 4882 #define ARIZONA_HP2L_DONE_EINT1 0x0004 /* HP2L_DONE_EINT1 */ 4883 #define ARIZONA_HP2L_DONE_EINT1_MASK 0x0004 /* HP2L_DONE_EINT1 */ 4884 #define ARIZONA_HP2L_DONE_EINT1_SHIFT 2 /* HP2L_DONE_EINT1 */ 4885 #define ARIZONA_HP2L_DONE_EINT1_WIDTH 1 /* HP2L_DONE_EINT1 */ 4886 #define ARIZONA_HP1R_DONE_EINT1 0x0002 /* HP1R_DONE_EINT1 */ 4887 #define ARIZONA_HP1R_DONE_EINT1_MASK 0x0002 /* HP1R_DONE_EINT1 */ 4888 #define ARIZONA_HP1R_DONE_EINT1_SHIFT 1 /* HP1R_DONE_EINT1 */ 4889 #define ARIZONA_HP1R_DONE_EINT1_WIDTH 1 /* HP1R_DONE_EINT1 */ 4890 #define ARIZONA_HP1L_DONE_EINT1 0x0001 /* HP1L_DONE_EINT1 */ 4891 #define ARIZONA_HP1L_DONE_EINT1_MASK 0x0001 /* HP1L_DONE_EINT1 */ 4892 #define ARIZONA_HP1L_DONE_EINT1_SHIFT 0 /* HP1L_DONE_EINT1 */ 4893 #define ARIZONA_HP1L_DONE_EINT1_WIDTH 1 /* HP1L_DONE_EINT1 */ 4894 4895 /* 4896 * R3331 (0xD03) - Interrupt Status 4 (Alternate layout) 4897 * 4898 * Alternate layout used on later devices, note only fields that have moved 4899 * are specified 4900 */ 4901 #define ARIZONA_V2_AIF3_ERR_EINT1 0x8000 /* AIF3_ERR_EINT1 */ 4902 #define ARIZONA_V2_AIF3_ERR_EINT1_MASK 0x8000 /* AIF3_ERR_EINT1 */ 4903 #define ARIZONA_V2_AIF3_ERR_EINT1_SHIFT 15 /* AIF3_ERR_EINT1 */ 4904 #define ARIZONA_V2_AIF3_ERR_EINT1_WIDTH 1 /* AIF3_ERR_EINT1 */ 4905 #define ARIZONA_V2_AIF2_ERR_EINT1 0x4000 /* AIF2_ERR_EINT1 */ 4906 #define ARIZONA_V2_AIF2_ERR_EINT1_MASK 0x4000 /* AIF2_ERR_EINT1 */ 4907 #define ARIZONA_V2_AIF2_ERR_EINT1_SHIFT 14 /* AIF2_ERR_EINT1 */ 4908 #define ARIZONA_V2_AIF2_ERR_EINT1_WIDTH 1 /* AIF2_ERR_EINT1 */ 4909 #define ARIZONA_V2_AIF1_ERR_EINT1 0x2000 /* AIF1_ERR_EINT1 */ 4910 #define ARIZONA_V2_AIF1_ERR_EINT1_MASK 0x2000 /* AIF1_ERR_EINT1 */ 4911 #define ARIZONA_V2_AIF1_ERR_EINT1_SHIFT 13 /* AIF1_ERR_EINT1 */ 4912 #define ARIZONA_V2_AIF1_ERR_EINT1_WIDTH 1 /* AIF1_ERR_EINT1 */ 4913 #define ARIZONA_V2_CTRLIF_ERR_EINT1 0x1000 /* CTRLIF_ERR_EINT1 */ 4914 #define ARIZONA_V2_CTRLIF_ERR_EINT1_MASK 0x1000 /* CTRLIF_ERR_EINT1 */ 4915 #define ARIZONA_V2_CTRLIF_ERR_EINT1_SHIFT 12 /* CTRLIF_ERR_EINT1 */ 4916 #define ARIZONA_V2_CTRLIF_ERR_EINT1_WIDTH 1 /* CTRLIF_ERR_EINT1 */ 4917 #define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1 0x0800 /* MIXER_DROPPED_SAMPLE_EINT1 */ 4918 #define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0800 /* MIXER_DROPPED_SAMPLE_EINT1 */ 4919 #define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 11 /* MIXER_DROPPED_SAMPLE_EINT1 */ 4920 #define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT1 */ 4921 #define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1 0x0400 /* ASYNC_CLK_ENA_LOW_EINT1 */ 4922 #define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0400 /* ASYNC_CLK_ENA_LOW_EINT1 */ 4923 #define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 10 /* ASYNC_CLK_ENA_LOW_EINT1 */ 4924 #define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT1 */ 4925 #define ARIZONA_V2_SYSCLK_ENA_LOW_EINT1 0x0200 /* SYSCLK_ENA_LOW_EINT1 */ 4926 #define ARIZONA_V2_SYSCLK_ENA_LOW_EINT1_MASK 0x0200 /* SYSCLK_ENA_LOW_EINT1 */ 4927 #define ARIZONA_V2_SYSCLK_ENA_LOW_EINT1_SHIFT 9 /* SYSCLK_ENA_LOW_EINT1 */ 4928 #define ARIZONA_V2_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* SYSCLK_ENA_LOW_EINT1 */ 4929 #define ARIZONA_V2_ISRC1_CFG_ERR_EINT1 0x0100 /* ISRC1_CFG_ERR_EINT1 */ 4930 #define ARIZONA_V2_ISRC1_CFG_ERR_EINT1_MASK 0x0100 /* ISRC1_CFG_ERR_EINT1 */ 4931 #define ARIZONA_V2_ISRC1_CFG_ERR_EINT1_SHIFT 8 /* ISRC1_CFG_ERR_EINT1 */ 4932 #define ARIZONA_V2_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* ISRC1_CFG_ERR_EINT1 */ 4933 #define ARIZONA_V2_ISRC2_CFG_ERR_EINT1 0x0080 /* ISRC2_CFG_ERR_EINT1 */ 4934 #define ARIZONA_V2_ISRC2_CFG_ERR_EINT1_MASK 0x0080 /* ISRC2_CFG_ERR_EINT1 */ 4935 #define ARIZONA_V2_ISRC2_CFG_ERR_EINT1_SHIFT 7 /* ISRC2_CFG_ERR_EINT1 */ 4936 #define ARIZONA_V2_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* ISRC2_CFG_ERR_EINT1 */ 4937 #define ARIZONA_V2_ISRC3_CFG_ERR_EINT1 0x0040 /* ISRC3_CFG_ERR_EINT1 */ 4938 #define ARIZONA_V2_ISRC3_CFG_ERR_EINT1_MASK 0x0040 /* ISRC3_CFG_ERR_EINT1 */ 4939 #define ARIZONA_V2_ISRC3_CFG_ERR_EINT1_SHIFT 6 /* ISRC3_CFG_ERR_EINT1 */ 4940 #define ARIZONA_V2_ISRC3_CFG_ERR_EINT1_WIDTH 1 /* ISRC3_CFG_ERR_EINT1 */ 4941 4942 /* 4943 * R3332 (0xD04) - Interrupt Status 5 4944 */ 4945 #define ARIZONA_BOOT_DONE_EINT1 0x0100 /* BOOT_DONE_EINT1 */ 4946 #define ARIZONA_BOOT_DONE_EINT1_MASK 0x0100 /* BOOT_DONE_EINT1 */ 4947 #define ARIZONA_BOOT_DONE_EINT1_SHIFT 8 /* BOOT_DONE_EINT1 */ 4948 #define ARIZONA_BOOT_DONE_EINT1_WIDTH 1 /* BOOT_DONE_EINT1 */ 4949 #define ARIZONA_DCS_DAC_DONE_EINT1 0x0080 /* DCS_DAC_DONE_EINT1 */ 4950 #define ARIZONA_DCS_DAC_DONE_EINT1_MASK 0x0080 /* DCS_DAC_DONE_EINT1 */ 4951 #define ARIZONA_DCS_DAC_DONE_EINT1_SHIFT 7 /* DCS_DAC_DONE_EINT1 */ 4952 #define ARIZONA_DCS_DAC_DONE_EINT1_WIDTH 1 /* DCS_DAC_DONE_EINT1 */ 4953 #define ARIZONA_DCS_HP_DONE_EINT1 0x0040 /* DCS_HP_DONE_EINT1 */ 4954 #define ARIZONA_DCS_HP_DONE_EINT1_MASK 0x0040 /* DCS_HP_DONE_EINT1 */ 4955 #define ARIZONA_DCS_HP_DONE_EINT1_SHIFT 6 /* DCS_HP_DONE_EINT1 */ 4956 #define ARIZONA_DCS_HP_DONE_EINT1_WIDTH 1 /* DCS_HP_DONE_EINT1 */ 4957 #define ARIZONA_FLL2_CLOCK_OK_EINT1 0x0002 /* FLL2_CLOCK_OK_EINT1 */ 4958 #define ARIZONA_FLL2_CLOCK_OK_EINT1_MASK 0x0002 /* FLL2_CLOCK_OK_EINT1 */ 4959 #define ARIZONA_FLL2_CLOCK_OK_EINT1_SHIFT 1 /* FLL2_CLOCK_OK_EINT1 */ 4960 #define ARIZONA_FLL2_CLOCK_OK_EINT1_WIDTH 1 /* FLL2_CLOCK_OK_EINT1 */ 4961 #define ARIZONA_FLL1_CLOCK_OK_EINT1 0x0001 /* FLL1_CLOCK_OK_EINT1 */ 4962 #define ARIZONA_FLL1_CLOCK_OK_EINT1_MASK 0x0001 /* FLL1_CLOCK_OK_EINT1 */ 4963 #define ARIZONA_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* FLL1_CLOCK_OK_EINT1 */ 4964 #define ARIZONA_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* FLL1_CLOCK_OK_EINT1 */ 4965 4966 /* 4967 * R3332 (0xD05) - Interrupt Status 5 (Alternate layout) 4968 * 4969 * Alternate layout used on later devices, note only fields that have moved 4970 * are specified 4971 */ 4972 #define ARIZONA_V2_ASRC_CFG_ERR_EINT1 0x0008 /* ASRC_CFG_ERR_EINT1 */ 4973 #define ARIZONA_V2_ASRC_CFG_ERR_EINT1_MASK 0x0008 /* ASRC_CFG_ERR_EINT1 */ 4974 #define ARIZONA_V2_ASRC_CFG_ERR_EINT1_SHIFT 3 /* ASRC_CFG_ERR_EINT1 */ 4975 #define ARIZONA_V2_ASRC_CFG_ERR_EINT1_WIDTH 1 /* ASRC_CFG_ERR_EINT1 */ 4976 4977 /* 4978 * R3333 (0xD05) - Interrupt Status 6 4979 */ 4980 #define ARIZONA_DSP_SHARED_WR_COLL_EINT1 0x8000 /* DSP_SHARED_WR_COLL_EINT1 */ 4981 #define ARIZONA_DSP_SHARED_WR_COLL_EINT1_MASK 0x8000 /* DSP_SHARED_WR_COLL_EINT1 */ 4982 #define ARIZONA_DSP_SHARED_WR_COLL_EINT1_SHIFT 15 /* DSP_SHARED_WR_COLL_EINT1 */ 4983 #define ARIZONA_DSP_SHARED_WR_COLL_EINT1_WIDTH 1 /* DSP_SHARED_WR_COLL_EINT1 */ 4984 #define ARIZONA_SPK_SHUTDOWN_EINT1 0x4000 /* SPK_SHUTDOWN_EINT1 */ 4985 #define ARIZONA_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* SPK_SHUTDOWN_EINT1 */ 4986 #define ARIZONA_SPK_SHUTDOWN_EINT1_SHIFT 14 /* SPK_SHUTDOWN_EINT1 */ 4987 #define ARIZONA_SPK_SHUTDOWN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_EINT1 */ 4988 #define ARIZONA_SPK1R_SHORT_EINT1 0x2000 /* SPK1R_SHORT_EINT1 */ 4989 #define ARIZONA_SPK1R_SHORT_EINT1_MASK 0x2000 /* SPK1R_SHORT_EINT1 */ 4990 #define ARIZONA_SPK1R_SHORT_EINT1_SHIFT 13 /* SPK1R_SHORT_EINT1 */ 4991 #define ARIZONA_SPK1R_SHORT_EINT1_WIDTH 1 /* SPK1R_SHORT_EINT1 */ 4992 #define ARIZONA_SPK1L_SHORT_EINT1 0x1000 /* SPK1L_SHORT_EINT1 */ 4993 #define ARIZONA_SPK1L_SHORT_EINT1_MASK 0x1000 /* SPK1L_SHORT_EINT1 */ 4994 #define ARIZONA_SPK1L_SHORT_EINT1_SHIFT 12 /* SPK1L_SHORT_EINT1 */ 4995 #define ARIZONA_SPK1L_SHORT_EINT1_WIDTH 1 /* SPK1L_SHORT_EINT1 */ 4996 #define ARIZONA_HP3R_SC_NEG_EINT1 0x0800 /* HP3R_SC_NEG_EINT1 */ 4997 #define ARIZONA_HP3R_SC_NEG_EINT1_MASK 0x0800 /* HP3R_SC_NEG_EINT1 */ 4998 #define ARIZONA_HP3R_SC_NEG_EINT1_SHIFT 11 /* HP3R_SC_NEG_EINT1 */ 4999 #define ARIZONA_HP3R_SC_NEG_EINT1_WIDTH 1 /* HP3R_SC_NEG_EINT1 */ 5000 #define ARIZONA_HP3R_SC_POS_EINT1 0x0400 /* HP3R_SC_POS_EINT1 */ 5001 #define ARIZONA_HP3R_SC_POS_EINT1_MASK 0x0400 /* HP3R_SC_POS_EINT1 */ 5002 #define ARIZONA_HP3R_SC_POS_EINT1_SHIFT 10 /* HP3R_SC_POS_EINT1 */ 5003 #define ARIZONA_HP3R_SC_POS_EINT1_WIDTH 1 /* HP3R_SC_POS_EINT1 */ 5004 #define ARIZONA_HP3L_SC_NEG_EINT1 0x0200 /* HP3L_SC_NEG_EINT1 */ 5005 #define ARIZONA_HP3L_SC_NEG_EINT1_MASK 0x0200 /* HP3L_SC_NEG_EINT1 */ 5006 #define ARIZONA_HP3L_SC_NEG_EINT1_SHIFT 9 /* HP3L_SC_NEG_EINT1 */ 5007 #define ARIZONA_HP3L_SC_NEG_EINT1_WIDTH 1 /* HP3L_SC_NEG_EINT1 */ 5008 #define ARIZONA_HP3L_SC_POS_EINT1 0x0100 /* HP3L_SC_POS_EINT1 */ 5009 #define ARIZONA_HP3L_SC_POS_EINT1_MASK 0x0100 /* HP3L_SC_POS_EINT1 */ 5010 #define ARIZONA_HP3L_SC_POS_EINT1_SHIFT 8 /* HP3L_SC_POS_EINT1 */ 5011 #define ARIZONA_HP3L_SC_POS_EINT1_WIDTH 1 /* HP3L_SC_POS_EINT1 */ 5012 #define ARIZONA_HP2R_SC_NEG_EINT1 0x0080 /* HP2R_SC_NEG_EINT1 */ 5013 #define ARIZONA_HP2R_SC_NEG_EINT1_MASK 0x0080 /* HP2R_SC_NEG_EINT1 */ 5014 #define ARIZONA_HP2R_SC_NEG_EINT1_SHIFT 7 /* HP2R_SC_NEG_EINT1 */ 5015 #define ARIZONA_HP2R_SC_NEG_EINT1_WIDTH 1 /* HP2R_SC_NEG_EINT1 */ 5016 #define ARIZONA_HP2R_SC_POS_EINT1 0x0040 /* HP2R_SC_POS_EINT1 */ 5017 #define ARIZONA_HP2R_SC_POS_EINT1_MASK 0x0040 /* HP2R_SC_POS_EINT1 */ 5018 #define ARIZONA_HP2R_SC_POS_EINT1_SHIFT 6 /* HP2R_SC_POS_EINT1 */ 5019 #define ARIZONA_HP2R_SC_POS_EINT1_WIDTH 1 /* HP2R_SC_POS_EINT1 */ 5020 #define ARIZONA_HP2L_SC_NEG_EINT1 0x0020 /* HP2L_SC_NEG_EINT1 */ 5021 #define ARIZONA_HP2L_SC_NEG_EINT1_MASK 0x0020 /* HP2L_SC_NEG_EINT1 */ 5022 #define ARIZONA_HP2L_SC_NEG_EINT1_SHIFT 5 /* HP2L_SC_NEG_EINT1 */ 5023 #define ARIZONA_HP2L_SC_NEG_EINT1_WIDTH 1 /* HP2L_SC_NEG_EINT1 */ 5024 #define ARIZONA_HP2L_SC_POS_EINT1 0x0010 /* HP2L_SC_POS_EINT1 */ 5025 #define ARIZONA_HP2L_SC_POS_EINT1_MASK 0x0010 /* HP2L_SC_POS_EINT1 */ 5026 #define ARIZONA_HP2L_SC_POS_EINT1_SHIFT 4 /* HP2L_SC_POS_EINT1 */ 5027 #define ARIZONA_HP2L_SC_POS_EINT1_WIDTH 1 /* HP2L_SC_POS_EINT1 */ 5028 #define ARIZONA_HP1R_SC_NEG_EINT1 0x0008 /* HP1R_SC_NEG_EINT1 */ 5029 #define ARIZONA_HP1R_SC_NEG_EINT1_MASK 0x0008 /* HP1R_SC_NEG_EINT1 */ 5030 #define ARIZONA_HP1R_SC_NEG_EINT1_SHIFT 3 /* HP1R_SC_NEG_EINT1 */ 5031 #define ARIZONA_HP1R_SC_NEG_EINT1_WIDTH 1 /* HP1R_SC_NEG_EINT1 */ 5032 #define ARIZONA_HP1R_SC_POS_EINT1 0x0004 /* HP1R_SC_POS_EINT1 */ 5033 #define ARIZONA_HP1R_SC_POS_EINT1_MASK 0x0004 /* HP1R_SC_POS_EINT1 */ 5034 #define ARIZONA_HP1R_SC_POS_EINT1_SHIFT 2 /* HP1R_SC_POS_EINT1 */ 5035 #define ARIZONA_HP1R_SC_POS_EINT1_WIDTH 1 /* HP1R_SC_POS_EINT1 */ 5036 #define ARIZONA_HP1L_SC_NEG_EINT1 0x0002 /* HP1L_SC_NEG_EINT1 */ 5037 #define ARIZONA_HP1L_SC_NEG_EINT1_MASK 0x0002 /* HP1L_SC_NEG_EINT1 */ 5038 #define ARIZONA_HP1L_SC_NEG_EINT1_SHIFT 1 /* HP1L_SC_NEG_EINT1 */ 5039 #define ARIZONA_HP1L_SC_NEG_EINT1_WIDTH 1 /* HP1L_SC_NEG_EINT1 */ 5040 #define ARIZONA_HP1L_SC_POS_EINT1 0x0001 /* HP1L_SC_POS_EINT1 */ 5041 #define ARIZONA_HP1L_SC_POS_EINT1_MASK 0x0001 /* HP1L_SC_POS_EINT1 */ 5042 #define ARIZONA_HP1L_SC_POS_EINT1_SHIFT 0 /* HP1L_SC_POS_EINT1 */ 5043 #define ARIZONA_HP1L_SC_POS_EINT1_WIDTH 1 /* HP1L_SC_POS_EINT1 */ 5044 5045 /* 5046 * R3336 (0xD08) - Interrupt Status 1 Mask 5047 */ 5048 #define ARIZONA_IM_GP4_EINT1 0x0008 /* IM_GP4_EINT1 */ 5049 #define ARIZONA_IM_GP4_EINT1_MASK 0x0008 /* IM_GP4_EINT1 */ 5050 #define ARIZONA_IM_GP4_EINT1_SHIFT 3 /* IM_GP4_EINT1 */ 5051 #define ARIZONA_IM_GP4_EINT1_WIDTH 1 /* IM_GP4_EINT1 */ 5052 #define ARIZONA_IM_GP3_EINT1 0x0004 /* IM_GP3_EINT1 */ 5053 #define ARIZONA_IM_GP3_EINT1_MASK 0x0004 /* IM_GP3_EINT1 */ 5054 #define ARIZONA_IM_GP3_EINT1_SHIFT 2 /* IM_GP3_EINT1 */ 5055 #define ARIZONA_IM_GP3_EINT1_WIDTH 1 /* IM_GP3_EINT1 */ 5056 #define ARIZONA_IM_GP2_EINT1 0x0002 /* IM_GP2_EINT1 */ 5057 #define ARIZONA_IM_GP2_EINT1_MASK 0x0002 /* IM_GP2_EINT1 */ 5058 #define ARIZONA_IM_GP2_EINT1_SHIFT 1 /* IM_GP2_EINT1 */ 5059 #define ARIZONA_IM_GP2_EINT1_WIDTH 1 /* IM_GP2_EINT1 */ 5060 #define ARIZONA_IM_GP1_EINT1 0x0001 /* IM_GP1_EINT1 */ 5061 #define ARIZONA_IM_GP1_EINT1_MASK 0x0001 /* IM_GP1_EINT1 */ 5062 #define ARIZONA_IM_GP1_EINT1_SHIFT 0 /* IM_GP1_EINT1 */ 5063 #define ARIZONA_IM_GP1_EINT1_WIDTH 1 /* IM_GP1_EINT1 */ 5064 5065 /* 5066 * R3337 (0xD09) - Interrupt Status 2 Mask 5067 */ 5068 #define ARIZONA_IM_DSP1_RAM_RDY_EINT1 0x0100 /* IM_DSP1_RAM_RDY_EINT1 */ 5069 #define ARIZONA_IM_DSP1_RAM_RDY_EINT1_MASK 0x0100 /* IM_DSP1_RAM_RDY_EINT1 */ 5070 #define ARIZONA_IM_DSP1_RAM_RDY_EINT1_SHIFT 8 /* IM_DSP1_RAM_RDY_EINT1 */ 5071 #define ARIZONA_IM_DSP1_RAM_RDY_EINT1_WIDTH 1 /* IM_DSP1_RAM_RDY_EINT1 */ 5072 #define ARIZONA_IM_DSP_IRQ2_EINT1 0x0002 /* IM_DSP_IRQ2_EINT1 */ 5073 #define ARIZONA_IM_DSP_IRQ2_EINT1_MASK 0x0002 /* IM_DSP_IRQ2_EINT1 */ 5074 #define ARIZONA_IM_DSP_IRQ2_EINT1_SHIFT 1 /* IM_DSP_IRQ2_EINT1 */ 5075 #define ARIZONA_IM_DSP_IRQ2_EINT1_WIDTH 1 /* IM_DSP_IRQ2_EINT1 */ 5076 #define ARIZONA_IM_DSP_IRQ1_EINT1 0x0001 /* IM_DSP_IRQ1_EINT1 */ 5077 #define ARIZONA_IM_DSP_IRQ1_EINT1_MASK 0x0001 /* IM_DSP_IRQ1_EINT1 */ 5078 #define ARIZONA_IM_DSP_IRQ1_EINT1_SHIFT 0 /* IM_DSP_IRQ1_EINT1 */ 5079 #define ARIZONA_IM_DSP_IRQ1_EINT1_WIDTH 1 /* IM_DSP_IRQ1_EINT1 */ 5080 5081 /* 5082 * R3338 (0xD0A) - Interrupt Status 3 Mask 5083 */ 5084 #define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1 0x8000 /* IM_SPK_OVERHEAT_WARN_EINT1 */ 5085 #define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1_MASK 0x8000 /* IM_SPK_OVERHEAT_WARN_EINT1 */ 5086 #define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1_SHIFT 15 /* IM_SPK_OVERHEAT_WARN_EINT1 */ 5087 #define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1_WIDTH 1 /* IM_SPK_OVERHEAT_WARN_EINT1 */ 5088 #define ARIZONA_IM_SPK_OVERHEAT_EINT1 0x4000 /* IM_SPK_OVERHEAT_EINT1 */ 5089 #define ARIZONA_IM_SPK_OVERHEAT_EINT1_MASK 0x4000 /* IM_SPK_OVERHEAT_EINT1 */ 5090 #define ARIZONA_IM_SPK_OVERHEAT_EINT1_SHIFT 14 /* IM_SPK_OVERHEAT_EINT1 */ 5091 #define ARIZONA_IM_SPK_OVERHEAT_EINT1_WIDTH 1 /* IM_SPK_OVERHEAT_EINT1 */ 5092 #define ARIZONA_IM_HPDET_EINT1 0x2000 /* IM_HPDET_EINT1 */ 5093 #define ARIZONA_IM_HPDET_EINT1_MASK 0x2000 /* IM_HPDET_EINT1 */ 5094 #define ARIZONA_IM_HPDET_EINT1_SHIFT 13 /* IM_HPDET_EINT1 */ 5095 #define ARIZONA_IM_HPDET_EINT1_WIDTH 1 /* IM_HPDET_EINT1 */ 5096 #define ARIZONA_IM_MICDET_EINT1 0x1000 /* IM_MICDET_EINT1 */ 5097 #define ARIZONA_IM_MICDET_EINT1_MASK 0x1000 /* IM_MICDET_EINT1 */ 5098 #define ARIZONA_IM_MICDET_EINT1_SHIFT 12 /* IM_MICDET_EINT1 */ 5099 #define ARIZONA_IM_MICDET_EINT1_WIDTH 1 /* IM_MICDET_EINT1 */ 5100 #define ARIZONA_IM_WSEQ_DONE_EINT1 0x0800 /* IM_WSEQ_DONE_EINT1 */ 5101 #define ARIZONA_IM_WSEQ_DONE_EINT1_MASK 0x0800 /* IM_WSEQ_DONE_EINT1 */ 5102 #define ARIZONA_IM_WSEQ_DONE_EINT1_SHIFT 11 /* IM_WSEQ_DONE_EINT1 */ 5103 #define ARIZONA_IM_WSEQ_DONE_EINT1_WIDTH 1 /* IM_WSEQ_DONE_EINT1 */ 5104 #define ARIZONA_IM_DRC2_SIG_DET_EINT1 0x0400 /* IM_DRC2_SIG_DET_EINT1 */ 5105 #define ARIZONA_IM_DRC2_SIG_DET_EINT1_MASK 0x0400 /* IM_DRC2_SIG_DET_EINT1 */ 5106 #define ARIZONA_IM_DRC2_SIG_DET_EINT1_SHIFT 10 /* IM_DRC2_SIG_DET_EINT1 */ 5107 #define ARIZONA_IM_DRC2_SIG_DET_EINT1_WIDTH 1 /* IM_DRC2_SIG_DET_EINT1 */ 5108 #define ARIZONA_IM_DRC1_SIG_DET_EINT1 0x0200 /* IM_DRC1_SIG_DET_EINT1 */ 5109 #define ARIZONA_IM_DRC1_SIG_DET_EINT1_MASK 0x0200 /* IM_DRC1_SIG_DET_EINT1 */ 5110 #define ARIZONA_IM_DRC1_SIG_DET_EINT1_SHIFT 9 /* IM_DRC1_SIG_DET_EINT1 */ 5111 #define ARIZONA_IM_DRC1_SIG_DET_EINT1_WIDTH 1 /* IM_DRC1_SIG_DET_EINT1 */ 5112 #define ARIZONA_IM_ASRC2_LOCK_EINT1 0x0100 /* IM_ASRC2_LOCK_EINT1 */ 5113 #define ARIZONA_IM_ASRC2_LOCK_EINT1_MASK 0x0100 /* IM_ASRC2_LOCK_EINT1 */ 5114 #define ARIZONA_IM_ASRC2_LOCK_EINT1_SHIFT 8 /* IM_ASRC2_LOCK_EINT1 */ 5115 #define ARIZONA_IM_ASRC2_LOCK_EINT1_WIDTH 1 /* IM_ASRC2_LOCK_EINT1 */ 5116 #define ARIZONA_IM_ASRC1_LOCK_EINT1 0x0080 /* IM_ASRC1_LOCK_EINT1 */ 5117 #define ARIZONA_IM_ASRC1_LOCK_EINT1_MASK 0x0080 /* IM_ASRC1_LOCK_EINT1 */ 5118 #define ARIZONA_IM_ASRC1_LOCK_EINT1_SHIFT 7 /* IM_ASRC1_LOCK_EINT1 */ 5119 #define ARIZONA_IM_ASRC1_LOCK_EINT1_WIDTH 1 /* IM_ASRC1_LOCK_EINT1 */ 5120 #define ARIZONA_IM_UNDERCLOCKED_EINT1 0x0040 /* IM_UNDERCLOCKED_EINT1 */ 5121 #define ARIZONA_IM_UNDERCLOCKED_EINT1_MASK 0x0040 /* IM_UNDERCLOCKED_EINT1 */ 5122 #define ARIZONA_IM_UNDERCLOCKED_EINT1_SHIFT 6 /* IM_UNDERCLOCKED_EINT1 */ 5123 #define ARIZONA_IM_UNDERCLOCKED_EINT1_WIDTH 1 /* IM_UNDERCLOCKED_EINT1 */ 5124 #define ARIZONA_IM_OVERCLOCKED_EINT1 0x0020 /* IM_OVERCLOCKED_EINT1 */ 5125 #define ARIZONA_IM_OVERCLOCKED_EINT1_MASK 0x0020 /* IM_OVERCLOCKED_EINT1 */ 5126 #define ARIZONA_IM_OVERCLOCKED_EINT1_SHIFT 5 /* IM_OVERCLOCKED_EINT1 */ 5127 #define ARIZONA_IM_OVERCLOCKED_EINT1_WIDTH 1 /* IM_OVERCLOCKED_EINT1 */ 5128 #define ARIZONA_IM_FLL2_LOCK_EINT1 0x0008 /* IM_FLL2_LOCK_EINT1 */ 5129 #define ARIZONA_IM_FLL2_LOCK_EINT1_MASK 0x0008 /* IM_FLL2_LOCK_EINT1 */ 5130 #define ARIZONA_IM_FLL2_LOCK_EINT1_SHIFT 3 /* IM_FLL2_LOCK_EINT1 */ 5131 #define ARIZONA_IM_FLL2_LOCK_EINT1_WIDTH 1 /* IM_FLL2_LOCK_EINT1 */ 5132 #define ARIZONA_IM_FLL1_LOCK_EINT1 0x0004 /* IM_FLL1_LOCK_EINT1 */ 5133 #define ARIZONA_IM_FLL1_LOCK_EINT1_MASK 0x0004 /* IM_FLL1_LOCK_EINT1 */ 5134 #define ARIZONA_IM_FLL1_LOCK_EINT1_SHIFT 2 /* IM_FLL1_LOCK_EINT1 */ 5135 #define ARIZONA_IM_FLL1_LOCK_EINT1_WIDTH 1 /* IM_FLL1_LOCK_EINT1 */ 5136 #define ARIZONA_IM_CLKGEN_ERR_EINT1 0x0002 /* IM_CLKGEN_ERR_EINT1 */ 5137 #define ARIZONA_IM_CLKGEN_ERR_EINT1_MASK 0x0002 /* IM_CLKGEN_ERR_EINT1 */ 5138 #define ARIZONA_IM_CLKGEN_ERR_EINT1_SHIFT 1 /* IM_CLKGEN_ERR_EINT1 */ 5139 #define ARIZONA_IM_CLKGEN_ERR_EINT1_WIDTH 1 /* IM_CLKGEN_ERR_EINT1 */ 5140 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT1 */ 5141 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT1 */ 5142 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT1 */ 5143 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT1 */ 5144 5145 /* 5146 * R3339 (0xD0B) - Interrupt Status 4 Mask 5147 */ 5148 #define ARIZONA_IM_ASRC_CFG_ERR_EINT1 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */ 5149 #define ARIZONA_IM_ASRC_CFG_ERR_EINT1_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */ 5150 #define ARIZONA_IM_ASRC_CFG_ERR_EINT1_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT1 */ 5151 #define ARIZONA_IM_ASRC_CFG_ERR_EINT1_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT1 */ 5152 #define ARIZONA_IM_AIF3_ERR_EINT1 0x4000 /* IM_AIF3_ERR_EINT1 */ 5153 #define ARIZONA_IM_AIF3_ERR_EINT1_MASK 0x4000 /* IM_AIF3_ERR_EINT1 */ 5154 #define ARIZONA_IM_AIF3_ERR_EINT1_SHIFT 14 /* IM_AIF3_ERR_EINT1 */ 5155 #define ARIZONA_IM_AIF3_ERR_EINT1_WIDTH 1 /* IM_AIF3_ERR_EINT1 */ 5156 #define ARIZONA_IM_AIF2_ERR_EINT1 0x2000 /* IM_AIF2_ERR_EINT1 */ 5157 #define ARIZONA_IM_AIF2_ERR_EINT1_MASK 0x2000 /* IM_AIF2_ERR_EINT1 */ 5158 #define ARIZONA_IM_AIF2_ERR_EINT1_SHIFT 13 /* IM_AIF2_ERR_EINT1 */ 5159 #define ARIZONA_IM_AIF2_ERR_EINT1_WIDTH 1 /* IM_AIF2_ERR_EINT1 */ 5160 #define ARIZONA_IM_AIF1_ERR_EINT1 0x1000 /* IM_AIF1_ERR_EINT1 */ 5161 #define ARIZONA_IM_AIF1_ERR_EINT1_MASK 0x1000 /* IM_AIF1_ERR_EINT1 */ 5162 #define ARIZONA_IM_AIF1_ERR_EINT1_SHIFT 12 /* IM_AIF1_ERR_EINT1 */ 5163 #define ARIZONA_IM_AIF1_ERR_EINT1_WIDTH 1 /* IM_AIF1_ERR_EINT1 */ 5164 #define ARIZONA_IM_CTRLIF_ERR_EINT1 0x0800 /* IM_CTRLIF_ERR_EINT1 */ 5165 #define ARIZONA_IM_CTRLIF_ERR_EINT1_MASK 0x0800 /* IM_CTRLIF_ERR_EINT1 */ 5166 #define ARIZONA_IM_CTRLIF_ERR_EINT1_SHIFT 11 /* IM_CTRLIF_ERR_EINT1 */ 5167 #define ARIZONA_IM_CTRLIF_ERR_EINT1_WIDTH 1 /* IM_CTRLIF_ERR_EINT1 */ 5168 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ 5169 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ 5170 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ 5171 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ 5172 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ 5173 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ 5174 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ 5175 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ 5176 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */ 5177 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */ 5178 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT1 */ 5179 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT1 */ 5180 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */ 5181 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */ 5182 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT1 */ 5183 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT1 */ 5184 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */ 5185 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */ 5186 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT1 */ 5187 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT1 */ 5188 #define ARIZONA_IM_HP3R_DONE_EINT1 0x0020 /* IM_HP3R_DONE_EINT1 */ 5189 #define ARIZONA_IM_HP3R_DONE_EINT1_MASK 0x0020 /* IM_HP3R_DONE_EINT1 */ 5190 #define ARIZONA_IM_HP3R_DONE_EINT1_SHIFT 5 /* IM_HP3R_DONE_EINT1 */ 5191 #define ARIZONA_IM_HP3R_DONE_EINT1_WIDTH 1 /* IM_HP3R_DONE_EINT1 */ 5192 #define ARIZONA_IM_HP3L_DONE_EINT1 0x0010 /* IM_HP3L_DONE_EINT1 */ 5193 #define ARIZONA_IM_HP3L_DONE_EINT1_MASK 0x0010 /* IM_HP3L_DONE_EINT1 */ 5194 #define ARIZONA_IM_HP3L_DONE_EINT1_SHIFT 4 /* IM_HP3L_DONE_EINT1 */ 5195 #define ARIZONA_IM_HP3L_DONE_EINT1_WIDTH 1 /* IM_HP3L_DONE_EINT1 */ 5196 #define ARIZONA_IM_HP2R_DONE_EINT1 0x0008 /* IM_HP2R_DONE_EINT1 */ 5197 #define ARIZONA_IM_HP2R_DONE_EINT1_MASK 0x0008 /* IM_HP2R_DONE_EINT1 */ 5198 #define ARIZONA_IM_HP2R_DONE_EINT1_SHIFT 3 /* IM_HP2R_DONE_EINT1 */ 5199 #define ARIZONA_IM_HP2R_DONE_EINT1_WIDTH 1 /* IM_HP2R_DONE_EINT1 */ 5200 #define ARIZONA_IM_HP2L_DONE_EINT1 0x0004 /* IM_HP2L_DONE_EINT1 */ 5201 #define ARIZONA_IM_HP2L_DONE_EINT1_MASK 0x0004 /* IM_HP2L_DONE_EINT1 */ 5202 #define ARIZONA_IM_HP2L_DONE_EINT1_SHIFT 2 /* IM_HP2L_DONE_EINT1 */ 5203 #define ARIZONA_IM_HP2L_DONE_EINT1_WIDTH 1 /* IM_HP2L_DONE_EINT1 */ 5204 #define ARIZONA_IM_HP1R_DONE_EINT1 0x0002 /* IM_HP1R_DONE_EINT1 */ 5205 #define ARIZONA_IM_HP1R_DONE_EINT1_MASK 0x0002 /* IM_HP1R_DONE_EINT1 */ 5206 #define ARIZONA_IM_HP1R_DONE_EINT1_SHIFT 1 /* IM_HP1R_DONE_EINT1 */ 5207 #define ARIZONA_IM_HP1R_DONE_EINT1_WIDTH 1 /* IM_HP1R_DONE_EINT1 */ 5208 #define ARIZONA_IM_HP1L_DONE_EINT1 0x0001 /* IM_HP1L_DONE_EINT1 */ 5209 #define ARIZONA_IM_HP1L_DONE_EINT1_MASK 0x0001 /* IM_HP1L_DONE_EINT1 */ 5210 #define ARIZONA_IM_HP1L_DONE_EINT1_SHIFT 0 /* IM_HP1L_DONE_EINT1 */ 5211 #define ARIZONA_IM_HP1L_DONE_EINT1_WIDTH 1 /* IM_HP1L_DONE_EINT1 */ 5212 5213 /* 5214 * R3339 (0xD0B) - Interrupt Status 4 Mask (Alternate layout) 5215 * 5216 * Alternate layout used on later devices, note only fields that have moved 5217 * are specified 5218 */ 5219 #define ARIZONA_V2_IM_AIF3_ERR_EINT1 0x8000 /* IM_AIF3_ERR_EINT1 */ 5220 #define ARIZONA_V2_IM_AIF3_ERR_EINT1_MASK 0x8000 /* IM_AIF3_ERR_EINT1 */ 5221 #define ARIZONA_V2_IM_AIF3_ERR_EINT1_SHIFT 15 /* IM_AIF3_ERR_EINT1 */ 5222 #define ARIZONA_V2_IM_AIF3_ERR_EINT1_WIDTH 1 /* IM_AIF3_ERR_EINT1 */ 5223 #define ARIZONA_V2_IM_AIF2_ERR_EINT1 0x4000 /* IM_AIF2_ERR_EINT1 */ 5224 #define ARIZONA_V2_IM_AIF2_ERR_EINT1_MASK 0x4000 /* IM_AIF2_ERR_EINT1 */ 5225 #define ARIZONA_V2_IM_AIF2_ERR_EINT1_SHIFT 14 /* IM_AIF2_ERR_EINT1 */ 5226 #define ARIZONA_V2_IM_AIF2_ERR_EINT1_WIDTH 1 /* IM_AIF2_ERR_EINT1 */ 5227 #define ARIZONA_V2_IM_AIF1_ERR_EINT1 0x2000 /* IM_AIF1_ERR_EINT1 */ 5228 #define ARIZONA_V2_IM_AIF1_ERR_EINT1_MASK 0x2000 /* IM_AIF1_ERR_EINT1 */ 5229 #define ARIZONA_V2_IM_AIF1_ERR_EINT1_SHIFT 13 /* IM_AIF1_ERR_EINT1 */ 5230 #define ARIZONA_V2_IM_AIF1_ERR_EINT1_WIDTH 1 /* IM_AIF1_ERR_EINT1 */ 5231 #define ARIZONA_V2_IM_CTRLIF_ERR_EINT1 0x1000 /* IM_CTRLIF_ERR_EINT1 */ 5232 #define ARIZONA_V2_IM_CTRLIF_ERR_EINT1_MASK 0x1000 /* IM_CTRLIF_ERR_EINT1 */ 5233 #define ARIZONA_V2_IM_CTRLIF_ERR_EINT1_SHIFT 12 /* IM_CTRLIF_ERR_EINT1 */ 5234 #define ARIZONA_V2_IM_CTRLIF_ERR_EINT1_WIDTH 1 /* IM_CTRLIF_ERR_EINT1 */ 5235 #define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1 0x0800 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ 5236 #define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0800 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ 5237 #define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 11 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ 5238 #define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ 5239 #define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1 0x0400 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ 5240 #define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0400 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ 5241 #define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 10 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ 5242 #define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ 5243 #define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1 0x0200 /* IM_SYSCLK_ENA_LOW_EINT1 */ 5244 #define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1_MASK 0x0200 /* IM_SYSCLK_ENA_LOW_EINT1 */ 5245 #define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1_SHIFT 9 /* IM_SYSCLK_ENA_LOW_EINT1 */ 5246 #define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT1 */ 5247 #define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1 0x0100 /* IM_ISRC1_CFG_ERR_EINT1 */ 5248 #define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1_MASK 0x0100 /* IM_ISRC1_CFG_ERR_EINT1 */ 5249 #define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1_SHIFT 8 /* IM_ISRC1_CFG_ERR_EINT1 */ 5250 #define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT1 */ 5251 #define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1 0x0080 /* IM_ISRC2_CFG_ERR_EINT1 */ 5252 #define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1_MASK 0x0080 /* IM_ISRC2_CFG_ERR_EINT1 */ 5253 #define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1_SHIFT 7 /* IM_ISRC2_CFG_ERR_EINT1 */ 5254 #define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT1 */ 5255 #define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1 0x0040 /* IM_ISRC3_CFG_ERR_EINT1 */ 5256 #define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1_MASK 0x0040 /* IM_ISRC3_CFG_ERR_EINT1 */ 5257 #define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1_SHIFT 6 /* IM_ISRC3_CFG_ERR_EINT1 */ 5258 #define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC3_CFG_ERR_EINT1 */ 5259 5260 /* 5261 * R3340 (0xD0C) - Interrupt Status 5 Mask 5262 */ 5263 #define ARIZONA_IM_BOOT_DONE_EINT1 0x0100 /* IM_BOOT_DONE_EINT1 */ 5264 #define ARIZONA_IM_BOOT_DONE_EINT1_MASK 0x0100 /* IM_BOOT_DONE_EINT1 */ 5265 #define ARIZONA_IM_BOOT_DONE_EINT1_SHIFT 8 /* IM_BOOT_DONE_EINT1 */ 5266 #define ARIZONA_IM_BOOT_DONE_EINT1_WIDTH 1 /* IM_BOOT_DONE_EINT1 */ 5267 #define ARIZONA_IM_DCS_DAC_DONE_EINT1 0x0080 /* IM_DCS_DAC_DONE_EINT1 */ 5268 #define ARIZONA_IM_DCS_DAC_DONE_EINT1_MASK 0x0080 /* IM_DCS_DAC_DONE_EINT1 */ 5269 #define ARIZONA_IM_DCS_DAC_DONE_EINT1_SHIFT 7 /* IM_DCS_DAC_DONE_EINT1 */ 5270 #define ARIZONA_IM_DCS_DAC_DONE_EINT1_WIDTH 1 /* IM_DCS_DAC_DONE_EINT1 */ 5271 #define ARIZONA_IM_DCS_HP_DONE_EINT1 0x0040 /* IM_DCS_HP_DONE_EINT1 */ 5272 #define ARIZONA_IM_DCS_HP_DONE_EINT1_MASK 0x0040 /* IM_DCS_HP_DONE_EINT1 */ 5273 #define ARIZONA_IM_DCS_HP_DONE_EINT1_SHIFT 6 /* IM_DCS_HP_DONE_EINT1 */ 5274 #define ARIZONA_IM_DCS_HP_DONE_EINT1_WIDTH 1 /* IM_DCS_HP_DONE_EINT1 */ 5275 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1 0x0002 /* IM_FLL2_CLOCK_OK_EINT1 */ 5276 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_MASK 0x0002 /* IM_FLL2_CLOCK_OK_EINT1 */ 5277 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_SHIFT 1 /* IM_FLL2_CLOCK_OK_EINT1 */ 5278 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_WIDTH 1 /* IM_FLL2_CLOCK_OK_EINT1 */ 5279 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1 0x0001 /* IM_FLL1_CLOCK_OK_EINT1 */ 5280 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_MASK 0x0001 /* IM_FLL1_CLOCK_OK_EINT1 */ 5281 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT1 */ 5282 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT1 */ 5283 5284 /* 5285 * R3340 (0xD0C) - Interrupt Status 5 Mask (Alternate layout) 5286 * 5287 * Alternate layout used on later devices, note only fields that have moved 5288 * are specified 5289 */ 5290 #define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1 0x0008 /* IM_ASRC_CFG_ERR_EINT1 */ 5291 #define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1_MASK 0x0008 /* IM_ASRC_CFG_ERR_EINT1 */ 5292 #define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1_SHIFT 3 /* IM_ASRC_CFG_ERR_EINT1 */ 5293 #define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT1 */ 5294 5295 /* 5296 * R3341 (0xD0D) - Interrupt Status 6 Mask 5297 */ 5298 #define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT1 */ 5299 #define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1_MASK 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT1 */ 5300 #define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1_SHIFT 15 /* IM_DSP_SHARED_WR_COLL_EINT1 */ 5301 #define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1_WIDTH 1 /* IM_DSP_SHARED_WR_COLL_EINT1 */ 5302 #define ARIZONA_IM_SPK_SHUTDOWN_EINT1 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */ 5303 #define ARIZONA_IM_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */ 5304 #define ARIZONA_IM_SPK_SHUTDOWN_EINT1_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT1 */ 5305 #define ARIZONA_IM_SPK_SHUTDOWN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT1 */ 5306 #define ARIZONA_IM_SPK1R_SHORT_EINT1 0x2000 /* IM_SPK1R_SHORT_EINT1 */ 5307 #define ARIZONA_IM_SPK1R_SHORT_EINT1_MASK 0x2000 /* IM_SPK1R_SHORT_EINT1 */ 5308 #define ARIZONA_IM_SPK1R_SHORT_EINT1_SHIFT 13 /* IM_SPK1R_SHORT_EINT1 */ 5309 #define ARIZONA_IM_SPK1R_SHORT_EINT1_WIDTH 1 /* IM_SPK1R_SHORT_EINT1 */ 5310 #define ARIZONA_IM_SPK1L_SHORT_EINT1 0x1000 /* IM_SPK1L_SHORT_EINT1 */ 5311 #define ARIZONA_IM_SPK1L_SHORT_EINT1_MASK 0x1000 /* IM_SPK1L_SHORT_EINT1 */ 5312 #define ARIZONA_IM_SPK1L_SHORT_EINT1_SHIFT 12 /* IM_SPK1L_SHORT_EINT1 */ 5313 #define ARIZONA_IM_SPK1L_SHORT_EINT1_WIDTH 1 /* IM_SPK1L_SHORT_EINT1 */ 5314 #define ARIZONA_IM_HP3R_SC_NEG_EINT1 0x0800 /* IM_HP3R_SC_NEG_EINT1 */ 5315 #define ARIZONA_IM_HP3R_SC_NEG_EINT1_MASK 0x0800 /* IM_HP3R_SC_NEG_EINT1 */ 5316 #define ARIZONA_IM_HP3R_SC_NEG_EINT1_SHIFT 11 /* IM_HP3R_SC_NEG_EINT1 */ 5317 #define ARIZONA_IM_HP3R_SC_NEG_EINT1_WIDTH 1 /* IM_HP3R_SC_NEG_EINT1 */ 5318 #define ARIZONA_IM_HP3R_SC_POS_EINT1 0x0400 /* IM_HP3R_SC_POS_EINT1 */ 5319 #define ARIZONA_IM_HP3R_SC_POS_EINT1_MASK 0x0400 /* IM_HP3R_SC_POS_EINT1 */ 5320 #define ARIZONA_IM_HP3R_SC_POS_EINT1_SHIFT 10 /* IM_HP3R_SC_POS_EINT1 */ 5321 #define ARIZONA_IM_HP3R_SC_POS_EINT1_WIDTH 1 /* IM_HP3R_SC_POS_EINT1 */ 5322 #define ARIZONA_IM_HP3L_SC_NEG_EINT1 0x0200 /* IM_HP3L_SC_NEG_EINT1 */ 5323 #define ARIZONA_IM_HP3L_SC_NEG_EINT1_MASK 0x0200 /* IM_HP3L_SC_NEG_EINT1 */ 5324 #define ARIZONA_IM_HP3L_SC_NEG_EINT1_SHIFT 9 /* IM_HP3L_SC_NEG_EINT1 */ 5325 #define ARIZONA_IM_HP3L_SC_NEG_EINT1_WIDTH 1 /* IM_HP3L_SC_NEG_EINT1 */ 5326 #define ARIZONA_IM_HP3L_SC_POS_EINT1 0x0100 /* IM_HP3L_SC_POS_EINT1 */ 5327 #define ARIZONA_IM_HP3L_SC_POS_EINT1_MASK 0x0100 /* IM_HP3L_SC_POS_EINT1 */ 5328 #define ARIZONA_IM_HP3L_SC_POS_EINT1_SHIFT 8 /* IM_HP3L_SC_POS_EINT1 */ 5329 #define ARIZONA_IM_HP3L_SC_POS_EINT1_WIDTH 1 /* IM_HP3L_SC_POS_EINT1 */ 5330 #define ARIZONA_IM_HP2R_SC_NEG_EINT1 0x0080 /* IM_HP2R_SC_NEG_EINT1 */ 5331 #define ARIZONA_IM_HP2R_SC_NEG_EINT1_MASK 0x0080 /* IM_HP2R_SC_NEG_EINT1 */ 5332 #define ARIZONA_IM_HP2R_SC_NEG_EINT1_SHIFT 7 /* IM_HP2R_SC_NEG_EINT1 */ 5333 #define ARIZONA_IM_HP2R_SC_NEG_EINT1_WIDTH 1 /* IM_HP2R_SC_NEG_EINT1 */ 5334 #define ARIZONA_IM_HP2R_SC_POS_EINT1 0x0040 /* IM_HP2R_SC_POS_EINT1 */ 5335 #define ARIZONA_IM_HP2R_SC_POS_EINT1_MASK 0x0040 /* IM_HP2R_SC_POS_EINT1 */ 5336 #define ARIZONA_IM_HP2R_SC_POS_EINT1_SHIFT 6 /* IM_HP2R_SC_POS_EINT1 */ 5337 #define ARIZONA_IM_HP2R_SC_POS_EINT1_WIDTH 1 /* IM_HP2R_SC_POS_EINT1 */ 5338 #define ARIZONA_IM_HP2L_SC_NEG_EINT1 0x0020 /* IM_HP2L_SC_NEG_EINT1 */ 5339 #define ARIZONA_IM_HP2L_SC_NEG_EINT1_MASK 0x0020 /* IM_HP2L_SC_NEG_EINT1 */ 5340 #define ARIZONA_IM_HP2L_SC_NEG_EINT1_SHIFT 5 /* IM_HP2L_SC_NEG_EINT1 */ 5341 #define ARIZONA_IM_HP2L_SC_NEG_EINT1_WIDTH 1 /* IM_HP2L_SC_NEG_EINT1 */ 5342 #define ARIZONA_IM_HP2L_SC_POS_EINT1 0x0010 /* IM_HP2L_SC_POS_EINT1 */ 5343 #define ARIZONA_IM_HP2L_SC_POS_EINT1_MASK 0x0010 /* IM_HP2L_SC_POS_EINT1 */ 5344 #define ARIZONA_IM_HP2L_SC_POS_EINT1_SHIFT 4 /* IM_HP2L_SC_POS_EINT1 */ 5345 #define ARIZONA_IM_HP2L_SC_POS_EINT1_WIDTH 1 /* IM_HP2L_SC_POS_EINT1 */ 5346 #define ARIZONA_IM_HP1R_SC_NEG_EINT1 0x0008 /* IM_HP1R_SC_NEG_EINT1 */ 5347 #define ARIZONA_IM_HP1R_SC_NEG_EINT1_MASK 0x0008 /* IM_HP1R_SC_NEG_EINT1 */ 5348 #define ARIZONA_IM_HP1R_SC_NEG_EINT1_SHIFT 3 /* IM_HP1R_SC_NEG_EINT1 */ 5349 #define ARIZONA_IM_HP1R_SC_NEG_EINT1_WIDTH 1 /* IM_HP1R_SC_NEG_EINT1 */ 5350 #define ARIZONA_IM_HP1R_SC_POS_EINT1 0x0004 /* IM_HP1R_SC_POS_EINT1 */ 5351 #define ARIZONA_IM_HP1R_SC_POS_EINT1_MASK 0x0004 /* IM_HP1R_SC_POS_EINT1 */ 5352 #define ARIZONA_IM_HP1R_SC_POS_EINT1_SHIFT 2 /* IM_HP1R_SC_POS_EINT1 */ 5353 #define ARIZONA_IM_HP1R_SC_POS_EINT1_WIDTH 1 /* IM_HP1R_SC_POS_EINT1 */ 5354 #define ARIZONA_IM_HP1L_SC_NEG_EINT1 0x0002 /* IM_HP1L_SC_NEG_EINT1 */ 5355 #define ARIZONA_IM_HP1L_SC_NEG_EINT1_MASK 0x0002 /* IM_HP1L_SC_NEG_EINT1 */ 5356 #define ARIZONA_IM_HP1L_SC_NEG_EINT1_SHIFT 1 /* IM_HP1L_SC_NEG_EINT1 */ 5357 #define ARIZONA_IM_HP1L_SC_NEG_EINT1_WIDTH 1 /* IM_HP1L_SC_NEG_EINT1 */ 5358 #define ARIZONA_IM_HP1L_SC_POS_EINT1 0x0001 /* IM_HP1L_SC_POS_EINT1 */ 5359 #define ARIZONA_IM_HP1L_SC_POS_EINT1_MASK 0x0001 /* IM_HP1L_SC_POS_EINT1 */ 5360 #define ARIZONA_IM_HP1L_SC_POS_EINT1_SHIFT 0 /* IM_HP1L_SC_POS_EINT1 */ 5361 #define ARIZONA_IM_HP1L_SC_POS_EINT1_WIDTH 1 /* IM_HP1L_SC_POS_EINT1 */ 5362 5363 /* 5364 * R3343 (0xD0F) - Interrupt Control 5365 */ 5366 #define ARIZONA_IM_IRQ1 0x0001 /* IM_IRQ1 */ 5367 #define ARIZONA_IM_IRQ1_MASK 0x0001 /* IM_IRQ1 */ 5368 #define ARIZONA_IM_IRQ1_SHIFT 0 /* IM_IRQ1 */ 5369 #define ARIZONA_IM_IRQ1_WIDTH 1 /* IM_IRQ1 */ 5370 5371 /* 5372 * R3344 (0xD10) - IRQ2 Status 1 5373 */ 5374 #define ARIZONA_GP4_EINT2 0x0008 /* GP4_EINT2 */ 5375 #define ARIZONA_GP4_EINT2_MASK 0x0008 /* GP4_EINT2 */ 5376 #define ARIZONA_GP4_EINT2_SHIFT 3 /* GP4_EINT2 */ 5377 #define ARIZONA_GP4_EINT2_WIDTH 1 /* GP4_EINT2 */ 5378 #define ARIZONA_GP3_EINT2 0x0004 /* GP3_EINT2 */ 5379 #define ARIZONA_GP3_EINT2_MASK 0x0004 /* GP3_EINT2 */ 5380 #define ARIZONA_GP3_EINT2_SHIFT 2 /* GP3_EINT2 */ 5381 #define ARIZONA_GP3_EINT2_WIDTH 1 /* GP3_EINT2 */ 5382 #define ARIZONA_GP2_EINT2 0x0002 /* GP2_EINT2 */ 5383 #define ARIZONA_GP2_EINT2_MASK 0x0002 /* GP2_EINT2 */ 5384 #define ARIZONA_GP2_EINT2_SHIFT 1 /* GP2_EINT2 */ 5385 #define ARIZONA_GP2_EINT2_WIDTH 1 /* GP2_EINT2 */ 5386 #define ARIZONA_GP1_EINT2 0x0001 /* GP1_EINT2 */ 5387 #define ARIZONA_GP1_EINT2_MASK 0x0001 /* GP1_EINT2 */ 5388 #define ARIZONA_GP1_EINT2_SHIFT 0 /* GP1_EINT2 */ 5389 #define ARIZONA_GP1_EINT2_WIDTH 1 /* GP1_EINT2 */ 5390 5391 /* 5392 * R3345 (0xD11) - IRQ2 Status 2 5393 */ 5394 #define ARIZONA_DSP1_RAM_RDY_EINT2 0x0100 /* DSP1_RAM_RDY_EINT2 */ 5395 #define ARIZONA_DSP1_RAM_RDY_EINT2_MASK 0x0100 /* DSP1_RAM_RDY_EINT2 */ 5396 #define ARIZONA_DSP1_RAM_RDY_EINT2_SHIFT 8 /* DSP1_RAM_RDY_EINT2 */ 5397 #define ARIZONA_DSP1_RAM_RDY_EINT2_WIDTH 1 /* DSP1_RAM_RDY_EINT2 */ 5398 #define ARIZONA_DSP_IRQ2_EINT2 0x0002 /* DSP_IRQ2_EINT2 */ 5399 #define ARIZONA_DSP_IRQ2_EINT2_MASK 0x0002 /* DSP_IRQ2_EINT2 */ 5400 #define ARIZONA_DSP_IRQ2_EINT2_SHIFT 1 /* DSP_IRQ2_EINT2 */ 5401 #define ARIZONA_DSP_IRQ2_EINT2_WIDTH 1 /* DSP_IRQ2_EINT2 */ 5402 #define ARIZONA_DSP_IRQ1_EINT2 0x0001 /* DSP_IRQ1_EINT2 */ 5403 #define ARIZONA_DSP_IRQ1_EINT2_MASK 0x0001 /* DSP_IRQ1_EINT2 */ 5404 #define ARIZONA_DSP_IRQ1_EINT2_SHIFT 0 /* DSP_IRQ1_EINT2 */ 5405 #define ARIZONA_DSP_IRQ1_EINT2_WIDTH 1 /* DSP_IRQ1_EINT2 */ 5406 5407 /* 5408 * R3346 (0xD12) - IRQ2 Status 3 5409 */ 5410 #define ARIZONA_SPK_OVERHEAT_WARN_EINT2 0x8000 /* SPK_OVERHEAT_WARN_EINT2 */ 5411 #define ARIZONA_SPK_OVERHEAT_WARN_EINT2_MASK 0x8000 /* SPK_OVERHEAT_WARN_EINT2 */ 5412 #define ARIZONA_SPK_OVERHEAT_WARN_EINT2_SHIFT 15 /* SPK_OVERHEAT_WARN_EINT2 */ 5413 #define ARIZONA_SPK_OVERHEAT_WARN_EINT2_WIDTH 1 /* SPK_OVERHEAT_WARN_EINT2 */ 5414 #define ARIZONA_SPK_OVERHEAT_EINT2 0x4000 /* SPK_OVERHEAT_EINT2 */ 5415 #define ARIZONA_SPK_OVERHEAT_EINT2_MASK 0x4000 /* SPK_OVERHEAT_EINT2 */ 5416 #define ARIZONA_SPK_OVERHEAT_EINT2_SHIFT 14 /* SPK_OVERHEAT_EINT2 */ 5417 #define ARIZONA_SPK_OVERHEAT_EINT2_WIDTH 1 /* SPK_OVERHEAT_EINT2 */ 5418 #define ARIZONA_HPDET_EINT2 0x2000 /* HPDET_EINT2 */ 5419 #define ARIZONA_HPDET_EINT2_MASK 0x2000 /* HPDET_EINT2 */ 5420 #define ARIZONA_HPDET_EINT2_SHIFT 13 /* HPDET_EINT2 */ 5421 #define ARIZONA_HPDET_EINT2_WIDTH 1 /* HPDET_EINT2 */ 5422 #define ARIZONA_MICDET_EINT2 0x1000 /* MICDET_EINT2 */ 5423 #define ARIZONA_MICDET_EINT2_MASK 0x1000 /* MICDET_EINT2 */ 5424 #define ARIZONA_MICDET_EINT2_SHIFT 12 /* MICDET_EINT2 */ 5425 #define ARIZONA_MICDET_EINT2_WIDTH 1 /* MICDET_EINT2 */ 5426 #define ARIZONA_WSEQ_DONE_EINT2 0x0800 /* WSEQ_DONE_EINT2 */ 5427 #define ARIZONA_WSEQ_DONE_EINT2_MASK 0x0800 /* WSEQ_DONE_EINT2 */ 5428 #define ARIZONA_WSEQ_DONE_EINT2_SHIFT 11 /* WSEQ_DONE_EINT2 */ 5429 #define ARIZONA_WSEQ_DONE_EINT2_WIDTH 1 /* WSEQ_DONE_EINT2 */ 5430 #define ARIZONA_DRC2_SIG_DET_EINT2 0x0400 /* DRC2_SIG_DET_EINT2 */ 5431 #define ARIZONA_DRC2_SIG_DET_EINT2_MASK 0x0400 /* DRC2_SIG_DET_EINT2 */ 5432 #define ARIZONA_DRC2_SIG_DET_EINT2_SHIFT 10 /* DRC2_SIG_DET_EINT2 */ 5433 #define ARIZONA_DRC2_SIG_DET_EINT2_WIDTH 1 /* DRC2_SIG_DET_EINT2 */ 5434 #define ARIZONA_DRC1_SIG_DET_EINT2 0x0200 /* DRC1_SIG_DET_EINT2 */ 5435 #define ARIZONA_DRC1_SIG_DET_EINT2_MASK 0x0200 /* DRC1_SIG_DET_EINT2 */ 5436 #define ARIZONA_DRC1_SIG_DET_EINT2_SHIFT 9 /* DRC1_SIG_DET_EINT2 */ 5437 #define ARIZONA_DRC1_SIG_DET_EINT2_WIDTH 1 /* DRC1_SIG_DET_EINT2 */ 5438 #define ARIZONA_ASRC2_LOCK_EINT2 0x0100 /* ASRC2_LOCK_EINT2 */ 5439 #define ARIZONA_ASRC2_LOCK_EINT2_MASK 0x0100 /* ASRC2_LOCK_EINT2 */ 5440 #define ARIZONA_ASRC2_LOCK_EINT2_SHIFT 8 /* ASRC2_LOCK_EINT2 */ 5441 #define ARIZONA_ASRC2_LOCK_EINT2_WIDTH 1 /* ASRC2_LOCK_EINT2 */ 5442 #define ARIZONA_ASRC1_LOCK_EINT2 0x0080 /* ASRC1_LOCK_EINT2 */ 5443 #define ARIZONA_ASRC1_LOCK_EINT2_MASK 0x0080 /* ASRC1_LOCK_EINT2 */ 5444 #define ARIZONA_ASRC1_LOCK_EINT2_SHIFT 7 /* ASRC1_LOCK_EINT2 */ 5445 #define ARIZONA_ASRC1_LOCK_EINT2_WIDTH 1 /* ASRC1_LOCK_EINT2 */ 5446 #define ARIZONA_UNDERCLOCKED_EINT2 0x0040 /* UNDERCLOCKED_EINT2 */ 5447 #define ARIZONA_UNDERCLOCKED_EINT2_MASK 0x0040 /* UNDERCLOCKED_EINT2 */ 5448 #define ARIZONA_UNDERCLOCKED_EINT2_SHIFT 6 /* UNDERCLOCKED_EINT2 */ 5449 #define ARIZONA_UNDERCLOCKED_EINT2_WIDTH 1 /* UNDERCLOCKED_EINT2 */ 5450 #define ARIZONA_OVERCLOCKED_EINT2 0x0020 /* OVERCLOCKED_EINT2 */ 5451 #define ARIZONA_OVERCLOCKED_EINT2_MASK 0x0020 /* OVERCLOCKED_EINT2 */ 5452 #define ARIZONA_OVERCLOCKED_EINT2_SHIFT 5 /* OVERCLOCKED_EINT2 */ 5453 #define ARIZONA_OVERCLOCKED_EINT2_WIDTH 1 /* OVERCLOCKED_EINT2 */ 5454 #define ARIZONA_FLL2_LOCK_EINT2 0x0008 /* FLL2_LOCK_EINT2 */ 5455 #define ARIZONA_FLL2_LOCK_EINT2_MASK 0x0008 /* FLL2_LOCK_EINT2 */ 5456 #define ARIZONA_FLL2_LOCK_EINT2_SHIFT 3 /* FLL2_LOCK_EINT2 */ 5457 #define ARIZONA_FLL2_LOCK_EINT2_WIDTH 1 /* FLL2_LOCK_EINT2 */ 5458 #define ARIZONA_FLL1_LOCK_EINT2 0x0004 /* FLL1_LOCK_EINT2 */ 5459 #define ARIZONA_FLL1_LOCK_EINT2_MASK 0x0004 /* FLL1_LOCK_EINT2 */ 5460 #define ARIZONA_FLL1_LOCK_EINT2_SHIFT 2 /* FLL1_LOCK_EINT2 */ 5461 #define ARIZONA_FLL1_LOCK_EINT2_WIDTH 1 /* FLL1_LOCK_EINT2 */ 5462 #define ARIZONA_CLKGEN_ERR_EINT2 0x0002 /* CLKGEN_ERR_EINT2 */ 5463 #define ARIZONA_CLKGEN_ERR_EINT2_MASK 0x0002 /* CLKGEN_ERR_EINT2 */ 5464 #define ARIZONA_CLKGEN_ERR_EINT2_SHIFT 1 /* CLKGEN_ERR_EINT2 */ 5465 #define ARIZONA_CLKGEN_ERR_EINT2_WIDTH 1 /* CLKGEN_ERR_EINT2 */ 5466 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2 0x0001 /* CLKGEN_ERR_ASYNC_EINT2 */ 5467 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT2 */ 5468 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT2 */ 5469 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT2 */ 5470 5471 /* 5472 * R3347 (0xD13) - IRQ2 Status 4 5473 */ 5474 #define ARIZONA_ASRC_CFG_ERR_EINT2 0x8000 /* ASRC_CFG_ERR_EINT2 */ 5475 #define ARIZONA_ASRC_CFG_ERR_EINT2_MASK 0x8000 /* ASRC_CFG_ERR_EINT2 */ 5476 #define ARIZONA_ASRC_CFG_ERR_EINT2_SHIFT 15 /* ASRC_CFG_ERR_EINT2 */ 5477 #define ARIZONA_ASRC_CFG_ERR_EINT2_WIDTH 1 /* ASRC_CFG_ERR_EINT2 */ 5478 #define ARIZONA_AIF3_ERR_EINT2 0x4000 /* AIF3_ERR_EINT2 */ 5479 #define ARIZONA_AIF3_ERR_EINT2_MASK 0x4000 /* AIF3_ERR_EINT2 */ 5480 #define ARIZONA_AIF3_ERR_EINT2_SHIFT 14 /* AIF3_ERR_EINT2 */ 5481 #define ARIZONA_AIF3_ERR_EINT2_WIDTH 1 /* AIF3_ERR_EINT2 */ 5482 #define ARIZONA_AIF2_ERR_EINT2 0x2000 /* AIF2_ERR_EINT2 */ 5483 #define ARIZONA_AIF2_ERR_EINT2_MASK 0x2000 /* AIF2_ERR_EINT2 */ 5484 #define ARIZONA_AIF2_ERR_EINT2_SHIFT 13 /* AIF2_ERR_EINT2 */ 5485 #define ARIZONA_AIF2_ERR_EINT2_WIDTH 1 /* AIF2_ERR_EINT2 */ 5486 #define ARIZONA_AIF1_ERR_EINT2 0x1000 /* AIF1_ERR_EINT2 */ 5487 #define ARIZONA_AIF1_ERR_EINT2_MASK 0x1000 /* AIF1_ERR_EINT2 */ 5488 #define ARIZONA_AIF1_ERR_EINT2_SHIFT 12 /* AIF1_ERR_EINT2 */ 5489 #define ARIZONA_AIF1_ERR_EINT2_WIDTH 1 /* AIF1_ERR_EINT2 */ 5490 #define ARIZONA_CTRLIF_ERR_EINT2 0x0800 /* CTRLIF_ERR_EINT2 */ 5491 #define ARIZONA_CTRLIF_ERR_EINT2_MASK 0x0800 /* CTRLIF_ERR_EINT2 */ 5492 #define ARIZONA_CTRLIF_ERR_EINT2_SHIFT 11 /* CTRLIF_ERR_EINT2 */ 5493 #define ARIZONA_CTRLIF_ERR_EINT2_WIDTH 1 /* CTRLIF_ERR_EINT2 */ 5494 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2 0x0400 /* MIXER_DROPPED_SAMPLE_EINT2 */ 5495 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_EINT2 */ 5496 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 10 /* MIXER_DROPPED_SAMPLE_EINT2 */ 5497 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT2 */ 5498 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2 0x0200 /* ASYNC_CLK_ENA_LOW_EINT2 */ 5499 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_EINT2 */ 5500 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 9 /* ASYNC_CLK_ENA_LOW_EINT2 */ 5501 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT2 */ 5502 #define ARIZONA_SYSCLK_ENA_LOW_EINT2 0x0100 /* SYSCLK_ENA_LOW_EINT2 */ 5503 #define ARIZONA_SYSCLK_ENA_LOW_EINT2_MASK 0x0100 /* SYSCLK_ENA_LOW_EINT2 */ 5504 #define ARIZONA_SYSCLK_ENA_LOW_EINT2_SHIFT 8 /* SYSCLK_ENA_LOW_EINT2 */ 5505 #define ARIZONA_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* SYSCLK_ENA_LOW_EINT2 */ 5506 #define ARIZONA_ISRC1_CFG_ERR_EINT2 0x0080 /* ISRC1_CFG_ERR_EINT2 */ 5507 #define ARIZONA_ISRC1_CFG_ERR_EINT2_MASK 0x0080 /* ISRC1_CFG_ERR_EINT2 */ 5508 #define ARIZONA_ISRC1_CFG_ERR_EINT2_SHIFT 7 /* ISRC1_CFG_ERR_EINT2 */ 5509 #define ARIZONA_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* ISRC1_CFG_ERR_EINT2 */ 5510 #define ARIZONA_ISRC2_CFG_ERR_EINT2 0x0040 /* ISRC2_CFG_ERR_EINT2 */ 5511 #define ARIZONA_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* ISRC2_CFG_ERR_EINT2 */ 5512 #define ARIZONA_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* ISRC2_CFG_ERR_EINT2 */ 5513 #define ARIZONA_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* ISRC2_CFG_ERR_EINT2 */ 5514 #define ARIZONA_HP3R_DONE_EINT2 0x0020 /* HP3R_DONE_EINT2 */ 5515 #define ARIZONA_HP3R_DONE_EINT2_MASK 0x0020 /* HP3R_DONE_EINT2 */ 5516 #define ARIZONA_HP3R_DONE_EINT2_SHIFT 5 /* HP3R_DONE_EINT2 */ 5517 #define ARIZONA_HP3R_DONE_EINT2_WIDTH 1 /* HP3R_DONE_EINT2 */ 5518 #define ARIZONA_HP3L_DONE_EINT2 0x0010 /* HP3L_DONE_EINT2 */ 5519 #define ARIZONA_HP3L_DONE_EINT2_MASK 0x0010 /* HP3L_DONE_EINT2 */ 5520 #define ARIZONA_HP3L_DONE_EINT2_SHIFT 4 /* HP3L_DONE_EINT2 */ 5521 #define ARIZONA_HP3L_DONE_EINT2_WIDTH 1 /* HP3L_DONE_EINT2 */ 5522 #define ARIZONA_HP2R_DONE_EINT2 0x0008 /* HP2R_DONE_EINT2 */ 5523 #define ARIZONA_HP2R_DONE_EINT2_MASK 0x0008 /* HP2R_DONE_EINT2 */ 5524 #define ARIZONA_HP2R_DONE_EINT2_SHIFT 3 /* HP2R_DONE_EINT2 */ 5525 #define ARIZONA_HP2R_DONE_EINT2_WIDTH 1 /* HP2R_DONE_EINT2 */ 5526 #define ARIZONA_HP2L_DONE_EINT2 0x0004 /* HP2L_DONE_EINT2 */ 5527 #define ARIZONA_HP2L_DONE_EINT2_MASK 0x0004 /* HP2L_DONE_EINT2 */ 5528 #define ARIZONA_HP2L_DONE_EINT2_SHIFT 2 /* HP2L_DONE_EINT2 */ 5529 #define ARIZONA_HP2L_DONE_EINT2_WIDTH 1 /* HP2L_DONE_EINT2 */ 5530 #define ARIZONA_HP1R_DONE_EINT2 0x0002 /* HP1R_DONE_EINT2 */ 5531 #define ARIZONA_HP1R_DONE_EINT2_MASK 0x0002 /* HP1R_DONE_EINT2 */ 5532 #define ARIZONA_HP1R_DONE_EINT2_SHIFT 1 /* HP1R_DONE_EINT2 */ 5533 #define ARIZONA_HP1R_DONE_EINT2_WIDTH 1 /* HP1R_DONE_EINT2 */ 5534 #define ARIZONA_HP1L_DONE_EINT2 0x0001 /* HP1L_DONE_EINT2 */ 5535 #define ARIZONA_HP1L_DONE_EINT2_MASK 0x0001 /* HP1L_DONE_EINT2 */ 5536 #define ARIZONA_HP1L_DONE_EINT2_SHIFT 0 /* HP1L_DONE_EINT2 */ 5537 #define ARIZONA_HP1L_DONE_EINT2_WIDTH 1 /* HP1L_DONE_EINT2 */ 5538 5539 /* 5540 * R3347 (0xD13) - IRQ2 Status 4 (Alternate layout) 5541 * 5542 * Alternate layout used on later devices, note only fields that have moved 5543 * are specified 5544 */ 5545 #define ARIZONA_V2_AIF3_ERR_EINT2 0x8000 /* AIF3_ERR_EINT2 */ 5546 #define ARIZONA_V2_AIF3_ERR_EINT2_MASK 0x8000 /* AIF3_ERR_EINT2 */ 5547 #define ARIZONA_V2_AIF3_ERR_EINT2_SHIFT 15 /* AIF3_ERR_EINT2 */ 5548 #define ARIZONA_V2_AIF3_ERR_EINT2_WIDTH 1 /* AIF3_ERR_EINT2 */ 5549 #define ARIZONA_V2_AIF2_ERR_EINT2 0x4000 /* AIF2_ERR_EINT2 */ 5550 #define ARIZONA_V2_AIF2_ERR_EINT2_MASK 0x4000 /* AIF2_ERR_EINT2 */ 5551 #define ARIZONA_V2_AIF2_ERR_EINT2_SHIFT 14 /* AIF2_ERR_EINT2 */ 5552 #define ARIZONA_V2_AIF2_ERR_EINT2_WIDTH 1 /* AIF2_ERR_EINT2 */ 5553 #define ARIZONA_V2_AIF1_ERR_EINT2 0x2000 /* AIF1_ERR_EINT2 */ 5554 #define ARIZONA_V2_AIF1_ERR_EINT2_MASK 0x2000 /* AIF1_ERR_EINT2 */ 5555 #define ARIZONA_V2_AIF1_ERR_EINT2_SHIFT 13 /* AIF1_ERR_EINT2 */ 5556 #define ARIZONA_V2_AIF1_ERR_EINT2_WIDTH 1 /* AIF1_ERR_EINT2 */ 5557 #define ARIZONA_V2_CTRLIF_ERR_EINT2 0x1000 /* CTRLIF_ERR_EINT2 */ 5558 #define ARIZONA_V2_CTRLIF_ERR_EINT2_MASK 0x1000 /* CTRLIF_ERR_EINT2 */ 5559 #define ARIZONA_V2_CTRLIF_ERR_EINT2_SHIFT 12 /* CTRLIF_ERR_EINT2 */ 5560 #define ARIZONA_V2_CTRLIF_ERR_EINT2_WIDTH 1 /* CTRLIF_ERR_EINT2 */ 5561 #define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2 0x0800 /* MIXER_DROPPED_SAMPLE_EINT2 */ 5562 #define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0800 /* MIXER_DROPPED_SAMPLE_EINT2 */ 5563 #define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 11 /* MIXER_DROPPED_SAMPLE_EINT2 */ 5564 #define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT2 */ 5565 #define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2 0x0400 /* ASYNC_CLK_ENA_LOW_EINT2 */ 5566 #define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0400 /* ASYNC_CLK_ENA_LOW_EINT2 */ 5567 #define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 10 /* ASYNC_CLK_ENA_LOW_EINT2 */ 5568 #define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT2 */ 5569 #define ARIZONA_V2_SYSCLK_ENA_LOW_EINT2 0x0200 /* SYSCLK_ENA_LOW_EINT2 */ 5570 #define ARIZONA_V2_SYSCLK_ENA_LOW_EINT2_MASK 0x0200 /* SYSCLK_ENA_LOW_EINT2 */ 5571 #define ARIZONA_V2_SYSCLK_ENA_LOW_EINT2_SHIFT 9 /* SYSCLK_ENA_LOW_EINT2 */ 5572 #define ARIZONA_V2_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* SYSCLK_ENA_LOW_EINT2 */ 5573 #define ARIZONA_V2_ISRC1_CFG_ERR_EINT2 0x0100 /* ISRC1_CFG_ERR_EINT2 */ 5574 #define ARIZONA_V2_ISRC1_CFG_ERR_EINT2_MASK 0x0100 /* ISRC1_CFG_ERR_EINT2 */ 5575 #define ARIZONA_V2_ISRC1_CFG_ERR_EINT2_SHIFT 8 /* ISRC1_CFG_ERR_EINT2 */ 5576 #define ARIZONA_V2_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* ISRC1_CFG_ERR_EINT2 */ 5577 #define ARIZONA_V2_ISRC2_CFG_ERR_EINT2 0x0080 /* ISRC2_CFG_ERR_EINT2 */ 5578 #define ARIZONA_V2_ISRC2_CFG_ERR_EINT2_MASK 0x0080 /* ISRC2_CFG_ERR_EINT2 */ 5579 #define ARIZONA_V2_ISRC2_CFG_ERR_EINT2_SHIFT 7 /* ISRC2_CFG_ERR_EINT2 */ 5580 #define ARIZONA_V2_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* ISRC2_CFG_ERR_EINT2 */ 5581 #define ARIZONA_V2_ISRC3_CFG_ERR_EINT2 0x0040 /* ISRC3_CFG_ERR_EINT2 */ 5582 #define ARIZONA_V2_ISRC3_CFG_ERR_EINT2_MASK 0x0040 /* ISRC3_CFG_ERR_EINT2 */ 5583 #define ARIZONA_V2_ISRC3_CFG_ERR_EINT2_SHIFT 6 /* ISRC3_CFG_ERR_EINT2 */ 5584 #define ARIZONA_V2_ISRC3_CFG_ERR_EINT2_WIDTH 1 /* ISRC3_CFG_ERR_EINT2 */ 5585 5586 /* 5587 * R3348 (0xD14) - IRQ2 Status 5 5588 */ 5589 #define ARIZONA_BOOT_DONE_EINT2 0x0100 /* BOOT_DONE_EINT2 */ 5590 #define ARIZONA_BOOT_DONE_EINT2_MASK 0x0100 /* BOOT_DONE_EINT2 */ 5591 #define ARIZONA_BOOT_DONE_EINT2_SHIFT 8 /* BOOT_DONE_EINT2 */ 5592 #define ARIZONA_BOOT_DONE_EINT2_WIDTH 1 /* BOOT_DONE_EINT2 */ 5593 #define ARIZONA_DCS_DAC_DONE_EINT2 0x0080 /* DCS_DAC_DONE_EINT2 */ 5594 #define ARIZONA_DCS_DAC_DONE_EINT2_MASK 0x0080 /* DCS_DAC_DONE_EINT2 */ 5595 #define ARIZONA_DCS_DAC_DONE_EINT2_SHIFT 7 /* DCS_DAC_DONE_EINT2 */ 5596 #define ARIZONA_DCS_DAC_DONE_EINT2_WIDTH 1 /* DCS_DAC_DONE_EINT2 */ 5597 #define ARIZONA_DCS_HP_DONE_EINT2 0x0040 /* DCS_HP_DONE_EINT2 */ 5598 #define ARIZONA_DCS_HP_DONE_EINT2_MASK 0x0040 /* DCS_HP_DONE_EINT2 */ 5599 #define ARIZONA_DCS_HP_DONE_EINT2_SHIFT 6 /* DCS_HP_DONE_EINT2 */ 5600 #define ARIZONA_DCS_HP_DONE_EINT2_WIDTH 1 /* DCS_HP_DONE_EINT2 */ 5601 #define ARIZONA_FLL2_CLOCK_OK_EINT2 0x0002 /* FLL2_CLOCK_OK_EINT2 */ 5602 #define ARIZONA_FLL2_CLOCK_OK_EINT2_MASK 0x0002 /* FLL2_CLOCK_OK_EINT2 */ 5603 #define ARIZONA_FLL2_CLOCK_OK_EINT2_SHIFT 1 /* FLL2_CLOCK_OK_EINT2 */ 5604 #define ARIZONA_FLL2_CLOCK_OK_EINT2_WIDTH 1 /* FLL2_CLOCK_OK_EINT2 */ 5605 #define ARIZONA_FLL1_CLOCK_OK_EINT2 0x0001 /* FLL1_CLOCK_OK_EINT2 */ 5606 #define ARIZONA_FLL1_CLOCK_OK_EINT2_MASK 0x0001 /* FLL1_CLOCK_OK_EINT2 */ 5607 #define ARIZONA_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* FLL1_CLOCK_OK_EINT2 */ 5608 #define ARIZONA_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* FLL1_CLOCK_OK_EINT2 */ 5609 5610 /* 5611 * R3348 (0xD14) - IRQ2 Status 5 (Alternate layout) 5612 * 5613 * Alternate layout used on later devices, note only fields that have moved 5614 * are specified 5615 */ 5616 #define ARIZONA_V2_ASRC_CFG_ERR_EINT2 0x0008 /* ASRC_CFG_ERR_EINT2 */ 5617 #define ARIZONA_V2_ASRC_CFG_ERR_EINT2_MASK 0x0008 /* ASRC_CFG_ERR_EINT2 */ 5618 #define ARIZONA_V2_ASRC_CFG_ERR_EINT2_SHIFT 3 /* ASRC_CFG_ERR_EINT2 */ 5619 #define ARIZONA_V2_ASRC_CFG_ERR_EINT2_WIDTH 1 /* ASRC_CFG_ERR_EINT2 */ 5620 5621 /* 5622 * R3349 (0xD15) - IRQ2 Status 6 5623 */ 5624 #define ARIZONA_DSP_SHARED_WR_COLL_EINT2 0x8000 /* DSP_SHARED_WR_COLL_EINT2 */ 5625 #define ARIZONA_DSP_SHARED_WR_COLL_EINT2_MASK 0x8000 /* DSP_SHARED_WR_COLL_EINT2 */ 5626 #define ARIZONA_DSP_SHARED_WR_COLL_EINT2_SHIFT 15 /* DSP_SHARED_WR_COLL_EINT2 */ 5627 #define ARIZONA_DSP_SHARED_WR_COLL_EINT2_WIDTH 1 /* DSP_SHARED_WR_COLL_EINT2 */ 5628 #define ARIZONA_SPK_SHUTDOWN_EINT2 0x4000 /* SPK_SHUTDOWN_EINT2 */ 5629 #define ARIZONA_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* SPK_SHUTDOWN_EINT2 */ 5630 #define ARIZONA_SPK_SHUTDOWN_EINT2_SHIFT 14 /* SPK_SHUTDOWN_EINT2 */ 5631 #define ARIZONA_SPK_SHUTDOWN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_EINT2 */ 5632 #define ARIZONA_SPK1R_SHORT_EINT2 0x2000 /* SPK1R_SHORT_EINT2 */ 5633 #define ARIZONA_SPK1R_SHORT_EINT2_MASK 0x2000 /* SPK1R_SHORT_EINT2 */ 5634 #define ARIZONA_SPK1R_SHORT_EINT2_SHIFT 13 /* SPK1R_SHORT_EINT2 */ 5635 #define ARIZONA_SPK1R_SHORT_EINT2_WIDTH 1 /* SPK1R_SHORT_EINT2 */ 5636 #define ARIZONA_SPK1L_SHORT_EINT2 0x1000 /* SPK1L_SHORT_EINT2 */ 5637 #define ARIZONA_SPK1L_SHORT_EINT2_MASK 0x1000 /* SPK1L_SHORT_EINT2 */ 5638 #define ARIZONA_SPK1L_SHORT_EINT2_SHIFT 12 /* SPK1L_SHORT_EINT2 */ 5639 #define ARIZONA_SPK1L_SHORT_EINT2_WIDTH 1 /* SPK1L_SHORT_EINT2 */ 5640 #define ARIZONA_HP3R_SC_NEG_EINT2 0x0800 /* HP3R_SC_NEG_EINT2 */ 5641 #define ARIZONA_HP3R_SC_NEG_EINT2_MASK 0x0800 /* HP3R_SC_NEG_EINT2 */ 5642 #define ARIZONA_HP3R_SC_NEG_EINT2_SHIFT 11 /* HP3R_SC_NEG_EINT2 */ 5643 #define ARIZONA_HP3R_SC_NEG_EINT2_WIDTH 1 /* HP3R_SC_NEG_EINT2 */ 5644 #define ARIZONA_HP3R_SC_POS_EINT2 0x0400 /* HP3R_SC_POS_EINT2 */ 5645 #define ARIZONA_HP3R_SC_POS_EINT2_MASK 0x0400 /* HP3R_SC_POS_EINT2 */ 5646 #define ARIZONA_HP3R_SC_POS_EINT2_SHIFT 10 /* HP3R_SC_POS_EINT2 */ 5647 #define ARIZONA_HP3R_SC_POS_EINT2_WIDTH 1 /* HP3R_SC_POS_EINT2 */ 5648 #define ARIZONA_HP3L_SC_NEG_EINT2 0x0200 /* HP3L_SC_NEG_EINT2 */ 5649 #define ARIZONA_HP3L_SC_NEG_EINT2_MASK 0x0200 /* HP3L_SC_NEG_EINT2 */ 5650 #define ARIZONA_HP3L_SC_NEG_EINT2_SHIFT 9 /* HP3L_SC_NEG_EINT2 */ 5651 #define ARIZONA_HP3L_SC_NEG_EINT2_WIDTH 1 /* HP3L_SC_NEG_EINT2 */ 5652 #define ARIZONA_HP3L_SC_POS_EINT2 0x0100 /* HP3L_SC_POS_EINT2 */ 5653 #define ARIZONA_HP3L_SC_POS_EINT2_MASK 0x0100 /* HP3L_SC_POS_EINT2 */ 5654 #define ARIZONA_HP3L_SC_POS_EINT2_SHIFT 8 /* HP3L_SC_POS_EINT2 */ 5655 #define ARIZONA_HP3L_SC_POS_EINT2_WIDTH 1 /* HP3L_SC_POS_EINT2 */ 5656 #define ARIZONA_HP2R_SC_NEG_EINT2 0x0080 /* HP2R_SC_NEG_EINT2 */ 5657 #define ARIZONA_HP2R_SC_NEG_EINT2_MASK 0x0080 /* HP2R_SC_NEG_EINT2 */ 5658 #define ARIZONA_HP2R_SC_NEG_EINT2_SHIFT 7 /* HP2R_SC_NEG_EINT2 */ 5659 #define ARIZONA_HP2R_SC_NEG_EINT2_WIDTH 1 /* HP2R_SC_NEG_EINT2 */ 5660 #define ARIZONA_HP2R_SC_POS_EINT2 0x0040 /* HP2R_SC_POS_EINT2 */ 5661 #define ARIZONA_HP2R_SC_POS_EINT2_MASK 0x0040 /* HP2R_SC_POS_EINT2 */ 5662 #define ARIZONA_HP2R_SC_POS_EINT2_SHIFT 6 /* HP2R_SC_POS_EINT2 */ 5663 #define ARIZONA_HP2R_SC_POS_EINT2_WIDTH 1 /* HP2R_SC_POS_EINT2 */ 5664 #define ARIZONA_HP2L_SC_NEG_EINT2 0x0020 /* HP2L_SC_NEG_EINT2 */ 5665 #define ARIZONA_HP2L_SC_NEG_EINT2_MASK 0x0020 /* HP2L_SC_NEG_EINT2 */ 5666 #define ARIZONA_HP2L_SC_NEG_EINT2_SHIFT 5 /* HP2L_SC_NEG_EINT2 */ 5667 #define ARIZONA_HP2L_SC_NEG_EINT2_WIDTH 1 /* HP2L_SC_NEG_EINT2 */ 5668 #define ARIZONA_HP2L_SC_POS_EINT2 0x0010 /* HP2L_SC_POS_EINT2 */ 5669 #define ARIZONA_HP2L_SC_POS_EINT2_MASK 0x0010 /* HP2L_SC_POS_EINT2 */ 5670 #define ARIZONA_HP2L_SC_POS_EINT2_SHIFT 4 /* HP2L_SC_POS_EINT2 */ 5671 #define ARIZONA_HP2L_SC_POS_EINT2_WIDTH 1 /* HP2L_SC_POS_EINT2 */ 5672 #define ARIZONA_HP1R_SC_NEG_EINT2 0x0008 /* HP1R_SC_NEG_EINT2 */ 5673 #define ARIZONA_HP1R_SC_NEG_EINT2_MASK 0x0008 /* HP1R_SC_NEG_EINT2 */ 5674 #define ARIZONA_HP1R_SC_NEG_EINT2_SHIFT 3 /* HP1R_SC_NEG_EINT2 */ 5675 #define ARIZONA_HP1R_SC_NEG_EINT2_WIDTH 1 /* HP1R_SC_NEG_EINT2 */ 5676 #define ARIZONA_HP1R_SC_POS_EINT2 0x0004 /* HP1R_SC_POS_EINT2 */ 5677 #define ARIZONA_HP1R_SC_POS_EINT2_MASK 0x0004 /* HP1R_SC_POS_EINT2 */ 5678 #define ARIZONA_HP1R_SC_POS_EINT2_SHIFT 2 /* HP1R_SC_POS_EINT2 */ 5679 #define ARIZONA_HP1R_SC_POS_EINT2_WIDTH 1 /* HP1R_SC_POS_EINT2 */ 5680 #define ARIZONA_HP1L_SC_NEG_EINT2 0x0002 /* HP1L_SC_NEG_EINT2 */ 5681 #define ARIZONA_HP1L_SC_NEG_EINT2_MASK 0x0002 /* HP1L_SC_NEG_EINT2 */ 5682 #define ARIZONA_HP1L_SC_NEG_EINT2_SHIFT 1 /* HP1L_SC_NEG_EINT2 */ 5683 #define ARIZONA_HP1L_SC_NEG_EINT2_WIDTH 1 /* HP1L_SC_NEG_EINT2 */ 5684 #define ARIZONA_HP1L_SC_POS_EINT2 0x0001 /* HP1L_SC_POS_EINT2 */ 5685 #define ARIZONA_HP1L_SC_POS_EINT2_MASK 0x0001 /* HP1L_SC_POS_EINT2 */ 5686 #define ARIZONA_HP1L_SC_POS_EINT2_SHIFT 0 /* HP1L_SC_POS_EINT2 */ 5687 #define ARIZONA_HP1L_SC_POS_EINT2_WIDTH 1 /* HP1L_SC_POS_EINT2 */ 5688 5689 /* 5690 * R3352 (0xD18) - IRQ2 Status 1 Mask 5691 */ 5692 #define ARIZONA_IM_GP4_EINT2 0x0008 /* IM_GP4_EINT2 */ 5693 #define ARIZONA_IM_GP4_EINT2_MASK 0x0008 /* IM_GP4_EINT2 */ 5694 #define ARIZONA_IM_GP4_EINT2_SHIFT 3 /* IM_GP4_EINT2 */ 5695 #define ARIZONA_IM_GP4_EINT2_WIDTH 1 /* IM_GP4_EINT2 */ 5696 #define ARIZONA_IM_GP3_EINT2 0x0004 /* IM_GP3_EINT2 */ 5697 #define ARIZONA_IM_GP3_EINT2_MASK 0x0004 /* IM_GP3_EINT2 */ 5698 #define ARIZONA_IM_GP3_EINT2_SHIFT 2 /* IM_GP3_EINT2 */ 5699 #define ARIZONA_IM_GP3_EINT2_WIDTH 1 /* IM_GP3_EINT2 */ 5700 #define ARIZONA_IM_GP2_EINT2 0x0002 /* IM_GP2_EINT2 */ 5701 #define ARIZONA_IM_GP2_EINT2_MASK 0x0002 /* IM_GP2_EINT2 */ 5702 #define ARIZONA_IM_GP2_EINT2_SHIFT 1 /* IM_GP2_EINT2 */ 5703 #define ARIZONA_IM_GP2_EINT2_WIDTH 1 /* IM_GP2_EINT2 */ 5704 #define ARIZONA_IM_GP1_EINT2 0x0001 /* IM_GP1_EINT2 */ 5705 #define ARIZONA_IM_GP1_EINT2_MASK 0x0001 /* IM_GP1_EINT2 */ 5706 #define ARIZONA_IM_GP1_EINT2_SHIFT 0 /* IM_GP1_EINT2 */ 5707 #define ARIZONA_IM_GP1_EINT2_WIDTH 1 /* IM_GP1_EINT2 */ 5708 5709 /* 5710 * R3353 (0xD19) - IRQ2 Status 2 Mask 5711 */ 5712 #define ARIZONA_IM_DSP1_RAM_RDY_EINT2 0x0100 /* IM_DSP1_RAM_RDY_EINT2 */ 5713 #define ARIZONA_IM_DSP1_RAM_RDY_EINT2_MASK 0x0100 /* IM_DSP1_RAM_RDY_EINT2 */ 5714 #define ARIZONA_IM_DSP1_RAM_RDY_EINT2_SHIFT 8 /* IM_DSP1_RAM_RDY_EINT2 */ 5715 #define ARIZONA_IM_DSP1_RAM_RDY_EINT2_WIDTH 1 /* IM_DSP1_RAM_RDY_EINT2 */ 5716 #define ARIZONA_IM_DSP_IRQ2_EINT2 0x0002 /* IM_DSP_IRQ2_EINT2 */ 5717 #define ARIZONA_IM_DSP_IRQ2_EINT2_MASK 0x0002 /* IM_DSP_IRQ2_EINT2 */ 5718 #define ARIZONA_IM_DSP_IRQ2_EINT2_SHIFT 1 /* IM_DSP_IRQ2_EINT2 */ 5719 #define ARIZONA_IM_DSP_IRQ2_EINT2_WIDTH 1 /* IM_DSP_IRQ2_EINT2 */ 5720 #define ARIZONA_IM_DSP_IRQ1_EINT2 0x0001 /* IM_DSP_IRQ1_EINT2 */ 5721 #define ARIZONA_IM_DSP_IRQ1_EINT2_MASK 0x0001 /* IM_DSP_IRQ1_EINT2 */ 5722 #define ARIZONA_IM_DSP_IRQ1_EINT2_SHIFT 0 /* IM_DSP_IRQ1_EINT2 */ 5723 #define ARIZONA_IM_DSP_IRQ1_EINT2_WIDTH 1 /* IM_DSP_IRQ1_EINT2 */ 5724 5725 /* 5726 * R3354 (0xD1A) - IRQ2 Status 3 Mask 5727 */ 5728 #define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2 0x8000 /* IM_SPK_OVERHEAT_WARN_EINT2 */ 5729 #define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2_MASK 0x8000 /* IM_SPK_OVERHEAT_WARN_EINT2 */ 5730 #define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2_SHIFT 15 /* IM_SPK_OVERHEAT_WARN_EINT2 */ 5731 #define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2_WIDTH 1 /* IM_SPK_OVERHEAT_WARN_EINT2 */ 5732 #define ARIZONA_IM_SPK_OVERHEAT_EINT2 0x4000 /* IM_SPK_OVERHEAT_EINT2 */ 5733 #define ARIZONA_IM_SPK_OVERHEAT_EINT2_MASK 0x4000 /* IM_SPK_OVERHEAT_EINT2 */ 5734 #define ARIZONA_IM_SPK_OVERHEAT_EINT2_SHIFT 14 /* IM_SPK_OVERHEAT_EINT2 */ 5735 #define ARIZONA_IM_SPK_OVERHEAT_EINT2_WIDTH 1 /* IM_SPK_OVERHEAT_EINT2 */ 5736 #define ARIZONA_IM_HPDET_EINT2 0x2000 /* IM_HPDET_EINT2 */ 5737 #define ARIZONA_IM_HPDET_EINT2_MASK 0x2000 /* IM_HPDET_EINT2 */ 5738 #define ARIZONA_IM_HPDET_EINT2_SHIFT 13 /* IM_HPDET_EINT2 */ 5739 #define ARIZONA_IM_HPDET_EINT2_WIDTH 1 /* IM_HPDET_EINT2 */ 5740 #define ARIZONA_IM_MICDET_EINT2 0x1000 /* IM_MICDET_EINT2 */ 5741 #define ARIZONA_IM_MICDET_EINT2_MASK 0x1000 /* IM_MICDET_EINT2 */ 5742 #define ARIZONA_IM_MICDET_EINT2_SHIFT 12 /* IM_MICDET_EINT2 */ 5743 #define ARIZONA_IM_MICDET_EINT2_WIDTH 1 /* IM_MICDET_EINT2 */ 5744 #define ARIZONA_IM_WSEQ_DONE_EINT2 0x0800 /* IM_WSEQ_DONE_EINT2 */ 5745 #define ARIZONA_IM_WSEQ_DONE_EINT2_MASK 0x0800 /* IM_WSEQ_DONE_EINT2 */ 5746 #define ARIZONA_IM_WSEQ_DONE_EINT2_SHIFT 11 /* IM_WSEQ_DONE_EINT2 */ 5747 #define ARIZONA_IM_WSEQ_DONE_EINT2_WIDTH 1 /* IM_WSEQ_DONE_EINT2 */ 5748 #define ARIZONA_IM_DRC2_SIG_DET_EINT2 0x0400 /* IM_DRC2_SIG_DET_EINT2 */ 5749 #define ARIZONA_IM_DRC2_SIG_DET_EINT2_MASK 0x0400 /* IM_DRC2_SIG_DET_EINT2 */ 5750 #define ARIZONA_IM_DRC2_SIG_DET_EINT2_SHIFT 10 /* IM_DRC2_SIG_DET_EINT2 */ 5751 #define ARIZONA_IM_DRC2_SIG_DET_EINT2_WIDTH 1 /* IM_DRC2_SIG_DET_EINT2 */ 5752 #define ARIZONA_IM_DRC1_SIG_DET_EINT2 0x0200 /* IM_DRC1_SIG_DET_EINT2 */ 5753 #define ARIZONA_IM_DRC1_SIG_DET_EINT2_MASK 0x0200 /* IM_DRC1_SIG_DET_EINT2 */ 5754 #define ARIZONA_IM_DRC1_SIG_DET_EINT2_SHIFT 9 /* IM_DRC1_SIG_DET_EINT2 */ 5755 #define ARIZONA_IM_DRC1_SIG_DET_EINT2_WIDTH 1 /* IM_DRC1_SIG_DET_EINT2 */ 5756 #define ARIZONA_IM_ASRC2_LOCK_EINT2 0x0100 /* IM_ASRC2_LOCK_EINT2 */ 5757 #define ARIZONA_IM_ASRC2_LOCK_EINT2_MASK 0x0100 /* IM_ASRC2_LOCK_EINT2 */ 5758 #define ARIZONA_IM_ASRC2_LOCK_EINT2_SHIFT 8 /* IM_ASRC2_LOCK_EINT2 */ 5759 #define ARIZONA_IM_ASRC2_LOCK_EINT2_WIDTH 1 /* IM_ASRC2_LOCK_EINT2 */ 5760 #define ARIZONA_IM_ASRC1_LOCK_EINT2 0x0080 /* IM_ASRC1_LOCK_EINT2 */ 5761 #define ARIZONA_IM_ASRC1_LOCK_EINT2_MASK 0x0080 /* IM_ASRC1_LOCK_EINT2 */ 5762 #define ARIZONA_IM_ASRC1_LOCK_EINT2_SHIFT 7 /* IM_ASRC1_LOCK_EINT2 */ 5763 #define ARIZONA_IM_ASRC1_LOCK_EINT2_WIDTH 1 /* IM_ASRC1_LOCK_EINT2 */ 5764 #define ARIZONA_IM_UNDERCLOCKED_EINT2 0x0040 /* IM_UNDERCLOCKED_EINT2 */ 5765 #define ARIZONA_IM_UNDERCLOCKED_EINT2_MASK 0x0040 /* IM_UNDERCLOCKED_EINT2 */ 5766 #define ARIZONA_IM_UNDERCLOCKED_EINT2_SHIFT 6 /* IM_UNDERCLOCKED_EINT2 */ 5767 #define ARIZONA_IM_UNDERCLOCKED_EINT2_WIDTH 1 /* IM_UNDERCLOCKED_EINT2 */ 5768 #define ARIZONA_IM_OVERCLOCKED_EINT2 0x0020 /* IM_OVERCLOCKED_EINT2 */ 5769 #define ARIZONA_IM_OVERCLOCKED_EINT2_MASK 0x0020 /* IM_OVERCLOCKED_EINT2 */ 5770 #define ARIZONA_IM_OVERCLOCKED_EINT2_SHIFT 5 /* IM_OVERCLOCKED_EINT2 */ 5771 #define ARIZONA_IM_OVERCLOCKED_EINT2_WIDTH 1 /* IM_OVERCLOCKED_EINT2 */ 5772 #define ARIZONA_IM_FLL2_LOCK_EINT2 0x0008 /* IM_FLL2_LOCK_EINT2 */ 5773 #define ARIZONA_IM_FLL2_LOCK_EINT2_MASK 0x0008 /* IM_FLL2_LOCK_EINT2 */ 5774 #define ARIZONA_IM_FLL2_LOCK_EINT2_SHIFT 3 /* IM_FLL2_LOCK_EINT2 */ 5775 #define ARIZONA_IM_FLL2_LOCK_EINT2_WIDTH 1 /* IM_FLL2_LOCK_EINT2 */ 5776 #define ARIZONA_IM_FLL1_LOCK_EINT2 0x0004 /* IM_FLL1_LOCK_EINT2 */ 5777 #define ARIZONA_IM_FLL1_LOCK_EINT2_MASK 0x0004 /* IM_FLL1_LOCK_EINT2 */ 5778 #define ARIZONA_IM_FLL1_LOCK_EINT2_SHIFT 2 /* IM_FLL1_LOCK_EINT2 */ 5779 #define ARIZONA_IM_FLL1_LOCK_EINT2_WIDTH 1 /* IM_FLL1_LOCK_EINT2 */ 5780 #define ARIZONA_IM_CLKGEN_ERR_EINT2 0x0002 /* IM_CLKGEN_ERR_EINT2 */ 5781 #define ARIZONA_IM_CLKGEN_ERR_EINT2_MASK 0x0002 /* IM_CLKGEN_ERR_EINT2 */ 5782 #define ARIZONA_IM_CLKGEN_ERR_EINT2_SHIFT 1 /* IM_CLKGEN_ERR_EINT2 */ 5783 #define ARIZONA_IM_CLKGEN_ERR_EINT2_WIDTH 1 /* IM_CLKGEN_ERR_EINT2 */ 5784 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT2 */ 5785 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT2 */ 5786 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT2 */ 5787 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT2 */ 5788 5789 /* 5790 * R3355 (0xD1B) - IRQ2 Status 4 Mask 5791 */ 5792 #define ARIZONA_IM_ASRC_CFG_ERR_EINT2 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */ 5793 #define ARIZONA_IM_ASRC_CFG_ERR_EINT2_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */ 5794 #define ARIZONA_IM_ASRC_CFG_ERR_EINT2_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT2 */ 5795 #define ARIZONA_IM_ASRC_CFG_ERR_EINT2_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT2 */ 5796 #define ARIZONA_IM_AIF3_ERR_EINT2 0x4000 /* IM_AIF3_ERR_EINT2 */ 5797 #define ARIZONA_IM_AIF3_ERR_EINT2_MASK 0x4000 /* IM_AIF3_ERR_EINT2 */ 5798 #define ARIZONA_IM_AIF3_ERR_EINT2_SHIFT 14 /* IM_AIF3_ERR_EINT2 */ 5799 #define ARIZONA_IM_AIF3_ERR_EINT2_WIDTH 1 /* IM_AIF3_ERR_EINT2 */ 5800 #define ARIZONA_IM_AIF2_ERR_EINT2 0x2000 /* IM_AIF2_ERR_EINT2 */ 5801 #define ARIZONA_IM_AIF2_ERR_EINT2_MASK 0x2000 /* IM_AIF2_ERR_EINT2 */ 5802 #define ARIZONA_IM_AIF2_ERR_EINT2_SHIFT 13 /* IM_AIF2_ERR_EINT2 */ 5803 #define ARIZONA_IM_AIF2_ERR_EINT2_WIDTH 1 /* IM_AIF2_ERR_EINT2 */ 5804 #define ARIZONA_IM_AIF1_ERR_EINT2 0x1000 /* IM_AIF1_ERR_EINT2 */ 5805 #define ARIZONA_IM_AIF1_ERR_EINT2_MASK 0x1000 /* IM_AIF1_ERR_EINT2 */ 5806 #define ARIZONA_IM_AIF1_ERR_EINT2_SHIFT 12 /* IM_AIF1_ERR_EINT2 */ 5807 #define ARIZONA_IM_AIF1_ERR_EINT2_WIDTH 1 /* IM_AIF1_ERR_EINT2 */ 5808 #define ARIZONA_IM_CTRLIF_ERR_EINT2 0x0800 /* IM_CTRLIF_ERR_EINT2 */ 5809 #define ARIZONA_IM_CTRLIF_ERR_EINT2_MASK 0x0800 /* IM_CTRLIF_ERR_EINT2 */ 5810 #define ARIZONA_IM_CTRLIF_ERR_EINT2_SHIFT 11 /* IM_CTRLIF_ERR_EINT2 */ 5811 #define ARIZONA_IM_CTRLIF_ERR_EINT2_WIDTH 1 /* IM_CTRLIF_ERR_EINT2 */ 5812 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ 5813 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ 5814 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ 5815 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ 5816 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ 5817 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ 5818 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ 5819 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ 5820 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */ 5821 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */ 5822 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT2 */ 5823 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT2 */ 5824 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */ 5825 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */ 5826 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT2 */ 5827 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT2 */ 5828 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */ 5829 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */ 5830 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT2 */ 5831 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT2 */ 5832 #define ARIZONA_IM_HP3R_DONE_EINT2 0x0020 /* IM_HP3R_DONE_EINT2 */ 5833 #define ARIZONA_IM_HP3R_DONE_EINT2_MASK 0x0020 /* IM_HP3R_DONE_EINT2 */ 5834 #define ARIZONA_IM_HP3R_DONE_EINT2_SHIFT 5 /* IM_HP3R_DONE_EINT2 */ 5835 #define ARIZONA_IM_HP3R_DONE_EINT2_WIDTH 1 /* IM_HP3R_DONE_EINT2 */ 5836 #define ARIZONA_IM_HP3L_DONE_EINT2 0x0010 /* IM_HP3L_DONE_EINT2 */ 5837 #define ARIZONA_IM_HP3L_DONE_EINT2_MASK 0x0010 /* IM_HP3L_DONE_EINT2 */ 5838 #define ARIZONA_IM_HP3L_DONE_EINT2_SHIFT 4 /* IM_HP3L_DONE_EINT2 */ 5839 #define ARIZONA_IM_HP3L_DONE_EINT2_WIDTH 1 /* IM_HP3L_DONE_EINT2 */ 5840 #define ARIZONA_IM_HP2R_DONE_EINT2 0x0008 /* IM_HP2R_DONE_EINT2 */ 5841 #define ARIZONA_IM_HP2R_DONE_EINT2_MASK 0x0008 /* IM_HP2R_DONE_EINT2 */ 5842 #define ARIZONA_IM_HP2R_DONE_EINT2_SHIFT 3 /* IM_HP2R_DONE_EINT2 */ 5843 #define ARIZONA_IM_HP2R_DONE_EINT2_WIDTH 1 /* IM_HP2R_DONE_EINT2 */ 5844 #define ARIZONA_IM_HP2L_DONE_EINT2 0x0004 /* IM_HP2L_DONE_EINT2 */ 5845 #define ARIZONA_IM_HP2L_DONE_EINT2_MASK 0x0004 /* IM_HP2L_DONE_EINT2 */ 5846 #define ARIZONA_IM_HP2L_DONE_EINT2_SHIFT 2 /* IM_HP2L_DONE_EINT2 */ 5847 #define ARIZONA_IM_HP2L_DONE_EINT2_WIDTH 1 /* IM_HP2L_DONE_EINT2 */ 5848 #define ARIZONA_IM_HP1R_DONE_EINT2 0x0002 /* IM_HP1R_DONE_EINT2 */ 5849 #define ARIZONA_IM_HP1R_DONE_EINT2_MASK 0x0002 /* IM_HP1R_DONE_EINT2 */ 5850 #define ARIZONA_IM_HP1R_DONE_EINT2_SHIFT 1 /* IM_HP1R_DONE_EINT2 */ 5851 #define ARIZONA_IM_HP1R_DONE_EINT2_WIDTH 1 /* IM_HP1R_DONE_EINT2 */ 5852 #define ARIZONA_IM_HP1L_DONE_EINT2 0x0001 /* IM_HP1L_DONE_EINT2 */ 5853 #define ARIZONA_IM_HP1L_DONE_EINT2_MASK 0x0001 /* IM_HP1L_DONE_EINT2 */ 5854 #define ARIZONA_IM_HP1L_DONE_EINT2_SHIFT 0 /* IM_HP1L_DONE_EINT2 */ 5855 #define ARIZONA_IM_HP1L_DONE_EINT2_WIDTH 1 /* IM_HP1L_DONE_EINT2 */ 5856 5857 /* 5858 * R3355 (0xD1B) - IRQ2 Status 4 Mask (Alternate layout) 5859 * 5860 * Alternate layout used on later devices, note only fields that have moved 5861 * are specified 5862 */ 5863 #define ARIZONA_V2_IM_AIF3_ERR_EINT2 0x8000 /* IM_AIF3_ERR_EINT2 */ 5864 #define ARIZONA_V2_IM_AIF3_ERR_EINT2_MASK 0x8000 /* IM_AIF3_ERR_EINT2 */ 5865 #define ARIZONA_V2_IM_AIF3_ERR_EINT2_SHIFT 15 /* IM_AIF3_ERR_EINT2 */ 5866 #define ARIZONA_V2_IM_AIF3_ERR_EINT2_WIDTH 1 /* IM_AIF3_ERR_EINT2 */ 5867 #define ARIZONA_V2_IM_AIF2_ERR_EINT2 0x4000 /* IM_AIF2_ERR_EINT2 */ 5868 #define ARIZONA_V2_IM_AIF2_ERR_EINT2_MASK 0x4000 /* IM_AIF2_ERR_EINT2 */ 5869 #define ARIZONA_V2_IM_AIF2_ERR_EINT2_SHIFT 14 /* IM_AIF2_ERR_EINT2 */ 5870 #define ARIZONA_V2_IM_AIF2_ERR_EINT2_WIDTH 1 /* IM_AIF2_ERR_EINT2 */ 5871 #define ARIZONA_V2_IM_AIF1_ERR_EINT2 0x2000 /* IM_AIF1_ERR_EINT2 */ 5872 #define ARIZONA_V2_IM_AIF1_ERR_EINT2_MASK 0x2000 /* IM_AIF1_ERR_EINT2 */ 5873 #define ARIZONA_V2_IM_AIF1_ERR_EINT2_SHIFT 13 /* IM_AIF1_ERR_EINT2 */ 5874 #define ARIZONA_V2_IM_AIF1_ERR_EINT2_WIDTH 1 /* IM_AIF1_ERR_EINT2 */ 5875 #define ARIZONA_V2_IM_CTRLIF_ERR_EINT2 0x1000 /* IM_CTRLIF_ERR_EINT2 */ 5876 #define ARIZONA_V2_IM_CTRLIF_ERR_EINT2_MASK 0x1000 /* IM_CTRLIF_ERR_EINT2 */ 5877 #define ARIZONA_V2_IM_CTRLIF_ERR_EINT2_SHIFT 12 /* IM_CTRLIF_ERR_EINT2 */ 5878 #define ARIZONA_V2_IM_CTRLIF_ERR_EINT2_WIDTH 1 /* IM_CTRLIF_ERR_EINT2 */ 5879 #define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2 0x0800 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ 5880 #define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0800 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ 5881 #define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 11 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ 5882 #define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ 5883 #define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2 0x0400 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ 5884 #define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0400 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ 5885 #define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 10 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ 5886 #define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ 5887 #define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2 0x0200 /* IM_SYSCLK_ENA_LOW_EINT2 */ 5888 #define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2_MASK 0x0200 /* IM_SYSCLK_ENA_LOW_EINT2 */ 5889 #define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2_SHIFT 9 /* IM_SYSCLK_ENA_LOW_EINT2 */ 5890 #define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT2 */ 5891 #define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2 0x0100 /* IM_ISRC1_CFG_ERR_EINT2 */ 5892 #define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2_MASK 0x0100 /* IM_ISRC1_CFG_ERR_EINT2 */ 5893 #define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2_SHIFT 8 /* IM_ISRC1_CFG_ERR_EINT2 */ 5894 #define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT2 */ 5895 #define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2 0x0080 /* IM_ISRC2_CFG_ERR_EINT2 */ 5896 #define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2_MASK 0x0080 /* IM_ISRC2_CFG_ERR_EINT2 */ 5897 #define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2_SHIFT 7 /* IM_ISRC2_CFG_ERR_EINT2 */ 5898 #define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT2 */ 5899 #define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2 0x0040 /* IM_ISRC3_CFG_ERR_EINT2 */ 5900 #define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2_MASK 0x0040 /* IM_ISRC3_CFG_ERR_EINT2 */ 5901 #define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2_SHIFT 6 /* IM_ISRC3_CFG_ERR_EINT2 */ 5902 #define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC3_CFG_ERR_EINT2 */ 5903 5904 /* 5905 * R3356 (0xD1C) - IRQ2 Status 5 Mask 5906 */ 5907 5908 #define ARIZONA_IM_BOOT_DONE_EINT2 0x0100 /* IM_BOOT_DONE_EINT2 */ 5909 #define ARIZONA_IM_BOOT_DONE_EINT2_MASK 0x0100 /* IM_BOOT_DONE_EINT2 */ 5910 #define ARIZONA_IM_BOOT_DONE_EINT2_SHIFT 8 /* IM_BOOT_DONE_EINT2 */ 5911 #define ARIZONA_IM_BOOT_DONE_EINT2_WIDTH 1 /* IM_BOOT_DONE_EINT2 */ 5912 #define ARIZONA_IM_DCS_DAC_DONE_EINT2 0x0080 /* IM_DCS_DAC_DONE_EINT2 */ 5913 #define ARIZONA_IM_DCS_DAC_DONE_EINT2_MASK 0x0080 /* IM_DCS_DAC_DONE_EINT2 */ 5914 #define ARIZONA_IM_DCS_DAC_DONE_EINT2_SHIFT 7 /* IM_DCS_DAC_DONE_EINT2 */ 5915 #define ARIZONA_IM_DCS_DAC_DONE_EINT2_WIDTH 1 /* IM_DCS_DAC_DONE_EINT2 */ 5916 #define ARIZONA_IM_DCS_HP_DONE_EINT2 0x0040 /* IM_DCS_HP_DONE_EINT2 */ 5917 #define ARIZONA_IM_DCS_HP_DONE_EINT2_MASK 0x0040 /* IM_DCS_HP_DONE_EINT2 */ 5918 #define ARIZONA_IM_DCS_HP_DONE_EINT2_SHIFT 6 /* IM_DCS_HP_DONE_EINT2 */ 5919 #define ARIZONA_IM_DCS_HP_DONE_EINT2_WIDTH 1 /* IM_DCS_HP_DONE_EINT2 */ 5920 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2 0x0002 /* IM_FLL2_CLOCK_OK_EINT2 */ 5921 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_MASK 0x0002 /* IM_FLL2_CLOCK_OK_EINT2 */ 5922 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_SHIFT 1 /* IM_FLL2_CLOCK_OK_EINT2 */ 5923 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_WIDTH 1 /* IM_FLL2_CLOCK_OK_EINT2 */ 5924 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2 0x0001 /* IM_FLL1_CLOCK_OK_EINT2 */ 5925 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_MASK 0x0001 /* IM_FLL1_CLOCK_OK_EINT2 */ 5926 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT2 */ 5927 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT2 */ 5928 5929 /* 5930 * R3340 (0xD0C) - Interrupt Status 5 Mask (Alternate layout) 5931 * 5932 * Alternate layout used on later devices, note only fields that have moved 5933 * are specified 5934 */ 5935 #define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2 0x0008 /* IM_ASRC_CFG_ERR_EINT2 */ 5936 #define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2_MASK 0x0008 /* IM_ASRC_CFG_ERR_EINT2 */ 5937 #define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2_SHIFT 3 /* IM_ASRC_CFG_ERR_EINT2 */ 5938 #define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT2 */ 5939 5940 /* 5941 * R3357 (0xD1D) - IRQ2 Status 6 Mask 5942 */ 5943 #define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT2 */ 5944 #define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2_MASK 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT2 */ 5945 #define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2_SHIFT 15 /* IM_DSP_SHARED_WR_COLL_EINT2 */ 5946 #define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2_WIDTH 1 /* IM_DSP_SHARED_WR_COLL_EINT2 */ 5947 #define ARIZONA_IM_SPK_SHUTDOWN_EINT2 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */ 5948 #define ARIZONA_IM_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */ 5949 #define ARIZONA_IM_SPK_SHUTDOWN_EINT2_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT2 */ 5950 #define ARIZONA_IM_SPK_SHUTDOWN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT2 */ 5951 #define ARIZONA_IM_SPK1R_SHORT_EINT2 0x2000 /* IM_SPK1R_SHORT_EINT2 */ 5952 #define ARIZONA_IM_SPK1R_SHORT_EINT2_MASK 0x2000 /* IM_SPK1R_SHORT_EINT2 */ 5953 #define ARIZONA_IM_SPK1R_SHORT_EINT2_SHIFT 13 /* IM_SPK1R_SHORT_EINT2 */ 5954 #define ARIZONA_IM_SPK1R_SHORT_EINT2_WIDTH 1 /* IM_SPK1R_SHORT_EINT2 */ 5955 #define ARIZONA_IM_SPK1L_SHORT_EINT2 0x1000 /* IM_SPK1L_SHORT_EINT2 */ 5956 #define ARIZONA_IM_SPK1L_SHORT_EINT2_MASK 0x1000 /* IM_SPK1L_SHORT_EINT2 */ 5957 #define ARIZONA_IM_SPK1L_SHORT_EINT2_SHIFT 12 /* IM_SPK1L_SHORT_EINT2 */ 5958 #define ARIZONA_IM_SPK1L_SHORT_EINT2_WIDTH 1 /* IM_SPK1L_SHORT_EINT2 */ 5959 #define ARIZONA_IM_HP3R_SC_NEG_EINT2 0x0800 /* IM_HP3R_SC_NEG_EINT2 */ 5960 #define ARIZONA_IM_HP3R_SC_NEG_EINT2_MASK 0x0800 /* IM_HP3R_SC_NEG_EINT2 */ 5961 #define ARIZONA_IM_HP3R_SC_NEG_EINT2_SHIFT 11 /* IM_HP3R_SC_NEG_EINT2 */ 5962 #define ARIZONA_IM_HP3R_SC_NEG_EINT2_WIDTH 1 /* IM_HP3R_SC_NEG_EINT2 */ 5963 #define ARIZONA_IM_HP3R_SC_POS_EINT2 0x0400 /* IM_HP3R_SC_POS_EINT2 */ 5964 #define ARIZONA_IM_HP3R_SC_POS_EINT2_MASK 0x0400 /* IM_HP3R_SC_POS_EINT2 */ 5965 #define ARIZONA_IM_HP3R_SC_POS_EINT2_SHIFT 10 /* IM_HP3R_SC_POS_EINT2 */ 5966 #define ARIZONA_IM_HP3R_SC_POS_EINT2_WIDTH 1 /* IM_HP3R_SC_POS_EINT2 */ 5967 #define ARIZONA_IM_HP3L_SC_NEG_EINT2 0x0200 /* IM_HP3L_SC_NEG_EINT2 */ 5968 #define ARIZONA_IM_HP3L_SC_NEG_EINT2_MASK 0x0200 /* IM_HP3L_SC_NEG_EINT2 */ 5969 #define ARIZONA_IM_HP3L_SC_NEG_EINT2_SHIFT 9 /* IM_HP3L_SC_NEG_EINT2 */ 5970 #define ARIZONA_IM_HP3L_SC_NEG_EINT2_WIDTH 1 /* IM_HP3L_SC_NEG_EINT2 */ 5971 #define ARIZONA_IM_HP3L_SC_POS_EINT2 0x0100 /* IM_HP3L_SC_POS_EINT2 */ 5972 #define ARIZONA_IM_HP3L_SC_POS_EINT2_MASK 0x0100 /* IM_HP3L_SC_POS_EINT2 */ 5973 #define ARIZONA_IM_HP3L_SC_POS_EINT2_SHIFT 8 /* IM_HP3L_SC_POS_EINT2 */ 5974 #define ARIZONA_IM_HP3L_SC_POS_EINT2_WIDTH 1 /* IM_HP3L_SC_POS_EINT2 */ 5975 #define ARIZONA_IM_HP2R_SC_NEG_EINT2 0x0080 /* IM_HP2R_SC_NEG_EINT2 */ 5976 #define ARIZONA_IM_HP2R_SC_NEG_EINT2_MASK 0x0080 /* IM_HP2R_SC_NEG_EINT2 */ 5977 #define ARIZONA_IM_HP2R_SC_NEG_EINT2_SHIFT 7 /* IM_HP2R_SC_NEG_EINT2 */ 5978 #define ARIZONA_IM_HP2R_SC_NEG_EINT2_WIDTH 1 /* IM_HP2R_SC_NEG_EINT2 */ 5979 #define ARIZONA_IM_HP2R_SC_POS_EINT2 0x0040 /* IM_HP2R_SC_POS_EINT2 */ 5980 #define ARIZONA_IM_HP2R_SC_POS_EINT2_MASK 0x0040 /* IM_HP2R_SC_POS_EINT2 */ 5981 #define ARIZONA_IM_HP2R_SC_POS_EINT2_SHIFT 6 /* IM_HP2R_SC_POS_EINT2 */ 5982 #define ARIZONA_IM_HP2R_SC_POS_EINT2_WIDTH 1 /* IM_HP2R_SC_POS_EINT2 */ 5983 #define ARIZONA_IM_HP2L_SC_NEG_EINT2 0x0020 /* IM_HP2L_SC_NEG_EINT2 */ 5984 #define ARIZONA_IM_HP2L_SC_NEG_EINT2_MASK 0x0020 /* IM_HP2L_SC_NEG_EINT2 */ 5985 #define ARIZONA_IM_HP2L_SC_NEG_EINT2_SHIFT 5 /* IM_HP2L_SC_NEG_EINT2 */ 5986 #define ARIZONA_IM_HP2L_SC_NEG_EINT2_WIDTH 1 /* IM_HP2L_SC_NEG_EINT2 */ 5987 #define ARIZONA_IM_HP2L_SC_POS_EINT2 0x0010 /* IM_HP2L_SC_POS_EINT2 */ 5988 #define ARIZONA_IM_HP2L_SC_POS_EINT2_MASK 0x0010 /* IM_HP2L_SC_POS_EINT2 */ 5989 #define ARIZONA_IM_HP2L_SC_POS_EINT2_SHIFT 4 /* IM_HP2L_SC_POS_EINT2 */ 5990 #define ARIZONA_IM_HP2L_SC_POS_EINT2_WIDTH 1 /* IM_HP2L_SC_POS_EINT2 */ 5991 #define ARIZONA_IM_HP1R_SC_NEG_EINT2 0x0008 /* IM_HP1R_SC_NEG_EINT2 */ 5992 #define ARIZONA_IM_HP1R_SC_NEG_EINT2_MASK 0x0008 /* IM_HP1R_SC_NEG_EINT2 */ 5993 #define ARIZONA_IM_HP1R_SC_NEG_EINT2_SHIFT 3 /* IM_HP1R_SC_NEG_EINT2 */ 5994 #define ARIZONA_IM_HP1R_SC_NEG_EINT2_WIDTH 1 /* IM_HP1R_SC_NEG_EINT2 */ 5995 #define ARIZONA_IM_HP1R_SC_POS_EINT2 0x0004 /* IM_HP1R_SC_POS_EINT2 */ 5996 #define ARIZONA_IM_HP1R_SC_POS_EINT2_MASK 0x0004 /* IM_HP1R_SC_POS_EINT2 */ 5997 #define ARIZONA_IM_HP1R_SC_POS_EINT2_SHIFT 2 /* IM_HP1R_SC_POS_EINT2 */ 5998 #define ARIZONA_IM_HP1R_SC_POS_EINT2_WIDTH 1 /* IM_HP1R_SC_POS_EINT2 */ 5999 #define ARIZONA_IM_HP1L_SC_NEG_EINT2 0x0002 /* IM_HP1L_SC_NEG_EINT2 */ 6000 #define ARIZONA_IM_HP1L_SC_NEG_EINT2_MASK 0x0002 /* IM_HP1L_SC_NEG_EINT2 */ 6001 #define ARIZONA_IM_HP1L_SC_NEG_EINT2_SHIFT 1 /* IM_HP1L_SC_NEG_EINT2 */ 6002 #define ARIZONA_IM_HP1L_SC_NEG_EINT2_WIDTH 1 /* IM_HP1L_SC_NEG_EINT2 */ 6003 #define ARIZONA_IM_HP1L_SC_POS_EINT2 0x0001 /* IM_HP1L_SC_POS_EINT2 */ 6004 #define ARIZONA_IM_HP1L_SC_POS_EINT2_MASK 0x0001 /* IM_HP1L_SC_POS_EINT2 */ 6005 #define ARIZONA_IM_HP1L_SC_POS_EINT2_SHIFT 0 /* IM_HP1L_SC_POS_EINT2 */ 6006 #define ARIZONA_IM_HP1L_SC_POS_EINT2_WIDTH 1 /* IM_HP1L_SC_POS_EINT2 */ 6007 6008 /* 6009 * R3359 (0xD1F) - IRQ2 Control 6010 */ 6011 #define ARIZONA_IM_IRQ2 0x0001 /* IM_IRQ2 */ 6012 #define ARIZONA_IM_IRQ2_MASK 0x0001 /* IM_IRQ2 */ 6013 #define ARIZONA_IM_IRQ2_SHIFT 0 /* IM_IRQ2 */ 6014 #define ARIZONA_IM_IRQ2_WIDTH 1 /* IM_IRQ2 */ 6015 6016 /* 6017 * R3360 (0xD20) - Interrupt Raw Status 2 6018 */ 6019 #define ARIZONA_DSP1_RAM_RDY_STS 0x0100 /* DSP1_RAM_RDY_STS */ 6020 #define ARIZONA_DSP1_RAM_RDY_STS_MASK 0x0100 /* DSP1_RAM_RDY_STS */ 6021 #define ARIZONA_DSP1_RAM_RDY_STS_SHIFT 8 /* DSP1_RAM_RDY_STS */ 6022 #define ARIZONA_DSP1_RAM_RDY_STS_WIDTH 1 /* DSP1_RAM_RDY_STS */ 6023 #define ARIZONA_DSP_IRQ2_STS 0x0002 /* DSP_IRQ2_STS */ 6024 #define ARIZONA_DSP_IRQ2_STS_MASK 0x0002 /* DSP_IRQ2_STS */ 6025 #define ARIZONA_DSP_IRQ2_STS_SHIFT 1 /* DSP_IRQ2_STS */ 6026 #define ARIZONA_DSP_IRQ2_STS_WIDTH 1 /* DSP_IRQ2_STS */ 6027 #define ARIZONA_DSP_IRQ1_STS 0x0001 /* DSP_IRQ1_STS */ 6028 #define ARIZONA_DSP_IRQ1_STS_MASK 0x0001 /* DSP_IRQ1_STS */ 6029 #define ARIZONA_DSP_IRQ1_STS_SHIFT 0 /* DSP_IRQ1_STS */ 6030 #define ARIZONA_DSP_IRQ1_STS_WIDTH 1 /* DSP_IRQ1_STS */ 6031 6032 /* 6033 * R3361 (0xD21) - Interrupt Raw Status 3 6034 */ 6035 #define ARIZONA_SPK_OVERHEAT_WARN_STS 0x8000 /* SPK_OVERHEAT_WARN_STS */ 6036 #define ARIZONA_SPK_OVERHEAT_WARN_STS_MASK 0x8000 /* SPK_OVERHEAT_WARN_STS */ 6037 #define ARIZONA_SPK_OVERHEAT_WARN_STS_SHIFT 15 /* SPK_OVERHEAT_WARN_STS */ 6038 #define ARIZONA_SPK_OVERHEAT_WARN_STS_WIDTH 1 /* SPK_OVERHEAT_WARN_STS */ 6039 #define ARIZONA_SPK_OVERHEAT_STS 0x4000 /* SPK_OVERHEAT_STS */ 6040 #define ARIZONA_SPK_OVERHEAT_STS_MASK 0x4000 /* SPK_OVERHEAT_STS */ 6041 #define ARIZONA_SPK_OVERHEAT_STS_SHIFT 14 /* SPK_OVERHEAT_STS */ 6042 #define ARIZONA_SPK_OVERHEAT_STS_WIDTH 1 /* SPK_OVERHEAT_STS */ 6043 #define ARIZONA_HPDET_STS 0x2000 /* HPDET_STS */ 6044 #define ARIZONA_HPDET_STS_MASK 0x2000 /* HPDET_STS */ 6045 #define ARIZONA_HPDET_STS_SHIFT 13 /* HPDET_STS */ 6046 #define ARIZONA_HPDET_STS_WIDTH 1 /* HPDET_STS */ 6047 #define ARIZONA_MICDET_STS 0x1000 /* MICDET_STS */ 6048 #define ARIZONA_MICDET_STS_MASK 0x1000 /* MICDET_STS */ 6049 #define ARIZONA_MICDET_STS_SHIFT 12 /* MICDET_STS */ 6050 #define ARIZONA_MICDET_STS_WIDTH 1 /* MICDET_STS */ 6051 #define ARIZONA_WSEQ_DONE_STS 0x0800 /* WSEQ_DONE_STS */ 6052 #define ARIZONA_WSEQ_DONE_STS_MASK 0x0800 /* WSEQ_DONE_STS */ 6053 #define ARIZONA_WSEQ_DONE_STS_SHIFT 11 /* WSEQ_DONE_STS */ 6054 #define ARIZONA_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */ 6055 #define ARIZONA_DRC2_SIG_DET_STS 0x0400 /* DRC2_SIG_DET_STS */ 6056 #define ARIZONA_DRC2_SIG_DET_STS_MASK 0x0400 /* DRC2_SIG_DET_STS */ 6057 #define ARIZONA_DRC2_SIG_DET_STS_SHIFT 10 /* DRC2_SIG_DET_STS */ 6058 #define ARIZONA_DRC2_SIG_DET_STS_WIDTH 1 /* DRC2_SIG_DET_STS */ 6059 #define ARIZONA_DRC1_SIG_DET_STS 0x0200 /* DRC1_SIG_DET_STS */ 6060 #define ARIZONA_DRC1_SIG_DET_STS_MASK 0x0200 /* DRC1_SIG_DET_STS */ 6061 #define ARIZONA_DRC1_SIG_DET_STS_SHIFT 9 /* DRC1_SIG_DET_STS */ 6062 #define ARIZONA_DRC1_SIG_DET_STS_WIDTH 1 /* DRC1_SIG_DET_STS */ 6063 #define ARIZONA_ASRC2_LOCK_STS 0x0100 /* ASRC2_LOCK_STS */ 6064 #define ARIZONA_ASRC2_LOCK_STS_MASK 0x0100 /* ASRC2_LOCK_STS */ 6065 #define ARIZONA_ASRC2_LOCK_STS_SHIFT 8 /* ASRC2_LOCK_STS */ 6066 #define ARIZONA_ASRC2_LOCK_STS_WIDTH 1 /* ASRC2_LOCK_STS */ 6067 #define ARIZONA_ASRC1_LOCK_STS 0x0080 /* ASRC1_LOCK_STS */ 6068 #define ARIZONA_ASRC1_LOCK_STS_MASK 0x0080 /* ASRC1_LOCK_STS */ 6069 #define ARIZONA_ASRC1_LOCK_STS_SHIFT 7 /* ASRC1_LOCK_STS */ 6070 #define ARIZONA_ASRC1_LOCK_STS_WIDTH 1 /* ASRC1_LOCK_STS */ 6071 #define ARIZONA_UNDERCLOCKED_STS 0x0040 /* UNDERCLOCKED_STS */ 6072 #define ARIZONA_UNDERCLOCKED_STS_MASK 0x0040 /* UNDERCLOCKED_STS */ 6073 #define ARIZONA_UNDERCLOCKED_STS_SHIFT 6 /* UNDERCLOCKED_STS */ 6074 #define ARIZONA_UNDERCLOCKED_STS_WIDTH 1 /* UNDERCLOCKED_STS */ 6075 #define ARIZONA_OVERCLOCKED_STS 0x0020 /* OVERCLOCKED_STS */ 6076 #define ARIZONA_OVERCLOCKED_STS_MASK 0x0020 /* OVERCLOCKED_STS */ 6077 #define ARIZONA_OVERCLOCKED_STS_SHIFT 5 /* OVERCLOCKED_STS */ 6078 #define ARIZONA_OVERCLOCKED_STS_WIDTH 1 /* OVERCLOCKED_STS */ 6079 #define ARIZONA_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */ 6080 #define ARIZONA_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */ 6081 #define ARIZONA_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */ 6082 #define ARIZONA_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */ 6083 #define ARIZONA_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */ 6084 #define ARIZONA_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */ 6085 #define ARIZONA_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */ 6086 #define ARIZONA_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */ 6087 #define ARIZONA_CLKGEN_ERR_STS 0x0002 /* CLKGEN_ERR_STS */ 6088 #define ARIZONA_CLKGEN_ERR_STS_MASK 0x0002 /* CLKGEN_ERR_STS */ 6089 #define ARIZONA_CLKGEN_ERR_STS_SHIFT 1 /* CLKGEN_ERR_STS */ 6090 #define ARIZONA_CLKGEN_ERR_STS_WIDTH 1 /* CLKGEN_ERR_STS */ 6091 #define ARIZONA_CLKGEN_ERR_ASYNC_STS 0x0001 /* CLKGEN_ERR_ASYNC_STS */ 6092 #define ARIZONA_CLKGEN_ERR_ASYNC_STS_MASK 0x0001 /* CLKGEN_ERR_ASYNC_STS */ 6093 #define ARIZONA_CLKGEN_ERR_ASYNC_STS_SHIFT 0 /* CLKGEN_ERR_ASYNC_STS */ 6094 #define ARIZONA_CLKGEN_ERR_ASYNC_STS_WIDTH 1 /* CLKGEN_ERR_ASYNC_STS */ 6095 6096 /* 6097 * R3362 (0xD22) - Interrupt Raw Status 4 6098 */ 6099 #define ARIZONA_ASRC_CFG_ERR_STS 0x8000 /* ASRC_CFG_ERR_STS */ 6100 #define ARIZONA_ASRC_CFG_ERR_STS_MASK 0x8000 /* ASRC_CFG_ERR_STS */ 6101 #define ARIZONA_ASRC_CFG_ERR_STS_SHIFT 15 /* ASRC_CFG_ERR_STS */ 6102 #define ARIZONA_ASRC_CFG_ERR_STS_WIDTH 1 /* ASRC_CFG_ERR_STS */ 6103 #define ARIZONA_AIF3_ERR_STS 0x4000 /* AIF3_ERR_STS */ 6104 #define ARIZONA_AIF3_ERR_STS_MASK 0x4000 /* AIF3_ERR_STS */ 6105 #define ARIZONA_AIF3_ERR_STS_SHIFT 14 /* AIF3_ERR_STS */ 6106 #define ARIZONA_AIF3_ERR_STS_WIDTH 1 /* AIF3_ERR_STS */ 6107 #define ARIZONA_AIF2_ERR_STS 0x2000 /* AIF2_ERR_STS */ 6108 #define ARIZONA_AIF2_ERR_STS_MASK 0x2000 /* AIF2_ERR_STS */ 6109 #define ARIZONA_AIF2_ERR_STS_SHIFT 13 /* AIF2_ERR_STS */ 6110 #define ARIZONA_AIF2_ERR_STS_WIDTH 1 /* AIF2_ERR_STS */ 6111 #define ARIZONA_AIF1_ERR_STS 0x1000 /* AIF1_ERR_STS */ 6112 #define ARIZONA_AIF1_ERR_STS_MASK 0x1000 /* AIF1_ERR_STS */ 6113 #define ARIZONA_AIF1_ERR_STS_SHIFT 12 /* AIF1_ERR_STS */ 6114 #define ARIZONA_AIF1_ERR_STS_WIDTH 1 /* AIF1_ERR_STS */ 6115 #define ARIZONA_CTRLIF_ERR_STS 0x0800 /* CTRLIF_ERR_STS */ 6116 #define ARIZONA_CTRLIF_ERR_STS_MASK 0x0800 /* CTRLIF_ERR_STS */ 6117 #define ARIZONA_CTRLIF_ERR_STS_SHIFT 11 /* CTRLIF_ERR_STS */ 6118 #define ARIZONA_CTRLIF_ERR_STS_WIDTH 1 /* CTRLIF_ERR_STS */ 6119 #define ARIZONA_MIXER_DROPPED_SAMPLE_STS 0x0400 /* MIXER_DROPPED_SAMPLE_STS */ 6120 #define ARIZONA_MIXER_DROPPED_SAMPLE_STS_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_STS */ 6121 #define ARIZONA_MIXER_DROPPED_SAMPLE_STS_SHIFT 10 /* MIXER_DROPPED_SAMPLE_STS */ 6122 #define ARIZONA_MIXER_DROPPED_SAMPLE_STS_WIDTH 1 /* MIXER_DROPPED_SAMPLE_STS */ 6123 #define ARIZONA_ASYNC_CLK_ENA_LOW_STS 0x0200 /* ASYNC_CLK_ENA_LOW_STS */ 6124 #define ARIZONA_ASYNC_CLK_ENA_LOW_STS_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_STS */ 6125 #define ARIZONA_ASYNC_CLK_ENA_LOW_STS_SHIFT 9 /* ASYNC_CLK_ENA_LOW_STS */ 6126 #define ARIZONA_ASYNC_CLK_ENA_LOW_STS_WIDTH 1 /* ASYNC_CLK_ENA_LOW_STS */ 6127 #define ARIZONA_SYSCLK_ENA_LOW_STS 0x0100 /* SYSCLK_ENA_LOW_STS */ 6128 #define ARIZONA_SYSCLK_ENA_LOW_STS_MASK 0x0100 /* SYSCLK_ENA_LOW_STS */ 6129 #define ARIZONA_SYSCLK_ENA_LOW_STS_SHIFT 8 /* SYSCLK_ENA_LOW_STS */ 6130 #define ARIZONA_SYSCLK_ENA_LOW_STS_WIDTH 1 /* SYSCLK_ENA_LOW_STS */ 6131 #define ARIZONA_ISRC1_CFG_ERR_STS 0x0080 /* ISRC1_CFG_ERR_STS */ 6132 #define ARIZONA_ISRC1_CFG_ERR_STS_MASK 0x0080 /* ISRC1_CFG_ERR_STS */ 6133 #define ARIZONA_ISRC1_CFG_ERR_STS_SHIFT 7 /* ISRC1_CFG_ERR_STS */ 6134 #define ARIZONA_ISRC1_CFG_ERR_STS_WIDTH 1 /* ISRC1_CFG_ERR_STS */ 6135 #define ARIZONA_ISRC2_CFG_ERR_STS 0x0040 /* ISRC2_CFG_ERR_STS */ 6136 #define ARIZONA_ISRC2_CFG_ERR_STS_MASK 0x0040 /* ISRC2_CFG_ERR_STS */ 6137 #define ARIZONA_ISRC2_CFG_ERR_STS_SHIFT 6 /* ISRC2_CFG_ERR_STS */ 6138 #define ARIZONA_ISRC2_CFG_ERR_STS_WIDTH 1 /* ISRC2_CFG_ERR_STS */ 6139 #define ARIZONA_HP3R_DONE_STS 0x0020 /* HP3R_DONE_STS */ 6140 #define ARIZONA_HP3R_DONE_STS_MASK 0x0020 /* HP3R_DONE_STS */ 6141 #define ARIZONA_HP3R_DONE_STS_SHIFT 5 /* HP3R_DONE_STS */ 6142 #define ARIZONA_HP3R_DONE_STS_WIDTH 1 /* HP3R_DONE_STS */ 6143 #define ARIZONA_HP3L_DONE_STS 0x0010 /* HP3L_DONE_STS */ 6144 #define ARIZONA_HP3L_DONE_STS_MASK 0x0010 /* HP3L_DONE_STS */ 6145 #define ARIZONA_HP3L_DONE_STS_SHIFT 4 /* HP3L_DONE_STS */ 6146 #define ARIZONA_HP3L_DONE_STS_WIDTH 1 /* HP3L_DONE_STS */ 6147 #define ARIZONA_HP2R_DONE_STS 0x0008 /* HP2R_DONE_STS */ 6148 #define ARIZONA_HP2R_DONE_STS_MASK 0x0008 /* HP2R_DONE_STS */ 6149 #define ARIZONA_HP2R_DONE_STS_SHIFT 3 /* HP2R_DONE_STS */ 6150 #define ARIZONA_HP2R_DONE_STS_WIDTH 1 /* HP2R_DONE_STS */ 6151 #define ARIZONA_HP2L_DONE_STS 0x0004 /* HP2L_DONE_STS */ 6152 #define ARIZONA_HP2L_DONE_STS_MASK 0x0004 /* HP2L_DONE_STS */ 6153 #define ARIZONA_HP2L_DONE_STS_SHIFT 2 /* HP2L_DONE_STS */ 6154 #define ARIZONA_HP2L_DONE_STS_WIDTH 1 /* HP2L_DONE_STS */ 6155 #define ARIZONA_HP1R_DONE_STS 0x0002 /* HP1R_DONE_STS */ 6156 #define ARIZONA_HP1R_DONE_STS_MASK 0x0002 /* HP1R_DONE_STS */ 6157 #define ARIZONA_HP1R_DONE_STS_SHIFT 1 /* HP1R_DONE_STS */ 6158 #define ARIZONA_HP1R_DONE_STS_WIDTH 1 /* HP1R_DONE_STS */ 6159 #define ARIZONA_HP1L_DONE_STS 0x0001 /* HP1L_DONE_STS */ 6160 #define ARIZONA_HP1L_DONE_STS_MASK 0x0001 /* HP1L_DONE_STS */ 6161 #define ARIZONA_HP1L_DONE_STS_SHIFT 0 /* HP1L_DONE_STS */ 6162 #define ARIZONA_HP1L_DONE_STS_WIDTH 1 /* HP1L_DONE_STS */ 6163 6164 /* 6165 * R3363 (0xD23) - Interrupt Raw Status 5 6166 */ 6167 #define ARIZONA_BOOT_DONE_STS 0x0100 /* BOOT_DONE_STS */ 6168 #define ARIZONA_BOOT_DONE_STS_MASK 0x0100 /* BOOT_DONE_STS */ 6169 #define ARIZONA_BOOT_DONE_STS_SHIFT 8 /* BOOT_DONE_STS */ 6170 #define ARIZONA_BOOT_DONE_STS_WIDTH 1 /* BOOT_DONE_STS */ 6171 #define ARIZONA_DCS_DAC_DONE_STS 0x0080 /* DCS_DAC_DONE_STS */ 6172 #define ARIZONA_DCS_DAC_DONE_STS_MASK 0x0080 /* DCS_DAC_DONE_STS */ 6173 #define ARIZONA_DCS_DAC_DONE_STS_SHIFT 7 /* DCS_DAC_DONE_STS */ 6174 #define ARIZONA_DCS_DAC_DONE_STS_WIDTH 1 /* DCS_DAC_DONE_STS */ 6175 #define ARIZONA_DCS_HP_DONE_STS 0x0040 /* DCS_HP_DONE_STS */ 6176 #define ARIZONA_DCS_HP_DONE_STS_MASK 0x0040 /* DCS_HP_DONE_STS */ 6177 #define ARIZONA_DCS_HP_DONE_STS_SHIFT 6 /* DCS_HP_DONE_STS */ 6178 #define ARIZONA_DCS_HP_DONE_STS_WIDTH 1 /* DCS_HP_DONE_STS */ 6179 #define ARIZONA_FLL2_CLOCK_OK_STS 0x0002 /* FLL2_CLOCK_OK_STS */ 6180 #define ARIZONA_FLL2_CLOCK_OK_STS_MASK 0x0002 /* FLL2_CLOCK_OK_STS */ 6181 #define ARIZONA_FLL2_CLOCK_OK_STS_SHIFT 1 /* FLL2_CLOCK_OK_STS */ 6182 #define ARIZONA_FLL2_CLOCK_OK_STS_WIDTH 1 /* FLL2_CLOCK_OK_STS */ 6183 #define ARIZONA_FLL1_CLOCK_OK_STS 0x0001 /* FLL1_CLOCK_OK_STS */ 6184 #define ARIZONA_FLL1_CLOCK_OK_STS_MASK 0x0001 /* FLL1_CLOCK_OK_STS */ 6185 #define ARIZONA_FLL1_CLOCK_OK_STS_SHIFT 0 /* FLL1_CLOCK_OK_STS */ 6186 #define ARIZONA_FLL1_CLOCK_OK_STS_WIDTH 1 /* FLL1_CLOCK_OK_STS */ 6187 6188 /* 6189 * R3364 (0xD24) - Interrupt Raw Status 6 6190 */ 6191 #define ARIZONA_PWM_OVERCLOCKED_STS 0x2000 /* PWM_OVERCLOCKED_STS */ 6192 #define ARIZONA_PWM_OVERCLOCKED_STS_MASK 0x2000 /* PWM_OVERCLOCKED_STS */ 6193 #define ARIZONA_PWM_OVERCLOCKED_STS_SHIFT 13 /* PWM_OVERCLOCKED_STS */ 6194 #define ARIZONA_PWM_OVERCLOCKED_STS_WIDTH 1 /* PWM_OVERCLOCKED_STS */ 6195 #define ARIZONA_FX_CORE_OVERCLOCKED_STS 0x1000 /* FX_CORE_OVERCLOCKED_STS */ 6196 #define ARIZONA_FX_CORE_OVERCLOCKED_STS_MASK 0x1000 /* FX_CORE_OVERCLOCKED_STS */ 6197 #define ARIZONA_FX_CORE_OVERCLOCKED_STS_SHIFT 12 /* FX_CORE_OVERCLOCKED_STS */ 6198 #define ARIZONA_FX_CORE_OVERCLOCKED_STS_WIDTH 1 /* FX_CORE_OVERCLOCKED_STS */ 6199 #define ARIZONA_DAC_SYS_OVERCLOCKED_STS 0x0400 /* DAC_SYS_OVERCLOCKED_STS */ 6200 #define ARIZONA_DAC_SYS_OVERCLOCKED_STS_MASK 0x0400 /* DAC_SYS_OVERCLOCKED_STS */ 6201 #define ARIZONA_DAC_SYS_OVERCLOCKED_STS_SHIFT 10 /* DAC_SYS_OVERCLOCKED_STS */ 6202 #define ARIZONA_DAC_SYS_OVERCLOCKED_STS_WIDTH 1 /* DAC_SYS_OVERCLOCKED_STS */ 6203 #define ARIZONA_DAC_WARP_OVERCLOCKED_STS 0x0200 /* DAC_WARP_OVERCLOCKED_STS */ 6204 #define ARIZONA_DAC_WARP_OVERCLOCKED_STS_MASK 0x0200 /* DAC_WARP_OVERCLOCKED_STS */ 6205 #define ARIZONA_DAC_WARP_OVERCLOCKED_STS_SHIFT 9 /* DAC_WARP_OVERCLOCKED_STS */ 6206 #define ARIZONA_DAC_WARP_OVERCLOCKED_STS_WIDTH 1 /* DAC_WARP_OVERCLOCKED_STS */ 6207 #define ARIZONA_ADC_OVERCLOCKED_STS 0x0100 /* ADC_OVERCLOCKED_STS */ 6208 #define ARIZONA_ADC_OVERCLOCKED_STS_MASK 0x0100 /* ADC_OVERCLOCKED_STS */ 6209 #define ARIZONA_ADC_OVERCLOCKED_STS_SHIFT 8 /* ADC_OVERCLOCKED_STS */ 6210 #define ARIZONA_ADC_OVERCLOCKED_STS_WIDTH 1 /* ADC_OVERCLOCKED_STS */ 6211 #define ARIZONA_MIXER_OVERCLOCKED_STS 0x0080 /* MIXER_OVERCLOCKED_STS */ 6212 #define ARIZONA_MIXER_OVERCLOCKED_STS_MASK 0x0080 /* MIXER_OVERCLOCKED_STS */ 6213 #define ARIZONA_MIXER_OVERCLOCKED_STS_SHIFT 7 /* MIXER_OVERCLOCKED_STS */ 6214 #define ARIZONA_MIXER_OVERCLOCKED_STS_WIDTH 1 /* MIXER_OVERCLOCKED_STS */ 6215 #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS 0x0040 /* AIF3_ASYNC_OVERCLOCKED_STS */ 6216 #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_MASK 0x0040 /* AIF3_ASYNC_OVERCLOCKED_STS */ 6217 #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_SHIFT 6 /* AIF3_ASYNC_OVERCLOCKED_STS */ 6218 #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF3_ASYNC_OVERCLOCKED_STS */ 6219 #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS 0x0020 /* AIF2_ASYNC_OVERCLOCKED_STS */ 6220 #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_MASK 0x0020 /* AIF2_ASYNC_OVERCLOCKED_STS */ 6221 #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_SHIFT 5 /* AIF2_ASYNC_OVERCLOCKED_STS */ 6222 #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF2_ASYNC_OVERCLOCKED_STS */ 6223 #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS 0x0010 /* AIF1_ASYNC_OVERCLOCKED_STS */ 6224 #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_MASK 0x0010 /* AIF1_ASYNC_OVERCLOCKED_STS */ 6225 #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_SHIFT 4 /* AIF1_ASYNC_OVERCLOCKED_STS */ 6226 #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF1_ASYNC_OVERCLOCKED_STS */ 6227 #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS 0x0008 /* AIF3_SYNC_OVERCLOCKED_STS */ 6228 #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_MASK 0x0008 /* AIF3_SYNC_OVERCLOCKED_STS */ 6229 #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_SHIFT 3 /* AIF3_SYNC_OVERCLOCKED_STS */ 6230 #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF3_SYNC_OVERCLOCKED_STS */ 6231 #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS 0x0004 /* AIF2_SYNC_OVERCLOCKED_STS */ 6232 #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_MASK 0x0004 /* AIF2_SYNC_OVERCLOCKED_STS */ 6233 #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_SHIFT 2 /* AIF2_SYNC_OVERCLOCKED_STS */ 6234 #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF2_SYNC_OVERCLOCKED_STS */ 6235 #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS 0x0002 /* AIF1_SYNC_OVERCLOCKED_STS */ 6236 #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_MASK 0x0002 /* AIF1_SYNC_OVERCLOCKED_STS */ 6237 #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_SHIFT 1 /* AIF1_SYNC_OVERCLOCKED_STS */ 6238 #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF1_SYNC_OVERCLOCKED_STS */ 6239 #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS 0x0001 /* PAD_CTRL_OVERCLOCKED_STS */ 6240 #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_MASK 0x0001 /* PAD_CTRL_OVERCLOCKED_STS */ 6241 #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_SHIFT 0 /* PAD_CTRL_OVERCLOCKED_STS */ 6242 #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_WIDTH 1 /* PAD_CTRL_OVERCLOCKED_STS */ 6243 6244 /* 6245 * R3365 (0xD25) - Interrupt Raw Status 7 6246 */ 6247 #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */ 6248 #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_MASK 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */ 6249 #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_SHIFT 15 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */ 6250 #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */ 6251 #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */ 6252 #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_MASK 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */ 6253 #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_SHIFT 14 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */ 6254 #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */ 6255 #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */ 6256 #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_MASK 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */ 6257 #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_SHIFT 13 /* SLIMBUS_SYNC_OVERCLOCKED_STS */ 6258 #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SYNC_OVERCLOCKED_STS */ 6259 #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */ 6260 #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_MASK 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */ 6261 #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_SHIFT 12 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */ 6262 #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */ 6263 #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */ 6264 #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_MASK 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */ 6265 #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_SHIFT 11 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */ 6266 #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */ 6267 #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */ 6268 #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_MASK 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */ 6269 #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_SHIFT 10 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */ 6270 #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */ 6271 #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */ 6272 #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_MASK 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */ 6273 #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_SHIFT 9 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */ 6274 #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */ 6275 #define ARIZONA_ADSP2_1_OVERCLOCKED_STS 0x0008 /* ADSP2_1_OVERCLOCKED_STS */ 6276 #define ARIZONA_ADSP2_1_OVERCLOCKED_STS_MASK 0x0008 /* ADSP2_1_OVERCLOCKED_STS */ 6277 #define ARIZONA_ADSP2_1_OVERCLOCKED_STS_SHIFT 3 /* ADSP2_1_OVERCLOCKED_STS */ 6278 #define ARIZONA_ADSP2_1_OVERCLOCKED_STS_WIDTH 1 /* ADSP2_1_OVERCLOCKED_STS */ 6279 #define ARIZONA_ISRC3_OVERCLOCKED_STS 0x0004 /* ISRC3_OVERCLOCKED_STS */ 6280 #define ARIZONA_ISRC3_OVERCLOCKED_STS_MASK 0x0004 /* ISRC3_OVERCLOCKED_STS */ 6281 #define ARIZONA_ISRC3_OVERCLOCKED_STS_SHIFT 2 /* ISRC3_OVERCLOCKED_STS */ 6282 #define ARIZONA_ISRC3_OVERCLOCKED_STS_WIDTH 1 /* ISRC3_OVERCLOCKED_STS */ 6283 #define ARIZONA_ISRC2_OVERCLOCKED_STS 0x0002 /* ISRC2_OVERCLOCKED_STS */ 6284 #define ARIZONA_ISRC2_OVERCLOCKED_STS_MASK 0x0002 /* ISRC2_OVERCLOCKED_STS */ 6285 #define ARIZONA_ISRC2_OVERCLOCKED_STS_SHIFT 1 /* ISRC2_OVERCLOCKED_STS */ 6286 #define ARIZONA_ISRC2_OVERCLOCKED_STS_WIDTH 1 /* ISRC2_OVERCLOCKED_STS */ 6287 #define ARIZONA_ISRC1_OVERCLOCKED_STS 0x0001 /* ISRC1_OVERCLOCKED_STS */ 6288 #define ARIZONA_ISRC1_OVERCLOCKED_STS_MASK 0x0001 /* ISRC1_OVERCLOCKED_STS */ 6289 #define ARIZONA_ISRC1_OVERCLOCKED_STS_SHIFT 0 /* ISRC1_OVERCLOCKED_STS */ 6290 #define ARIZONA_ISRC1_OVERCLOCKED_STS_WIDTH 1 /* ISRC1_OVERCLOCKED_STS */ 6291 6292 /* 6293 * R3366 (0xD26) - Interrupt Raw Status 8 6294 */ 6295 #define ARIZONA_AIF3_UNDERCLOCKED_STS 0x0400 /* AIF3_UNDERCLOCKED_STS */ 6296 #define ARIZONA_AIF3_UNDERCLOCKED_STS_MASK 0x0400 /* AIF3_UNDERCLOCKED_STS */ 6297 #define ARIZONA_AIF3_UNDERCLOCKED_STS_SHIFT 10 /* AIF3_UNDERCLOCKED_STS */ 6298 #define ARIZONA_AIF3_UNDERCLOCKED_STS_WIDTH 1 /* AIF3_UNDERCLOCKED_STS */ 6299 #define ARIZONA_AIF2_UNDERCLOCKED_STS 0x0200 /* AIF2_UNDERCLOCKED_STS */ 6300 #define ARIZONA_AIF2_UNDERCLOCKED_STS_MASK 0x0200 /* AIF2_UNDERCLOCKED_STS */ 6301 #define ARIZONA_AIF2_UNDERCLOCKED_STS_SHIFT 9 /* AIF2_UNDERCLOCKED_STS */ 6302 #define ARIZONA_AIF2_UNDERCLOCKED_STS_WIDTH 1 /* AIF2_UNDERCLOCKED_STS */ 6303 #define ARIZONA_AIF1_UNDERCLOCKED_STS 0x0100 /* AIF1_UNDERCLOCKED_STS */ 6304 #define ARIZONA_AIF1_UNDERCLOCKED_STS_MASK 0x0100 /* AIF1_UNDERCLOCKED_STS */ 6305 #define ARIZONA_AIF1_UNDERCLOCKED_STS_SHIFT 8 /* AIF1_UNDERCLOCKED_STS */ 6306 #define ARIZONA_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */ 6307 #define ARIZONA_ISRC3_UNDERCLOCKED_STS 0x0080 /* ISRC3_UNDERCLOCKED_STS */ 6308 #define ARIZONA_ISRC3_UNDERCLOCKED_STS_MASK 0x0080 /* ISRC3_UNDERCLOCKED_STS */ 6309 #define ARIZONA_ISRC3_UNDERCLOCKED_STS_SHIFT 7 /* ISRC3_UNDERCLOCKED_STS */ 6310 #define ARIZONA_ISRC3_UNDERCLOCKED_STS_WIDTH 1 /* ISRC3_UNDERCLOCKED_STS */ 6311 #define ARIZONA_ISRC2_UNDERCLOCKED_STS 0x0040 /* ISRC2_UNDERCLOCKED_STS */ 6312 #define ARIZONA_ISRC2_UNDERCLOCKED_STS_MASK 0x0040 /* ISRC2_UNDERCLOCKED_STS */ 6313 #define ARIZONA_ISRC2_UNDERCLOCKED_STS_SHIFT 6 /* ISRC2_UNDERCLOCKED_STS */ 6314 #define ARIZONA_ISRC2_UNDERCLOCKED_STS_WIDTH 1 /* ISRC2_UNDERCLOCKED_STS */ 6315 #define ARIZONA_ISRC1_UNDERCLOCKED_STS 0x0020 /* ISRC1_UNDERCLOCKED_STS */ 6316 #define ARIZONA_ISRC1_UNDERCLOCKED_STS_MASK 0x0020 /* ISRC1_UNDERCLOCKED_STS */ 6317 #define ARIZONA_ISRC1_UNDERCLOCKED_STS_SHIFT 5 /* ISRC1_UNDERCLOCKED_STS */ 6318 #define ARIZONA_ISRC1_UNDERCLOCKED_STS_WIDTH 1 /* ISRC1_UNDERCLOCKED_STS */ 6319 #define ARIZONA_FX_UNDERCLOCKED_STS 0x0010 /* FX_UNDERCLOCKED_STS */ 6320 #define ARIZONA_FX_UNDERCLOCKED_STS_MASK 0x0010 /* FX_UNDERCLOCKED_STS */ 6321 #define ARIZONA_FX_UNDERCLOCKED_STS_SHIFT 4 /* FX_UNDERCLOCKED_STS */ 6322 #define ARIZONA_FX_UNDERCLOCKED_STS_WIDTH 1 /* FX_UNDERCLOCKED_STS */ 6323 #define ARIZONA_ASRC_UNDERCLOCKED_STS 0x0008 /* ASRC_UNDERCLOCKED_STS */ 6324 #define ARIZONA_ASRC_UNDERCLOCKED_STS_MASK 0x0008 /* ASRC_UNDERCLOCKED_STS */ 6325 #define ARIZONA_ASRC_UNDERCLOCKED_STS_SHIFT 3 /* ASRC_UNDERCLOCKED_STS */ 6326 #define ARIZONA_ASRC_UNDERCLOCKED_STS_WIDTH 1 /* ASRC_UNDERCLOCKED_STS */ 6327 #define ARIZONA_DAC_UNDERCLOCKED_STS 0x0004 /* DAC_UNDERCLOCKED_STS */ 6328 #define ARIZONA_DAC_UNDERCLOCKED_STS_MASK 0x0004 /* DAC_UNDERCLOCKED_STS */ 6329 #define ARIZONA_DAC_UNDERCLOCKED_STS_SHIFT 2 /* DAC_UNDERCLOCKED_STS */ 6330 #define ARIZONA_DAC_UNDERCLOCKED_STS_WIDTH 1 /* DAC_UNDERCLOCKED_STS */ 6331 #define ARIZONA_ADC_UNDERCLOCKED_STS 0x0002 /* ADC_UNDERCLOCKED_STS */ 6332 #define ARIZONA_ADC_UNDERCLOCKED_STS_MASK 0x0002 /* ADC_UNDERCLOCKED_STS */ 6333 #define ARIZONA_ADC_UNDERCLOCKED_STS_SHIFT 1 /* ADC_UNDERCLOCKED_STS */ 6334 #define ARIZONA_ADC_UNDERCLOCKED_STS_WIDTH 1 /* ADC_UNDERCLOCKED_STS */ 6335 #define ARIZONA_MIXER_UNDERCLOCKED_STS 0x0001 /* MIXER_UNDERCLOCKED_STS */ 6336 #define ARIZONA_MIXER_UNDERCLOCKED_STS_MASK 0x0001 /* MIXER_UNDERCLOCKED_STS */ 6337 #define ARIZONA_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */ 6338 #define ARIZONA_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */ 6339 6340 /* 6341 * R3368 (0xD28) - Interrupt Raw Status 9 6342 */ 6343 #define ARIZONA_DSP_SHARED_WR_COLL_STS 0x8000 /* DSP_SHARED_WR_COLL_STS */ 6344 #define ARIZONA_DSP_SHARED_WR_COLL_STS_MASK 0x8000 /* DSP_SHARED_WR_COLL_STS */ 6345 #define ARIZONA_DSP_SHARED_WR_COLL_STS_SHIFT 15 /* DSP_SHARED_WR_COLL_STS */ 6346 #define ARIZONA_DSP_SHARED_WR_COLL_STS_WIDTH 1 /* DSP_SHARED_WR_COLL_STS */ 6347 #define ARIZONA_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */ 6348 #define ARIZONA_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */ 6349 #define ARIZONA_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */ 6350 #define ARIZONA_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */ 6351 #define ARIZONA_SPK1R_SHORT_STS 0x2000 /* SPK1R_SHORT_STS */ 6352 #define ARIZONA_SPK1R_SHORT_STS_MASK 0x2000 /* SPK1R_SHORT_STS */ 6353 #define ARIZONA_SPK1R_SHORT_STS_SHIFT 13 /* SPK1R_SHORT_STS */ 6354 #define ARIZONA_SPK1R_SHORT_STS_WIDTH 1 /* SPK1R_SHORT_STS */ 6355 #define ARIZONA_SPK1L_SHORT_STS 0x1000 /* SPK1L_SHORT_STS */ 6356 #define ARIZONA_SPK1L_SHORT_STS_MASK 0x1000 /* SPK1L_SHORT_STS */ 6357 #define ARIZONA_SPK1L_SHORT_STS_SHIFT 12 /* SPK1L_SHORT_STS */ 6358 #define ARIZONA_SPK1L_SHORT_STS_WIDTH 1 /* SPK1L_SHORT_STS */ 6359 #define ARIZONA_HP3R_SC_NEG_STS 0x0800 /* HP3R_SC_NEG_STS */ 6360 #define ARIZONA_HP3R_SC_NEG_STS_MASK 0x0800 /* HP3R_SC_NEG_STS */ 6361 #define ARIZONA_HP3R_SC_NEG_STS_SHIFT 11 /* HP3R_SC_NEG_STS */ 6362 #define ARIZONA_HP3R_SC_NEG_STS_WIDTH 1 /* HP3R_SC_NEG_STS */ 6363 #define ARIZONA_HP3R_SC_POS_STS 0x0400 /* HP3R_SC_POS_STS */ 6364 #define ARIZONA_HP3R_SC_POS_STS_MASK 0x0400 /* HP3R_SC_POS_STS */ 6365 #define ARIZONA_HP3R_SC_POS_STS_SHIFT 10 /* HP3R_SC_POS_STS */ 6366 #define ARIZONA_HP3R_SC_POS_STS_WIDTH 1 /* HP3R_SC_POS_STS */ 6367 #define ARIZONA_HP3L_SC_NEG_STS 0x0200 /* HP3L_SC_NEG_STS */ 6368 #define ARIZONA_HP3L_SC_NEG_STS_MASK 0x0200 /* HP3L_SC_NEG_STS */ 6369 #define ARIZONA_HP3L_SC_NEG_STS_SHIFT 9 /* HP3L_SC_NEG_STS */ 6370 #define ARIZONA_HP3L_SC_NEG_STS_WIDTH 1 /* HP3L_SC_NEG_STS */ 6371 #define ARIZONA_HP3L_SC_POS_STS 0x0100 /* HP3L_SC_POS_STS */ 6372 #define ARIZONA_HP3L_SC_POS_STS_MASK 0x0100 /* HP3L_SC_POS_STS */ 6373 #define ARIZONA_HP3L_SC_POS_STS_SHIFT 8 /* HP3L_SC_POS_STS */ 6374 #define ARIZONA_HP3L_SC_POS_STS_WIDTH 1 /* HP3L_SC_POS_STS */ 6375 #define ARIZONA_HP2R_SC_NEG_STS 0x0080 /* HP2R_SC_NEG_STS */ 6376 #define ARIZONA_HP2R_SC_NEG_STS_MASK 0x0080 /* HP2R_SC_NEG_STS */ 6377 #define ARIZONA_HP2R_SC_NEG_STS_SHIFT 7 /* HP2R_SC_NEG_STS */ 6378 #define ARIZONA_HP2R_SC_NEG_STS_WIDTH 1 /* HP2R_SC_NEG_STS */ 6379 #define ARIZONA_HP2R_SC_POS_STS 0x0040 /* HP2R_SC_POS_STS */ 6380 #define ARIZONA_HP2R_SC_POS_STS_MASK 0x0040 /* HP2R_SC_POS_STS */ 6381 #define ARIZONA_HP2R_SC_POS_STS_SHIFT 6 /* HP2R_SC_POS_STS */ 6382 #define ARIZONA_HP2R_SC_POS_STS_WIDTH 1 /* HP2R_SC_POS_STS */ 6383 #define ARIZONA_HP2L_SC_NEG_STS 0x0020 /* HP2L_SC_NEG_STS */ 6384 #define ARIZONA_HP2L_SC_NEG_STS_MASK 0x0020 /* HP2L_SC_NEG_STS */ 6385 #define ARIZONA_HP2L_SC_NEG_STS_SHIFT 5 /* HP2L_SC_NEG_STS */ 6386 #define ARIZONA_HP2L_SC_NEG_STS_WIDTH 1 /* HP2L_SC_NEG_STS */ 6387 #define ARIZONA_HP2L_SC_POS_STS 0x0010 /* HP2L_SC_POS_STS */ 6388 #define ARIZONA_HP2L_SC_POS_STS_MASK 0x0010 /* HP2L_SC_POS_STS */ 6389 #define ARIZONA_HP2L_SC_POS_STS_SHIFT 4 /* HP2L_SC_POS_STS */ 6390 #define ARIZONA_HP2L_SC_POS_STS_WIDTH 1 /* HP2L_SC_POS_STS */ 6391 #define ARIZONA_HP1R_SC_NEG_STS 0x0008 /* HP1R_SC_NEG_STS */ 6392 #define ARIZONA_HP1R_SC_NEG_STS_MASK 0x0008 /* HP1R_SC_NEG_STS */ 6393 #define ARIZONA_HP1R_SC_NEG_STS_SHIFT 3 /* HP1R_SC_NEG_STS */ 6394 #define ARIZONA_HP1R_SC_NEG_STS_WIDTH 1 /* HP1R_SC_NEG_STS */ 6395 #define ARIZONA_HP1R_SC_POS_STS 0x0004 /* HP1R_SC_POS_STS */ 6396 #define ARIZONA_HP1R_SC_POS_STS_MASK 0x0004 /* HP1R_SC_POS_STS */ 6397 #define ARIZONA_HP1R_SC_POS_STS_SHIFT 2 /* HP1R_SC_POS_STS */ 6398 #define ARIZONA_HP1R_SC_POS_STS_WIDTH 1 /* HP1R_SC_POS_STS */ 6399 #define ARIZONA_HP1L_SC_NEG_STS 0x0002 /* HP1L_SC_NEG_STS */ 6400 #define ARIZONA_HP1L_SC_NEG_STS_MASK 0x0002 /* HP1L_SC_NEG_STS */ 6401 #define ARIZONA_HP1L_SC_NEG_STS_SHIFT 1 /* HP1L_SC_NEG_STS */ 6402 #define ARIZONA_HP1L_SC_NEG_STS_WIDTH 1 /* HP1L_SC_NEG_STS */ 6403 #define ARIZONA_HP1L_SC_POS_STS 0x0001 /* HP1L_SC_POS_STS */ 6404 #define ARIZONA_HP1L_SC_POS_STS_MASK 0x0001 /* HP1L_SC_POS_STS */ 6405 #define ARIZONA_HP1L_SC_POS_STS_SHIFT 0 /* HP1L_SC_POS_STS */ 6406 #define ARIZONA_HP1L_SC_POS_STS_WIDTH 1 /* HP1L_SC_POS_STS */ 6407 6408 /* 6409 * R3392 (0xD40) - IRQ Pin Status 6410 */ 6411 #define ARIZONA_IRQ2_STS 0x0002 /* IRQ2_STS */ 6412 #define ARIZONA_IRQ2_STS_MASK 0x0002 /* IRQ2_STS */ 6413 #define ARIZONA_IRQ2_STS_SHIFT 1 /* IRQ2_STS */ 6414 #define ARIZONA_IRQ2_STS_WIDTH 1 /* IRQ2_STS */ 6415 #define ARIZONA_IRQ1_STS 0x0001 /* IRQ1_STS */ 6416 #define ARIZONA_IRQ1_STS_MASK 0x0001 /* IRQ1_STS */ 6417 #define ARIZONA_IRQ1_STS_SHIFT 0 /* IRQ1_STS */ 6418 #define ARIZONA_IRQ1_STS_WIDTH 1 /* IRQ1_STS */ 6419 6420 /* 6421 * R3393 (0xD41) - ADSP2 IRQ0 6422 */ 6423 #define ARIZONA_DSP_IRQ2 0x0002 /* DSP_IRQ2 */ 6424 #define ARIZONA_DSP_IRQ2_MASK 0x0002 /* DSP_IRQ2 */ 6425 #define ARIZONA_DSP_IRQ2_SHIFT 1 /* DSP_IRQ2 */ 6426 #define ARIZONA_DSP_IRQ2_WIDTH 1 /* DSP_IRQ2 */ 6427 #define ARIZONA_DSP_IRQ1 0x0001 /* DSP_IRQ1 */ 6428 #define ARIZONA_DSP_IRQ1_MASK 0x0001 /* DSP_IRQ1 */ 6429 #define ARIZONA_DSP_IRQ1_SHIFT 0 /* DSP_IRQ1 */ 6430 #define ARIZONA_DSP_IRQ1_WIDTH 1 /* DSP_IRQ1 */ 6431 6432 /* 6433 * R3408 (0xD50) - AOD wkup and trig 6434 */ 6435 #define ARIZONA_MICD_CLAMP_FALL_TRIG_STS 0x0080 /* MICD_CLAMP_FALL_TRIG_STS */ 6436 #define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_MASK 0x0080 /* MICD_CLAMP_FALL_TRIG_STS */ 6437 #define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_SHIFT 7 /* MICD_CLAMP_FALL_TRIG_STS */ 6438 #define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_WIDTH 1 /* MICD_CLAMP_FALL_TRIG_STS */ 6439 #define ARIZONA_MICD_CLAMP_RISE_TRIG_STS 0x0040 /* MICD_CLAMP_RISE_TRIG_STS */ 6440 #define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_MASK 0x0040 /* MICD_CLAMP_RISE_TRIG_STS */ 6441 #define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_SHIFT 6 /* MICD_CLAMP_RISE_TRIG_STS */ 6442 #define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_WIDTH 1 /* MICD_CLAMP_RISE_TRIG_STS */ 6443 #define ARIZONA_GP5_FALL_TRIG_STS 0x0020 /* GP5_FALL_TRIG_STS */ 6444 #define ARIZONA_GP5_FALL_TRIG_STS_MASK 0x0020 /* GP5_FALL_TRIG_STS */ 6445 #define ARIZONA_GP5_FALL_TRIG_STS_SHIFT 5 /* GP5_FALL_TRIG_STS */ 6446 #define ARIZONA_GP5_FALL_TRIG_STS_WIDTH 1 /* GP5_FALL_TRIG_STS */ 6447 #define ARIZONA_GP5_RISE_TRIG_STS 0x0010 /* GP5_RISE_TRIG_STS */ 6448 #define ARIZONA_GP5_RISE_TRIG_STS_MASK 0x0010 /* GP5_RISE_TRIG_STS */ 6449 #define ARIZONA_GP5_RISE_TRIG_STS_SHIFT 4 /* GP5_RISE_TRIG_STS */ 6450 #define ARIZONA_GP5_RISE_TRIG_STS_WIDTH 1 /* GP5_RISE_TRIG_STS */ 6451 #define ARIZONA_JD1_FALL_TRIG_STS 0x0008 /* JD1_FALL_TRIG_STS */ 6452 #define ARIZONA_JD1_FALL_TRIG_STS_MASK 0x0008 /* JD1_FALL_TRIG_STS */ 6453 #define ARIZONA_JD1_FALL_TRIG_STS_SHIFT 3 /* JD1_FALL_TRIG_STS */ 6454 #define ARIZONA_JD1_FALL_TRIG_STS_WIDTH 1 /* JD1_FALL_TRIG_STS */ 6455 #define ARIZONA_JD1_RISE_TRIG_STS 0x0004 /* JD1_RISE_TRIG_STS */ 6456 #define ARIZONA_JD1_RISE_TRIG_STS_MASK 0x0004 /* JD1_RISE_TRIG_STS */ 6457 #define ARIZONA_JD1_RISE_TRIG_STS_SHIFT 2 /* JD1_RISE_TRIG_STS */ 6458 #define ARIZONA_JD1_RISE_TRIG_STS_WIDTH 1 /* JD1_RISE_TRIG_STS */ 6459 #define ARIZONA_JD2_FALL_TRIG_STS 0x0002 /* JD2_FALL_TRIG_STS */ 6460 #define ARIZONA_JD2_FALL_TRIG_STS_MASK 0x0002 /* JD2_FALL_TRIG_STS */ 6461 #define ARIZONA_JD2_FALL_TRIG_STS_SHIFT 1 /* JD2_FALL_TRIG_STS */ 6462 #define ARIZONA_JD2_FALL_TRIG_STS_WIDTH 1 /* JD2_FALL_TRIG_STS */ 6463 #define ARIZONA_JD2_RISE_TRIG_STS 0x0001 /* JD2_RISE_TRIG_STS */ 6464 #define ARIZONA_JD2_RISE_TRIG_STS_MASK 0x0001 /* JD2_RISE_TRIG_STS */ 6465 #define ARIZONA_JD2_RISE_TRIG_STS_SHIFT 0 /* JD2_RISE_TRIG_STS */ 6466 #define ARIZONA_JD2_RISE_TRIG_STS_WIDTH 1 /* JD2_RISE_TRIG_STS */ 6467 6468 /* 6469 * R3409 (0xD51) - AOD IRQ1 6470 */ 6471 #define ARIZONA_MICD_CLAMP_FALL_EINT1 0x0080 /* MICD_CLAMP_FALL_EINT1 */ 6472 #define ARIZONA_MICD_CLAMP_FALL_EINT1_MASK 0x0080 /* MICD_CLAMP_FALL_EINT1 */ 6473 #define ARIZONA_MICD_CLAMP_FALL_EINT1_SHIFT 7 /* MICD_CLAMP_FALL_EINT1 */ 6474 #define ARIZONA_MICD_CLAMP_RISE_EINT1 0x0040 /* MICD_CLAMP_RISE_EINT1 */ 6475 #define ARIZONA_MICD_CLAMP_RISE_EINT1_MASK 0x0040 /* MICD_CLAMP_RISE_EINT1 */ 6476 #define ARIZONA_MICD_CLAMP_RISE_EINT1_SHIFT 6 /* MICD_CLAMP_RISE_EINT1 */ 6477 #define ARIZONA_GP5_FALL_EINT1 0x0020 /* GP5_FALL_EINT1 */ 6478 #define ARIZONA_GP5_FALL_EINT1_MASK 0x0020 /* GP5_FALL_EINT1 */ 6479 #define ARIZONA_GP5_FALL_EINT1_SHIFT 5 /* GP5_FALL_EINT1 */ 6480 #define ARIZONA_GP5_FALL_EINT1_WIDTH 1 /* GP5_FALL_EINT1 */ 6481 #define ARIZONA_GP5_RISE_EINT1 0x0010 /* GP5_RISE_EINT1 */ 6482 #define ARIZONA_GP5_RISE_EINT1_MASK 0x0010 /* GP5_RISE_EINT1 */ 6483 #define ARIZONA_GP5_RISE_EINT1_SHIFT 4 /* GP5_RISE_EINT1 */ 6484 #define ARIZONA_GP5_RISE_EINT1_WIDTH 1 /* GP5_RISE_EINT1 */ 6485 #define ARIZONA_JD1_FALL_EINT1 0x0008 /* JD1_FALL_EINT1 */ 6486 #define ARIZONA_JD1_FALL_EINT1_MASK 0x0008 /* JD1_FALL_EINT1 */ 6487 #define ARIZONA_JD1_FALL_EINT1_SHIFT 3 /* JD1_FALL_EINT1 */ 6488 #define ARIZONA_JD1_FALL_EINT1_WIDTH 1 /* JD1_FALL_EINT1 */ 6489 #define ARIZONA_JD1_RISE_EINT1 0x0004 /* JD1_RISE_EINT1 */ 6490 #define ARIZONA_JD1_RISE_EINT1_MASK 0x0004 /* JD1_RISE_EINT1 */ 6491 #define ARIZONA_JD1_RISE_EINT1_SHIFT 2 /* JD1_RISE_EINT1 */ 6492 #define ARIZONA_JD1_RISE_EINT1_WIDTH 1 /* JD1_RISE_EINT1 */ 6493 #define ARIZONA_JD2_FALL_EINT1 0x0002 /* JD2_FALL_EINT1 */ 6494 #define ARIZONA_JD2_FALL_EINT1_MASK 0x0002 /* JD2_FALL_EINT1 */ 6495 #define ARIZONA_JD2_FALL_EINT1_SHIFT 1 /* JD2_FALL_EINT1 */ 6496 #define ARIZONA_JD2_FALL_EINT1_WIDTH 1 /* JD2_FALL_EINT1 */ 6497 #define ARIZONA_JD2_RISE_EINT1 0x0001 /* JD2_RISE_EINT1 */ 6498 #define ARIZONA_JD2_RISE_EINT1_MASK 0x0001 /* JD2_RISE_EINT1 */ 6499 #define ARIZONA_JD2_RISE_EINT1_SHIFT 0 /* JD2_RISE_EINT1 */ 6500 #define ARIZONA_JD2_RISE_EINT1_WIDTH 1 /* JD2_RISE_EINT1 */ 6501 6502 /* 6503 * R3410 (0xD52) - AOD IRQ2 6504 */ 6505 #define ARIZONA_MICD_CLAMP_FALL_EINT2 0x0080 /* MICD_CLAMP_FALL_EINT2 */ 6506 #define ARIZONA_MICD_CLAMP_FALL_EINT2_MASK 0x0080 /* MICD_CLAMP_FALL_EINT2 */ 6507 #define ARIZONA_MICD_CLAMP_FALL_EINT2_SHIFT 7 /* MICD_CLAMP_FALL_EINT2 */ 6508 #define ARIZONA_MICD_CLAMP_RISE_EINT2 0x0040 /* MICD_CLAMP_RISE_EINT2 */ 6509 #define ARIZONA_MICD_CLAMP_RISE_EINT2_MASK 0x0040 /* MICD_CLAMP_RISE_EINT2 */ 6510 #define ARIZONA_MICD_CLAMP_RISE_EINT2_SHIFT 6 /* MICD_CLAMP_RISE_EINT2 */ 6511 #define ARIZONA_GP5_FALL_EINT2 0x0020 /* GP5_FALL_EINT2 */ 6512 #define ARIZONA_GP5_FALL_EINT2_MASK 0x0020 /* GP5_FALL_EINT2 */ 6513 #define ARIZONA_GP5_FALL_EINT2_SHIFT 5 /* GP5_FALL_EINT2 */ 6514 #define ARIZONA_GP5_FALL_EINT2_WIDTH 1 /* GP5_FALL_EINT2 */ 6515 #define ARIZONA_GP5_RISE_EINT2 0x0010 /* GP5_RISE_EINT2 */ 6516 #define ARIZONA_GP5_RISE_EINT2_MASK 0x0010 /* GP5_RISE_EINT2 */ 6517 #define ARIZONA_GP5_RISE_EINT2_SHIFT 4 /* GP5_RISE_EINT2 */ 6518 #define ARIZONA_GP5_RISE_EINT2_WIDTH 1 /* GP5_RISE_EINT2 */ 6519 #define ARIZONA_JD1_FALL_EINT2 0x0008 /* JD1_FALL_EINT2 */ 6520 #define ARIZONA_JD1_FALL_EINT2_MASK 0x0008 /* JD1_FALL_EINT2 */ 6521 #define ARIZONA_JD1_FALL_EINT2_SHIFT 3 /* JD1_FALL_EINT2 */ 6522 #define ARIZONA_JD1_FALL_EINT2_WIDTH 1 /* JD1_FALL_EINT2 */ 6523 #define ARIZONA_JD1_RISE_EINT2 0x0004 /* JD1_RISE_EINT2 */ 6524 #define ARIZONA_JD1_RISE_EINT2_MASK 0x0004 /* JD1_RISE_EINT2 */ 6525 #define ARIZONA_JD1_RISE_EINT2_SHIFT 2 /* JD1_RISE_EINT2 */ 6526 #define ARIZONA_JD1_RISE_EINT2_WIDTH 1 /* JD1_RISE_EINT2 */ 6527 #define ARIZONA_JD2_FALL_EINT2 0x0002 /* JD2_FALL_EINT2 */ 6528 #define ARIZONA_JD2_FALL_EINT2_MASK 0x0002 /* JD2_FALL_EINT2 */ 6529 #define ARIZONA_JD2_FALL_EINT2_SHIFT 1 /* JD2_FALL_EINT2 */ 6530 #define ARIZONA_JD2_FALL_EINT2_WIDTH 1 /* JD2_FALL_EINT2 */ 6531 #define ARIZONA_JD2_RISE_EINT2 0x0001 /* JD2_RISE_EINT2 */ 6532 #define ARIZONA_JD2_RISE_EINT2_MASK 0x0001 /* JD2_RISE_EINT2 */ 6533 #define ARIZONA_JD2_RISE_EINT2_SHIFT 0 /* JD2_RISE_EINT2 */ 6534 #define ARIZONA_JD2_RISE_EINT2_WIDTH 1 /* JD2_RISE_EINT2 */ 6535 6536 /* 6537 * R3411 (0xD53) - AOD IRQ Mask IRQ1 6538 */ 6539 #define ARIZONA_IM_GP5_FALL_EINT1 0x0020 /* IM_GP5_FALL_EINT1 */ 6540 #define ARIZONA_IM_GP5_FALL_EINT1_MASK 0x0020 /* IM_GP5_FALL_EINT1 */ 6541 #define ARIZONA_IM_GP5_FALL_EINT1_SHIFT 5 /* IM_GP5_FALL_EINT1 */ 6542 #define ARIZONA_IM_GP5_FALL_EINT1_WIDTH 1 /* IM_GP5_FALL_EINT1 */ 6543 #define ARIZONA_IM_GP5_RISE_EINT1 0x0010 /* IM_GP5_RISE_EINT1 */ 6544 #define ARIZONA_IM_GP5_RISE_EINT1_MASK 0x0010 /* IM_GP5_RISE_EINT1 */ 6545 #define ARIZONA_IM_GP5_RISE_EINT1_SHIFT 4 /* IM_GP5_RISE_EINT1 */ 6546 #define ARIZONA_IM_GP5_RISE_EINT1_WIDTH 1 /* IM_GP5_RISE_EINT1 */ 6547 #define ARIZONA_IM_JD1_FALL_EINT1 0x0008 /* IM_JD1_FALL_EINT1 */ 6548 #define ARIZONA_IM_JD1_FALL_EINT1_MASK 0x0008 /* IM_JD1_FALL_EINT1 */ 6549 #define ARIZONA_IM_JD1_FALL_EINT1_SHIFT 3 /* IM_JD1_FALL_EINT1 */ 6550 #define ARIZONA_IM_JD1_FALL_EINT1_WIDTH 1 /* IM_JD1_FALL_EINT1 */ 6551 #define ARIZONA_IM_JD1_RISE_EINT1 0x0004 /* IM_JD1_RISE_EINT1 */ 6552 #define ARIZONA_IM_JD1_RISE_EINT1_MASK 0x0004 /* IM_JD1_RISE_EINT1 */ 6553 #define ARIZONA_IM_JD1_RISE_EINT1_SHIFT 2 /* IM_JD1_RISE_EINT1 */ 6554 #define ARIZONA_IM_JD1_RISE_EINT1_WIDTH 1 /* IM_JD1_RISE_EINT1 */ 6555 #define ARIZONA_IM_JD2_FALL_EINT1 0x0002 /* IM_JD2_FALL_EINT1 */ 6556 #define ARIZONA_IM_JD2_FALL_EINT1_MASK 0x0002 /* IM_JD2_FALL_EINT1 */ 6557 #define ARIZONA_IM_JD2_FALL_EINT1_SHIFT 1 /* IM_JD2_FALL_EINT1 */ 6558 #define ARIZONA_IM_JD2_FALL_EINT1_WIDTH 1 /* IM_JD2_FALL_EINT1 */ 6559 #define ARIZONA_IM_JD2_RISE_EINT1 0x0001 /* IM_JD2_RISE_EINT1 */ 6560 #define ARIZONA_IM_JD2_RISE_EINT1_MASK 0x0001 /* IM_JD2_RISE_EINT1 */ 6561 #define ARIZONA_IM_JD2_RISE_EINT1_SHIFT 0 /* IM_JD2_RISE_EINT1 */ 6562 #define ARIZONA_IM_JD2_RISE_EINT1_WIDTH 1 /* IM_JD2_RISE_EINT1 */ 6563 6564 /* 6565 * R3412 (0xD54) - AOD IRQ Mask IRQ2 6566 */ 6567 #define ARIZONA_IM_GP5_FALL_EINT2 0x0020 /* IM_GP5_FALL_EINT2 */ 6568 #define ARIZONA_IM_GP5_FALL_EINT2_MASK 0x0020 /* IM_GP5_FALL_EINT2 */ 6569 #define ARIZONA_IM_GP5_FALL_EINT2_SHIFT 5 /* IM_GP5_FALL_EINT2 */ 6570 #define ARIZONA_IM_GP5_FALL_EINT2_WIDTH 1 /* IM_GP5_FALL_EINT2 */ 6571 #define ARIZONA_IM_GP5_RISE_EINT2 0x0010 /* IM_GP5_RISE_EINT2 */ 6572 #define ARIZONA_IM_GP5_RISE_EINT2_MASK 0x0010 /* IM_GP5_RISE_EINT2 */ 6573 #define ARIZONA_IM_GP5_RISE_EINT2_SHIFT 4 /* IM_GP5_RISE_EINT2 */ 6574 #define ARIZONA_IM_GP5_RISE_EINT2_WIDTH 1 /* IM_GP5_RISE_EINT2 */ 6575 #define ARIZONA_IM_JD1_FALL_EINT2 0x0008 /* IM_JD1_FALL_EINT2 */ 6576 #define ARIZONA_IM_JD1_FALL_EINT2_MASK 0x0008 /* IM_JD1_FALL_EINT2 */ 6577 #define ARIZONA_IM_JD1_FALL_EINT2_SHIFT 3 /* IM_JD1_FALL_EINT2 */ 6578 #define ARIZONA_IM_JD1_FALL_EINT2_WIDTH 1 /* IM_JD1_FALL_EINT2 */ 6579 #define ARIZONA_IM_JD1_RISE_EINT2 0x0004 /* IM_JD1_RISE_EINT2 */ 6580 #define ARIZONA_IM_JD1_RISE_EINT2_MASK 0x0004 /* IM_JD1_RISE_EINT2 */ 6581 #define ARIZONA_IM_JD1_RISE_EINT2_SHIFT 2 /* IM_JD1_RISE_EINT2 */ 6582 #define ARIZONA_IM_JD1_RISE_EINT2_WIDTH 1 /* IM_JD1_RISE_EINT2 */ 6583 #define ARIZONA_IM_JD2_FALL_EINT2 0x0002 /* IM_JD2_FALL_EINT2 */ 6584 #define ARIZONA_IM_JD2_FALL_EINT2_MASK 0x0002 /* IM_JD2_FALL_EINT2 */ 6585 #define ARIZONA_IM_JD2_FALL_EINT2_SHIFT 1 /* IM_JD2_FALL_EINT2 */ 6586 #define ARIZONA_IM_JD2_FALL_EINT2_WIDTH 1 /* IM_JD2_FALL_EINT2 */ 6587 #define ARIZONA_IM_JD2_RISE_EINT2 0x0001 /* IM_JD2_RISE_EINT2 */ 6588 #define ARIZONA_IM_JD2_RISE_EINT2_MASK 0x0001 /* IM_JD2_RISE_EINT2 */ 6589 #define ARIZONA_IM_JD2_RISE_EINT2_SHIFT 0 /* IM_JD2_RISE_EINT2 */ 6590 #define ARIZONA_IM_JD2_RISE_EINT2_WIDTH 1 /* IM_JD2_RISE_EINT2 */ 6591 6592 /* 6593 * R3413 (0xD55) - AOD IRQ Raw Status 6594 */ 6595 #define ARIZONA_MICD_CLAMP_STS 0x0008 /* MICD_CLAMP_STS */ 6596 #define ARIZONA_MICD_CLAMP_STS_MASK 0x0008 /* MICD_CLAMP_STS */ 6597 #define ARIZONA_MICD_CLAMP_STS_SHIFT 3 /* MICD_CLAMP_STS */ 6598 #define ARIZONA_MICD_CLAMP_STS_WIDTH 1 /* MICD_CLAMP_STS */ 6599 #define ARIZONA_GP5_STS 0x0004 /* GP5_STS */ 6600 #define ARIZONA_GP5_STS_MASK 0x0004 /* GP5_STS */ 6601 #define ARIZONA_GP5_STS_SHIFT 2 /* GP5_STS */ 6602 #define ARIZONA_GP5_STS_WIDTH 1 /* GP5_STS */ 6603 #define ARIZONA_JD2_STS 0x0002 /* JD2_STS */ 6604 #define ARIZONA_JD2_STS_MASK 0x0002 /* JD2_STS */ 6605 #define ARIZONA_JD2_STS_SHIFT 1 /* JD2_STS */ 6606 #define ARIZONA_JD2_STS_WIDTH 1 /* JD2_STS */ 6607 #define ARIZONA_JD1_STS 0x0001 /* JD1_STS */ 6608 #define ARIZONA_JD1_STS_MASK 0x0001 /* JD1_STS */ 6609 #define ARIZONA_JD1_STS_SHIFT 0 /* JD1_STS */ 6610 #define ARIZONA_JD1_STS_WIDTH 1 /* JD1_STS */ 6611 6612 /* 6613 * R3414 (0xD56) - Jack detect debounce 6614 */ 6615 #define ARIZONA_MICD_CLAMP_DB 0x0008 /* MICD_CLAMP_DB */ 6616 #define ARIZONA_MICD_CLAMP_DB_MASK 0x0008 /* MICD_CLAMP_DB */ 6617 #define ARIZONA_MICD_CLAMP_DB_SHIFT 3 /* MICD_CLAMP_DB */ 6618 #define ARIZONA_MICD_CLAMP_DB_WIDTH 1 /* MICD_CLAMP_DB */ 6619 #define ARIZONA_JD2_DB 0x0002 /* JD2_DB */ 6620 #define ARIZONA_JD2_DB_MASK 0x0002 /* JD2_DB */ 6621 #define ARIZONA_JD2_DB_SHIFT 1 /* JD2_DB */ 6622 #define ARIZONA_JD2_DB_WIDTH 1 /* JD2_DB */ 6623 #define ARIZONA_JD1_DB 0x0001 /* JD1_DB */ 6624 #define ARIZONA_JD1_DB_MASK 0x0001 /* JD1_DB */ 6625 #define ARIZONA_JD1_DB_SHIFT 0 /* JD1_DB */ 6626 #define ARIZONA_JD1_DB_WIDTH 1 /* JD1_DB */ 6627 6628 /* 6629 * R3584 (0xE00) - FX_Ctrl1 6630 */ 6631 #define ARIZONA_FX_RATE_MASK 0x7800 /* FX_RATE - [14:11] */ 6632 #define ARIZONA_FX_RATE_SHIFT 11 /* FX_RATE - [14:11] */ 6633 #define ARIZONA_FX_RATE_WIDTH 4 /* FX_RATE - [14:11] */ 6634 6635 /* 6636 * R3585 (0xE01) - FX_Ctrl2 6637 */ 6638 #define ARIZONA_FX_STS_MASK 0xFFF0 /* FX_STS - [15:4] */ 6639 #define ARIZONA_FX_STS_SHIFT 4 /* FX_STS - [15:4] */ 6640 #define ARIZONA_FX_STS_WIDTH 12 /* FX_STS - [15:4] */ 6641 6642 /* 6643 * R3600 (0xE10) - EQ1_1 6644 */ 6645 #define ARIZONA_EQ1_B1_GAIN_MASK 0xF800 /* EQ1_B1_GAIN - [15:11] */ 6646 #define ARIZONA_EQ1_B1_GAIN_SHIFT 11 /* EQ1_B1_GAIN - [15:11] */ 6647 #define ARIZONA_EQ1_B1_GAIN_WIDTH 5 /* EQ1_B1_GAIN - [15:11] */ 6648 #define ARIZONA_EQ1_B2_GAIN_MASK 0x07C0 /* EQ1_B2_GAIN - [10:6] */ 6649 #define ARIZONA_EQ1_B2_GAIN_SHIFT 6 /* EQ1_B2_GAIN - [10:6] */ 6650 #define ARIZONA_EQ1_B2_GAIN_WIDTH 5 /* EQ1_B2_GAIN - [10:6] */ 6651 #define ARIZONA_EQ1_B3_GAIN_MASK 0x003E /* EQ1_B3_GAIN - [5:1] */ 6652 #define ARIZONA_EQ1_B3_GAIN_SHIFT 1 /* EQ1_B3_GAIN - [5:1] */ 6653 #define ARIZONA_EQ1_B3_GAIN_WIDTH 5 /* EQ1_B3_GAIN - [5:1] */ 6654 #define ARIZONA_EQ1_ENA 0x0001 /* EQ1_ENA */ 6655 #define ARIZONA_EQ1_ENA_MASK 0x0001 /* EQ1_ENA */ 6656 #define ARIZONA_EQ1_ENA_SHIFT 0 /* EQ1_ENA */ 6657 #define ARIZONA_EQ1_ENA_WIDTH 1 /* EQ1_ENA */ 6658 6659 /* 6660 * R3601 (0xE11) - EQ1_2 6661 */ 6662 #define ARIZONA_EQ1_B4_GAIN_MASK 0xF800 /* EQ1_B4_GAIN - [15:11] */ 6663 #define ARIZONA_EQ1_B4_GAIN_SHIFT 11 /* EQ1_B4_GAIN - [15:11] */ 6664 #define ARIZONA_EQ1_B4_GAIN_WIDTH 5 /* EQ1_B4_GAIN - [15:11] */ 6665 #define ARIZONA_EQ1_B5_GAIN_MASK 0x07C0 /* EQ1_B5_GAIN - [10:6] */ 6666 #define ARIZONA_EQ1_B5_GAIN_SHIFT 6 /* EQ1_B5_GAIN - [10:6] */ 6667 #define ARIZONA_EQ1_B5_GAIN_WIDTH 5 /* EQ1_B5_GAIN - [10:6] */ 6668 #define ARIZONA_EQ1_B1_MODE 0x0001 /* EQ1_B1_MODE */ 6669 #define ARIZONA_EQ1_B1_MODE_MASK 0x0001 /* EQ1_B1_MODE */ 6670 #define ARIZONA_EQ1_B1_MODE_SHIFT 0 /* EQ1_B1_MODE */ 6671 #define ARIZONA_EQ1_B1_MODE_WIDTH 1 /* EQ1_B1_MODE */ 6672 6673 /* 6674 * R3602 (0xE12) - EQ1_3 6675 */ 6676 #define ARIZONA_EQ1_B1_A_MASK 0xFFFF /* EQ1_B1_A - [15:0] */ 6677 #define ARIZONA_EQ1_B1_A_SHIFT 0 /* EQ1_B1_A - [15:0] */ 6678 #define ARIZONA_EQ1_B1_A_WIDTH 16 /* EQ1_B1_A - [15:0] */ 6679 6680 /* 6681 * R3603 (0xE13) - EQ1_4 6682 */ 6683 #define ARIZONA_EQ1_B1_B_MASK 0xFFFF /* EQ1_B1_B - [15:0] */ 6684 #define ARIZONA_EQ1_B1_B_SHIFT 0 /* EQ1_B1_B - [15:0] */ 6685 #define ARIZONA_EQ1_B1_B_WIDTH 16 /* EQ1_B1_B - [15:0] */ 6686 6687 /* 6688 * R3604 (0xE14) - EQ1_5 6689 */ 6690 #define ARIZONA_EQ1_B1_PG_MASK 0xFFFF /* EQ1_B1_PG - [15:0] */ 6691 #define ARIZONA_EQ1_B1_PG_SHIFT 0 /* EQ1_B1_PG - [15:0] */ 6692 #define ARIZONA_EQ1_B1_PG_WIDTH 16 /* EQ1_B1_PG - [15:0] */ 6693 6694 /* 6695 * R3605 (0xE15) - EQ1_6 6696 */ 6697 #define ARIZONA_EQ1_B2_A_MASK 0xFFFF /* EQ1_B2_A - [15:0] */ 6698 #define ARIZONA_EQ1_B2_A_SHIFT 0 /* EQ1_B2_A - [15:0] */ 6699 #define ARIZONA_EQ1_B2_A_WIDTH 16 /* EQ1_B2_A - [15:0] */ 6700 6701 /* 6702 * R3606 (0xE16) - EQ1_7 6703 */ 6704 #define ARIZONA_EQ1_B2_B_MASK 0xFFFF /* EQ1_B2_B - [15:0] */ 6705 #define ARIZONA_EQ1_B2_B_SHIFT 0 /* EQ1_B2_B - [15:0] */ 6706 #define ARIZONA_EQ1_B2_B_WIDTH 16 /* EQ1_B2_B - [15:0] */ 6707 6708 /* 6709 * R3607 (0xE17) - EQ1_8 6710 */ 6711 #define ARIZONA_EQ1_B2_C_MASK 0xFFFF /* EQ1_B2_C - [15:0] */ 6712 #define ARIZONA_EQ1_B2_C_SHIFT 0 /* EQ1_B2_C - [15:0] */ 6713 #define ARIZONA_EQ1_B2_C_WIDTH 16 /* EQ1_B2_C - [15:0] */ 6714 6715 /* 6716 * R3608 (0xE18) - EQ1_9 6717 */ 6718 #define ARIZONA_EQ1_B2_PG_MASK 0xFFFF /* EQ1_B2_PG - [15:0] */ 6719 #define ARIZONA_EQ1_B2_PG_SHIFT 0 /* EQ1_B2_PG - [15:0] */ 6720 #define ARIZONA_EQ1_B2_PG_WIDTH 16 /* EQ1_B2_PG - [15:0] */ 6721 6722 /* 6723 * R3609 (0xE19) - EQ1_10 6724 */ 6725 #define ARIZONA_EQ1_B3_A_MASK 0xFFFF /* EQ1_B3_A - [15:0] */ 6726 #define ARIZONA_EQ1_B3_A_SHIFT 0 /* EQ1_B3_A - [15:0] */ 6727 #define ARIZONA_EQ1_B3_A_WIDTH 16 /* EQ1_B3_A - [15:0] */ 6728 6729 /* 6730 * R3610 (0xE1A) - EQ1_11 6731 */ 6732 #define ARIZONA_EQ1_B3_B_MASK 0xFFFF /* EQ1_B3_B - [15:0] */ 6733 #define ARIZONA_EQ1_B3_B_SHIFT 0 /* EQ1_B3_B - [15:0] */ 6734 #define ARIZONA_EQ1_B3_B_WIDTH 16 /* EQ1_B3_B - [15:0] */ 6735 6736 /* 6737 * R3611 (0xE1B) - EQ1_12 6738 */ 6739 #define ARIZONA_EQ1_B3_C_MASK 0xFFFF /* EQ1_B3_C - [15:0] */ 6740 #define ARIZONA_EQ1_B3_C_SHIFT 0 /* EQ1_B3_C - [15:0] */ 6741 #define ARIZONA_EQ1_B3_C_WIDTH 16 /* EQ1_B3_C - [15:0] */ 6742 6743 /* 6744 * R3612 (0xE1C) - EQ1_13 6745 */ 6746 #define ARIZONA_EQ1_B3_PG_MASK 0xFFFF /* EQ1_B3_PG - [15:0] */ 6747 #define ARIZONA_EQ1_B3_PG_SHIFT 0 /* EQ1_B3_PG - [15:0] */ 6748 #define ARIZONA_EQ1_B3_PG_WIDTH 16 /* EQ1_B3_PG - [15:0] */ 6749 6750 /* 6751 * R3613 (0xE1D) - EQ1_14 6752 */ 6753 #define ARIZONA_EQ1_B4_A_MASK 0xFFFF /* EQ1_B4_A - [15:0] */ 6754 #define ARIZONA_EQ1_B4_A_SHIFT 0 /* EQ1_B4_A - [15:0] */ 6755 #define ARIZONA_EQ1_B4_A_WIDTH 16 /* EQ1_B4_A - [15:0] */ 6756 6757 /* 6758 * R3614 (0xE1E) - EQ1_15 6759 */ 6760 #define ARIZONA_EQ1_B4_B_MASK 0xFFFF /* EQ1_B4_B - [15:0] */ 6761 #define ARIZONA_EQ1_B4_B_SHIFT 0 /* EQ1_B4_B - [15:0] */ 6762 #define ARIZONA_EQ1_B4_B_WIDTH 16 /* EQ1_B4_B - [15:0] */ 6763 6764 /* 6765 * R3615 (0xE1F) - EQ1_16 6766 */ 6767 #define ARIZONA_EQ1_B4_C_MASK 0xFFFF /* EQ1_B4_C - [15:0] */ 6768 #define ARIZONA_EQ1_B4_C_SHIFT 0 /* EQ1_B4_C - [15:0] */ 6769 #define ARIZONA_EQ1_B4_C_WIDTH 16 /* EQ1_B4_C - [15:0] */ 6770 6771 /* 6772 * R3616 (0xE20) - EQ1_17 6773 */ 6774 #define ARIZONA_EQ1_B4_PG_MASK 0xFFFF /* EQ1_B4_PG - [15:0] */ 6775 #define ARIZONA_EQ1_B4_PG_SHIFT 0 /* EQ1_B4_PG - [15:0] */ 6776 #define ARIZONA_EQ1_B4_PG_WIDTH 16 /* EQ1_B4_PG - [15:0] */ 6777 6778 /* 6779 * R3617 (0xE21) - EQ1_18 6780 */ 6781 #define ARIZONA_EQ1_B5_A_MASK 0xFFFF /* EQ1_B5_A - [15:0] */ 6782 #define ARIZONA_EQ1_B5_A_SHIFT 0 /* EQ1_B5_A - [15:0] */ 6783 #define ARIZONA_EQ1_B5_A_WIDTH 16 /* EQ1_B5_A - [15:0] */ 6784 6785 /* 6786 * R3618 (0xE22) - EQ1_19 6787 */ 6788 #define ARIZONA_EQ1_B5_B_MASK 0xFFFF /* EQ1_B5_B - [15:0] */ 6789 #define ARIZONA_EQ1_B5_B_SHIFT 0 /* EQ1_B5_B - [15:0] */ 6790 #define ARIZONA_EQ1_B5_B_WIDTH 16 /* EQ1_B5_B - [15:0] */ 6791 6792 /* 6793 * R3619 (0xE23) - EQ1_20 6794 */ 6795 #define ARIZONA_EQ1_B5_PG_MASK 0xFFFF /* EQ1_B5_PG - [15:0] */ 6796 #define ARIZONA_EQ1_B5_PG_SHIFT 0 /* EQ1_B5_PG - [15:0] */ 6797 #define ARIZONA_EQ1_B5_PG_WIDTH 16 /* EQ1_B5_PG - [15:0] */ 6798 6799 /* 6800 * R3620 (0xE24) - EQ1_21 6801 */ 6802 #define ARIZONA_EQ1_B1_C_MASK 0xFFFF /* EQ1_B1_C - [15:0] */ 6803 #define ARIZONA_EQ1_B1_C_SHIFT 0 /* EQ1_B1_C - [15:0] */ 6804 #define ARIZONA_EQ1_B1_C_WIDTH 16 /* EQ1_B1_C - [15:0] */ 6805 6806 /* 6807 * R3622 (0xE26) - EQ2_1 6808 */ 6809 #define ARIZONA_EQ2_B1_GAIN_MASK 0xF800 /* EQ2_B1_GAIN - [15:11] */ 6810 #define ARIZONA_EQ2_B1_GAIN_SHIFT 11 /* EQ2_B1_GAIN - [15:11] */ 6811 #define ARIZONA_EQ2_B1_GAIN_WIDTH 5 /* EQ2_B1_GAIN - [15:11] */ 6812 #define ARIZONA_EQ2_B2_GAIN_MASK 0x07C0 /* EQ2_B2_GAIN - [10:6] */ 6813 #define ARIZONA_EQ2_B2_GAIN_SHIFT 6 /* EQ2_B2_GAIN - [10:6] */ 6814 #define ARIZONA_EQ2_B2_GAIN_WIDTH 5 /* EQ2_B2_GAIN - [10:6] */ 6815 #define ARIZONA_EQ2_B3_GAIN_MASK 0x003E /* EQ2_B3_GAIN - [5:1] */ 6816 #define ARIZONA_EQ2_B3_GAIN_SHIFT 1 /* EQ2_B3_GAIN - [5:1] */ 6817 #define ARIZONA_EQ2_B3_GAIN_WIDTH 5 /* EQ2_B3_GAIN - [5:1] */ 6818 #define ARIZONA_EQ2_ENA 0x0001 /* EQ2_ENA */ 6819 #define ARIZONA_EQ2_ENA_MASK 0x0001 /* EQ2_ENA */ 6820 #define ARIZONA_EQ2_ENA_SHIFT 0 /* EQ2_ENA */ 6821 #define ARIZONA_EQ2_ENA_WIDTH 1 /* EQ2_ENA */ 6822 6823 /* 6824 * R3623 (0xE27) - EQ2_2 6825 */ 6826 #define ARIZONA_EQ2_B4_GAIN_MASK 0xF800 /* EQ2_B4_GAIN - [15:11] */ 6827 #define ARIZONA_EQ2_B4_GAIN_SHIFT 11 /* EQ2_B4_GAIN - [15:11] */ 6828 #define ARIZONA_EQ2_B4_GAIN_WIDTH 5 /* EQ2_B4_GAIN - [15:11] */ 6829 #define ARIZONA_EQ2_B5_GAIN_MASK 0x07C0 /* EQ2_B5_GAIN - [10:6] */ 6830 #define ARIZONA_EQ2_B5_GAIN_SHIFT 6 /* EQ2_B5_GAIN - [10:6] */ 6831 #define ARIZONA_EQ2_B5_GAIN_WIDTH 5 /* EQ2_B5_GAIN - [10:6] */ 6832 #define ARIZONA_EQ2_B1_MODE 0x0001 /* EQ2_B1_MODE */ 6833 #define ARIZONA_EQ2_B1_MODE_MASK 0x0001 /* EQ2_B1_MODE */ 6834 #define ARIZONA_EQ2_B1_MODE_SHIFT 0 /* EQ2_B1_MODE */ 6835 #define ARIZONA_EQ2_B1_MODE_WIDTH 1 /* EQ2_B1_MODE */ 6836 6837 /* 6838 * R3624 (0xE28) - EQ2_3 6839 */ 6840 #define ARIZONA_EQ2_B1_A_MASK 0xFFFF /* EQ2_B1_A - [15:0] */ 6841 #define ARIZONA_EQ2_B1_A_SHIFT 0 /* EQ2_B1_A - [15:0] */ 6842 #define ARIZONA_EQ2_B1_A_WIDTH 16 /* EQ2_B1_A - [15:0] */ 6843 6844 /* 6845 * R3625 (0xE29) - EQ2_4 6846 */ 6847 #define ARIZONA_EQ2_B1_B_MASK 0xFFFF /* EQ2_B1_B - [15:0] */ 6848 #define ARIZONA_EQ2_B1_B_SHIFT 0 /* EQ2_B1_B - [15:0] */ 6849 #define ARIZONA_EQ2_B1_B_WIDTH 16 /* EQ2_B1_B - [15:0] */ 6850 6851 /* 6852 * R3626 (0xE2A) - EQ2_5 6853 */ 6854 #define ARIZONA_EQ2_B1_PG_MASK 0xFFFF /* EQ2_B1_PG - [15:0] */ 6855 #define ARIZONA_EQ2_B1_PG_SHIFT 0 /* EQ2_B1_PG - [15:0] */ 6856 #define ARIZONA_EQ2_B1_PG_WIDTH 16 /* EQ2_B1_PG - [15:0] */ 6857 6858 /* 6859 * R3627 (0xE2B) - EQ2_6 6860 */ 6861 #define ARIZONA_EQ2_B2_A_MASK 0xFFFF /* EQ2_B2_A - [15:0] */ 6862 #define ARIZONA_EQ2_B2_A_SHIFT 0 /* EQ2_B2_A - [15:0] */ 6863 #define ARIZONA_EQ2_B2_A_WIDTH 16 /* EQ2_B2_A - [15:0] */ 6864 6865 /* 6866 * R3628 (0xE2C) - EQ2_7 6867 */ 6868 #define ARIZONA_EQ2_B2_B_MASK 0xFFFF /* EQ2_B2_B - [15:0] */ 6869 #define ARIZONA_EQ2_B2_B_SHIFT 0 /* EQ2_B2_B - [15:0] */ 6870 #define ARIZONA_EQ2_B2_B_WIDTH 16 /* EQ2_B2_B - [15:0] */ 6871 6872 /* 6873 * R3629 (0xE2D) - EQ2_8 6874 */ 6875 #define ARIZONA_EQ2_B2_C_MASK 0xFFFF /* EQ2_B2_C - [15:0] */ 6876 #define ARIZONA_EQ2_B2_C_SHIFT 0 /* EQ2_B2_C - [15:0] */ 6877 #define ARIZONA_EQ2_B2_C_WIDTH 16 /* EQ2_B2_C - [15:0] */ 6878 6879 /* 6880 * R3630 (0xE2E) - EQ2_9 6881 */ 6882 #define ARIZONA_EQ2_B2_PG_MASK 0xFFFF /* EQ2_B2_PG - [15:0] */ 6883 #define ARIZONA_EQ2_B2_PG_SHIFT 0 /* EQ2_B2_PG - [15:0] */ 6884 #define ARIZONA_EQ2_B2_PG_WIDTH 16 /* EQ2_B2_PG - [15:0] */ 6885 6886 /* 6887 * R3631 (0xE2F) - EQ2_10 6888 */ 6889 #define ARIZONA_EQ2_B3_A_MASK 0xFFFF /* EQ2_B3_A - [15:0] */ 6890 #define ARIZONA_EQ2_B3_A_SHIFT 0 /* EQ2_B3_A - [15:0] */ 6891 #define ARIZONA_EQ2_B3_A_WIDTH 16 /* EQ2_B3_A - [15:0] */ 6892 6893 /* 6894 * R3632 (0xE30) - EQ2_11 6895 */ 6896 #define ARIZONA_EQ2_B3_B_MASK 0xFFFF /* EQ2_B3_B - [15:0] */ 6897 #define ARIZONA_EQ2_B3_B_SHIFT 0 /* EQ2_B3_B - [15:0] */ 6898 #define ARIZONA_EQ2_B3_B_WIDTH 16 /* EQ2_B3_B - [15:0] */ 6899 6900 /* 6901 * R3633 (0xE31) - EQ2_12 6902 */ 6903 #define ARIZONA_EQ2_B3_C_MASK 0xFFFF /* EQ2_B3_C - [15:0] */ 6904 #define ARIZONA_EQ2_B3_C_SHIFT 0 /* EQ2_B3_C - [15:0] */ 6905 #define ARIZONA_EQ2_B3_C_WIDTH 16 /* EQ2_B3_C - [15:0] */ 6906 6907 /* 6908 * R3634 (0xE32) - EQ2_13 6909 */ 6910 #define ARIZONA_EQ2_B3_PG_MASK 0xFFFF /* EQ2_B3_PG - [15:0] */ 6911 #define ARIZONA_EQ2_B3_PG_SHIFT 0 /* EQ2_B3_PG - [15:0] */ 6912 #define ARIZONA_EQ2_B3_PG_WIDTH 16 /* EQ2_B3_PG - [15:0] */ 6913 6914 /* 6915 * R3635 (0xE33) - EQ2_14 6916 */ 6917 #define ARIZONA_EQ2_B4_A_MASK 0xFFFF /* EQ2_B4_A - [15:0] */ 6918 #define ARIZONA_EQ2_B4_A_SHIFT 0 /* EQ2_B4_A - [15:0] */ 6919 #define ARIZONA_EQ2_B4_A_WIDTH 16 /* EQ2_B4_A - [15:0] */ 6920 6921 /* 6922 * R3636 (0xE34) - EQ2_15 6923 */ 6924 #define ARIZONA_EQ2_B4_B_MASK 0xFFFF /* EQ2_B4_B - [15:0] */ 6925 #define ARIZONA_EQ2_B4_B_SHIFT 0 /* EQ2_B4_B - [15:0] */ 6926 #define ARIZONA_EQ2_B4_B_WIDTH 16 /* EQ2_B4_B - [15:0] */ 6927 6928 /* 6929 * R3637 (0xE35) - EQ2_16 6930 */ 6931 #define ARIZONA_EQ2_B4_C_MASK 0xFFFF /* EQ2_B4_C - [15:0] */ 6932 #define ARIZONA_EQ2_B4_C_SHIFT 0 /* EQ2_B4_C - [15:0] */ 6933 #define ARIZONA_EQ2_B4_C_WIDTH 16 /* EQ2_B4_C - [15:0] */ 6934 6935 /* 6936 * R3638 (0xE36) - EQ2_17 6937 */ 6938 #define ARIZONA_EQ2_B4_PG_MASK 0xFFFF /* EQ2_B4_PG - [15:0] */ 6939 #define ARIZONA_EQ2_B4_PG_SHIFT 0 /* EQ2_B4_PG - [15:0] */ 6940 #define ARIZONA_EQ2_B4_PG_WIDTH 16 /* EQ2_B4_PG - [15:0] */ 6941 6942 /* 6943 * R3639 (0xE37) - EQ2_18 6944 */ 6945 #define ARIZONA_EQ2_B5_A_MASK 0xFFFF /* EQ2_B5_A - [15:0] */ 6946 #define ARIZONA_EQ2_B5_A_SHIFT 0 /* EQ2_B5_A - [15:0] */ 6947 #define ARIZONA_EQ2_B5_A_WIDTH 16 /* EQ2_B5_A - [15:0] */ 6948 6949 /* 6950 * R3640 (0xE38) - EQ2_19 6951 */ 6952 #define ARIZONA_EQ2_B5_B_MASK 0xFFFF /* EQ2_B5_B - [15:0] */ 6953 #define ARIZONA_EQ2_B5_B_SHIFT 0 /* EQ2_B5_B - [15:0] */ 6954 #define ARIZONA_EQ2_B5_B_WIDTH 16 /* EQ2_B5_B - [15:0] */ 6955 6956 /* 6957 * R3641 (0xE39) - EQ2_20 6958 */ 6959 #define ARIZONA_EQ2_B5_PG_MASK 0xFFFF /* EQ2_B5_PG - [15:0] */ 6960 #define ARIZONA_EQ2_B5_PG_SHIFT 0 /* EQ2_B5_PG - [15:0] */ 6961 #define ARIZONA_EQ2_B5_PG_WIDTH 16 /* EQ2_B5_PG - [15:0] */ 6962 6963 /* 6964 * R3642 (0xE3A) - EQ2_21 6965 */ 6966 #define ARIZONA_EQ2_B1_C_MASK 0xFFFF /* EQ2_B1_C - [15:0] */ 6967 #define ARIZONA_EQ2_B1_C_SHIFT 0 /* EQ2_B1_C - [15:0] */ 6968 #define ARIZONA_EQ2_B1_C_WIDTH 16 /* EQ2_B1_C - [15:0] */ 6969 6970 /* 6971 * R3644 (0xE3C) - EQ3_1 6972 */ 6973 #define ARIZONA_EQ3_B1_GAIN_MASK 0xF800 /* EQ3_B1_GAIN - [15:11] */ 6974 #define ARIZONA_EQ3_B1_GAIN_SHIFT 11 /* EQ3_B1_GAIN - [15:11] */ 6975 #define ARIZONA_EQ3_B1_GAIN_WIDTH 5 /* EQ3_B1_GAIN - [15:11] */ 6976 #define ARIZONA_EQ3_B2_GAIN_MASK 0x07C0 /* EQ3_B2_GAIN - [10:6] */ 6977 #define ARIZONA_EQ3_B2_GAIN_SHIFT 6 /* EQ3_B2_GAIN - [10:6] */ 6978 #define ARIZONA_EQ3_B2_GAIN_WIDTH 5 /* EQ3_B2_GAIN - [10:6] */ 6979 #define ARIZONA_EQ3_B3_GAIN_MASK 0x003E /* EQ3_B3_GAIN - [5:1] */ 6980 #define ARIZONA_EQ3_B3_GAIN_SHIFT 1 /* EQ3_B3_GAIN - [5:1] */ 6981 #define ARIZONA_EQ3_B3_GAIN_WIDTH 5 /* EQ3_B3_GAIN - [5:1] */ 6982 #define ARIZONA_EQ3_ENA 0x0001 /* EQ3_ENA */ 6983 #define ARIZONA_EQ3_ENA_MASK 0x0001 /* EQ3_ENA */ 6984 #define ARIZONA_EQ3_ENA_SHIFT 0 /* EQ3_ENA */ 6985 #define ARIZONA_EQ3_ENA_WIDTH 1 /* EQ3_ENA */ 6986 6987 /* 6988 * R3645 (0xE3D) - EQ3_2 6989 */ 6990 #define ARIZONA_EQ3_B4_GAIN_MASK 0xF800 /* EQ3_B4_GAIN - [15:11] */ 6991 #define ARIZONA_EQ3_B4_GAIN_SHIFT 11 /* EQ3_B4_GAIN - [15:11] */ 6992 #define ARIZONA_EQ3_B4_GAIN_WIDTH 5 /* EQ3_B4_GAIN - [15:11] */ 6993 #define ARIZONA_EQ3_B5_GAIN_MASK 0x07C0 /* EQ3_B5_GAIN - [10:6] */ 6994 #define ARIZONA_EQ3_B5_GAIN_SHIFT 6 /* EQ3_B5_GAIN - [10:6] */ 6995 #define ARIZONA_EQ3_B5_GAIN_WIDTH 5 /* EQ3_B5_GAIN - [10:6] */ 6996 #define ARIZONA_EQ3_B1_MODE 0x0001 /* EQ3_B1_MODE */ 6997 #define ARIZONA_EQ3_B1_MODE_MASK 0x0001 /* EQ3_B1_MODE */ 6998 #define ARIZONA_EQ3_B1_MODE_SHIFT 0 /* EQ3_B1_MODE */ 6999 #define ARIZONA_EQ3_B1_MODE_WIDTH 1 /* EQ3_B1_MODE */ 7000 7001 /* 7002 * R3646 (0xE3E) - EQ3_3 7003 */ 7004 #define ARIZONA_EQ3_B1_A_MASK 0xFFFF /* EQ3_B1_A - [15:0] */ 7005 #define ARIZONA_EQ3_B1_A_SHIFT 0 /* EQ3_B1_A - [15:0] */ 7006 #define ARIZONA_EQ3_B1_A_WIDTH 16 /* EQ3_B1_A - [15:0] */ 7007 7008 /* 7009 * R3647 (0xE3F) - EQ3_4 7010 */ 7011 #define ARIZONA_EQ3_B1_B_MASK 0xFFFF /* EQ3_B1_B - [15:0] */ 7012 #define ARIZONA_EQ3_B1_B_SHIFT 0 /* EQ3_B1_B - [15:0] */ 7013 #define ARIZONA_EQ3_B1_B_WIDTH 16 /* EQ3_B1_B - [15:0] */ 7014 7015 /* 7016 * R3648 (0xE40) - EQ3_5 7017 */ 7018 #define ARIZONA_EQ3_B1_PG_MASK 0xFFFF /* EQ3_B1_PG - [15:0] */ 7019 #define ARIZONA_EQ3_B1_PG_SHIFT 0 /* EQ3_B1_PG - [15:0] */ 7020 #define ARIZONA_EQ3_B1_PG_WIDTH 16 /* EQ3_B1_PG - [15:0] */ 7021 7022 /* 7023 * R3649 (0xE41) - EQ3_6 7024 */ 7025 #define ARIZONA_EQ3_B2_A_MASK 0xFFFF /* EQ3_B2_A - [15:0] */ 7026 #define ARIZONA_EQ3_B2_A_SHIFT 0 /* EQ3_B2_A - [15:0] */ 7027 #define ARIZONA_EQ3_B2_A_WIDTH 16 /* EQ3_B2_A - [15:0] */ 7028 7029 /* 7030 * R3650 (0xE42) - EQ3_7 7031 */ 7032 #define ARIZONA_EQ3_B2_B_MASK 0xFFFF /* EQ3_B2_B - [15:0] */ 7033 #define ARIZONA_EQ3_B2_B_SHIFT 0 /* EQ3_B2_B - [15:0] */ 7034 #define ARIZONA_EQ3_B2_B_WIDTH 16 /* EQ3_B2_B - [15:0] */ 7035 7036 /* 7037 * R3651 (0xE43) - EQ3_8 7038 */ 7039 #define ARIZONA_EQ3_B2_C_MASK 0xFFFF /* EQ3_B2_C - [15:0] */ 7040 #define ARIZONA_EQ3_B2_C_SHIFT 0 /* EQ3_B2_C - [15:0] */ 7041 #define ARIZONA_EQ3_B2_C_WIDTH 16 /* EQ3_B2_C - [15:0] */ 7042 7043 /* 7044 * R3652 (0xE44) - EQ3_9 7045 */ 7046 #define ARIZONA_EQ3_B2_PG_MASK 0xFFFF /* EQ3_B2_PG - [15:0] */ 7047 #define ARIZONA_EQ3_B2_PG_SHIFT 0 /* EQ3_B2_PG - [15:0] */ 7048 #define ARIZONA_EQ3_B2_PG_WIDTH 16 /* EQ3_B2_PG - [15:0] */ 7049 7050 /* 7051 * R3653 (0xE45) - EQ3_10 7052 */ 7053 #define ARIZONA_EQ3_B3_A_MASK 0xFFFF /* EQ3_B3_A - [15:0] */ 7054 #define ARIZONA_EQ3_B3_A_SHIFT 0 /* EQ3_B3_A - [15:0] */ 7055 #define ARIZONA_EQ3_B3_A_WIDTH 16 /* EQ3_B3_A - [15:0] */ 7056 7057 /* 7058 * R3654 (0xE46) - EQ3_11 7059 */ 7060 #define ARIZONA_EQ3_B3_B_MASK 0xFFFF /* EQ3_B3_B - [15:0] */ 7061 #define ARIZONA_EQ3_B3_B_SHIFT 0 /* EQ3_B3_B - [15:0] */ 7062 #define ARIZONA_EQ3_B3_B_WIDTH 16 /* EQ3_B3_B - [15:0] */ 7063 7064 /* 7065 * R3655 (0xE47) - EQ3_12 7066 */ 7067 #define ARIZONA_EQ3_B3_C_MASK 0xFFFF /* EQ3_B3_C - [15:0] */ 7068 #define ARIZONA_EQ3_B3_C_SHIFT 0 /* EQ3_B3_C - [15:0] */ 7069 #define ARIZONA_EQ3_B3_C_WIDTH 16 /* EQ3_B3_C - [15:0] */ 7070 7071 /* 7072 * R3656 (0xE48) - EQ3_13 7073 */ 7074 #define ARIZONA_EQ3_B3_PG_MASK 0xFFFF /* EQ3_B3_PG - [15:0] */ 7075 #define ARIZONA_EQ3_B3_PG_SHIFT 0 /* EQ3_B3_PG - [15:0] */ 7076 #define ARIZONA_EQ3_B3_PG_WIDTH 16 /* EQ3_B3_PG - [15:0] */ 7077 7078 /* 7079 * R3657 (0xE49) - EQ3_14 7080 */ 7081 #define ARIZONA_EQ3_B4_A_MASK 0xFFFF /* EQ3_B4_A - [15:0] */ 7082 #define ARIZONA_EQ3_B4_A_SHIFT 0 /* EQ3_B4_A - [15:0] */ 7083 #define ARIZONA_EQ3_B4_A_WIDTH 16 /* EQ3_B4_A - [15:0] */ 7084 7085 /* 7086 * R3658 (0xE4A) - EQ3_15 7087 */ 7088 #define ARIZONA_EQ3_B4_B_MASK 0xFFFF /* EQ3_B4_B - [15:0] */ 7089 #define ARIZONA_EQ3_B4_B_SHIFT 0 /* EQ3_B4_B - [15:0] */ 7090 #define ARIZONA_EQ3_B4_B_WIDTH 16 /* EQ3_B4_B - [15:0] */ 7091 7092 /* 7093 * R3659 (0xE4B) - EQ3_16 7094 */ 7095 #define ARIZONA_EQ3_B4_C_MASK 0xFFFF /* EQ3_B4_C - [15:0] */ 7096 #define ARIZONA_EQ3_B4_C_SHIFT 0 /* EQ3_B4_C - [15:0] */ 7097 #define ARIZONA_EQ3_B4_C_WIDTH 16 /* EQ3_B4_C - [15:0] */ 7098 7099 /* 7100 * R3660 (0xE4C) - EQ3_17 7101 */ 7102 #define ARIZONA_EQ3_B4_PG_MASK 0xFFFF /* EQ3_B4_PG - [15:0] */ 7103 #define ARIZONA_EQ3_B4_PG_SHIFT 0 /* EQ3_B4_PG - [15:0] */ 7104 #define ARIZONA_EQ3_B4_PG_WIDTH 16 /* EQ3_B4_PG - [15:0] */ 7105 7106 /* 7107 * R3661 (0xE4D) - EQ3_18 7108 */ 7109 #define ARIZONA_EQ3_B5_A_MASK 0xFFFF /* EQ3_B5_A - [15:0] */ 7110 #define ARIZONA_EQ3_B5_A_SHIFT 0 /* EQ3_B5_A - [15:0] */ 7111 #define ARIZONA_EQ3_B5_A_WIDTH 16 /* EQ3_B5_A - [15:0] */ 7112 7113 /* 7114 * R3662 (0xE4E) - EQ3_19 7115 */ 7116 #define ARIZONA_EQ3_B5_B_MASK 0xFFFF /* EQ3_B5_B - [15:0] */ 7117 #define ARIZONA_EQ3_B5_B_SHIFT 0 /* EQ3_B5_B - [15:0] */ 7118 #define ARIZONA_EQ3_B5_B_WIDTH 16 /* EQ3_B5_B - [15:0] */ 7119 7120 /* 7121 * R3663 (0xE4F) - EQ3_20 7122 */ 7123 #define ARIZONA_EQ3_B5_PG_MASK 0xFFFF /* EQ3_B5_PG - [15:0] */ 7124 #define ARIZONA_EQ3_B5_PG_SHIFT 0 /* EQ3_B5_PG - [15:0] */ 7125 #define ARIZONA_EQ3_B5_PG_WIDTH 16 /* EQ3_B5_PG - [15:0] */ 7126 7127 /* 7128 * R3664 (0xE50) - EQ3_21 7129 */ 7130 #define ARIZONA_EQ3_B1_C_MASK 0xFFFF /* EQ3_B1_C - [15:0] */ 7131 #define ARIZONA_EQ3_B1_C_SHIFT 0 /* EQ3_B1_C - [15:0] */ 7132 #define ARIZONA_EQ3_B1_C_WIDTH 16 /* EQ3_B1_C - [15:0] */ 7133 7134 /* 7135 * R3666 (0xE52) - EQ4_1 7136 */ 7137 #define ARIZONA_EQ4_B1_GAIN_MASK 0xF800 /* EQ4_B1_GAIN - [15:11] */ 7138 #define ARIZONA_EQ4_B1_GAIN_SHIFT 11 /* EQ4_B1_GAIN - [15:11] */ 7139 #define ARIZONA_EQ4_B1_GAIN_WIDTH 5 /* EQ4_B1_GAIN - [15:11] */ 7140 #define ARIZONA_EQ4_B2_GAIN_MASK 0x07C0 /* EQ4_B2_GAIN - [10:6] */ 7141 #define ARIZONA_EQ4_B2_GAIN_SHIFT 6 /* EQ4_B2_GAIN - [10:6] */ 7142 #define ARIZONA_EQ4_B2_GAIN_WIDTH 5 /* EQ4_B2_GAIN - [10:6] */ 7143 #define ARIZONA_EQ4_B3_GAIN_MASK 0x003E /* EQ4_B3_GAIN - [5:1] */ 7144 #define ARIZONA_EQ4_B3_GAIN_SHIFT 1 /* EQ4_B3_GAIN - [5:1] */ 7145 #define ARIZONA_EQ4_B3_GAIN_WIDTH 5 /* EQ4_B3_GAIN - [5:1] */ 7146 #define ARIZONA_EQ4_ENA 0x0001 /* EQ4_ENA */ 7147 #define ARIZONA_EQ4_ENA_MASK 0x0001 /* EQ4_ENA */ 7148 #define ARIZONA_EQ4_ENA_SHIFT 0 /* EQ4_ENA */ 7149 #define ARIZONA_EQ4_ENA_WIDTH 1 /* EQ4_ENA */ 7150 7151 /* 7152 * R3667 (0xE53) - EQ4_2 7153 */ 7154 #define ARIZONA_EQ4_B4_GAIN_MASK 0xF800 /* EQ4_B4_GAIN - [15:11] */ 7155 #define ARIZONA_EQ4_B4_GAIN_SHIFT 11 /* EQ4_B4_GAIN - [15:11] */ 7156 #define ARIZONA_EQ4_B4_GAIN_WIDTH 5 /* EQ4_B4_GAIN - [15:11] */ 7157 #define ARIZONA_EQ4_B5_GAIN_MASK 0x07C0 /* EQ4_B5_GAIN - [10:6] */ 7158 #define ARIZONA_EQ4_B5_GAIN_SHIFT 6 /* EQ4_B5_GAIN - [10:6] */ 7159 #define ARIZONA_EQ4_B5_GAIN_WIDTH 5 /* EQ4_B5_GAIN - [10:6] */ 7160 #define ARIZONA_EQ4_B1_MODE 0x0001 /* EQ4_B1_MODE */ 7161 #define ARIZONA_EQ4_B1_MODE_MASK 0x0001 /* EQ4_B1_MODE */ 7162 #define ARIZONA_EQ4_B1_MODE_SHIFT 0 /* EQ4_B1_MODE */ 7163 #define ARIZONA_EQ4_B1_MODE_WIDTH 1 /* EQ4_B1_MODE */ 7164 7165 /* 7166 * R3668 (0xE54) - EQ4_3 7167 */ 7168 #define ARIZONA_EQ4_B1_A_MASK 0xFFFF /* EQ4_B1_A - [15:0] */ 7169 #define ARIZONA_EQ4_B1_A_SHIFT 0 /* EQ4_B1_A - [15:0] */ 7170 #define ARIZONA_EQ4_B1_A_WIDTH 16 /* EQ4_B1_A - [15:0] */ 7171 7172 /* 7173 * R3669 (0xE55) - EQ4_4 7174 */ 7175 #define ARIZONA_EQ4_B1_B_MASK 0xFFFF /* EQ4_B1_B - [15:0] */ 7176 #define ARIZONA_EQ4_B1_B_SHIFT 0 /* EQ4_B1_B - [15:0] */ 7177 #define ARIZONA_EQ4_B1_B_WIDTH 16 /* EQ4_B1_B - [15:0] */ 7178 7179 /* 7180 * R3670 (0xE56) - EQ4_5 7181 */ 7182 #define ARIZONA_EQ4_B1_PG_MASK 0xFFFF /* EQ4_B1_PG - [15:0] */ 7183 #define ARIZONA_EQ4_B1_PG_SHIFT 0 /* EQ4_B1_PG - [15:0] */ 7184 #define ARIZONA_EQ4_B1_PG_WIDTH 16 /* EQ4_B1_PG - [15:0] */ 7185 7186 /* 7187 * R3671 (0xE57) - EQ4_6 7188 */ 7189 #define ARIZONA_EQ4_B2_A_MASK 0xFFFF /* EQ4_B2_A - [15:0] */ 7190 #define ARIZONA_EQ4_B2_A_SHIFT 0 /* EQ4_B2_A - [15:0] */ 7191 #define ARIZONA_EQ4_B2_A_WIDTH 16 /* EQ4_B2_A - [15:0] */ 7192 7193 /* 7194 * R3672 (0xE58) - EQ4_7 7195 */ 7196 #define ARIZONA_EQ4_B2_B_MASK 0xFFFF /* EQ4_B2_B - [15:0] */ 7197 #define ARIZONA_EQ4_B2_B_SHIFT 0 /* EQ4_B2_B - [15:0] */ 7198 #define ARIZONA_EQ4_B2_B_WIDTH 16 /* EQ4_B2_B - [15:0] */ 7199 7200 /* 7201 * R3673 (0xE59) - EQ4_8 7202 */ 7203 #define ARIZONA_EQ4_B2_C_MASK 0xFFFF /* EQ4_B2_C - [15:0] */ 7204 #define ARIZONA_EQ4_B2_C_SHIFT 0 /* EQ4_B2_C - [15:0] */ 7205 #define ARIZONA_EQ4_B2_C_WIDTH 16 /* EQ4_B2_C - [15:0] */ 7206 7207 /* 7208 * R3674 (0xE5A) - EQ4_9 7209 */ 7210 #define ARIZONA_EQ4_B2_PG_MASK 0xFFFF /* EQ4_B2_PG - [15:0] */ 7211 #define ARIZONA_EQ4_B2_PG_SHIFT 0 /* EQ4_B2_PG - [15:0] */ 7212 #define ARIZONA_EQ4_B2_PG_WIDTH 16 /* EQ4_B2_PG - [15:0] */ 7213 7214 /* 7215 * R3675 (0xE5B) - EQ4_10 7216 */ 7217 #define ARIZONA_EQ4_B3_A_MASK 0xFFFF /* EQ4_B3_A - [15:0] */ 7218 #define ARIZONA_EQ4_B3_A_SHIFT 0 /* EQ4_B3_A - [15:0] */ 7219 #define ARIZONA_EQ4_B3_A_WIDTH 16 /* EQ4_B3_A - [15:0] */ 7220 7221 /* 7222 * R3676 (0xE5C) - EQ4_11 7223 */ 7224 #define ARIZONA_EQ4_B3_B_MASK 0xFFFF /* EQ4_B3_B - [15:0] */ 7225 #define ARIZONA_EQ4_B3_B_SHIFT 0 /* EQ4_B3_B - [15:0] */ 7226 #define ARIZONA_EQ4_B3_B_WIDTH 16 /* EQ4_B3_B - [15:0] */ 7227 7228 /* 7229 * R3677 (0xE5D) - EQ4_12 7230 */ 7231 #define ARIZONA_EQ4_B3_C_MASK 0xFFFF /* EQ4_B3_C - [15:0] */ 7232 #define ARIZONA_EQ4_B3_C_SHIFT 0 /* EQ4_B3_C - [15:0] */ 7233 #define ARIZONA_EQ4_B3_C_WIDTH 16 /* EQ4_B3_C - [15:0] */ 7234 7235 /* 7236 * R3678 (0xE5E) - EQ4_13 7237 */ 7238 #define ARIZONA_EQ4_B3_PG_MASK 0xFFFF /* EQ4_B3_PG - [15:0] */ 7239 #define ARIZONA_EQ4_B3_PG_SHIFT 0 /* EQ4_B3_PG - [15:0] */ 7240 #define ARIZONA_EQ4_B3_PG_WIDTH 16 /* EQ4_B3_PG - [15:0] */ 7241 7242 /* 7243 * R3679 (0xE5F) - EQ4_14 7244 */ 7245 #define ARIZONA_EQ4_B4_A_MASK 0xFFFF /* EQ4_B4_A - [15:0] */ 7246 #define ARIZONA_EQ4_B4_A_SHIFT 0 /* EQ4_B4_A - [15:0] */ 7247 #define ARIZONA_EQ4_B4_A_WIDTH 16 /* EQ4_B4_A - [15:0] */ 7248 7249 /* 7250 * R3680 (0xE60) - EQ4_15 7251 */ 7252 #define ARIZONA_EQ4_B4_B_MASK 0xFFFF /* EQ4_B4_B - [15:0] */ 7253 #define ARIZONA_EQ4_B4_B_SHIFT 0 /* EQ4_B4_B - [15:0] */ 7254 #define ARIZONA_EQ4_B4_B_WIDTH 16 /* EQ4_B4_B - [15:0] */ 7255 7256 /* 7257 * R3681 (0xE61) - EQ4_16 7258 */ 7259 #define ARIZONA_EQ4_B4_C_MASK 0xFFFF /* EQ4_B4_C - [15:0] */ 7260 #define ARIZONA_EQ4_B4_C_SHIFT 0 /* EQ4_B4_C - [15:0] */ 7261 #define ARIZONA_EQ4_B4_C_WIDTH 16 /* EQ4_B4_C - [15:0] */ 7262 7263 /* 7264 * R3682 (0xE62) - EQ4_17 7265 */ 7266 #define ARIZONA_EQ4_B4_PG_MASK 0xFFFF /* EQ4_B4_PG - [15:0] */ 7267 #define ARIZONA_EQ4_B4_PG_SHIFT 0 /* EQ4_B4_PG - [15:0] */ 7268 #define ARIZONA_EQ4_B4_PG_WIDTH 16 /* EQ4_B4_PG - [15:0] */ 7269 7270 /* 7271 * R3683 (0xE63) - EQ4_18 7272 */ 7273 #define ARIZONA_EQ4_B5_A_MASK 0xFFFF /* EQ4_B5_A - [15:0] */ 7274 #define ARIZONA_EQ4_B5_A_SHIFT 0 /* EQ4_B5_A - [15:0] */ 7275 #define ARIZONA_EQ4_B5_A_WIDTH 16 /* EQ4_B5_A - [15:0] */ 7276 7277 /* 7278 * R3684 (0xE64) - EQ4_19 7279 */ 7280 #define ARIZONA_EQ4_B5_B_MASK 0xFFFF /* EQ4_B5_B - [15:0] */ 7281 #define ARIZONA_EQ4_B5_B_SHIFT 0 /* EQ4_B5_B - [15:0] */ 7282 #define ARIZONA_EQ4_B5_B_WIDTH 16 /* EQ4_B5_B - [15:0] */ 7283 7284 /* 7285 * R3685 (0xE65) - EQ4_20 7286 */ 7287 #define ARIZONA_EQ4_B5_PG_MASK 0xFFFF /* EQ4_B5_PG - [15:0] */ 7288 #define ARIZONA_EQ4_B5_PG_SHIFT 0 /* EQ4_B5_PG - [15:0] */ 7289 #define ARIZONA_EQ4_B5_PG_WIDTH 16 /* EQ4_B5_PG - [15:0] */ 7290 7291 /* 7292 * R3686 (0xE66) - EQ4_21 7293 */ 7294 #define ARIZONA_EQ4_B1_C_MASK 0xFFFF /* EQ4_B1_C - [15:0] */ 7295 #define ARIZONA_EQ4_B1_C_SHIFT 0 /* EQ4_B1_C - [15:0] */ 7296 #define ARIZONA_EQ4_B1_C_WIDTH 16 /* EQ4_B1_C - [15:0] */ 7297 7298 /* 7299 * R3712 (0xE80) - DRC1 ctrl1 7300 */ 7301 #define ARIZONA_DRC1_SIG_DET_RMS_MASK 0xF800 /* DRC1_SIG_DET_RMS - [15:11] */ 7302 #define ARIZONA_DRC1_SIG_DET_RMS_SHIFT 11 /* DRC1_SIG_DET_RMS - [15:11] */ 7303 #define ARIZONA_DRC1_SIG_DET_RMS_WIDTH 5 /* DRC1_SIG_DET_RMS - [15:11] */ 7304 #define ARIZONA_DRC1_SIG_DET_PK_MASK 0x0600 /* DRC1_SIG_DET_PK - [10:9] */ 7305 #define ARIZONA_DRC1_SIG_DET_PK_SHIFT 9 /* DRC1_SIG_DET_PK - [10:9] */ 7306 #define ARIZONA_DRC1_SIG_DET_PK_WIDTH 2 /* DRC1_SIG_DET_PK - [10:9] */ 7307 #define ARIZONA_DRC1_NG_ENA 0x0100 /* DRC1_NG_ENA */ 7308 #define ARIZONA_DRC1_NG_ENA_MASK 0x0100 /* DRC1_NG_ENA */ 7309 #define ARIZONA_DRC1_NG_ENA_SHIFT 8 /* DRC1_NG_ENA */ 7310 #define ARIZONA_DRC1_NG_ENA_WIDTH 1 /* DRC1_NG_ENA */ 7311 #define ARIZONA_DRC1_SIG_DET_MODE 0x0080 /* DRC1_SIG_DET_MODE */ 7312 #define ARIZONA_DRC1_SIG_DET_MODE_MASK 0x0080 /* DRC1_SIG_DET_MODE */ 7313 #define ARIZONA_DRC1_SIG_DET_MODE_SHIFT 7 /* DRC1_SIG_DET_MODE */ 7314 #define ARIZONA_DRC1_SIG_DET_MODE_WIDTH 1 /* DRC1_SIG_DET_MODE */ 7315 #define ARIZONA_DRC1_SIG_DET 0x0040 /* DRC1_SIG_DET */ 7316 #define ARIZONA_DRC1_SIG_DET_MASK 0x0040 /* DRC1_SIG_DET */ 7317 #define ARIZONA_DRC1_SIG_DET_SHIFT 6 /* DRC1_SIG_DET */ 7318 #define ARIZONA_DRC1_SIG_DET_WIDTH 1 /* DRC1_SIG_DET */ 7319 #define ARIZONA_DRC1_KNEE2_OP_ENA 0x0020 /* DRC1_KNEE2_OP_ENA */ 7320 #define ARIZONA_DRC1_KNEE2_OP_ENA_MASK 0x0020 /* DRC1_KNEE2_OP_ENA */ 7321 #define ARIZONA_DRC1_KNEE2_OP_ENA_SHIFT 5 /* DRC1_KNEE2_OP_ENA */ 7322 #define ARIZONA_DRC1_KNEE2_OP_ENA_WIDTH 1 /* DRC1_KNEE2_OP_ENA */ 7323 #define ARIZONA_DRC1_QR 0x0010 /* DRC1_QR */ 7324 #define ARIZONA_DRC1_QR_MASK 0x0010 /* DRC1_QR */ 7325 #define ARIZONA_DRC1_QR_SHIFT 4 /* DRC1_QR */ 7326 #define ARIZONA_DRC1_QR_WIDTH 1 /* DRC1_QR */ 7327 #define ARIZONA_DRC1_ANTICLIP 0x0008 /* DRC1_ANTICLIP */ 7328 #define ARIZONA_DRC1_ANTICLIP_MASK 0x0008 /* DRC1_ANTICLIP */ 7329 #define ARIZONA_DRC1_ANTICLIP_SHIFT 3 /* DRC1_ANTICLIP */ 7330 #define ARIZONA_DRC1_ANTICLIP_WIDTH 1 /* DRC1_ANTICLIP */ 7331 #define ARIZONA_DRC1L_ENA 0x0002 /* DRC1L_ENA */ 7332 #define ARIZONA_DRC1L_ENA_MASK 0x0002 /* DRC1L_ENA */ 7333 #define ARIZONA_DRC1L_ENA_SHIFT 1 /* DRC1L_ENA */ 7334 #define ARIZONA_DRC1L_ENA_WIDTH 1 /* DRC1L_ENA */ 7335 #define ARIZONA_DRC1R_ENA 0x0001 /* DRC1R_ENA */ 7336 #define ARIZONA_DRC1R_ENA_MASK 0x0001 /* DRC1R_ENA */ 7337 #define ARIZONA_DRC1R_ENA_SHIFT 0 /* DRC1R_ENA */ 7338 #define ARIZONA_DRC1R_ENA_WIDTH 1 /* DRC1R_ENA */ 7339 7340 /* 7341 * R3713 (0xE81) - DRC1 ctrl2 7342 */ 7343 #define ARIZONA_DRC1_ATK_MASK 0x1E00 /* DRC1_ATK - [12:9] */ 7344 #define ARIZONA_DRC1_ATK_SHIFT 9 /* DRC1_ATK - [12:9] */ 7345 #define ARIZONA_DRC1_ATK_WIDTH 4 /* DRC1_ATK - [12:9] */ 7346 #define ARIZONA_DRC1_DCY_MASK 0x01E0 /* DRC1_DCY - [8:5] */ 7347 #define ARIZONA_DRC1_DCY_SHIFT 5 /* DRC1_DCY - [8:5] */ 7348 #define ARIZONA_DRC1_DCY_WIDTH 4 /* DRC1_DCY - [8:5] */ 7349 #define ARIZONA_DRC1_MINGAIN_MASK 0x001C /* DRC1_MINGAIN - [4:2] */ 7350 #define ARIZONA_DRC1_MINGAIN_SHIFT 2 /* DRC1_MINGAIN - [4:2] */ 7351 #define ARIZONA_DRC1_MINGAIN_WIDTH 3 /* DRC1_MINGAIN - [4:2] */ 7352 #define ARIZONA_DRC1_MAXGAIN_MASK 0x0003 /* DRC1_MAXGAIN - [1:0] */ 7353 #define ARIZONA_DRC1_MAXGAIN_SHIFT 0 /* DRC1_MAXGAIN - [1:0] */ 7354 #define ARIZONA_DRC1_MAXGAIN_WIDTH 2 /* DRC1_MAXGAIN - [1:0] */ 7355 7356 /* 7357 * R3714 (0xE82) - DRC1 ctrl3 7358 */ 7359 #define ARIZONA_DRC1_NG_MINGAIN_MASK 0xF000 /* DRC1_NG_MINGAIN - [15:12] */ 7360 #define ARIZONA_DRC1_NG_MINGAIN_SHIFT 12 /* DRC1_NG_MINGAIN - [15:12] */ 7361 #define ARIZONA_DRC1_NG_MINGAIN_WIDTH 4 /* DRC1_NG_MINGAIN - [15:12] */ 7362 #define ARIZONA_DRC1_NG_EXP_MASK 0x0C00 /* DRC1_NG_EXP - [11:10] */ 7363 #define ARIZONA_DRC1_NG_EXP_SHIFT 10 /* DRC1_NG_EXP - [11:10] */ 7364 #define ARIZONA_DRC1_NG_EXP_WIDTH 2 /* DRC1_NG_EXP - [11:10] */ 7365 #define ARIZONA_DRC1_QR_THR_MASK 0x0300 /* DRC1_QR_THR - [9:8] */ 7366 #define ARIZONA_DRC1_QR_THR_SHIFT 8 /* DRC1_QR_THR - [9:8] */ 7367 #define ARIZONA_DRC1_QR_THR_WIDTH 2 /* DRC1_QR_THR - [9:8] */ 7368 #define ARIZONA_DRC1_QR_DCY_MASK 0x00C0 /* DRC1_QR_DCY - [7:6] */ 7369 #define ARIZONA_DRC1_QR_DCY_SHIFT 6 /* DRC1_QR_DCY - [7:6] */ 7370 #define ARIZONA_DRC1_QR_DCY_WIDTH 2 /* DRC1_QR_DCY - [7:6] */ 7371 #define ARIZONA_DRC1_HI_COMP_MASK 0x0038 /* DRC1_HI_COMP - [5:3] */ 7372 #define ARIZONA_DRC1_HI_COMP_SHIFT 3 /* DRC1_HI_COMP - [5:3] */ 7373 #define ARIZONA_DRC1_HI_COMP_WIDTH 3 /* DRC1_HI_COMP - [5:3] */ 7374 #define ARIZONA_DRC1_LO_COMP_MASK 0x0007 /* DRC1_LO_COMP - [2:0] */ 7375 #define ARIZONA_DRC1_LO_COMP_SHIFT 0 /* DRC1_LO_COMP - [2:0] */ 7376 #define ARIZONA_DRC1_LO_COMP_WIDTH 3 /* DRC1_LO_COMP - [2:0] */ 7377 7378 /* 7379 * R3715 (0xE83) - DRC1 ctrl4 7380 */ 7381 #define ARIZONA_DRC1_KNEE_IP_MASK 0x07E0 /* DRC1_KNEE_IP - [10:5] */ 7382 #define ARIZONA_DRC1_KNEE_IP_SHIFT 5 /* DRC1_KNEE_IP - [10:5] */ 7383 #define ARIZONA_DRC1_KNEE_IP_WIDTH 6 /* DRC1_KNEE_IP - [10:5] */ 7384 #define ARIZONA_DRC1_KNEE_OP_MASK 0x001F /* DRC1_KNEE_OP - [4:0] */ 7385 #define ARIZONA_DRC1_KNEE_OP_SHIFT 0 /* DRC1_KNEE_OP - [4:0] */ 7386 #define ARIZONA_DRC1_KNEE_OP_WIDTH 5 /* DRC1_KNEE_OP - [4:0] */ 7387 7388 /* 7389 * R3716 (0xE84) - DRC1 ctrl5 7390 */ 7391 #define ARIZONA_DRC1_KNEE2_IP_MASK 0x03E0 /* DRC1_KNEE2_IP - [9:5] */ 7392 #define ARIZONA_DRC1_KNEE2_IP_SHIFT 5 /* DRC1_KNEE2_IP - [9:5] */ 7393 #define ARIZONA_DRC1_KNEE2_IP_WIDTH 5 /* DRC1_KNEE2_IP - [9:5] */ 7394 #define ARIZONA_DRC1_KNEE2_OP_MASK 0x001F /* DRC1_KNEE2_OP - [4:0] */ 7395 #define ARIZONA_DRC1_KNEE2_OP_SHIFT 0 /* DRC1_KNEE2_OP - [4:0] */ 7396 #define ARIZONA_DRC1_KNEE2_OP_WIDTH 5 /* DRC1_KNEE2_OP - [4:0] */ 7397 7398 /* 7399 * R3721 (0xE89) - DRC2 ctrl1 7400 */ 7401 #define ARIZONA_DRC2_SIG_DET_RMS_MASK 0xF800 /* DRC2_SIG_DET_RMS - [15:11] */ 7402 #define ARIZONA_DRC2_SIG_DET_RMS_SHIFT 11 /* DRC2_SIG_DET_RMS - [15:11] */ 7403 #define ARIZONA_DRC2_SIG_DET_RMS_WIDTH 5 /* DRC2_SIG_DET_RMS - [15:11] */ 7404 #define ARIZONA_DRC2_SIG_DET_PK_MASK 0x0600 /* DRC2_SIG_DET_PK - [10:9] */ 7405 #define ARIZONA_DRC2_SIG_DET_PK_SHIFT 9 /* DRC2_SIG_DET_PK - [10:9] */ 7406 #define ARIZONA_DRC2_SIG_DET_PK_WIDTH 2 /* DRC2_SIG_DET_PK - [10:9] */ 7407 #define ARIZONA_DRC2_NG_ENA 0x0100 /* DRC2_NG_ENA */ 7408 #define ARIZONA_DRC2_NG_ENA_MASK 0x0100 /* DRC2_NG_ENA */ 7409 #define ARIZONA_DRC2_NG_ENA_SHIFT 8 /* DRC2_NG_ENA */ 7410 #define ARIZONA_DRC2_NG_ENA_WIDTH 1 /* DRC2_NG_ENA */ 7411 #define ARIZONA_DRC2_SIG_DET_MODE 0x0080 /* DRC2_SIG_DET_MODE */ 7412 #define ARIZONA_DRC2_SIG_DET_MODE_MASK 0x0080 /* DRC2_SIG_DET_MODE */ 7413 #define ARIZONA_DRC2_SIG_DET_MODE_SHIFT 7 /* DRC2_SIG_DET_MODE */ 7414 #define ARIZONA_DRC2_SIG_DET_MODE_WIDTH 1 /* DRC2_SIG_DET_MODE */ 7415 #define ARIZONA_DRC2_SIG_DET 0x0040 /* DRC2_SIG_DET */ 7416 #define ARIZONA_DRC2_SIG_DET_MASK 0x0040 /* DRC2_SIG_DET */ 7417 #define ARIZONA_DRC2_SIG_DET_SHIFT 6 /* DRC2_SIG_DET */ 7418 #define ARIZONA_DRC2_SIG_DET_WIDTH 1 /* DRC2_SIG_DET */ 7419 #define ARIZONA_DRC2_KNEE2_OP_ENA 0x0020 /* DRC2_KNEE2_OP_ENA */ 7420 #define ARIZONA_DRC2_KNEE2_OP_ENA_MASK 0x0020 /* DRC2_KNEE2_OP_ENA */ 7421 #define ARIZONA_DRC2_KNEE2_OP_ENA_SHIFT 5 /* DRC2_KNEE2_OP_ENA */ 7422 #define ARIZONA_DRC2_KNEE2_OP_ENA_WIDTH 1 /* DRC2_KNEE2_OP_ENA */ 7423 #define ARIZONA_DRC2_QR 0x0010 /* DRC2_QR */ 7424 #define ARIZONA_DRC2_QR_MASK 0x0010 /* DRC2_QR */ 7425 #define ARIZONA_DRC2_QR_SHIFT 4 /* DRC2_QR */ 7426 #define ARIZONA_DRC2_QR_WIDTH 1 /* DRC2_QR */ 7427 #define ARIZONA_DRC2_ANTICLIP 0x0008 /* DRC2_ANTICLIP */ 7428 #define ARIZONA_DRC2_ANTICLIP_MASK 0x0008 /* DRC2_ANTICLIP */ 7429 #define ARIZONA_DRC2_ANTICLIP_SHIFT 3 /* DRC2_ANTICLIP */ 7430 #define ARIZONA_DRC2_ANTICLIP_WIDTH 1 /* DRC2_ANTICLIP */ 7431 #define ARIZONA_DRC2L_ENA 0x0002 /* DRC2L_ENA */ 7432 #define ARIZONA_DRC2L_ENA_MASK 0x0002 /* DRC2L_ENA */ 7433 #define ARIZONA_DRC2L_ENA_SHIFT 1 /* DRC2L_ENA */ 7434 #define ARIZONA_DRC2L_ENA_WIDTH 1 /* DRC2L_ENA */ 7435 #define ARIZONA_DRC2R_ENA 0x0001 /* DRC2R_ENA */ 7436 #define ARIZONA_DRC2R_ENA_MASK 0x0001 /* DRC2R_ENA */ 7437 #define ARIZONA_DRC2R_ENA_SHIFT 0 /* DRC2R_ENA */ 7438 #define ARIZONA_DRC2R_ENA_WIDTH 1 /* DRC2R_ENA */ 7439 7440 /* 7441 * R3722 (0xE8A) - DRC2 ctrl2 7442 */ 7443 #define ARIZONA_DRC2_ATK_MASK 0x1E00 /* DRC2_ATK - [12:9] */ 7444 #define ARIZONA_DRC2_ATK_SHIFT 9 /* DRC2_ATK - [12:9] */ 7445 #define ARIZONA_DRC2_ATK_WIDTH 4 /* DRC2_ATK - [12:9] */ 7446 #define ARIZONA_DRC2_DCY_MASK 0x01E0 /* DRC2_DCY - [8:5] */ 7447 #define ARIZONA_DRC2_DCY_SHIFT 5 /* DRC2_DCY - [8:5] */ 7448 #define ARIZONA_DRC2_DCY_WIDTH 4 /* DRC2_DCY - [8:5] */ 7449 #define ARIZONA_DRC2_MINGAIN_MASK 0x001C /* DRC2_MINGAIN - [4:2] */ 7450 #define ARIZONA_DRC2_MINGAIN_SHIFT 2 /* DRC2_MINGAIN - [4:2] */ 7451 #define ARIZONA_DRC2_MINGAIN_WIDTH 3 /* DRC2_MINGAIN - [4:2] */ 7452 #define ARIZONA_DRC2_MAXGAIN_MASK 0x0003 /* DRC2_MAXGAIN - [1:0] */ 7453 #define ARIZONA_DRC2_MAXGAIN_SHIFT 0 /* DRC2_MAXGAIN - [1:0] */ 7454 #define ARIZONA_DRC2_MAXGAIN_WIDTH 2 /* DRC2_MAXGAIN - [1:0] */ 7455 7456 /* 7457 * R3723 (0xE8B) - DRC2 ctrl3 7458 */ 7459 #define ARIZONA_DRC2_NG_MINGAIN_MASK 0xF000 /* DRC2_NG_MINGAIN - [15:12] */ 7460 #define ARIZONA_DRC2_NG_MINGAIN_SHIFT 12 /* DRC2_NG_MINGAIN - [15:12] */ 7461 #define ARIZONA_DRC2_NG_MINGAIN_WIDTH 4 /* DRC2_NG_MINGAIN - [15:12] */ 7462 #define ARIZONA_DRC2_NG_EXP_MASK 0x0C00 /* DRC2_NG_EXP - [11:10] */ 7463 #define ARIZONA_DRC2_NG_EXP_SHIFT 10 /* DRC2_NG_EXP - [11:10] */ 7464 #define ARIZONA_DRC2_NG_EXP_WIDTH 2 /* DRC2_NG_EXP - [11:10] */ 7465 #define ARIZONA_DRC2_QR_THR_MASK 0x0300 /* DRC2_QR_THR - [9:8] */ 7466 #define ARIZONA_DRC2_QR_THR_SHIFT 8 /* DRC2_QR_THR - [9:8] */ 7467 #define ARIZONA_DRC2_QR_THR_WIDTH 2 /* DRC2_QR_THR - [9:8] */ 7468 #define ARIZONA_DRC2_QR_DCY_MASK 0x00C0 /* DRC2_QR_DCY - [7:6] */ 7469 #define ARIZONA_DRC2_QR_DCY_SHIFT 6 /* DRC2_QR_DCY - [7:6] */ 7470 #define ARIZONA_DRC2_QR_DCY_WIDTH 2 /* DRC2_QR_DCY - [7:6] */ 7471 #define ARIZONA_DRC2_HI_COMP_MASK 0x0038 /* DRC2_HI_COMP - [5:3] */ 7472 #define ARIZONA_DRC2_HI_COMP_SHIFT 3 /* DRC2_HI_COMP - [5:3] */ 7473 #define ARIZONA_DRC2_HI_COMP_WIDTH 3 /* DRC2_HI_COMP - [5:3] */ 7474 #define ARIZONA_DRC2_LO_COMP_MASK 0x0007 /* DRC2_LO_COMP - [2:0] */ 7475 #define ARIZONA_DRC2_LO_COMP_SHIFT 0 /* DRC2_LO_COMP - [2:0] */ 7476 #define ARIZONA_DRC2_LO_COMP_WIDTH 3 /* DRC2_LO_COMP - [2:0] */ 7477 7478 /* 7479 * R3724 (0xE8C) - DRC2 ctrl4 7480 */ 7481 #define ARIZONA_DRC2_KNEE_IP_MASK 0x07E0 /* DRC2_KNEE_IP - [10:5] */ 7482 #define ARIZONA_DRC2_KNEE_IP_SHIFT 5 /* DRC2_KNEE_IP - [10:5] */ 7483 #define ARIZONA_DRC2_KNEE_IP_WIDTH 6 /* DRC2_KNEE_IP - [10:5] */ 7484 #define ARIZONA_DRC2_KNEE_OP_MASK 0x001F /* DRC2_KNEE_OP - [4:0] */ 7485 #define ARIZONA_DRC2_KNEE_OP_SHIFT 0 /* DRC2_KNEE_OP - [4:0] */ 7486 #define ARIZONA_DRC2_KNEE_OP_WIDTH 5 /* DRC2_KNEE_OP - [4:0] */ 7487 7488 /* 7489 * R3725 (0xE8D) - DRC2 ctrl5 7490 */ 7491 #define ARIZONA_DRC2_KNEE2_IP_MASK 0x03E0 /* DRC2_KNEE2_IP - [9:5] */ 7492 #define ARIZONA_DRC2_KNEE2_IP_SHIFT 5 /* DRC2_KNEE2_IP - [9:5] */ 7493 #define ARIZONA_DRC2_KNEE2_IP_WIDTH 5 /* DRC2_KNEE2_IP - [9:5] */ 7494 #define ARIZONA_DRC2_KNEE2_OP_MASK 0x001F /* DRC2_KNEE2_OP - [4:0] */ 7495 #define ARIZONA_DRC2_KNEE2_OP_SHIFT 0 /* DRC2_KNEE2_OP - [4:0] */ 7496 #define ARIZONA_DRC2_KNEE2_OP_WIDTH 5 /* DRC2_KNEE2_OP - [4:0] */ 7497 7498 /* 7499 * R3776 (0xEC0) - HPLPF1_1 7500 */ 7501 #define ARIZONA_LHPF1_MODE 0x0002 /* LHPF1_MODE */ 7502 #define ARIZONA_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */ 7503 #define ARIZONA_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */ 7504 #define ARIZONA_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */ 7505 #define ARIZONA_LHPF1_ENA 0x0001 /* LHPF1_ENA */ 7506 #define ARIZONA_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */ 7507 #define ARIZONA_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */ 7508 #define ARIZONA_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */ 7509 7510 /* 7511 * R3777 (0xEC1) - HPLPF1_2 7512 */ 7513 #define ARIZONA_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */ 7514 #define ARIZONA_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */ 7515 #define ARIZONA_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */ 7516 7517 /* 7518 * R3780 (0xEC4) - HPLPF2_1 7519 */ 7520 #define ARIZONA_LHPF2_MODE 0x0002 /* LHPF2_MODE */ 7521 #define ARIZONA_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */ 7522 #define ARIZONA_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */ 7523 #define ARIZONA_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */ 7524 #define ARIZONA_LHPF2_ENA 0x0001 /* LHPF2_ENA */ 7525 #define ARIZONA_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */ 7526 #define ARIZONA_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */ 7527 #define ARIZONA_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */ 7528 7529 /* 7530 * R3781 (0xEC5) - HPLPF2_2 7531 */ 7532 #define ARIZONA_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */ 7533 #define ARIZONA_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */ 7534 #define ARIZONA_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */ 7535 7536 /* 7537 * R3784 (0xEC8) - HPLPF3_1 7538 */ 7539 #define ARIZONA_LHPF3_MODE 0x0002 /* LHPF3_MODE */ 7540 #define ARIZONA_LHPF3_MODE_MASK 0x0002 /* LHPF3_MODE */ 7541 #define ARIZONA_LHPF3_MODE_SHIFT 1 /* LHPF3_MODE */ 7542 #define ARIZONA_LHPF3_MODE_WIDTH 1 /* LHPF3_MODE */ 7543 #define ARIZONA_LHPF3_ENA 0x0001 /* LHPF3_ENA */ 7544 #define ARIZONA_LHPF3_ENA_MASK 0x0001 /* LHPF3_ENA */ 7545 #define ARIZONA_LHPF3_ENA_SHIFT 0 /* LHPF3_ENA */ 7546 #define ARIZONA_LHPF3_ENA_WIDTH 1 /* LHPF3_ENA */ 7547 7548 /* 7549 * R3785 (0xEC9) - HPLPF3_2 7550 */ 7551 #define ARIZONA_LHPF3_COEFF_MASK 0xFFFF /* LHPF3_COEFF - [15:0] */ 7552 #define ARIZONA_LHPF3_COEFF_SHIFT 0 /* LHPF3_COEFF - [15:0] */ 7553 #define ARIZONA_LHPF3_COEFF_WIDTH 16 /* LHPF3_COEFF - [15:0] */ 7554 7555 /* 7556 * R3788 (0xECC) - HPLPF4_1 7557 */ 7558 #define ARIZONA_LHPF4_MODE 0x0002 /* LHPF4_MODE */ 7559 #define ARIZONA_LHPF4_MODE_MASK 0x0002 /* LHPF4_MODE */ 7560 #define ARIZONA_LHPF4_MODE_SHIFT 1 /* LHPF4_MODE */ 7561 #define ARIZONA_LHPF4_MODE_WIDTH 1 /* LHPF4_MODE */ 7562 #define ARIZONA_LHPF4_ENA 0x0001 /* LHPF4_ENA */ 7563 #define ARIZONA_LHPF4_ENA_MASK 0x0001 /* LHPF4_ENA */ 7564 #define ARIZONA_LHPF4_ENA_SHIFT 0 /* LHPF4_ENA */ 7565 #define ARIZONA_LHPF4_ENA_WIDTH 1 /* LHPF4_ENA */ 7566 7567 /* 7568 * R3789 (0xECD) - HPLPF4_2 7569 */ 7570 #define ARIZONA_LHPF4_COEFF_MASK 0xFFFF /* LHPF4_COEFF - [15:0] */ 7571 #define ARIZONA_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */ 7572 #define ARIZONA_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */ 7573 7574 /* 7575 * R3808 (0xEE0) - ASRC_ENABLE 7576 */ 7577 #define ARIZONA_ASRC2L_ENA 0x0008 /* ASRC2L_ENA */ 7578 #define ARIZONA_ASRC2L_ENA_MASK 0x0008 /* ASRC2L_ENA */ 7579 #define ARIZONA_ASRC2L_ENA_SHIFT 3 /* ASRC2L_ENA */ 7580 #define ARIZONA_ASRC2L_ENA_WIDTH 1 /* ASRC2L_ENA */ 7581 #define ARIZONA_ASRC2R_ENA 0x0004 /* ASRC2R_ENA */ 7582 #define ARIZONA_ASRC2R_ENA_MASK 0x0004 /* ASRC2R_ENA */ 7583 #define ARIZONA_ASRC2R_ENA_SHIFT 2 /* ASRC2R_ENA */ 7584 #define ARIZONA_ASRC2R_ENA_WIDTH 1 /* ASRC2R_ENA */ 7585 #define ARIZONA_ASRC1L_ENA 0x0002 /* ASRC1L_ENA */ 7586 #define ARIZONA_ASRC1L_ENA_MASK 0x0002 /* ASRC1L_ENA */ 7587 #define ARIZONA_ASRC1L_ENA_SHIFT 1 /* ASRC1L_ENA */ 7588 #define ARIZONA_ASRC1L_ENA_WIDTH 1 /* ASRC1L_ENA */ 7589 #define ARIZONA_ASRC1R_ENA 0x0001 /* ASRC1R_ENA */ 7590 #define ARIZONA_ASRC1R_ENA_MASK 0x0001 /* ASRC1R_ENA */ 7591 #define ARIZONA_ASRC1R_ENA_SHIFT 0 /* ASRC1R_ENA */ 7592 #define ARIZONA_ASRC1R_ENA_WIDTH 1 /* ASRC1R_ENA */ 7593 7594 /* 7595 * R3810 (0xEE2) - ASRC_RATE1 7596 */ 7597 #define ARIZONA_ASRC_RATE1_MASK 0x7800 /* ASRC_RATE1 - [14:11] */ 7598 #define ARIZONA_ASRC_RATE1_SHIFT 11 /* ASRC_RATE1 - [14:11] */ 7599 #define ARIZONA_ASRC_RATE1_WIDTH 4 /* ASRC_RATE1 - [14:11] */ 7600 7601 /* 7602 * R3811 (0xEE3) - ASRC_RATE2 7603 */ 7604 #define ARIZONA_ASRC_RATE2_MASK 0x7800 /* ASRC_RATE2 - [14:11] */ 7605 #define ARIZONA_ASRC_RATE2_SHIFT 11 /* ASRC_RATE2 - [14:11] */ 7606 #define ARIZONA_ASRC_RATE2_WIDTH 4 /* ASRC_RATE2 - [14:11] */ 7607 7608 /* 7609 * R3824 (0xEF0) - ISRC 1 CTRL 1 7610 */ 7611 #define ARIZONA_ISRC1_FSH_MASK 0x7800 /* ISRC1_FSH - [14:11] */ 7612 #define ARIZONA_ISRC1_FSH_SHIFT 11 /* ISRC1_FSH - [14:11] */ 7613 #define ARIZONA_ISRC1_FSH_WIDTH 4 /* ISRC1_FSH - [14:11] */ 7614 #define ARIZONA_ISRC1_CLK_SEL_MASK 0x0700 /* ISRC1_CLK_SEL - [10:8] */ 7615 #define ARIZONA_ISRC1_CLK_SEL_SHIFT 8 /* ISRC1_CLK_SEL - [10:8] */ 7616 #define ARIZONA_ISRC1_CLK_SEL_WIDTH 3 /* ISRC1_CLK_SEL - [10:8] */ 7617 7618 /* 7619 * R3825 (0xEF1) - ISRC 1 CTRL 2 7620 */ 7621 #define ARIZONA_ISRC1_FSL_MASK 0x7800 /* ISRC1_FSL - [14:11] */ 7622 #define ARIZONA_ISRC1_FSL_SHIFT 11 /* ISRC1_FSL - [14:11] */ 7623 #define ARIZONA_ISRC1_FSL_WIDTH 4 /* ISRC1_FSL - [14:11] */ 7624 7625 /* 7626 * R3826 (0xEF2) - ISRC 1 CTRL 3 7627 */ 7628 #define ARIZONA_ISRC1_INT0_ENA 0x8000 /* ISRC1_INT0_ENA */ 7629 #define ARIZONA_ISRC1_INT0_ENA_MASK 0x8000 /* ISRC1_INT0_ENA */ 7630 #define ARIZONA_ISRC1_INT0_ENA_SHIFT 15 /* ISRC1_INT0_ENA */ 7631 #define ARIZONA_ISRC1_INT0_ENA_WIDTH 1 /* ISRC1_INT0_ENA */ 7632 #define ARIZONA_ISRC1_INT1_ENA 0x4000 /* ISRC1_INT1_ENA */ 7633 #define ARIZONA_ISRC1_INT1_ENA_MASK 0x4000 /* ISRC1_INT1_ENA */ 7634 #define ARIZONA_ISRC1_INT1_ENA_SHIFT 14 /* ISRC1_INT1_ENA */ 7635 #define ARIZONA_ISRC1_INT1_ENA_WIDTH 1 /* ISRC1_INT1_ENA */ 7636 #define ARIZONA_ISRC1_INT2_ENA 0x2000 /* ISRC1_INT2_ENA */ 7637 #define ARIZONA_ISRC1_INT2_ENA_MASK 0x2000 /* ISRC1_INT2_ENA */ 7638 #define ARIZONA_ISRC1_INT2_ENA_SHIFT 13 /* ISRC1_INT2_ENA */ 7639 #define ARIZONA_ISRC1_INT2_ENA_WIDTH 1 /* ISRC1_INT2_ENA */ 7640 #define ARIZONA_ISRC1_INT3_ENA 0x1000 /* ISRC1_INT3_ENA */ 7641 #define ARIZONA_ISRC1_INT3_ENA_MASK 0x1000 /* ISRC1_INT3_ENA */ 7642 #define ARIZONA_ISRC1_INT3_ENA_SHIFT 12 /* ISRC1_INT3_ENA */ 7643 #define ARIZONA_ISRC1_INT3_ENA_WIDTH 1 /* ISRC1_INT3_ENA */ 7644 #define ARIZONA_ISRC1_DEC0_ENA 0x0200 /* ISRC1_DEC0_ENA */ 7645 #define ARIZONA_ISRC1_DEC0_ENA_MASK 0x0200 /* ISRC1_DEC0_ENA */ 7646 #define ARIZONA_ISRC1_DEC0_ENA_SHIFT 9 /* ISRC1_DEC0_ENA */ 7647 #define ARIZONA_ISRC1_DEC0_ENA_WIDTH 1 /* ISRC1_DEC0_ENA */ 7648 #define ARIZONA_ISRC1_DEC1_ENA 0x0100 /* ISRC1_DEC1_ENA */ 7649 #define ARIZONA_ISRC1_DEC1_ENA_MASK 0x0100 /* ISRC1_DEC1_ENA */ 7650 #define ARIZONA_ISRC1_DEC1_ENA_SHIFT 8 /* ISRC1_DEC1_ENA */ 7651 #define ARIZONA_ISRC1_DEC1_ENA_WIDTH 1 /* ISRC1_DEC1_ENA */ 7652 #define ARIZONA_ISRC1_DEC2_ENA 0x0080 /* ISRC1_DEC2_ENA */ 7653 #define ARIZONA_ISRC1_DEC2_ENA_MASK 0x0080 /* ISRC1_DEC2_ENA */ 7654 #define ARIZONA_ISRC1_DEC2_ENA_SHIFT 7 /* ISRC1_DEC2_ENA */ 7655 #define ARIZONA_ISRC1_DEC2_ENA_WIDTH 1 /* ISRC1_DEC2_ENA */ 7656 #define ARIZONA_ISRC1_DEC3_ENA 0x0040 /* ISRC1_DEC3_ENA */ 7657 #define ARIZONA_ISRC1_DEC3_ENA_MASK 0x0040 /* ISRC1_DEC3_ENA */ 7658 #define ARIZONA_ISRC1_DEC3_ENA_SHIFT 6 /* ISRC1_DEC3_ENA */ 7659 #define ARIZONA_ISRC1_DEC3_ENA_WIDTH 1 /* ISRC1_DEC3_ENA */ 7660 #define ARIZONA_ISRC1_NOTCH_ENA 0x0001 /* ISRC1_NOTCH_ENA */ 7661 #define ARIZONA_ISRC1_NOTCH_ENA_MASK 0x0001 /* ISRC1_NOTCH_ENA */ 7662 #define ARIZONA_ISRC1_NOTCH_ENA_SHIFT 0 /* ISRC1_NOTCH_ENA */ 7663 #define ARIZONA_ISRC1_NOTCH_ENA_WIDTH 1 /* ISRC1_NOTCH_ENA */ 7664 7665 /* 7666 * R3827 (0xEF3) - ISRC 2 CTRL 1 7667 */ 7668 #define ARIZONA_ISRC2_FSH_MASK 0x7800 /* ISRC2_FSH - [14:11] */ 7669 #define ARIZONA_ISRC2_FSH_SHIFT 11 /* ISRC2_FSH - [14:11] */ 7670 #define ARIZONA_ISRC2_FSH_WIDTH 4 /* ISRC2_FSH - [14:11] */ 7671 #define ARIZONA_ISRC2_CLK_SEL_MASK 0x0700 /* ISRC2_CLK_SEL - [10:8] */ 7672 #define ARIZONA_ISRC2_CLK_SEL_SHIFT 8 /* ISRC2_CLK_SEL - [10:8] */ 7673 #define ARIZONA_ISRC2_CLK_SEL_WIDTH 3 /* ISRC2_CLK_SEL - [10:8] */ 7674 7675 /* 7676 * R3828 (0xEF4) - ISRC 2 CTRL 2 7677 */ 7678 #define ARIZONA_ISRC2_FSL_MASK 0x7800 /* ISRC2_FSL - [14:11] */ 7679 #define ARIZONA_ISRC2_FSL_SHIFT 11 /* ISRC2_FSL - [14:11] */ 7680 #define ARIZONA_ISRC2_FSL_WIDTH 4 /* ISRC2_FSL - [14:11] */ 7681 7682 /* 7683 * R3829 (0xEF5) - ISRC 2 CTRL 3 7684 */ 7685 #define ARIZONA_ISRC2_INT0_ENA 0x8000 /* ISRC2_INT0_ENA */ 7686 #define ARIZONA_ISRC2_INT0_ENA_MASK 0x8000 /* ISRC2_INT0_ENA */ 7687 #define ARIZONA_ISRC2_INT0_ENA_SHIFT 15 /* ISRC2_INT0_ENA */ 7688 #define ARIZONA_ISRC2_INT0_ENA_WIDTH 1 /* ISRC2_INT0_ENA */ 7689 #define ARIZONA_ISRC2_INT1_ENA 0x4000 /* ISRC2_INT1_ENA */ 7690 #define ARIZONA_ISRC2_INT1_ENA_MASK 0x4000 /* ISRC2_INT1_ENA */ 7691 #define ARIZONA_ISRC2_INT1_ENA_SHIFT 14 /* ISRC2_INT1_ENA */ 7692 #define ARIZONA_ISRC2_INT1_ENA_WIDTH 1 /* ISRC2_INT1_ENA */ 7693 #define ARIZONA_ISRC2_INT2_ENA 0x2000 /* ISRC2_INT2_ENA */ 7694 #define ARIZONA_ISRC2_INT2_ENA_MASK 0x2000 /* ISRC2_INT2_ENA */ 7695 #define ARIZONA_ISRC2_INT2_ENA_SHIFT 13 /* ISRC2_INT2_ENA */ 7696 #define ARIZONA_ISRC2_INT2_ENA_WIDTH 1 /* ISRC2_INT2_ENA */ 7697 #define ARIZONA_ISRC2_INT3_ENA 0x1000 /* ISRC2_INT3_ENA */ 7698 #define ARIZONA_ISRC2_INT3_ENA_MASK 0x1000 /* ISRC2_INT3_ENA */ 7699 #define ARIZONA_ISRC2_INT3_ENA_SHIFT 12 /* ISRC2_INT3_ENA */ 7700 #define ARIZONA_ISRC2_INT3_ENA_WIDTH 1 /* ISRC2_INT3_ENA */ 7701 #define ARIZONA_ISRC2_DEC0_ENA 0x0200 /* ISRC2_DEC0_ENA */ 7702 #define ARIZONA_ISRC2_DEC0_ENA_MASK 0x0200 /* ISRC2_DEC0_ENA */ 7703 #define ARIZONA_ISRC2_DEC0_ENA_SHIFT 9 /* ISRC2_DEC0_ENA */ 7704 #define ARIZONA_ISRC2_DEC0_ENA_WIDTH 1 /* ISRC2_DEC0_ENA */ 7705 #define ARIZONA_ISRC2_DEC1_ENA 0x0100 /* ISRC2_DEC1_ENA */ 7706 #define ARIZONA_ISRC2_DEC1_ENA_MASK 0x0100 /* ISRC2_DEC1_ENA */ 7707 #define ARIZONA_ISRC2_DEC1_ENA_SHIFT 8 /* ISRC2_DEC1_ENA */ 7708 #define ARIZONA_ISRC2_DEC1_ENA_WIDTH 1 /* ISRC2_DEC1_ENA */ 7709 #define ARIZONA_ISRC2_DEC2_ENA 0x0080 /* ISRC2_DEC2_ENA */ 7710 #define ARIZONA_ISRC2_DEC2_ENA_MASK 0x0080 /* ISRC2_DEC2_ENA */ 7711 #define ARIZONA_ISRC2_DEC2_ENA_SHIFT 7 /* ISRC2_DEC2_ENA */ 7712 #define ARIZONA_ISRC2_DEC2_ENA_WIDTH 1 /* ISRC2_DEC2_ENA */ 7713 #define ARIZONA_ISRC2_DEC3_ENA 0x0040 /* ISRC2_DEC3_ENA */ 7714 #define ARIZONA_ISRC2_DEC3_ENA_MASK 0x0040 /* ISRC2_DEC3_ENA */ 7715 #define ARIZONA_ISRC2_DEC3_ENA_SHIFT 6 /* ISRC2_DEC3_ENA */ 7716 #define ARIZONA_ISRC2_DEC3_ENA_WIDTH 1 /* ISRC2_DEC3_ENA */ 7717 #define ARIZONA_ISRC2_NOTCH_ENA 0x0001 /* ISRC2_NOTCH_ENA */ 7718 #define ARIZONA_ISRC2_NOTCH_ENA_MASK 0x0001 /* ISRC2_NOTCH_ENA */ 7719 #define ARIZONA_ISRC2_NOTCH_ENA_SHIFT 0 /* ISRC2_NOTCH_ENA */ 7720 #define ARIZONA_ISRC2_NOTCH_ENA_WIDTH 1 /* ISRC2_NOTCH_ENA */ 7721 7722 /* 7723 * R3830 (0xEF6) - ISRC 3 CTRL 1 7724 */ 7725 #define ARIZONA_ISRC3_FSH_MASK 0x7800 /* ISRC3_FSH - [14:11] */ 7726 #define ARIZONA_ISRC3_FSH_SHIFT 11 /* ISRC3_FSH - [14:11] */ 7727 #define ARIZONA_ISRC3_FSH_WIDTH 4 /* ISRC3_FSH - [14:11] */ 7728 #define ARIZONA_ISRC3_CLK_SEL_MASK 0x0700 /* ISRC3_CLK_SEL - [10:8] */ 7729 #define ARIZONA_ISRC3_CLK_SEL_SHIFT 8 /* ISRC3_CLK_SEL - [10:8] */ 7730 #define ARIZONA_ISRC3_CLK_SEL_WIDTH 3 /* ISRC3_CLK_SEL - [10:8] */ 7731 7732 /* 7733 * R3831 (0xEF7) - ISRC 3 CTRL 2 7734 */ 7735 #define ARIZONA_ISRC3_FSL_MASK 0x7800 /* ISRC3_FSL - [14:11] */ 7736 #define ARIZONA_ISRC3_FSL_SHIFT 11 /* ISRC3_FSL - [14:11] */ 7737 #define ARIZONA_ISRC3_FSL_WIDTH 4 /* ISRC3_FSL - [14:11] */ 7738 7739 /* 7740 * R3832 (0xEF8) - ISRC 3 CTRL 3 7741 */ 7742 #define ARIZONA_ISRC3_INT0_ENA 0x8000 /* ISRC3_INT0_ENA */ 7743 #define ARIZONA_ISRC3_INT0_ENA_MASK 0x8000 /* ISRC3_INT0_ENA */ 7744 #define ARIZONA_ISRC3_INT0_ENA_SHIFT 15 /* ISRC3_INT0_ENA */ 7745 #define ARIZONA_ISRC3_INT0_ENA_WIDTH 1 /* ISRC3_INT0_ENA */ 7746 #define ARIZONA_ISRC3_INT1_ENA 0x4000 /* ISRC3_INT1_ENA */ 7747 #define ARIZONA_ISRC3_INT1_ENA_MASK 0x4000 /* ISRC3_INT1_ENA */ 7748 #define ARIZONA_ISRC3_INT1_ENA_SHIFT 14 /* ISRC3_INT1_ENA */ 7749 #define ARIZONA_ISRC3_INT1_ENA_WIDTH 1 /* ISRC3_INT1_ENA */ 7750 #define ARIZONA_ISRC3_INT2_ENA 0x2000 /* ISRC3_INT2_ENA */ 7751 #define ARIZONA_ISRC3_INT2_ENA_MASK 0x2000 /* ISRC3_INT2_ENA */ 7752 #define ARIZONA_ISRC3_INT2_ENA_SHIFT 13 /* ISRC3_INT2_ENA */ 7753 #define ARIZONA_ISRC3_INT2_ENA_WIDTH 1 /* ISRC3_INT2_ENA */ 7754 #define ARIZONA_ISRC3_INT3_ENA 0x1000 /* ISRC3_INT3_ENA */ 7755 #define ARIZONA_ISRC3_INT3_ENA_MASK 0x1000 /* ISRC3_INT3_ENA */ 7756 #define ARIZONA_ISRC3_INT3_ENA_SHIFT 12 /* ISRC3_INT3_ENA */ 7757 #define ARIZONA_ISRC3_INT3_ENA_WIDTH 1 /* ISRC3_INT3_ENA */ 7758 #define ARIZONA_ISRC3_DEC0_ENA 0x0200 /* ISRC3_DEC0_ENA */ 7759 #define ARIZONA_ISRC3_DEC0_ENA_MASK 0x0200 /* ISRC3_DEC0_ENA */ 7760 #define ARIZONA_ISRC3_DEC0_ENA_SHIFT 9 /* ISRC3_DEC0_ENA */ 7761 #define ARIZONA_ISRC3_DEC0_ENA_WIDTH 1 /* ISRC3_DEC0_ENA */ 7762 #define ARIZONA_ISRC3_DEC1_ENA 0x0100 /* ISRC3_DEC1_ENA */ 7763 #define ARIZONA_ISRC3_DEC1_ENA_MASK 0x0100 /* ISRC3_DEC1_ENA */ 7764 #define ARIZONA_ISRC3_DEC1_ENA_SHIFT 8 /* ISRC3_DEC1_ENA */ 7765 #define ARIZONA_ISRC3_DEC1_ENA_WIDTH 1 /* ISRC3_DEC1_ENA */ 7766 #define ARIZONA_ISRC3_DEC2_ENA 0x0080 /* ISRC3_DEC2_ENA */ 7767 #define ARIZONA_ISRC3_DEC2_ENA_MASK 0x0080 /* ISRC3_DEC2_ENA */ 7768 #define ARIZONA_ISRC3_DEC2_ENA_SHIFT 7 /* ISRC3_DEC2_ENA */ 7769 #define ARIZONA_ISRC3_DEC2_ENA_WIDTH 1 /* ISRC3_DEC2_ENA */ 7770 #define ARIZONA_ISRC3_DEC3_ENA 0x0040 /* ISRC3_DEC3_ENA */ 7771 #define ARIZONA_ISRC3_DEC3_ENA_MASK 0x0040 /* ISRC3_DEC3_ENA */ 7772 #define ARIZONA_ISRC3_DEC3_ENA_SHIFT 6 /* ISRC3_DEC3_ENA */ 7773 #define ARIZONA_ISRC3_DEC3_ENA_WIDTH 1 /* ISRC3_DEC3_ENA */ 7774 #define ARIZONA_ISRC3_NOTCH_ENA 0x0001 /* ISRC3_NOTCH_ENA */ 7775 #define ARIZONA_ISRC3_NOTCH_ENA_MASK 0x0001 /* ISRC3_NOTCH_ENA */ 7776 #define ARIZONA_ISRC3_NOTCH_ENA_SHIFT 0 /* ISRC3_NOTCH_ENA */ 7777 #define ARIZONA_ISRC3_NOTCH_ENA_WIDTH 1 /* ISRC3_NOTCH_ENA */ 7778 7779 /* 7780 * R4352 (0x1100) - DSP1 Control 1 7781 */ 7782 #define ARIZONA_DSP1_RATE_MASK 0x7800 /* DSP1_RATE - [14:11] */ 7783 #define ARIZONA_DSP1_RATE_SHIFT 11 /* DSP1_RATE - [14:11] */ 7784 #define ARIZONA_DSP1_RATE_WIDTH 4 /* DSP1_RATE - [14:11] */ 7785 #define ARIZONA_DSP1_MEM_ENA 0x0010 /* DSP1_MEM_ENA */ 7786 #define ARIZONA_DSP1_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */ 7787 #define ARIZONA_DSP1_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */ 7788 #define ARIZONA_DSP1_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */ 7789 #define ARIZONA_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ 7790 #define ARIZONA_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ 7791 #define ARIZONA_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ 7792 #define ARIZONA_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ 7793 #define ARIZONA_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ 7794 #define ARIZONA_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ 7795 #define ARIZONA_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ 7796 #define ARIZONA_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ 7797 #define ARIZONA_DSP1_START 0x0001 /* DSP1_START */ 7798 #define ARIZONA_DSP1_START_MASK 0x0001 /* DSP1_START */ 7799 #define ARIZONA_DSP1_START_SHIFT 0 /* DSP1_START */ 7800 #define ARIZONA_DSP1_START_WIDTH 1 /* DSP1_START */ 7801 7802 /* 7803 * R4353 (0x1101) - DSP1 Clocking 1 7804 */ 7805 #define ARIZONA_DSP1_CLK_SEL_MASK 0x0007 /* DSP1_CLK_SEL - [2:0] */ 7806 #define ARIZONA_DSP1_CLK_SEL_SHIFT 0 /* DSP1_CLK_SEL - [2:0] */ 7807 #define ARIZONA_DSP1_CLK_SEL_WIDTH 3 /* DSP1_CLK_SEL - [2:0] */ 7808 7809 /* 7810 * R4356 (0x1104) - DSP1 Status 1 7811 */ 7812 #define ARIZONA_DSP1_RAM_RDY 0x0001 /* DSP1_RAM_RDY */ 7813 #define ARIZONA_DSP1_RAM_RDY_MASK 0x0001 /* DSP1_RAM_RDY */ 7814 #define ARIZONA_DSP1_RAM_RDY_SHIFT 0 /* DSP1_RAM_RDY */ 7815 #define ARIZONA_DSP1_RAM_RDY_WIDTH 1 /* DSP1_RAM_RDY */ 7816 7817 /* 7818 * R4357 (0x1105) - DSP1 Status 2 7819 */ 7820 #define ARIZONA_DSP1_PING_FULL 0x8000 /* DSP1_PING_FULL */ 7821 #define ARIZONA_DSP1_PING_FULL_MASK 0x8000 /* DSP1_PING_FULL */ 7822 #define ARIZONA_DSP1_PING_FULL_SHIFT 15 /* DSP1_PING_FULL */ 7823 #define ARIZONA_DSP1_PING_FULL_WIDTH 1 /* DSP1_PING_FULL */ 7824 #define ARIZONA_DSP1_PONG_FULL 0x4000 /* DSP1_PONG_FULL */ 7825 #define ARIZONA_DSP1_PONG_FULL_MASK 0x4000 /* DSP1_PONG_FULL */ 7826 #define ARIZONA_DSP1_PONG_FULL_SHIFT 14 /* DSP1_PONG_FULL */ 7827 #define ARIZONA_DSP1_PONG_FULL_WIDTH 1 /* DSP1_PONG_FULL */ 7828 #define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ 7829 #define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ 7830 #define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ 7831 7832 #endif 7833