427 void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,  in vgic_reg_access()  argument
431 	u32 mask = (1UL << (mmio->len * 8)) - 1;  in vgic_reg_access()
446 	if (mmio->is_write) {  in vgic_reg_access()
447 		u32 data = mmio_data_read(mmio, mask) << word_offset;  in vgic_reg_access()
472 			mmio_data_write(mmio, mask, regval >> word_offset);  in vgic_reg_access()
477 bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,  in handle_mmio_raz_wi()  argument
480 	vgic_reg_access(mmio, NULL, offset,  in handle_mmio_raz_wi()
485 bool vgic_handle_enable_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio,  in vgic_handle_enable_reg()  argument
493 	vgic_reg_access(mmio, reg, offset, mode);  in vgic_handle_enable_reg()
494 	if (mmio->is_write) {  in vgic_handle_enable_reg()
508 				 struct kvm_exit_mmio *mmio,  in vgic_handle_set_pending_reg()  argument
522 	vgic_reg_access(mmio, reg, offset, mode);  in vgic_handle_set_pending_reg()
524 	if (mmio->is_write) {  in vgic_handle_set_pending_reg()
528 		vgic_reg_access(mmio, reg, offset, mode);  in vgic_handle_set_pending_reg()
545 				   struct kvm_exit_mmio *mmio,  in vgic_handle_clear_pending_reg()  argument
555 	vgic_reg_access(mmio, reg, offset, mode);  in vgic_handle_clear_pending_reg()
556 	if (mmio->is_write) {  in vgic_handle_clear_pending_reg()
572 		vgic_reg_access(mmio, reg, offset, mode);  in vgic_handle_clear_pending_reg()
581 				struct kvm_exit_mmio *mmio,  in vgic_handle_set_active_reg()  argument
588 	vgic_reg_access(mmio, reg, offset,  in vgic_handle_set_active_reg()
591 	if (mmio->is_write) {  in vgic_handle_set_active_reg()
600 				  struct kvm_exit_mmio *mmio,  in vgic_handle_clear_active_reg()  argument
607 	vgic_reg_access(mmio, reg, offset,  in vgic_handle_clear_active_reg()
610 	if (mmio->is_write) {  in vgic_handle_clear_active_reg()
653 bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio,  in vgic_handle_cfg_reg()  argument
664 	vgic_reg_access(mmio, &val, offset,  in vgic_handle_cfg_reg()
666 	if (mmio->is_write) {  in vgic_handle_cfg_reg()
775 			       struct kvm_exit_mmio *mmio,  in call_range_handler()  argument
782 	if (likely(mmio->len <= 4))  in call_range_handler()
783 		return range->handle_mmio(vcpu, mmio, offset);  in call_range_handler()
791 	mmio32.is_write = mmio->is_write;  in call_range_handler()
792 	mmio32.private = mmio->private;  in call_range_handler()
794 	mmio32.phys_addr = mmio->phys_addr + 4;  in call_range_handler()
795 	mmio32.data = &((u32 *)mmio->data)[1];  in call_range_handler()
798 	mmio32.phys_addr = mmio->phys_addr;  in call_range_handler()
799 	mmio32.data = &((u32 *)mmio->data)[0];  in call_range_handler()
826 	struct kvm_exit_mmio mmio;  in vgic_handle_mmio_access()  local
837 	mmio.phys_addr = addr;  in vgic_handle_mmio_access()
838 	mmio.len = len;  in vgic_handle_mmio_access()
839 	mmio.is_write = is_write;  in vgic_handle_mmio_access()
840 	mmio.data = val;  in vgic_handle_mmio_access()
841 	mmio.private = iodev->redist_vcpu;  in vgic_handle_mmio_access()
846 		updated_state = call_range_handler(vcpu, &mmio, offset, range);  in vgic_handle_mmio_access()
853 	run->mmio.is_write	= is_write;  in vgic_handle_mmio_access()
854 	run->mmio.len		= len;  in vgic_handle_mmio_access()
855 	run->mmio.phys_addr	= addr;  in vgic_handle_mmio_access()
856 	memcpy(run->mmio.data, val, len);  in vgic_handle_mmio_access()