53 			       struct kvm_exit_mmio *mmio, phys_addr_t offset)  in handle_mmio_rao_wi()  argument
57 	vgic_reg_access(mmio, &reg, offset,  in handle_mmio_rao_wi()
64 			     struct kvm_exit_mmio *mmio, phys_addr_t offset)  in handle_mmio_ctlr()  argument
76 	vgic_reg_access(mmio, &reg, offset,  in handle_mmio_ctlr()
94 			      struct kvm_exit_mmio *mmio, phys_addr_t offset)  in handle_mmio_typer()  argument
102 	vgic_reg_access(mmio, &reg, offset,  in handle_mmio_typer()
109 			     struct kvm_exit_mmio *mmio, phys_addr_t offset)  in handle_mmio_iidr()  argument
114 	vgic_reg_access(mmio, &reg, offset,  in handle_mmio_iidr()
122 					    phys_addr_t offset)  in handle_mmio_set_enable_reg_dist()  argument
124 	if (likely(offset >= VGIC_NR_PRIVATE_IRQS / 8))  in handle_mmio_set_enable_reg_dist()
125 		return vgic_handle_enable_reg(vcpu->kvm, mmio, offset,  in handle_mmio_set_enable_reg_dist()
129 	vgic_reg_access(mmio, NULL, offset,  in handle_mmio_set_enable_reg_dist()
136 					      phys_addr_t offset)  in handle_mmio_clear_enable_reg_dist()  argument
138 	if (likely(offset >= VGIC_NR_PRIVATE_IRQS / 8))  in handle_mmio_clear_enable_reg_dist()
139 		return vgic_handle_enable_reg(vcpu->kvm, mmio, offset,  in handle_mmio_clear_enable_reg_dist()
143 	vgic_reg_access(mmio, NULL, offset,  in handle_mmio_clear_enable_reg_dist()
150 					     phys_addr_t offset)  in handle_mmio_set_pending_reg_dist()  argument
152 	if (likely(offset >= VGIC_NR_PRIVATE_IRQS / 8))  in handle_mmio_set_pending_reg_dist()
153 		return vgic_handle_set_pending_reg(vcpu->kvm, mmio, offset,  in handle_mmio_set_pending_reg_dist()
156 	vgic_reg_access(mmio, NULL, offset,  in handle_mmio_set_pending_reg_dist()
163 					       phys_addr_t offset)  in handle_mmio_clear_pending_reg_dist()  argument
165 	if (likely(offset >= VGIC_NR_PRIVATE_IRQS / 8))  in handle_mmio_clear_pending_reg_dist()
166 		return vgic_handle_clear_pending_reg(vcpu->kvm, mmio, offset,  in handle_mmio_clear_pending_reg_dist()
169 	vgic_reg_access(mmio, NULL, offset,  in handle_mmio_clear_pending_reg_dist()
176 					    phys_addr_t offset)  in handle_mmio_set_active_reg_dist()  argument
178 	if (likely(offset >= VGIC_NR_PRIVATE_IRQS / 8))  in handle_mmio_set_active_reg_dist()
179 		return vgic_handle_set_active_reg(vcpu->kvm, mmio, offset,  in handle_mmio_set_active_reg_dist()
182 	vgic_reg_access(mmio, NULL, offset,  in handle_mmio_set_active_reg_dist()
189 					      phys_addr_t offset)  in handle_mmio_clear_active_reg_dist()  argument
191 	if (likely(offset >= VGIC_NR_PRIVATE_IRQS / 8))  in handle_mmio_clear_active_reg_dist()
192 		return vgic_handle_clear_active_reg(vcpu->kvm, mmio, offset,  in handle_mmio_clear_active_reg_dist()
195 	vgic_reg_access(mmio, NULL, offset,  in handle_mmio_clear_active_reg_dist()
202 					  phys_addr_t offset)  in handle_mmio_priority_reg_dist()  argument
206 	if (unlikely(offset < VGIC_NR_PRIVATE_IRQS)) {  in handle_mmio_priority_reg_dist()
207 		vgic_reg_access(mmio, NULL, offset,  in handle_mmio_priority_reg_dist()
213 				   vcpu->vcpu_id, offset);  in handle_mmio_priority_reg_dist()
214 	vgic_reg_access(mmio, reg, offset,  in handle_mmio_priority_reg_dist()
221 				     phys_addr_t offset)  in handle_mmio_cfg_reg_dist()  argument
225 	if (unlikely(offset < VGIC_NR_PRIVATE_IRQS / 4)) {  in handle_mmio_cfg_reg_dist()
226 		vgic_reg_access(mmio, NULL, offset,  in handle_mmio_cfg_reg_dist()
232 				  vcpu->vcpu_id, offset >> 1);  in handle_mmio_cfg_reg_dist()
234 	return vgic_handle_cfg_reg(reg, mmio, offset);  in handle_mmio_cfg_reg_dist()
276 				  phys_addr_t offset)  in handle_mmio_route_reg()  argument
289 	if ((offset & 4)) {  in handle_mmio_route_reg()
290 		vgic_reg_access(mmio, NULL, offset,  in handle_mmio_route_reg()
296 	spi = offset / 8;  in handle_mmio_route_reg()
302 	vgic_reg_access(mmio, &reg, offset,  in handle_mmio_route_reg()
351 			       phys_addr_t offset)  in handle_mmio_idregs()  argument
355 	switch (offset + GICD_IDREGS) {  in handle_mmio_idregs()
361 	vgic_reg_access(mmio, &reg, offset,  in handle_mmio_idregs()
531 				    phys_addr_t offset)  in handle_mmio_ctlr_redist()  argument
534 	vgic_reg_access(mmio, NULL, offset,  in handle_mmio_ctlr_redist()
541 				     phys_addr_t offset)  in handle_mmio_typer_redist()  argument
549 	if ((offset & ~3) == 4) {  in handle_mmio_typer_redist()
553 		vgic_reg_access(mmio, &reg, offset,  in handle_mmio_typer_redist()
561 	vgic_reg_access(mmio, &reg, offset,  in handle_mmio_typer_redist()
568 					      phys_addr_t offset)  in handle_mmio_set_enable_reg_redist()  argument
572 	return vgic_handle_enable_reg(vcpu->kvm, mmio, offset,  in handle_mmio_set_enable_reg_redist()
579 						phys_addr_t offset)  in handle_mmio_clear_enable_reg_redist()  argument
583 	return vgic_handle_enable_reg(vcpu->kvm, mmio, offset,  in handle_mmio_clear_enable_reg_redist()
590 					      phys_addr_t offset)  in handle_mmio_set_active_reg_redist()  argument
594 	return vgic_handle_set_active_reg(vcpu->kvm, mmio, offset,  in handle_mmio_set_active_reg_redist()
600 						phys_addr_t offset)  in handle_mmio_clear_active_reg_redist()  argument
604 	return vgic_handle_clear_active_reg(vcpu->kvm, mmio, offset,  in handle_mmio_clear_active_reg_redist()
610 					       phys_addr_t offset)  in handle_mmio_set_pending_reg_redist()  argument
614 	return vgic_handle_set_pending_reg(vcpu->kvm, mmio, offset,  in handle_mmio_set_pending_reg_redist()
620 						 phys_addr_t offset)  in handle_mmio_clear_pending_reg_redist()  argument
624 	return vgic_handle_clear_pending_reg(vcpu->kvm, mmio, offset,  in handle_mmio_clear_pending_reg_redist()
630 					    phys_addr_t offset)  in handle_mmio_priority_reg_redist()  argument
636 				   redist_vcpu->vcpu_id, offset);  in handle_mmio_priority_reg_redist()
637 	vgic_reg_access(mmio, reg, offset,  in handle_mmio_priority_reg_redist()
644 				       phys_addr_t offset)  in handle_mmio_cfg_reg_redist()  argument
649 				       redist_vcpu->vcpu_id, offset >> 1);  in handle_mmio_cfg_reg_redist()
651 	return vgic_handle_cfg_reg(reg, mmio, offset);  in handle_mmio_cfg_reg_redist()