Lines Matching refs:offset
44 struct kvm_exit_mmio *mmio, phys_addr_t offset) in handle_mmio_misc() argument
47 u32 word_offset = offset & 3; in handle_mmio_misc()
49 switch (offset & ~3) { in handle_mmio_misc()
80 phys_addr_t offset) in handle_mmio_set_enable_reg() argument
82 return vgic_handle_enable_reg(vcpu->kvm, mmio, offset, in handle_mmio_set_enable_reg()
88 phys_addr_t offset) in handle_mmio_clear_enable_reg() argument
90 return vgic_handle_enable_reg(vcpu->kvm, mmio, offset, in handle_mmio_clear_enable_reg()
96 phys_addr_t offset) in handle_mmio_set_pending_reg() argument
98 return vgic_handle_set_pending_reg(vcpu->kvm, mmio, offset, in handle_mmio_set_pending_reg()
104 phys_addr_t offset) in handle_mmio_clear_pending_reg() argument
106 return vgic_handle_clear_pending_reg(vcpu->kvm, mmio, offset, in handle_mmio_clear_pending_reg()
112 phys_addr_t offset) in handle_mmio_set_active_reg() argument
114 return vgic_handle_set_active_reg(vcpu->kvm, mmio, offset, in handle_mmio_set_active_reg()
120 phys_addr_t offset) in handle_mmio_clear_active_reg() argument
122 return vgic_handle_clear_active_reg(vcpu->kvm, mmio, offset, in handle_mmio_clear_active_reg()
128 phys_addr_t offset) in handle_mmio_priority_reg() argument
131 vcpu->vcpu_id, offset); in handle_mmio_priority_reg()
132 vgic_reg_access(mmio, reg, offset, in handle_mmio_priority_reg()
187 phys_addr_t offset) in handle_mmio_target_reg() argument
192 if (offset < 32) { in handle_mmio_target_reg()
199 vgic_reg_access(mmio, &roreg, offset, in handle_mmio_target_reg()
204 reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U); in handle_mmio_target_reg()
205 vgic_reg_access(mmio, ®, offset, in handle_mmio_target_reg()
208 vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U); in handle_mmio_target_reg()
217 struct kvm_exit_mmio *mmio, phys_addr_t offset) in handle_mmio_cfg_reg() argument
222 vcpu->vcpu_id, offset >> 1); in handle_mmio_cfg_reg()
224 return vgic_handle_cfg_reg(reg, mmio, offset); in handle_mmio_cfg_reg()
228 struct kvm_exit_mmio *mmio, phys_addr_t offset) in handle_mmio_sgi_reg() argument
232 vgic_reg_access(mmio, ®, offset, in handle_mmio_sgi_reg()
246 phys_addr_t offset) in read_set_clear_sgi_pend_reg() argument
250 int min_sgi = (offset & ~0x3); in read_set_clear_sgi_pend_reg()
268 phys_addr_t offset, bool set) in write_set_clear_sgi_pend_reg() argument
272 int min_sgi = (offset & ~0x3); in write_set_clear_sgi_pend_reg()
304 phys_addr_t offset) in handle_mmio_sgi_set() argument
307 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset); in handle_mmio_sgi_set()
309 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, true); in handle_mmio_sgi_set()
314 phys_addr_t offset) in handle_mmio_sgi_clear() argument
317 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset); in handle_mmio_sgi_clear()
319 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, false); in handle_mmio_sgi_clear()
574 struct kvm_exit_mmio *mmio, phys_addr_t offset) in handle_cpu_mmio_misc() argument
583 switch (offset & ~0x3) { in handle_cpu_mmio_misc()
615 struct kvm_exit_mmio *mmio, phys_addr_t offset) in handle_mmio_abpr() argument
622 phys_addr_t offset) in handle_cpu_mmio_ident() argument
669 phys_addr_t offset; in vgic_attr_regs_access() local
676 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; in vgic_attr_regs_access()
701 mmio.phys_addr = vgic->vgic_dist_base + offset; in vgic_attr_regs_access()
705 mmio.phys_addr = vgic->vgic_cpu_base + offset; in vgic_attr_regs_access()
711 r = vgic_find_range(ranges, 4, offset); in vgic_attr_regs_access()
743 offset -= r->base; in vgic_attr_regs_access()
744 r->handle_mmio(vcpu, &mmio, offset); in vgic_attr_regs_access()
822 phys_addr_t offset; in vgic_v2_has_attr() local
833 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; in vgic_v2_has_attr()
834 return vgic_has_attr_regs(vgic_dist_ranges, offset); in vgic_v2_has_attr()
836 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; in vgic_v2_has_attr()
837 return vgic_has_attr_regs(vgic_cpu_ranges, offset); in vgic_v2_has_attr()