40 static bool skl_check_fw_status(struct sst_dsp *ctx, u32 status)  in skl_check_fw_status()  argument
44 	cur_sts = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS) & SKL_FW_STS_MASK;  in skl_check_fw_status()
49 static int skl_transfer_firmware(struct sst_dsp *ctx,  in skl_transfer_firmware()  argument
54 	ret = ctx->cl_dev.ops.cl_copy_to_dmabuf(ctx, basefw, base_fw_size);  in skl_transfer_firmware()
58 	ret = sst_dsp_register_poll(ctx,  in skl_transfer_firmware()
65 	ctx->cl_dev.ops.cl_stop_dma(ctx);  in skl_transfer_firmware()
70 static int skl_load_base_firmware(struct sst_dsp *ctx)  in skl_load_base_firmware()  argument
73 	struct skl_sst *skl = ctx->thread_context;  in skl_load_base_firmware()
79 	if (ctx->fw == NULL) {  in skl_load_base_firmware()
80 		ret = request_firmware(&ctx->fw, "dsp_fw_release.bin", ctx->dev);  in skl_load_base_firmware()
82 			dev_err(ctx->dev, "Request firmware failed %d\n", ret);  in skl_load_base_firmware()
83 			skl_dsp_disable_core(ctx);  in skl_load_base_firmware()
88 	ret = skl_dsp_boot(ctx);  in skl_load_base_firmware()
90 		dev_err(ctx->dev, "Boot dsp core failed ret: %d", ret);  in skl_load_base_firmware()
94 	ret = skl_cldma_prepare(ctx);  in skl_load_base_firmware()
96 		dev_err(ctx->dev, "CL dma prepare failed : %d", ret);  in skl_load_base_firmware()
101 	skl_ipc_int_enable(ctx);  in skl_load_base_firmware()
102 	skl_ipc_op_int_enable(ctx);  in skl_load_base_firmware()
106 		if (skl_check_fw_status(ctx, SKL_FW_INIT)) {  in skl_load_base_firmware()
107 			dev_dbg(ctx->dev,  in skl_load_base_firmware()
114 		reg = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS);  in skl_load_base_firmware()
115 		dev_err(ctx->dev,  in skl_load_base_firmware()
121 	ret = skl_transfer_firmware(ctx, ctx->fw->data, ctx->fw->size);  in skl_load_base_firmware()
123 		dev_err(ctx->dev, "Transfer firmware failed%d\n", ret);  in skl_load_base_firmware()
129 			dev_err(ctx->dev, "DSP boot failed, FW Ready timed-out\n");  in skl_load_base_firmware()
134 		dev_dbg(ctx->dev, "Download firmware successful%d\n", ret);  in skl_load_base_firmware()
135 		skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);  in skl_load_base_firmware()
140 	skl_dsp_disable_core(ctx);  in skl_load_base_firmware()
141 	release_firmware(ctx->fw);  in skl_load_base_firmware()
142 	ctx->fw = NULL;  in skl_load_base_firmware()
146 static int skl_set_dsp_D0(struct sst_dsp *ctx)  in skl_set_dsp_D0()  argument
150 	ret = skl_load_base_firmware(ctx);  in skl_set_dsp_D0()
152 		dev_err(ctx->dev, "unable to load firmware\n");  in skl_set_dsp_D0()
156 	skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);  in skl_set_dsp_D0()
161 static int skl_set_dsp_D3(struct sst_dsp *ctx)  in skl_set_dsp_D3()  argument
165 	struct skl_sst *skl = ctx->thread_context;  in skl_set_dsp_D3()
167 	dev_dbg(ctx->dev, "In %s:\n", __func__);  in skl_set_dsp_D3()
168 	mutex_lock(&ctx->mutex);  in skl_set_dsp_D3()
169 	if (!is_skl_dsp_running(ctx)) {  in skl_set_dsp_D3()
170 		mutex_unlock(&ctx->mutex);  in skl_set_dsp_D3()
173 	mutex_unlock(&ctx->mutex);  in skl_set_dsp_D3()
179 		dev_err(ctx->dev, "Failed to set DSP to D3 state\n");  in skl_set_dsp_D3()
183 	ret = skl_dsp_disable_core(ctx);  in skl_set_dsp_D3()
185 		dev_err(ctx->dev, "disable dsp core failed ret: %d\n", ret);  in skl_set_dsp_D3()
188 	skl_dsp_set_state_locked(ctx, SKL_DSP_RESET);  in skl_set_dsp_D3()
191 	ctx->cl_dev.ops.cl_cleanup_controller(ctx);  in skl_set_dsp_D3()
192 	skl_cldma_int_disable(ctx);  in skl_set_dsp_D3()
193 	skl_ipc_op_int_disable(ctx);  in skl_set_dsp_D3()
194 	skl_ipc_int_disable(ctx);  in skl_set_dsp_D3()
199 static unsigned int skl_get_errorcode(struct sst_dsp *ctx)  in skl_get_errorcode()  argument
201 	 return sst_dsp_shim_read(ctx, SKL_ADSP_ERROR_CODE);  in skl_get_errorcode()
275 void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)  in skl_sst_dsp_cleanup()  argument
277 	skl_ipc_free(&ctx->ipc);  in skl_sst_dsp_cleanup()
278 	ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp);  in skl_sst_dsp_cleanup()
279 	ctx->dsp->ops->free(ctx->dsp);  in skl_sst_dsp_cleanup()