24 static void skl_cldma_int_enable(struct sst_dsp *ctx)  in skl_cldma_int_enable()  argument
26 	sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,  in skl_cldma_int_enable()
30 void skl_cldma_int_disable(struct sst_dsp *ctx)  in skl_cldma_int_disable()  argument
32 	sst_dsp_shim_update_bits_unlocked(ctx,  in skl_cldma_int_disable()
37 static void skl_cldma_setup_bdle(struct sst_dsp *ctx,  in skl_cldma_setup_bdle()  argument
43 	ctx->cl_dev.frags = 0;  in skl_cldma_setup_bdle()
46 				(ctx->cl_dev.frags * ctx->cl_dev.bufsize));  in skl_cldma_setup_bdle()
51 		bdl[2] = cpu_to_le32(ctx->cl_dev.bufsize);  in skl_cldma_setup_bdle()
53 		size -= ctx->cl_dev.bufsize;  in skl_cldma_setup_bdle()
57 		ctx->cl_dev.frags++;  in skl_cldma_setup_bdle()
67 static void skl_cldma_setup_controller(struct sst_dsp  *ctx,  in skl_cldma_setup_controller()  argument
71 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,  in skl_cldma_setup_controller()
73 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,  in skl_cldma_setup_controller()
76 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, max_size);  in skl_cldma_setup_controller()
77 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, count - 1);  in skl_cldma_setup_controller()
78 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,  in skl_cldma_setup_controller()
80 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,  in skl_cldma_setup_controller()
82 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,  in skl_cldma_setup_controller()
84 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,  in skl_cldma_setup_controller()
88 static void skl_cldma_setup_spb(struct sst_dsp  *ctx,  in skl_cldma_setup_spb()  argument
92 		sst_dsp_shim_update_bits_unlocked(ctx,  in skl_cldma_setup_spb()
97 	sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size);  in skl_cldma_setup_spb()
100 static void skl_cldma_cleanup_spb(struct sst_dsp  *ctx)  in skl_cldma_cleanup_spb()  argument
102 	sst_dsp_shim_update_bits_unlocked(ctx,  in skl_cldma_cleanup_spb()
107 	sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0);  in skl_cldma_cleanup_spb()
110 static void skl_cldma_trigger(struct sst_dsp  *ctx, bool enable)  in skl_cldma_trigger()  argument
113 		sst_dsp_shim_update_bits_unlocked(ctx,  in skl_cldma_trigger()
117 		sst_dsp_shim_update_bits_unlocked(ctx,  in skl_cldma_trigger()
122 static void skl_cldma_cleanup(struct sst_dsp  *ctx)  in skl_cldma_cleanup()  argument
124 	skl_cldma_cleanup_spb(ctx);  in skl_cldma_cleanup()
126 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,  in skl_cldma_cleanup()
128 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,  in skl_cldma_cleanup()
130 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,  in skl_cldma_cleanup()
132 	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,  in skl_cldma_cleanup()
135 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));  in skl_cldma_cleanup()
136 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);  in skl_cldma_cleanup()
138 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);  in skl_cldma_cleanup()
139 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);  in skl_cldma_cleanup()
142 static int skl_cldma_wait_interruptible(struct sst_dsp *ctx)  in skl_cldma_wait_interruptible()  argument
146 	if (!wait_event_timeout(ctx->cl_dev.wait_queue,  in skl_cldma_wait_interruptible()
147 				ctx->cl_dev.wait_condition,  in skl_cldma_wait_interruptible()
149 		dev_err(ctx->dev, "%s: Wait timeout\n", __func__);  in skl_cldma_wait_interruptible()
154 	dev_dbg(ctx->dev, "%s: Event wake\n", __func__);  in skl_cldma_wait_interruptible()
155 	if (ctx->cl_dev.wake_status != SKL_CL_DMA_BUF_COMPLETE) {  in skl_cldma_wait_interruptible()
156 		dev_err(ctx->dev, "%s: DMA Error\n", __func__);  in skl_cldma_wait_interruptible()
161 	ctx->cl_dev.wake_status = SKL_CL_DMA_STATUS_NONE;  in skl_cldma_wait_interruptible()
165 static void skl_cldma_stop(struct sst_dsp *ctx)  in skl_cldma_stop()  argument
167 	ctx->cl_dev.ops.cl_trigger(ctx, false);  in skl_cldma_stop()
170 static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size,  in skl_cldma_fill_buffer()  argument
173 	dev_dbg(ctx->dev, "Size: %x, intr_enable: %d\n", size, intr_enable);  in skl_cldma_fill_buffer()
174 	dev_dbg(ctx->dev, "buf_pos_index:%d, trigger:%d\n",  in skl_cldma_fill_buffer()
175 			ctx->cl_dev.dma_buffer_offset, trigger);  in skl_cldma_fill_buffer()
176 	dev_dbg(ctx->dev, "spib position: %d\n", ctx->cl_dev.curr_spib_pos);  in skl_cldma_fill_buffer()
178 	memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,  in skl_cldma_fill_buffer()
181 	if (ctx->cl_dev.curr_spib_pos == ctx->cl_dev.bufsize)  in skl_cldma_fill_buffer()
182 		ctx->cl_dev.dma_buffer_offset = 0;  in skl_cldma_fill_buffer()
184 		ctx->cl_dev.dma_buffer_offset = ctx->cl_dev.curr_spib_pos;  in skl_cldma_fill_buffer()
186 	ctx->cl_dev.wait_condition = false;  in skl_cldma_fill_buffer()
189 		skl_cldma_int_enable(ctx);  in skl_cldma_fill_buffer()
191 	ctx->cl_dev.ops.cl_setup_spb(ctx, ctx->cl_dev.curr_spib_pos, trigger);  in skl_cldma_fill_buffer()
193 		ctx->cl_dev.ops.cl_trigger(ctx, true);  in skl_cldma_fill_buffer()
208 skl_cldma_copy_to_buf(struct sst_dsp *ctx, const void *bin, u32 total_size)  in skl_cldma_copy_to_buf()  argument
220 	dev_dbg(ctx->dev, "%s: Total binary size: %u\n", __func__, bytes_left);  in skl_cldma_copy_to_buf()
223 		if (bytes_left > ctx->cl_dev.bufsize) {  in skl_cldma_copy_to_buf()
229 			if (ctx->cl_dev.curr_spib_pos == 0)  in skl_cldma_copy_to_buf()
230 				ctx->cl_dev.curr_spib_pos = ctx->cl_dev.bufsize;  in skl_cldma_copy_to_buf()
232 			size = ctx->cl_dev.bufsize;  in skl_cldma_copy_to_buf()
233 			skl_cldma_fill_buffer(ctx, size, curr_pos, true, start);  in skl_cldma_copy_to_buf()
236 			ret = skl_cldma_wait_interruptible(ctx);  in skl_cldma_copy_to_buf()
238 				skl_cldma_stop(ctx);  in skl_cldma_copy_to_buf()
243 			skl_cldma_int_disable(ctx);  in skl_cldma_copy_to_buf()
245 			if ((ctx->cl_dev.curr_spib_pos + bytes_left)  in skl_cldma_copy_to_buf()
246 							<= ctx->cl_dev.bufsize) {  in skl_cldma_copy_to_buf()
247 				ctx->cl_dev.curr_spib_pos += bytes_left;  in skl_cldma_copy_to_buf()
250 					(ctx->cl_dev.bufsize -  in skl_cldma_copy_to_buf()
251 					ctx->cl_dev.curr_spib_pos);  in skl_cldma_copy_to_buf()
252 				ctx->cl_dev.curr_spib_pos = excess_bytes;  in skl_cldma_copy_to_buf()
256 			skl_cldma_fill_buffer(ctx, size,  in skl_cldma_copy_to_buf()
266 void skl_cldma_process_intr(struct sst_dsp *ctx)  in skl_cldma_process_intr()  argument
271 		sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_CL_SD_STS);  in skl_cldma_process_intr()
274 		ctx->cl_dev.wake_status = SKL_CL_DMA_ERR;  in skl_cldma_process_intr()
276 		ctx->cl_dev.wake_status = SKL_CL_DMA_BUF_COMPLETE;  in skl_cldma_process_intr()
278 	ctx->cl_dev.wait_condition = true;  in skl_cldma_process_intr()
279 	wake_up(&ctx->cl_dev.wait_queue);  in skl_cldma_process_intr()
282 int skl_cldma_prepare(struct sst_dsp *ctx)  in skl_cldma_prepare()  argument
287 	ctx->cl_dev.bufsize = SKL_MAX_BUFFER_SIZE;  in skl_cldma_prepare()
290 	ctx->cl_dev.ops.cl_setup_bdle = skl_cldma_setup_bdle;  in skl_cldma_prepare()
291 	ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller;  in skl_cldma_prepare()
292 	ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb;  in skl_cldma_prepare()
293 	ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb;  in skl_cldma_prepare()
294 	ctx->cl_dev.ops.cl_trigger = skl_cldma_trigger;  in skl_cldma_prepare()
295 	ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup;  in skl_cldma_prepare()
296 	ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf;  in skl_cldma_prepare()
297 	ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;  in skl_cldma_prepare()
300 	ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,  in skl_cldma_prepare()
301 			&ctx->cl_dev.dmab_data, ctx->cl_dev.bufsize);  in skl_cldma_prepare()
303 		dev_err(ctx->dev, "Alloc buffer for base fw failed: %x", ret);  in skl_cldma_prepare()
307 	ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,  in skl_cldma_prepare()
308 			&ctx->cl_dev.dmab_bdl, PAGE_SIZE);  in skl_cldma_prepare()
310 		dev_err(ctx->dev, "Alloc buffer for blde failed: %x", ret);  in skl_cldma_prepare()
311 		ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);  in skl_cldma_prepare()
314 	bdl = (u32 *)ctx->cl_dev.dmab_bdl.area;  in skl_cldma_prepare()
317 	ctx->cl_dev.ops.cl_setup_bdle(ctx, &ctx->cl_dev.dmab_data,  in skl_cldma_prepare()
318 			&bdl, ctx->cl_dev.bufsize, 1);  in skl_cldma_prepare()
319 	ctx->cl_dev.ops.cl_setup_controller(ctx, &ctx->cl_dev.dmab_bdl,  in skl_cldma_prepare()
320 			ctx->cl_dev.bufsize, ctx->cl_dev.frags);  in skl_cldma_prepare()
322 	ctx->cl_dev.curr_spib_pos = 0;  in skl_cldma_prepare()
323 	ctx->cl_dev.dma_buffer_offset = 0;  in skl_cldma_prepare()
324 	init_waitqueue_head(&ctx->cl_dev.wait_queue);  in skl_cldma_prepare()