86 static void hsw_free(struct sst_dsp *sst);
218 	struct sst_dsp *sst = (struct sst_dsp *) context;  in hsw_irq()  local
222 	spin_lock(&sst->spinlock);  in hsw_irq()
225 	isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);  in hsw_irq()
228 			sst_dsp_shim_read_unlocked(sst, SST_IMRX));  in hsw_irq()
231 		sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,  in hsw_irq()
238 			sst_dsp_shim_read_unlocked(sst, SST_IMRX));  in hsw_irq()
241 		sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,  in hsw_irq()
246 	spin_unlock(&sst->spinlock);  in hsw_irq()
250 static void hsw_set_dsp_D3(struct sst_dsp *sst)  in hsw_set_dsp_D3()  argument
256 	reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_set_dsp_D3()
258 	writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_set_dsp_D3()
261 	val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);  in hsw_set_dsp_D3()
265 	writel(val, sst->addr.pci_cfg + SST_VDRTCTL0);  in hsw_set_dsp_D3()
268 	val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_set_dsp_D3()
270 	writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_set_dsp_D3()
273 	sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,  in hsw_set_dsp_D3()
277 	val = readl(sst->addr.pci_cfg + SST_PMCS);  in hsw_set_dsp_D3()
279 	writel(val, sst->addr.pci_cfg + SST_PMCS);  in hsw_set_dsp_D3()
283 	reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_set_dsp_D3()
285 	writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_set_dsp_D3()
291 static void hsw_reset(struct sst_dsp *sst)  in hsw_reset()  argument
294 	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,  in hsw_reset()
302 	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,  in hsw_reset()
306 static int hsw_set_dsp_D0(struct sst_dsp *sst)  in hsw_set_dsp_D0()  argument
312 	reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_set_dsp_D0()
314 	writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_set_dsp_D0()
317 	reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);  in hsw_set_dsp_D0()
319 	writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0);  in hsw_set_dsp_D0()
322 	reg = readl(sst->addr.pci_cfg + SST_PMCS);  in hsw_set_dsp_D0()
324 	writel(reg, sst->addr.pci_cfg + SST_PMCS);  in hsw_set_dsp_D0()
328 		reg = readl(sst->addr.pci_cfg + SST_PMCS) & SST_PMCS_PS_MASK;  in hsw_set_dsp_D0()
339 	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,  in hsw_set_dsp_D0()
343 	sst_dsp_shim_update_bits_unlocked(sst,  in hsw_set_dsp_D0()
348 	sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,  in hsw_set_dsp_D0()
353 	hsw_reset(sst);  in hsw_set_dsp_D0()
356 	reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_set_dsp_D0()
358 	writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_set_dsp_D0()
363 	reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_set_dsp_D0()
365 	writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_set_dsp_D0()
369 	reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);  in hsw_set_dsp_D0()
373 	writel(reg & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0);  in hsw_set_dsp_D0()
377 	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR2, SST_CSR2_SDFD_SSP1,  in hsw_set_dsp_D0()
381 	sst_dsp_shim_update_bits(sst, SST_HMDC,  in hsw_set_dsp_D0()
386 	sst_dsp_shim_update_bits(sst, SST_IMRX, (SST_IMRX_BUSY | SST_IMRX_DONE),  in hsw_set_dsp_D0()
388 	sst_dsp_shim_update_bits(sst, SST_IMRD, (SST_IMRD_DONE | SST_IMRD_BUSY |  in hsw_set_dsp_D0()
392 	sst_dsp_shim_write(sst, SST_IPCX, 0x0);  in hsw_set_dsp_D0()
393 	sst_dsp_shim_write(sst, SST_IPCD, 0x0);  in hsw_set_dsp_D0()
394 	sst_dsp_shim_write(sst, 0x80, 0x6);  in hsw_set_dsp_D0()
395 	sst_dsp_shim_write(sst, 0xe0, 0x300a);  in hsw_set_dsp_D0()
400 static void hsw_boot(struct sst_dsp *sst)  in hsw_boot()  argument
403 	sst_dsp_shim_update_bits(sst, SST_HMDC,  in hsw_boot()
407 	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, SST_CSR_STALL, 0x0);  in hsw_boot()
410 static void hsw_stall(struct sst_dsp *sst)  in hsw_stall()  argument
413 	sst_dsp_shim_update_bits(sst, SST_CSR,  in hsw_stall()
418 static void hsw_sleep(struct sst_dsp *sst)  in hsw_sleep()  argument
420 	dev_dbg(sst->dev, "HSW_PM dsp runtime suspend\n");  in hsw_sleep()
423 	sst_dsp_shim_update_bits(sst, SST_CSR,  in hsw_sleep()
427 	hsw_set_dsp_D3(sst);  in hsw_sleep()
428 	dev_dbg(sst->dev, "HSW_PM dsp runtime suspend exit\n");  in hsw_sleep()
431 static int hsw_wake(struct sst_dsp *sst)  in hsw_wake()  argument
435 	dev_dbg(sst->dev, "HSW_PM dsp runtime resume\n");  in hsw_wake()
437 	ret = hsw_set_dsp_D0(sst);  in hsw_wake()
441 	dev_dbg(sst->dev, "HSW_PM dsp runtime resume exit\n");  in hsw_wake()
466 static int hsw_acpi_resource_map(struct sst_dsp *sst, struct sst_pdata *pdata)  in hsw_acpi_resource_map()  argument
469 	sst->addr.lpe_base = pdata->lpe_base;  in hsw_acpi_resource_map()
470 	sst->addr.lpe = ioremap(pdata->lpe_base, pdata->lpe_size);  in hsw_acpi_resource_map()
471 	if (!sst->addr.lpe)  in hsw_acpi_resource_map()
475 	sst->addr.pci_cfg = ioremap(pdata->pcicfg_base, pdata->pcicfg_size);  in hsw_acpi_resource_map()
476 	if (!sst->addr.pci_cfg) {  in hsw_acpi_resource_map()
477 		iounmap(sst->addr.lpe);  in hsw_acpi_resource_map()
482 	sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset;  in hsw_acpi_resource_map()
500 	struct sst_dsp *sst = block->dsp;  in hsw_block_get_bit()  local
503 		if (sram_shift[index].dev_id == sst->id)  in hsw_block_get_bit()
531 	struct sst_dsp *sst = block->dsp;  in sst_mem_block_dummy_read()  local
534 	memcpy_fromio(tmp_buf, sst->addr.lpe + block->offset, size);  in sst_mem_block_dummy_read()
540 	struct sst_dsp *sst = block->dsp;  in hsw_block_enable()  local
550 	val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_block_enable()
552 	writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_block_enable()
554 	val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);  in hsw_block_enable()
556 	writel(val & ~bit, sst->addr.pci_cfg + SST_VDRTCTL0);  in hsw_block_enable()
562 	val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_block_enable()
564 	writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_block_enable()
576 	struct sst_dsp *sst = block->dsp;  in hsw_block_disable()  local
586 	val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_block_disable()
588 	writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_block_disable()
591 	val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);  in hsw_block_disable()
595 		writel(val | bit, sst->addr.pci_cfg + SST_VDRTCTL0);  in hsw_block_disable()
601 	val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_block_disable()
603 	writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);  in hsw_block_disable()
615 static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata)  in hsw_init()  argument
622 	dev = sst->dma_dev;  in hsw_init()
624 	switch (sst->id) {  in hsw_init()
628 		sst->addr.iram_offset = SST_LP_IRAM_OFFSET;  in hsw_init()
629 		sst->addr.dsp_iram_offset = SST_LPT_DSP_IRAM_OFFSET;  in hsw_init()
630 		sst->addr.dsp_dram_offset = SST_LPT_DSP_DRAM_OFFSET;  in hsw_init()
631 		sst->addr.shim_offset = SST_LP_SHIM_OFFSET;  in hsw_init()
636 		sst->addr.iram_offset = SST_WPT_IRAM_OFFSET;  in hsw_init()
637 		sst->addr.dsp_iram_offset = SST_WPT_DSP_IRAM_OFFSET;  in hsw_init()
638 		sst->addr.dsp_dram_offset = SST_WPT_DSP_DRAM_OFFSET;  in hsw_init()
639 		sst->addr.shim_offset = SST_WPT_SHIM_OFFSET;  in hsw_init()
646 	ret = hsw_acpi_resource_map(sst, pdata);  in hsw_init()
653 	ret = hsw_set_dsp_D0(sst);  in hsw_init()
671 			sst_mem_block_register(sst, offset, size,  in hsw_init()
672 				region[i].type, &sst_hsw_ops, j, sst);  in hsw_init()
681 	writel(0xffffffff & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0);  in hsw_init()
686 static void hsw_free(struct sst_dsp *sst)  in hsw_free()  argument
688 	sst_mem_block_unregister_all(sst);  in hsw_free()
689 	iounmap(sst->addr.lpe);  in hsw_free()
690 	iounmap(sst->addr.pci_cfg);  in hsw_free()