68 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in intel_sst_reset_dsp_mrfld()
70 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in intel_sst_reset_dsp_mrfld()
72 	csr.full |= 0x7;  in intel_sst_reset_dsp_mrfld()
73 	sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);  in intel_sst_reset_dsp_mrfld()
74 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in intel_sst_reset_dsp_mrfld()
76 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in intel_sst_reset_dsp_mrfld()
78 	csr.full &= ~(0x1);  in intel_sst_reset_dsp_mrfld()
79 	sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);  in intel_sst_reset_dsp_mrfld()
81 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in intel_sst_reset_dsp_mrfld()
82 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in intel_sst_reset_dsp_mrfld()
96 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in sst_start_mrfld()
97 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in sst_start_mrfld()
99 	csr.full |= 0x7;  in sst_start_mrfld()
100 	sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);  in sst_start_mrfld()
102 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in sst_start_mrfld()
103 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in sst_start_mrfld()
106 	csr.full &= ~(0x5);  in sst_start_mrfld()
107 	sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);  in sst_start_mrfld()
109 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in sst_start_mrfld()
111 			csr.full);  in sst_start_mrfld()