122 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,  in fsl_esai_divisor_cal()  argument
184 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),  in fsl_esai_divisor_cal()
193 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),  in fsl_esai_divisor_cal()
215 	bool tx = clk_id <= ESAI_HCKT_EXTAL;  in fsl_esai_set_dai_sysclk()  local
222 	if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])  in fsl_esai_set_dai_sysclk()
226 	esai_priv->sck_div[tx] = true;  in fsl_esai_set_dai_sysclk()
229 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),  in fsl_esai_set_dai_sysclk()
267 				tx ? 'T' : 'R');  in fsl_esai_set_dai_sysclk()
274 		ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;  in fsl_esai_set_dai_sysclk()
279 				tx ? 'T' : 'R');  in fsl_esai_set_dai_sysclk()
283 	ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);  in fsl_esai_set_dai_sysclk()
287 	esai_priv->sck_div[tx] = false;  in fsl_esai_set_dai_sysclk()
290 	esai_priv->hck_dir[tx] = dir;  in fsl_esai_set_dai_sysclk()
291 	esai_priv->hck_rate[tx] = freq;  in fsl_esai_set_dai_sysclk()
294 			   tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :  in fsl_esai_set_dai_sysclk()
303 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)  in fsl_esai_set_bclk()  argument
306 	u32 hck_rate = esai_priv->hck_rate[tx];  in fsl_esai_set_bclk()
311 	if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)  in fsl_esai_set_bclk()
324 				tx ? 'T' : 'R');  in fsl_esai_set_bclk()
329 	if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {  in fsl_esai_set_bclk()
334 	ret = fsl_esai_divisor_cal(dai, tx, ratio, true,  in fsl_esai_set_bclk()
335 			esai_priv->sck_div[tx] ? 0 : ratio);  in fsl_esai_set_bclk()
340 	esai_priv->sck_rate[tx] = freq;  in fsl_esai_set_bclk()
512 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;  in fsl_esai_hw_params()  local
526 	ret = fsl_esai_set_bclk(dai, tx, bclk);  in fsl_esai_hw_params()
531 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),  in fsl_esai_hw_params()
535 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),  in fsl_esai_hw_params()
539 	      (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);  in fsl_esai_hw_params()
541 	     (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));  in fsl_esai_hw_params()
543 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);  in fsl_esai_hw_params()
545 	mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);  in fsl_esai_hw_params()
546 	val = ESAI_xCR_xSWS(slot_width, width) | (tx ? ESAI_xCR_PADC : 0);  in fsl_esai_hw_params()
548 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);  in fsl_esai_hw_params()
574 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;  in fsl_esai_trigger()  local
582 		regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),  in fsl_esai_trigger()
586 		for (i = 0; tx && i < channels; i++)  in fsl_esai_trigger()
589 		regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),  in fsl_esai_trigger()
590 				   tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,  in fsl_esai_trigger()
591 				   tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));  in fsl_esai_trigger()
596 		regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),  in fsl_esai_trigger()
597 				   tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);  in fsl_esai_trigger()
600 		regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),  in fsl_esai_trigger()
602 		regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),  in fsl_esai_trigger()