105 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)  in i2s_write_reg()  function
121 			i2s_write_reg(dev->i2s_base, TER(i), 0);  in i2s_disable_channels()
124 			i2s_write_reg(dev->i2s_base, RER(i), 0);  in i2s_disable_channels()
145 	i2s_write_reg(dev->i2s_base, IER, 1);  in i2s_start()
150 			i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);  in i2s_start()
152 		i2s_write_reg(dev->i2s_base, ITER, 1);  in i2s_start()
156 			i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);  in i2s_start()
158 		i2s_write_reg(dev->i2s_base, IRER, 1);  in i2s_start()
161 	i2s_write_reg(dev->i2s_base, CER, 1);  in i2s_start()
171 		i2s_write_reg(dev->i2s_base, ITER, 0);  in i2s_stop()
175 			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);  in i2s_stop()
178 		i2s_write_reg(dev->i2s_base, IRER, 0);  in i2s_stop()
182 			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);  in i2s_stop()
187 		i2s_write_reg(dev->i2s_base, CER, 0);  in i2s_stop()
188 		i2s_write_reg(dev->i2s_base, IER, 0);  in i2s_stop()
265 			i2s_write_reg(dev->i2s_base, TCR(ch_reg),  in dw_i2s_hw_params()
267 			i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);  in dw_i2s_hw_params()
269 			i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);  in dw_i2s_hw_params()
270 			i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);  in dw_i2s_hw_params()
272 			i2s_write_reg(dev->i2s_base, RCR(ch_reg),  in dw_i2s_hw_params()
274 			i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);  in dw_i2s_hw_params()
276 			i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);  in dw_i2s_hw_params()
277 			i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);  in dw_i2s_hw_params()
281 	i2s_write_reg(dev->i2s_base, CCR, ccr);  in dw_i2s_hw_params()
319 		i2s_write_reg(dev->i2s_base, TXFFR, 1);  in dw_i2s_prepare()
321 		i2s_write_reg(dev->i2s_base, RXFFR, 1);  in dw_i2s_prepare()