Lines Matching refs:dev
96 struct device *dev; member
115 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream) in i2s_disable_channels() argument
121 i2s_write_reg(dev->i2s_base, TER(i), 0); in i2s_disable_channels()
124 i2s_write_reg(dev->i2s_base, RER(i), 0); in i2s_disable_channels()
128 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream) in i2s_clear_irqs() argument
134 i2s_read_reg(dev->i2s_base, TOR(i)); in i2s_clear_irqs()
137 i2s_read_reg(dev->i2s_base, ROR(i)); in i2s_clear_irqs()
141 static void i2s_start(struct dw_i2s_dev *dev, in i2s_start() argument
145 i2s_write_reg(dev->i2s_base, IER, 1); in i2s_start()
149 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_start()
150 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); in i2s_start()
152 i2s_write_reg(dev->i2s_base, ITER, 1); in i2s_start()
155 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_start()
156 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); in i2s_start()
158 i2s_write_reg(dev->i2s_base, IRER, 1); in i2s_start()
161 i2s_write_reg(dev->i2s_base, CER, 1); in i2s_start()
164 static void i2s_stop(struct dw_i2s_dev *dev, in i2s_stop() argument
169 i2s_clear_irqs(dev, substream->stream); in i2s_stop()
171 i2s_write_reg(dev->i2s_base, ITER, 0); in i2s_stop()
174 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_stop()
175 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); in i2s_stop()
178 i2s_write_reg(dev->i2s_base, IRER, 0); in i2s_stop()
181 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_stop()
182 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); in i2s_stop()
186 if (!dev->active) { in i2s_stop()
187 i2s_write_reg(dev->i2s_base, CER, 0); in i2s_stop()
188 i2s_write_reg(dev->i2s_base, IER, 0); in i2s_stop()
195 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); in dw_i2s_startup() local
198 if (!(dev->capability & DWC_I2S_RECORD) && in dw_i2s_startup()
202 if (!(dev->capability & DWC_I2S_PLAY) && in dw_i2s_startup()
207 dma_data = &dev->play_dma_data; in dw_i2s_startup()
209 dma_data = &dev->capture_dma_data; in dw_i2s_startup()
219 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); in dw_i2s_hw_params() local
220 struct i2s_clk_config_data *config = &dev->config; in dw_i2s_hw_params()
244 dev_err(dev->dev, "designware-i2s: unsuppted PCM fmt"); in dw_i2s_hw_params()
257 dev_err(dev->dev, "channel not supported\n"); in dw_i2s_hw_params()
261 i2s_disable_channels(dev, substream->stream); in dw_i2s_hw_params()
265 i2s_write_reg(dev->i2s_base, TCR(ch_reg), in dw_i2s_hw_params()
267 i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); in dw_i2s_hw_params()
268 irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); in dw_i2s_hw_params()
269 i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); in dw_i2s_hw_params()
270 i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); in dw_i2s_hw_params()
272 i2s_write_reg(dev->i2s_base, RCR(ch_reg), in dw_i2s_hw_params()
274 i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); in dw_i2s_hw_params()
275 irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); in dw_i2s_hw_params()
276 i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03); in dw_i2s_hw_params()
277 i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); in dw_i2s_hw_params()
281 i2s_write_reg(dev->i2s_base, CCR, ccr); in dw_i2s_hw_params()
285 if (dev->capability & DW_I2S_MASTER) { in dw_i2s_hw_params()
286 if (dev->i2s_clk_cfg) { in dw_i2s_hw_params()
287 ret = dev->i2s_clk_cfg(config); in dw_i2s_hw_params()
289 dev_err(dev->dev, "runtime audio clk config fail\n"); in dw_i2s_hw_params()
296 ret = clk_set_rate(dev->clk, bitclk); in dw_i2s_hw_params()
298 dev_err(dev->dev, "Can't set I2S clock rate: %d\n", in dw_i2s_hw_params()
316 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); in dw_i2s_prepare() local
319 i2s_write_reg(dev->i2s_base, TXFFR, 1); in dw_i2s_prepare()
321 i2s_write_reg(dev->i2s_base, RXFFR, 1); in dw_i2s_prepare()
329 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); in dw_i2s_trigger() local
336 dev->active++; in dw_i2s_trigger()
337 i2s_start(dev, substream); in dw_i2s_trigger()
343 dev->active--; in dw_i2s_trigger()
344 i2s_stop(dev, substream); in dw_i2s_trigger()
355 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); in dw_i2s_set_fmt() local
360 if (dev->capability & DW_I2S_SLAVE) in dw_i2s_set_fmt()
366 if (dev->capability & DW_I2S_MASTER) in dw_i2s_set_fmt()
376 dev_dbg(dev->dev, "dwc : Invalid master/slave format\n"); in dw_i2s_set_fmt()
400 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); in dw_i2s_suspend() local
402 if (dev->capability & DW_I2S_MASTER) in dw_i2s_suspend()
403 clk_disable(dev->clk); in dw_i2s_suspend()
409 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); in dw_i2s_resume() local
411 if (dev->capability & DW_I2S_MASTER) in dw_i2s_resume()
412 clk_enable(dev->clk); in dw_i2s_resume()
454 static int dw_configure_dai(struct dw_i2s_dev *dev, in dw_configure_dai() argument
462 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); in dw_configure_dai()
463 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); in dw_configure_dai()
467 dev_dbg(dev->dev, " designware: play supported\n"); in dw_configure_dai()
479 dev_dbg(dev->dev, "designware: record supported\n"); in dw_configure_dai()
491 dev_dbg(dev->dev, "designware: i2s master mode supported\n"); in dw_configure_dai()
492 dev->capability |= DW_I2S_MASTER; in dw_configure_dai()
494 dev_dbg(dev->dev, "designware: i2s slave mode supported\n"); in dw_configure_dai()
495 dev->capability |= DW_I2S_SLAVE; in dw_configure_dai()
501 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev, in dw_configure_dai_by_pd() argument
506 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); in dw_configure_dai_by_pd()
513 ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates); in dw_configure_dai_by_pd()
518 dev->play_dma_data.pd.data = pdata->play_dma_data; in dw_configure_dai_by_pd()
519 dev->capture_dma_data.pd.data = pdata->capture_dma_data; in dw_configure_dai_by_pd()
520 dev->play_dma_data.pd.addr = res->start + I2S_TXDMA; in dw_configure_dai_by_pd()
521 dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA; in dw_configure_dai_by_pd()
522 dev->play_dma_data.pd.max_burst = 16; in dw_configure_dai_by_pd()
523 dev->capture_dma_data.pd.max_burst = 16; in dw_configure_dai_by_pd()
524 dev->play_dma_data.pd.addr_width = bus_widths[idx]; in dw_configure_dai_by_pd()
525 dev->capture_dma_data.pd.addr_width = bus_widths[idx]; in dw_configure_dai_by_pd()
526 dev->play_dma_data.pd.filter = pdata->filter; in dw_configure_dai_by_pd()
527 dev->capture_dma_data.pd.filter = pdata->filter; in dw_configure_dai_by_pd()
532 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev, in dw_configure_dai_by_dt() argument
536 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); in dw_configure_dai_by_dt()
537 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); in dw_configure_dai_by_dt()
546 ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000); in dw_configure_dai_by_dt()
553 dev->capability |= DWC_I2S_PLAY; in dw_configure_dai_by_dt()
554 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; in dw_configure_dai_by_dt()
555 dev->play_dma_data.dt.addr_width = bus_widths[idx]; in dw_configure_dai_by_dt()
556 dev->play_dma_data.dt.chan_name = "TX"; in dw_configure_dai_by_dt()
557 dev->play_dma_data.dt.fifo_size = fifo_depth * in dw_configure_dai_by_dt()
559 dev->play_dma_data.dt.maxburst = 16; in dw_configure_dai_by_dt()
564 dev->capability |= DWC_I2S_RECORD; in dw_configure_dai_by_dt()
565 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; in dw_configure_dai_by_dt()
566 dev->capture_dma_data.dt.addr_width = bus_widths[idx]; in dw_configure_dai_by_dt()
567 dev->capture_dma_data.dt.chan_name = "RX"; in dw_configure_dai_by_dt()
568 dev->capture_dma_data.dt.fifo_size = fifo_depth * in dw_configure_dai_by_dt()
570 dev->capture_dma_data.dt.maxburst = 16; in dw_configure_dai_by_dt()
579 const struct i2s_platform_data *pdata = pdev->dev.platform_data; in dw_i2s_probe()
580 struct dw_i2s_dev *dev; in dw_i2s_probe() local
586 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); in dw_i2s_probe()
587 if (!dev) { in dw_i2s_probe()
588 dev_warn(&pdev->dev, "kzalloc fail\n"); in dw_i2s_probe()
592 dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL); in dw_i2s_probe()
601 dev->i2s_base = devm_ioremap_resource(&pdev->dev, res); in dw_i2s_probe()
602 if (IS_ERR(dev->i2s_base)) in dw_i2s_probe()
603 return PTR_ERR(dev->i2s_base); in dw_i2s_probe()
605 dev->dev = &pdev->dev; in dw_i2s_probe()
608 dev->capability = pdata->cap; in dw_i2s_probe()
610 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata); in dw_i2s_probe()
613 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res); in dw_i2s_probe()
618 if (dev->capability & DW_I2S_MASTER) { in dw_i2s_probe()
620 dev->i2s_clk_cfg = pdata->i2s_clk_cfg; in dw_i2s_probe()
621 if (!dev->i2s_clk_cfg) { in dw_i2s_probe()
622 dev_err(&pdev->dev, "no clock configure method\n"); in dw_i2s_probe()
626 dev->clk = devm_clk_get(&pdev->dev, clk_id); in dw_i2s_probe()
628 if (IS_ERR(dev->clk)) in dw_i2s_probe()
629 return PTR_ERR(dev->clk); in dw_i2s_probe()
631 ret = clk_prepare_enable(dev->clk); in dw_i2s_probe()
636 dev_set_drvdata(&pdev->dev, dev); in dw_i2s_probe()
637 ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component, in dw_i2s_probe()
640 dev_err(&pdev->dev, "not able to register dai\n"); in dw_i2s_probe()
645 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); in dw_i2s_probe()
647 dev_err(&pdev->dev, in dw_i2s_probe()
656 if (dev->capability & DW_I2S_MASTER) in dw_i2s_probe()
657 clk_disable_unprepare(dev->clk); in dw_i2s_probe()
663 struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev); in dw_i2s_remove() local
665 if (dev->capability & DW_I2S_MASTER) in dw_i2s_remove()
666 clk_disable_unprepare(dev->clk); in dw_i2s_remove()