Lines Matching refs:fll
385 struct fll_config fll[2], fll_suspend[2]; member
696 rate = wm8995->fll[0].out; in configure_aif_clock()
700 rate = wm8995->fll[1].out; in configure_aif_clock()
1725 static int wm8995_get_fll_config(struct fll_div *fll, in wm8995_get_fll_config() argument
1734 fll->clk_ref_div = 0; in wm8995_get_fll_config()
1736 fll->clk_ref_div++; in wm8995_get_fll_config()
1739 if (fll->clk_ref_div > 3) in wm8995_get_fll_config()
1742 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); in wm8995_get_fll_config()
1745 fll->outdiv = 3; in wm8995_get_fll_config()
1746 while (freq_out * (fll->outdiv + 1) < 90000000) { in wm8995_get_fll_config()
1747 fll->outdiv++; in wm8995_get_fll_config()
1748 if (fll->outdiv > 63) in wm8995_get_fll_config()
1751 freq_out *= fll->outdiv + 1; in wm8995_get_fll_config()
1752 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); in wm8995_get_fll_config()
1755 fll->fll_fratio = 0; in wm8995_get_fll_config()
1757 fll->fll_fratio = 1; in wm8995_get_fll_config()
1760 fll->fll_fratio = 2; in wm8995_get_fll_config()
1763 fll->fll_fratio = 3; in wm8995_get_fll_config()
1766 fll->fll_fratio = 4; in wm8995_get_fll_config()
1769 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); in wm8995_get_fll_config()
1774 fll->n = Ndiv; in wm8995_get_fll_config()
1789 fll->k = K / 10; in wm8995_get_fll_config()
1791 pr_debug("N=%x K=%x\n", fll->n, fll->k); in wm8995_get_fll_config()
1803 struct fll_div fll; in wm8995_set_fll() local
1844 if (wm8995->fll[id].src == src && in wm8995_set_fll()
1845 wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out) in wm8995_set_fll()
1853 ret = wm8995_get_fll_config(&fll, freq_in, freq_out); in wm8995_set_fll()
1855 ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in, in wm8995_set_fll()
1856 wm8995->fll[id].out); in wm8995_set_fll()
1870 reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) | in wm8995_set_fll()
1871 (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT); in wm8995_set_fll()
1876 snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); in wm8995_set_fll()
1880 fll.n << WM8995_FLL1_N_SHIFT); in wm8995_set_fll()
1885 (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) | in wm8995_set_fll()
1892 wm8995->fll[id].in = freq_in; in wm8995_set_fll()
1893 wm8995->fll[id].out = freq_out; in wm8995_set_fll()
1894 wm8995->fll[id].src = src; in wm8995_set_fll()