Lines Matching refs:dma
473 struct cs4281_dma dma[4]; member
670 struct cs4281_dma *dma = substream->runtime->private_data; in snd_cs4281_trigger() local
676 dma->valDCR |= BA0_DCR_MSK; in snd_cs4281_trigger()
677 dma->valFCR |= BA0_FCR_FEN; in snd_cs4281_trigger()
680 dma->valDCR &= ~BA0_DCR_MSK; in snd_cs4281_trigger()
681 dma->valFCR &= ~BA0_FCR_FEN; in snd_cs4281_trigger()
685 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA); in snd_cs4281_trigger()
686 dma->valDMR |= BA0_DMR_DMA; in snd_cs4281_trigger()
687 dma->valDCR &= ~BA0_DCR_MSK; in snd_cs4281_trigger()
688 dma->valFCR |= BA0_FCR_FEN; in snd_cs4281_trigger()
692 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL); in snd_cs4281_trigger()
693 dma->valDCR |= BA0_DCR_MSK; in snd_cs4281_trigger()
694 dma->valFCR &= ~BA0_FCR_FEN; in snd_cs4281_trigger()
696 if (dma->regFCR != BA0_FCR0) in snd_cs4281_trigger()
697 dma->valFCR &= ~BA0_FCR_FEN; in snd_cs4281_trigger()
703 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR); in snd_cs4281_trigger()
704 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR); in snd_cs4281_trigger()
705 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR); in snd_cs4281_trigger()
734 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma, in snd_cs4281_mode() argument
740 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO | in snd_cs4281_mode()
743 dma->valDMR |= BA0_DMR_MONO; in snd_cs4281_mode()
745 dma->valDMR |= BA0_DMR_USIGN; in snd_cs4281_mode()
747 dma->valDMR |= BA0_DMR_BEND; in snd_cs4281_mode()
749 case 8: dma->valDMR |= BA0_DMR_SIZE8; in snd_cs4281_mode()
751 dma->valDMR |= BA0_DMR_SWAPC; in snd_cs4281_mode()
753 case 32: dma->valDMR |= BA0_DMR_SIZE20; break; in snd_cs4281_mode()
755 dma->frag = 0; /* for workaround */ in snd_cs4281_mode()
756 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK; in snd_cs4281_mode()
758 dma->valDCR |= BA0_DCR_HTCIE; in snd_cs4281_mode()
760 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr); in snd_cs4281_mode()
761 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1); in snd_cs4281_mode()
762 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO; in snd_cs4281_mode()
770 if (dma->left_slot == chip->src_left_play_slot) { in snd_cs4281_mode()
772 snd_BUG_ON(dma->right_slot != chip->src_right_play_slot); in snd_cs4281_mode()
776 if (dma->left_slot == chip->src_left_rec_slot) { in snd_cs4281_mode()
778 snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot); in snd_cs4281_mode()
784 if (dma->regFCR == BA0_FCR0) in snd_cs4281_mode()
785 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN); in snd_cs4281_mode()
787 dma->valFCR = BA0_FCR_LS(dma->left_slot) | in snd_cs4281_mode()
788 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) | in snd_cs4281_mode()
790 BA0_FCR_OF(dma->fifo_offset); in snd_cs4281_mode()
791 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0)); in snd_cs4281_mode()
793 if (dma->regFCR == BA0_FCR0) in snd_cs4281_mode()
794 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN); in snd_cs4281_mode()
796 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0); in snd_cs4281_mode()
813 struct cs4281_dma *dma = runtime->private_data; in snd_cs4281_playback_prepare() local
817 snd_cs4281_mode(chip, dma, runtime, 0, 1); in snd_cs4281_playback_prepare()
825 struct cs4281_dma *dma = runtime->private_data; in snd_cs4281_capture_prepare() local
829 snd_cs4281_mode(chip, dma, runtime, 1, 1); in snd_cs4281_capture_prepare()
837 struct cs4281_dma *dma = runtime->private_data; in snd_cs4281_pointer() local
847 snd_cs4281_peekBA0(chip, dma->regDCC) - 1; in snd_cs4281_pointer()
904 struct cs4281_dma *dma; in snd_cs4281_playback_open() local
906 dma = &chip->dma[0]; in snd_cs4281_playback_open()
907 dma->substream = substream; in snd_cs4281_playback_open()
908 dma->left_slot = 0; in snd_cs4281_playback_open()
909 dma->right_slot = 1; in snd_cs4281_playback_open()
910 runtime->private_data = dma; in snd_cs4281_playback_open()
923 struct cs4281_dma *dma; in snd_cs4281_capture_open() local
925 dma = &chip->dma[1]; in snd_cs4281_capture_open()
926 dma->substream = substream; in snd_cs4281_capture_open()
927 dma->left_slot = 10; in snd_cs4281_capture_open()
928 dma->right_slot = 11; in snd_cs4281_capture_open()
929 runtime->private_data = dma; in snd_cs4281_capture_open()
940 struct cs4281_dma *dma = substream->runtime->private_data; in snd_cs4281_playback_close() local
942 dma->substream = NULL; in snd_cs4281_playback_close()
948 struct cs4281_dma *dma = substream->runtime->private_data; in snd_cs4281_capture_close() local
950 dma->substream = NULL; in snd_cs4281_capture_close()
1589 struct cs4281_dma *dma = &chip->dma[tmp]; in snd_cs4281_chip_init() local
1590 dma->regDBA = BA0_DBA0 + (tmp * 0x10); in snd_cs4281_chip_init()
1591 dma->regDCA = BA0_DCA0 + (tmp * 0x10); in snd_cs4281_chip_init()
1592 dma->regDBC = BA0_DBC0 + (tmp * 0x10); in snd_cs4281_chip_init()
1593 dma->regDCC = BA0_DCC0 + (tmp * 0x10); in snd_cs4281_chip_init()
1594 dma->regDMR = BA0_DMR0 + (tmp * 8); in snd_cs4281_chip_init()
1595 dma->regDCR = BA0_DCR0 + (tmp * 8); in snd_cs4281_chip_init()
1596 dma->regHDSR = BA0_HDSR0 + (tmp * 4); in snd_cs4281_chip_init()
1597 dma->regFCR = BA0_FCR0 + (tmp * 4); in snd_cs4281_chip_init()
1598 dma->regFSIC = BA0_FSIC0 + (tmp * 4); in snd_cs4281_chip_init()
1599 dma->fifo_offset = tmp * CS4281_FIFO_SIZE; in snd_cs4281_chip_init()
1600 snd_cs4281_pokeBA0(chip, dma->regFCR, in snd_cs4281_chip_init()
1604 BA0_FCR_OF(dma->fifo_offset)); in snd_cs4281_chip_init()
1613 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) | in snd_cs4281_chip_init()
1616 BA0_FCR_OF(chip->dma[0].fifo_offset); in snd_cs4281_chip_init()
1617 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR); in snd_cs4281_chip_init()
1807 unsigned int status, dma, val; in snd_cs4281_interrupt() local
1819 for (dma = 0; dma < 4; dma++) in snd_cs4281_interrupt()
1820 if (status & BA0_HISR_DMA(dma)) { in snd_cs4281_interrupt()
1821 cdma = &chip->dma[dma]; in snd_cs4281_interrupt()