Lines Matching refs:SS_CSR
166 #define SS_CSR(t) (SER_BASE+t) macro
582 __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD)); in ser_init()
584 __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE)); in ser_init()
585 __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ)); in ser_init()
586 __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ)); in ser_init()
588 __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH)); in ser_init()
589 __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH)); in ser_init()
590 __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH)); in ser_init()
595 SS_CSR(R_SER_LINE_MODE)); in ser_init()
684 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))|| in dma_init()
685 __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) { in dma_init()
702 SS_CSR(R_SER_DMA_CONFIG0_RX)); in dma_init()
703 __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX)); in dma_init()
704 __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX)); in dma_init()
706 __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX)); in dma_init()
707 __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX)); in dma_init()
708 __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX)); in dma_init()
711 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); in dma_init()
713 __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE)); in dma_init()
716 SS_CSR(R_SER_INT_MASK)); in dma_init()
721 __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD)); in dma_init()
723 __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD)); in dma_init()
726 while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1) in dma_init()
731 (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff))); in dma_init()
772 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX)); in serdma_reg_access()
827 SS_CSR(R_SER_DMA_ENABLE)); in stop_dac()
945 status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0; in cs4297a_update_ptr()
949 … hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - in cs4297a_update_ptr()
1011 __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); in cs4297a_update_ptr()
1067 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); in cs4297a_update_ptr()
1092 … hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - in cs4297a_update_ptr()
1639 while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) || in drain_dac()
1652 hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - in drain_dac()
1825 … hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - in cs4297a_write()
1888 __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX)); in cs4297a_write()
2025 … (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - in cs4297a_ioctl()
2034 … (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - in cs4297a_ioctl()
2418 "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG)))); in cs4297a_locked_open()
2444 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) { in cs4297a_locked_open()
2446 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) in cs4297a_locked_open()
2556 status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG)); in cs4297a_interrupt()
2564 status = __raw_readq(SS_CSR(R_SER_STATUS)); in cs4297a_interrupt()
2571 status = __raw_readq(SS_CSR(R_SER_STATUS)); in cs4297a_interrupt()
2583 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))) in cs4297a_interrupt()
2585 … newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - in cs4297a_interrupt()
2593 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); in cs4297a_interrupt()