Lines Matching refs:ad_write
231 static void ad_write(ad1848_info * devc, int reg, int data) in ad_write() function
412 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev); in ad1848_set_recmask()
413 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev); in ad1848_set_recmask()
437 ad_write(devc, devc->mix_devices[i][j].recreg, val); in ad1848_set_recmask()
523 ad_write(devc, regoffs, val); in ad1848_mixer_set_channel()
526 ad_write(devc, muteregoffs, muteval); in ad1848_mixer_set_channel()
656 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */ in ad1848_mixer_reset()
658 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */ in ad1848_mixer_reset()
665 ad_write(devc, 16, 0x60); in ad1848_mixer_reset()
689 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */ in ad1848_mixer_ioctl()
691 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */ in ad1848_mixer_ioctl()
1063 ad_write(devc, 15, (unsigned char) (cnt & 0xff)); in ad1848_output_block()
1064 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff)); in ad1848_output_block()
1106 ad_write(devc, 15, (unsigned char) (cnt & 0xff)); in ad1848_start_input()
1107 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff)); in ad1848_start_input()
1111 ad_write(devc, 31, (unsigned char) (cnt & 0xff)); in ad1848_start_input()
1112 ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff)); in ad1848_start_input()
1145 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */ in ad1848_prepare_for_output()
1146 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */ in ad1848_prepare_for_output()
1153 ad_write(devc, 16, tmp | 0x30); in ad1848_prepare_for_output()
1156 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */ in ad1848_prepare_for_output()
1158 ad_write(devc, 8, fs); in ad1848_prepare_for_output()
1172 ad_write(devc, 16, tmp & ~0x30); in ad1848_prepare_for_output()
1214 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */ in ad1848_prepare_for_input()
1215 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */ in ad1848_prepare_for_input()
1220 ad_write(devc, 16, tmp | 0x30); in ad1848_prepare_for_input()
1223 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */ in ad1848_prepare_for_input()
1232 ad_write(devc, 28, fs); in ad1848_prepare_for_input()
1255 ad_write(devc, 8, tmp); in ad1848_prepare_for_input()
1272 ad_write(devc, 8, fs); in ad1848_prepare_for_input()
1285 ad_write(devc, 16, tmp & ~0x30); in ad1848_prepare_for_input()
1342 ad_write(devc, 9, ad_read(devc, 9) & ~0x02); /* Stop capture */ in ad1848_halt_input()
1377 ad_write(devc, 9, ad_read(devc, 9) & ~0x01); /* Stop playback */ in ad1848_halt_output()
1422 ad_write(devc, 9, tmp); in ad1848_trigger()
1473 ad_write(devc, i, init_values[i]); in ad1848_init_hw()
1482 ad_write(devc, 12, ad_read(devc, 12) | 0x50); in ad1848_init_hw()
1484 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */ in ad1848_init_hw()
1487 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */ in ad1848_init_hw()
1491 ad_write(devc, i, init_values[i]); in ad1848_init_hw()
1494 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */ in ad1848_init_hw()
1499 ad_write(devc, 9, ad_read(devc, 9) & ~0x04); /* Dual DMA mode */ in ad1848_init_hw()
1501 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */ in ad1848_init_hw()
1504 ad_write(devc, 27, ad_read(devc, 27) | 0x08); /* Alternate freq select enabled */ in ad1848_init_hw()
1508 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */ in ad1848_init_hw()
1509 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */ in ad1848_init_hw()
1510 ad_write(devc, 17, 0xc2); /* Alternate feature enable */ in ad1848_init_hw()
1516 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */ in ad1848_init_hw()
1518 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */ in ad1848_init_hw()
1633 ad_write(devc, 0, 0xaa); in ad1848_detect()
1634 ad_write(devc, 1, 0x45); /* 0x55 with bit 0x10 clear */ in ad1848_detect()
1647 ad_write(devc, 0, 0x45); in ad1848_detect()
1648 ad_write(devc, 1, 0xaa); in ad1848_detect()
1668 ad_write(devc, 12, (~tmp) & 0x0f); in ad1848_detect()
1696 ad_write(devc, 12, 0); /* Mode2=disabled */ in ad1848_detect()
1719 ad_write(devc, 12, 0x40); /* Set mode2, clear 0x80 */ in ad1848_detect()
1742 ad_write(devc, 16, 0); /* Set I16 to known value */ in ad1848_detect()
1744 ad_write(devc, 0, 0x45); in ad1848_detect()
1747 ad_write(devc, 0, 0xaa); in ad1848_detect()
1760 ad_write(devc, 25, ~tmp1); /* Invert all bits */ in ad1848_detect()
1794 ad_write(devc, 23, ~tmp); in ad1848_detect()
1812 ad_write(devc, 12, ad_read(devc, 12) & ~0x40); /* Mode2 off */ in ad1848_detect()
1814 ad_write(devc, 23, tmp); /* Restore */ in ad1848_detect()
1822 ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */ in ad1848_detect()
1823 ad_write(devc, 23, 0x9c); /* select extended register 25 */ in ad1848_detect()
1825 ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */ in ad1848_detect()
1899 ad_write(devc, 25, tmp1); /* Restore bits */ in ad1848_detect()
2042 ad_write(devc, 21, 0x00); /* Timer MSB */ in ad1848_init()
2043 ad_write(devc, 20, 0x10); /* Timer LSB */ in ad1848_init()
2045 ad_write(devc, 16, tmp | 0x40); /* Enable timer */ in ad1848_init()
2047 ad_write(devc, 16, tmp & ~0x40); /* Disable timer */ in ad1848_init()
2111 ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5)); in ad1848_control()
2239 ad_write(devc, 24, ad_read(devc, 24) & ~alt_stat); /* Selective ack */ in adintr()
2733 ad_write(devc, 21, (divider >> 8) & 0xff); /* Set upper bits */ in ad1848_tmr_start()
2734 ad_write(devc, 20, divider & 0xff); /* Set lower bits */ in ad1848_tmr_start()
2735 ad_write(devc, 16, ad_read(devc, 16) | 0x40); /* Start the timer */ in ad1848_tmr_start()
2759 ad_write(devc, 16, ad_read(devc, 16) & ~0x40); in ad1848_tmr_disable()
2773 ad_write(devc, 16, ad_read(devc, 16) | 0x40); in ad1848_tmr_restart()